Management method for processing bad blocks of memory and memory system
Through the encoding management circuit and memory access instruction decoding unit, the memory bad blocks are identified and simulated, and the problem of configuring spare units occupying space and cost is solved, and efficient bad block management and repair in the absence of spare blocks is realized.
Patent Information
- Application Number
- CN202410589305.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-10
- Filing Date
- 2024-05-13
- Publication Date
- 2025-07-11
AI Technical Summary
In the prior art, when handling memory bad blocks, configuring more spare units will occupy available space and increase costs, while configuring fewer spare units will not be able to effectively repair bad blocks.
The bad block is identified through the encoding management circuit and the memory access instruction decoding unit, and the bad block content is simulated by encoding method, so as to achieve bad block management and repair without spare blocks.
Without configuring spare blocks, effectively manage and repair memory bad blocks, reduce costs, and monitor new bad blocks in real time to improve the efficiency of the memory system.
Smart Images
Figure CN120295551A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of memory technologies, and more particularly to a management method and a memory system for handling defective blocks in a memory. Background Art
[0002] For a memory containing defective blocks (such as a random access memory (RAM)), spare / idle cells (such as spare cells) can usually be configured. Before the chip / integrated circuit (IC) leaves the factory, the defective blocks are mapped one-to-one to the spare cells. However, as the demand for memory space increases, the memory in the chip will increase, and the failure rate may increase accordingly. Configuring more spare cells can increase reliability, but it will occupy available space and increase the burden cost. Configuring fewer spare cells may not be able to repair the defective blocks.
[0003] Therefore, how to effectively handle (such as manage and repair) a memory containing defective blocks is an important issue worthy of research. Summary of the Invention
[0004] To solve the above technical problems, this application proposes a management method and a memory system for handling defective blocks in a memory to manage and repair the defective blocks in the memory when there is no spare / idle block configured in the memory.
[0005] An embodiment of this application provides a memory system, including: a memory; an encoding management circuit; and a memory access instruction decoding unit, signal-connected to the memory and the encoding management circuit, for: receiving an instruction from a bus; identifying a defective block in the memory; determining whether the instruction indicates accessing the defective block; when the instruction indicates writing data to the defective block, outputting the address of the defective block and the data to the encoding management circuit to trigger the encoding management circuit to update the encoding management circuit; and when the instruction indicates reading the defective block, outputting the address of the defective block to the encoding management circuit to trigger the encoding management circuit to output simulated data of the defective block, where the encoding management circuit obtains the simulated data of the defective block according to the address of the defective block.
[0006] An embodiment of the present application further provides a management method for processing memory bad blocks, including receiving an instruction from a bus through a memory access instruction decoding unit; identifying a bad block in the memory through the memory access instruction decoding unit; determining whether the instruction indicates accessing the bad block through the memory access instruction decoding unit; when the instruction indicates writing data to the bad block, outputting the address of the bad block and the data to a coding management circuit through the memory access instruction decoding unit, and updating the coding management circuit through the coding management circuit; and when the instruction indicates reading the bad block, outputting the address of the bad block to the coding management circuit through the memory access instruction decoding unit, obtaining simulation data of the bad block by the coding management circuit according to the address of the bad block; and outputting the simulation data of the bad block by the coding management circuit.
[0007] Based on the above, the management method for processing memory bad blocks and the memory system of the present application can achieve simulating the content of bad blocks in the memory in a coding manner to manage and repair bad blocks without configuring spare / idle blocks in the memory, thereby reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The provided drawings are used to enable those skilled in the art to further understand the present application and are incorporated into and constitute a part of the specification of the present application. The drawings show exemplary embodiments of the present application and are used together with the specification of the present application to explain the principles of the present application.
[0009] Figure 1 It is a block diagram of a memory system according to an embodiment of the present application;
[0010] Figure 2 It is a schematic diagram of bad block address mapping in a memory according to an embodiment of the present application;
[0011] Figure 3 It is a block diagram of a coding management circuit according to an embodiment of the present application;
[0012] Figure 4 It is a circuit schematic diagram of a digital circuit applying a Karnaugh map according to an embodiment of the present application;
[0013] Figure 5 It is a flowchart of a management method for processing memory bad blocks according to an embodiment of the present application.
[0014] [Symbol Description]
[0015] 100: Memory system
[0016] 102: Memory
[0017] 104: Coding management circuit
[0018] 106: Memory access instruction decoding unit
[0019] 108: Multiplexer
[0020] 110: Bus
[0021] 120: Non-volatile memory
[0022] 1020: At least one bad block
[0023] 1022: At least one normal block
[0024] 200: Memory
[0025] 201, 202, 203: Bad blocks
[0026] 204: Block
[0027] 300: Encoding management circuit
[0028] 302: Controller
[0029] 304: Digital circuit
[0030] 306: Multiplexer
[0031] 400: Digital circuit
[0032] S502, S504, S506, S508, S510, S512, S514, S516: Steps Detailed implementation manners
[0033] This application proposes a management method and a memory system for processing bad blocks of a memory to solve the problems mentioned in the background art. To make the features and advantages of this application more obvious and understandable, the following will describe in detail the specific embodiments of this application with reference to the accompanying drawings. The following description contains specific information related to the exemplary embodiments in this application. The drawings and their accompanying detailed descriptions in this application are only exemplary embodiments. However, this application is not limited to these exemplary embodiments. Those skilled in the art will think of other variations and embodiments of this application. Unless otherwise stated, the same or corresponding components in the drawings may be indicated by the same or corresponding reference numerals. In addition, the drawings and illustrations in this application are generally not drawn to scale and are not intended to correspond to actual relative sizes.
[0034] Figure 1A block diagram of a memory system according to an embodiment of the present application. The memory system 100 includes a memory 102, an encoding management circuit 104, and a memory access instruction decoding unit 106. The memory access instruction decoding unit 106 is signal-connected to the memory 102 and the encoding management circuit 104. The encoding management circuit 104 may be a field programmable gate array (FPGA), but the present application is not limited thereto. The memory 102 may be a random access memory (RAM), but the present application is not limited thereto. The digital circuit may be replaced by a logic circuit or a combinational circuit, but the present application is not limited thereto.
[0035] The memory access instruction decoding unit 106 is configured to receive (access) an instruction from a bus 110; identify (or detect) at least one bad block 1020 in the memory 102; and determine whether the instruction indicates accessing the bad block 1020. When the instruction indicates writing data to the bad block 1020, the memory access instruction decoding unit 106 outputs the address of the bad block and the data to the encoding management circuit 104 to trigger the encoding management circuit 104 to update the encoding management circuit 104. The encoding management circuit 104 may update the encoding management circuit 104 (such as internal components, etc.) according to the address and the data of the bad block. When the instruction indicates reading the bad block 1020, the memory access instruction decoding unit 106 outputs the address of the bad block to the encoding management circuit 104 to trigger the encoding management circuit 104 to output the simulated data of the bad block, where the encoding management circuit obtains the simulated data of the bad block according to the address of the bad block. That is, the simulated data of the bad block can be used to replace the (error) output data DOUT of the bad block.
[0036] In some embodiments, the memory system may include a multiplexer 108, which is signal-connected to the memory 102, the encoding management circuit 104, and the memory access instruction decoding unit 106. The multiplexer 108 may be used to (e.g., triggered by the memory access instruction decoding unit 106) receive the simulated data of the bad block from the encoding management circuit 104 and output the simulated data of the bad block to the bus 110 when the instruction indicates reading the bad block 1020. In some embodiments, the multiplexer 108 may receive the output data DOUT of the bad block.
[0037] In some embodiments, when the instruction indicates to read the normal block 1022 in the memory 102, the multiplexer 108 can receive the actual data DOUT stored in the normal block 1022 from the memory 102 and output the actual data DOUT to the bus 110.
[0038] In some embodiments, the memory access instruction decoder unit 106 can identify the bad block 1020 by reading a non-volatile memory (NVM) or by performing dynamic detection on the memory 102. The dynamic detection can include at least one of responding to the received instruction and periodic detection. Specifically, bad blocks in the memory can be identified through the operation / function of built-in self-test (BIST) and stored in the non-volatile memory accordingly. The BIST operation (i.e., pre-determined / defined) can be performed in the final test (FT) stage before the chip leaves the factory. In addition, the BIST operation can also be performed during the process of accessing the memory (i.e., real-time detection), such as by comparing the data written to the block and the output data DOUT to see if they are the same. It should be noted that the dynamic detection can identify newly added bad blocks (compared to pre-determined bad blocks).
[0039] In some embodiments, the memory access instruction decoder unit 106 can obtain information about the bad block 1020 by reading a non-volatile memory or by performing dynamic detection on the memory 102. The information can include at least one of the address of the bad block 1020 and address mapping information (such as an index). Figure 2 Schematic diagram of bad block address mapping for a memory 200 according to an embodiment of the present application. Please refer to Figure 2 , the memory 200 with 16 bits (bit) includes a bad block 201 at the 3rd bit, a bad block 202 at the 5th bit, and a bad block 203 at the 14th bit. Data cannot be accessed from the bad blocks 201, 202, and 203. The bad blocks 201, 202, and 203 can apply 2-bit addresses {A, B}, and are respectively mapped (e.g., encoded for addressing) to 1 = 2'b00, 2 = 2'b01, and 3 = 2'b10.
[0040] In some embodiments, when a newly added bad block is identified (compared to pre-determined bad blocks), (e.g., by the encoding management circuit 104) address mapping information for the newly added bad block can be generated. For example, when it is identified that the block 204 at the 16th bit (e.g., a normal block when leaving the factory) becomes a bad block, the encoding management circuit 104 can map the block 204 (e.g., encoded for addressing) to 4 = 2'b11 and store it in the non-volatile memory.
[0041] In some embodiments, the encoding management circuit 104 may output simulation data of the bad block as the simulation data of the bad block. Specifically, the bandwidth of the bus is fixed, so the bus will only access a single data / bit at a time point. Therefore, according to the encoding management circuit 104 and the memory access instruction decoding unit 106 of the present application, all bad blocks in the memory can be managed. For example, assume that the correct data / values of bad block 201, bad block 202, and bad block 203 should be "0", "1", and "1" respectively. When the bus instructs to read the data of bad block 202, the encoding management circuit can output the value "1" to bad block 201, bad block 202, and bad block 203 at the same time. Since the bus will not read bad block 201 and bad block 203 at the same time point (i.e., bad block 201 and bad block 203 are in a non-enabled state), outputting the value "1" to bad block 201 will not cause a read error. Similarly, when the bus instructs to read the data of bad block 201, the encoding management circuit can output the value "0" to bad block 201, bad block 202, and bad block 203 at the same time. Since the bus will not read bad block 202 and bad block 203 at the same time point (i.e., bad block 202 and bad block 203 are in a non-enabled state), outputting the value "0" to bad block 202 and bad block 203 will not cause a read error.
[0042] In some embodiments, when the encoding management circuit 104 may include digital circuits, please refer to Figure 1 , Figure 3 and Figure 4 .
[0043] Figure 3 FIG. 300 is a block diagram of an encoding management circuit 300 according to an embodiment of the present application. The encoding management circuit 300 (which may be the encoding management circuit 104) includes a controller 302 and a digital circuit 304. The controller 302 may be signal-connected to the digital circuit 304. The digital circuit 304 may apply Karnaugh maps (for simplification), but the present application is not limited thereto.
[0044] Figure 4 FIG. 400 is a circuit diagram of a digital circuit 400 (which may be the digital circuit 304) applying Karnaugh maps according to an embodiment of the present application. The digital circuit 400 may indicate a plurality of encoding functions (functions), which may also be referred to as a plurality of data paths (datapaths). The plurality of encoding functions may respectively correspond to combinations of addresses and data of a plurality of bad blocks, for example Figure 4The 16 encoding functions f(x) therein. The 2-bit address {A, B} can be used as the input of the encoding function f(x). K can be used as the output of the encoding function f(x). Each encoding function can respectively correspond to different bad block writing states Sum(...). The plurality of encoding functions includes a first encoding function (e.g., f(x)=A'B') and a second encoding function (e.g., f(x)=A'). When the instruction indicates writing the first data to the first bad block, the operation of the encoding management circuit 300 for updating the encoding management circuit 300 includes: the controller 302 can select a first address (mapping information) corresponding to the first bad block and a first encoding function of the first data (e.g., whether it is the value "1") from the plurality of encoding functions. When the instruction indicates reading the first bad block, the operation of the encoding management circuit 300 for obtaining the simulated data of the bad block according to the address of the bad block includes: the controller 302 can obtain the first simulated data of the first bad block according to the first encoding function and the first address of the first bad block, and the controller 302 can output the first simulated data of the first bad block. Specifically, the controller 302 can substitute the first address (mapping information) of the first bad block into the first encoding function to obtain the first simulated data of the first bad block.
[0045] In some embodiments, after selecting the first encoding function, the controller 302 can store the first encoding function in an additional memory (such as a volatile memory (VM), a non-volatile memory, a register, etc.).
[0046] In some embodiments, when the instruction indicates writing second data to a second bad block, the controller 302 may select a second encoding function corresponding to the first address, the first data, the second address (mapping information) of the second bad block, and the second data (e.g., whether it is the value "1") of the first bad block from the plurality of encoding functions. When the instruction indicates reading the first bad block, the controller 302 may obtain second simulated data of the first bad block according to the first address of the first bad block and the second encoding function, and the controller 302 may output the second simulated data of the first bad block. When the instruction indicates reading the second bad block, the controller 302 may obtain first simulated data of the second bad block according to the second address of the second bad block and the second encoding function, and the controller 302 may output the first simulated data of the second bad block. Specifically, the controller 302 may substitute the second address (mapping information) of the second bad block into the second encoding function to obtain the first simulated data of the second bad block. For example, assume that currently only the bad block with address mapping information 1 = 2b'00 writes the value "1", and the controller 302 may apply the encoding function Sum(1), i.e., f(x) = A'B'. Then, when the instruction indicates writing the value "1" to the bad block with address mapping information 3 = 2b'10, the controller 302 may apply the encoding function Sum(1,3), i.e., f(x) = A'. Then, when the instruction indicates reading the bad block with address mapping information 1 = 2b'00, the controller 302 may substitute 1 = 2b'00 into f(x) = A' to obtain 1. Then, when the instruction indicates writing the value "0" to the bad block with address mapping information 1 = 2b'00, the controller 302 may apply the encoding function Sum(3), i.e., f(x) = A'B.
[0047] In Figure 4 it, f(sum(0)) may indicate that the written data of all bad blocks is not a specific data (e.g., all write the value "0") or there is no bad block. It should be noted that the encoding function can be initialized to f(sum(0)). f(sum(1,2,3,4)) may indicate that the written data of all bad blocks is a specific data (e.g., all write the value "1"). It should be noted that the digital circuit applying Karnaugh map is related to the number of bad blocks. For example, 2-bit input can be used to manage up to 4 bad blocks. 3-bit input can be used to manage up to 8 bad blocks. When the number of identified bad blocks exceeds the upper limit of bad blocks supported by a digital circuit, another digital circuit can be applied.
[0048] The following is an example. Assume that bad block 1, bad block 2, and bad block 3 can be respectively mapped (e.g., encoded and addressed) to 1 = 2'b00, 2 = 2'b01, and 3 = 2'b10. The 2-bit address {B,A} can be used as the input of the encoding function f.
[0049] After initial power-on, since no data has been written to the blocks in the memory, the corresponding encoding function is f(sum(0)). At this time, the simulated data obtained by reading any bad block is the value "0". After writing the value "1" to bad block 1, since only bad block 1 has the value "1" written to it, the encoding management circuit can update the encoding function to f(sum(1)) = A'B'. If bad block 1 (encoding address 2'b00) is read, the encoding management circuit can obtain and output the simulated data of bad block 1 as 1. Then, after writing the value "1" to bad block 3, since both bad block 1 and bad block 3 have the value "1" written to them, the encoding management circuit can update the encoding function to f(sum(1,3)) = A'. If bad block 1 (encoding address 2'b00) is read, the encoding management circuit can obtain and output the simulated data of bad block 1 as 1. If bad block 3 (encoding address 2'b10) is read, the encoding management circuit can obtain and output the simulated data of bad block 3 as 1. Then, after writing the value "1" to bad block 2, since bad block 1, bad block 2, and bad block 3 all have the value "1" written to them, the encoding management circuit can update the encoding function to f(sum(1,2,3)) = A'+B'. If bad block 1 (encoding address 2'b00) is read, the encoding management circuit can obtain and output the simulated data of bad block 1 as 0. If bad block 2 (encoding address 2'b01) is read, the encoding management circuit can obtain and output the simulated data of bad block 2 as 1. If bad block 3 (encoding address 2'b10) is read, the encoding management circuit can obtain and output the simulated data of bad block 3 as 1. Then, after writing the value "0" to bad block 1, since bad block 2 and bad block 3 both have the value "1" written to them, the encoding management circuit can update the encoding function to f(sum(2,3)) = AB'+A'B. If bad block 2 (encoding address 2'b01) is read, the encoding management circuit can obtain and output the simulated data of bad block 2 as 1. If bad block 3 (encoding address 2'b10) is read, the encoding management circuit can obtain and output the simulated data of bad block 3 as 1.
[0050] According to the above embodiments, the following management method for processing memory bad blocks can be obtained (for example, summarized). Figure 5 It is a schematic flowchart of a management method for processing memory bad blocks according to an embodiment of the present application.
[0051] As Figure 5 shown, this management method includes the following steps:
[0052] In step S502, at least one address mapping information of at least one bad block in the non-volatile memory is obtained from the non-volatile memory through the memory access instruction decoding unit.
[0053] In step S504, the encoding function f(x) is initialized by the encoding management circuit. Here, x represents the address mapping information of the bad block.
[0054] In step S506, an instruction is received from the bus by the memory access instruction decoding unit.
[0055] In step S508, the memory access instruction decoding unit determines whether the instruction indicates accessing at least one of the bad blocks. When the instruction indicates accessing at least one of the bad blocks, step S510 is executed. When the instruction indicates accessing at least one of the normal blocks in the memory, step S516 is executed.
[0056] In step S510, the memory access instruction decoding unit determines whether the instruction is a write instruction or a read instruction. When the instruction indicates writing data to a bad block among at least one bad block, step S512 is executed. When the instruction indicates reading a bad block among at least one bad block, step S514 is executed.
[0057] In step S512, the encoding management circuit updates the encoding function f(x). Step S506 is re-executed.
[0058] In step S514, the address mapping information of the bad block is substituted into the encoding function f(x) by the encoding management circuit to obtain the simulated data of the bad block, and the simulated data of the bad block is output to the bus. Step S506 is re-executed.
[0059] In step S516, the memory access instruction decoding unit triggers the memory to output the actual data of the normal block. Step S506 is re-executed.
[0060] In summary, the management method and memory system for processing memory bad blocks of the present application can achieve, in the case where the memory is not configured with spare / idle blocks, after identifying the bad blocks in the memory through BIST operation, simulating the content of the bad blocks in an encoding manner to manage and (automatically) repair the bad blocks, thereby reducing costs. Specifically, through the encoding method, it is not necessary to store the content of the bad blocks in an additional block, thus achieving the function of compressing the bad block information. In addition, it is also possible to achieve real-time monitoring of newly added bad blocks and repair them. In addition, compared with a more regular memory component (such as a spare unit), the digital circuit is more efficient in terms of area utilization and is more suitable for repairing a small number of bad blocks.
[0061] Although the present application has been disclosed by the above embodiments, it is not intended to limit the present application. Any person skilled in the art, without departing from the spirit and scope of the present application, making various changes and modifications to the above embodiments still belongs to the technical scope protected by the present application. Therefore, the protection scope of the present application shall be determined by the scope defined by the claims.
Claims
1. A memory system, characterized in that, Comprising: A memory; An encoding management circuit; and A memory access instruction decoding unit, signal-connected to the memory and the encoding management circuit, for: Receiving an instruction from a bus; Identifying a bad block in the memory; Determining whether the instruction indicates accessing the bad block; When the instruction indicates writing a data to the bad block, outputting an address of the bad block and the data to the encoding management circuit to trigger the encoding management circuit to update the encoding management circuit; And When the instruction indicates reading the bad block, outputting the address of the bad block to the encoding management circuit to trigger the encoding management circuit to output a simulated data of the bad block, wherein the encoding management circuit obtains the simulated data of the bad block according to the address of the bad block.
2. The memory system according to claim 1, wherein Further comprising a multiplexer, signal-connected to the memory, the encoding management circuit and the memory access instruction decoding unit, wherein when the instruction indicates reading the bad block, the multiplexer receives the simulated data of the bad block from the encoding management circuit and outputs the simulated data of the bad block to the bus, and when the instruction indicates reading a normal block in the memory, the multiplexer receives an actual data stored in the normal block from the memory and outputs the actual data to the bus.
3. The memory system according to claim 1, characterized in that, Wherein the encoding management circuit further comprises: A digital circuit, the digital circuit indicating a plurality of encoding functions, the plurality of encoding functions corresponding to combinations of addresses and data of a plurality of bad blocks respectively; and A controller, signal-connected to the digital circuit, wherein: When the instruction indicates writing a first data to a first bad block, the controller selects a first encoding function corresponding to a first address of the first bad block and the first data from the plurality of encoding functions; and When the instruction indicates reading the first bad block, the controller obtains a first simulated data of the first bad block according to the first encoding function and the first address of the first bad block, and the controller outputs the first simulated data of the first bad block.
4. The memory system according to claim 3, wherein Wherein: When the instruction indicates writing a second data to a second bad block, the controller selects a second encoding function corresponding to the first address of the first bad block, the first data, a second address of the second bad block and the second data from the plurality of encoding functions; When the instruction indicates reading the first bad block, the controller obtains a second simulated data of the first bad block according to the first address of the first bad block and the second encoding function, and the controller outputs the second simulated data of the first bad block; And When the instruction indicates reading the second bad block, the controller obtains a first simulated data of the second bad block according to the second address of the second bad block and the second encoding function, and the controller outputs the first simulated data of the second bad block.
5. The memory system according to claim 3, wherein Wherein after selecting the first encoding function, the controller stores the first encoding function in an additional memory.
6. The memory system according to claim 1, wherein The memory access instruction decoding unit identifies the bad block by reading a non-volatile memory or by performing dynamic detection on the memory, where the dynamic detection includes at least one of responding to receiving the instruction and periodic detection.
7. A management method for handling memory bad blocks, characterized in that, Comprising: Receiving an instruction from a bus through a memory access instruction decoding unit; Identifying a bad block in a memory through the memory access instruction decoding unit; Determining, through the memory access instruction decoding unit, whether the instruction indicates accessing the bad block; When the instruction indicates writing a data to the bad block, outputting, through the memory access instruction decoding unit, an address of the bad block and the data to a coding management circuit, and updating the coding management circuit through the coding management circuit; And When the instruction indicates reading the bad block, outputting, through the memory access instruction decoding unit, the address of the bad block to the coding management circuit, obtaining, through the coding management circuit, a simulated data of the bad block according to the address of the bad block, and outputting the simulated data of the bad block through the coding management circuit.
8. The management method according to claim 7, wherein, Wherein the coding management circuit includes a digital circuit, the digital circuit indicates a plurality of coding functions, the plurality of coding functions respectively correspond to combinations of addresses and data of a plurality of bad blocks, and the management method further includes: When the instruction indicates writing a first data to a first bad block, selecting, through the coding management circuit, a first coding function corresponding to a first address of the first bad block and the first data from the plurality of coding functions; And When the instruction indicates reading the first bad block, obtaining, through the coding management circuit, a first simulated data of the first bad block according to the first coding function and the first address of the first bad block, and outputting the first simulated data of the first bad block.
9. The management method according to claim 8, wherein Wherein: When the instruction indicates writing a second data to a second bad block, selecting, through the coding management circuit, a second coding function corresponding to the first address of the first bad block, the first data, a second address of the second bad block, and the second data from the plurality of coding functions; When the instruction indicates reading the first bad block, obtaining, through the coding management circuit, a second simulated data of the first bad block according to the first address of the first bad block and the second coding function, and outputting the second simulated data of the first bad block; And When the instruction indicates reading the second bad block, obtaining, through the coding management circuit, a first simulated data of the second bad block according to the second address of the second bad block and the second coding function, and outputting the first simulated data of the second bad block.
10. The management method according to claim 7, characterized in that, Wherein the memory access instruction decoding unit identifies the bad block by reading a non-volatile memory or by performing dynamic detection on the memory, where the dynamic detection includes at least one of responding to receiving the instruction and periodic detection.