Storage control method and memory storage device

Abstract

The invention provides a memory control method and a memory storage device, the memory storage device comprises a rewritable nonvolatile memory module of a plurality of class groups and a memory control circuit unit, each class group comprises a plurality of entity units, and the memory control method comprises the following steps: in a process of executing a data write-in operation, the memory control circuit unit is connected with the rewritable nonvolatile memory module, and the memory control circuit unit is connected with the rewritable nonvolatile memory module; obtaining a plurality of consumption capacities of the plurality of class groups every time data of unit capacity is written; generating a plurality of storage capabilities based on the plurality of consumption capacities; and if the at least one storage capability is smaller than the threshold value, determining a control strategy according to a plurality of pieces of class group information respectively corresponding to the plurality of class groups so as to execute data consolidation operation, the plurality of pieces of class group information including a plurality of storage capabilities, a plurality of execution efficiencies and a plurality of pieces of priority information of the plurality of class groups. In this way, the data consolidation operation is executed through the multi-dimensional judgment result, so that the accuracy and efficiency of the data consolidation operation are effectively improved.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and more particularly to a storage control method and a memory storage device. Background Art

[0002] In recent years, the growth of smart phones, tablet computers, and personal computers has been very rapid, resulting in a sharp increase in consumers' demand for storage media. Since rewritable non-volatile memory modules (such as flash memory) have characteristics such as data non-volatility, power saving, small size, and no mechanical structure, they are very suitable for being built into various portable multimedia devices exemplified above.

[0003] Generally speaking, in order to improve data processing capabilities, the storage space of rewritable non-volatile memory modules can be optimized by performing a garbage collection (GC) operation, thereby improving the performance of the storage media. Summary of the Invention

[0004] Exemplary embodiments of the present invention provide a storage control method and a memory storage device, which can use the real-time consumption amount and execution efficiency of physical units as the basis for determining whether to perform a garbage collection operation on the physical units, and can avoid ineffective garbage collection operations.

[0005] Exemplary embodiments of the present invention provide a storage control method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of groups. Each of the groups includes a plurality of physical units. The storage control method includes: during the execution of a data writing operation, whenever a unit capacity of data is written, obtaining the consumption capacities of the plurality of groups; generating a plurality of storage capabilities based on the plurality of consumption capacities; and if at least one of the storage capabilities is less than a threshold, determining a control strategy according to the plurality of group information corresponding to the plurality of groups to perform a data consolidation operation, where the plurality of group information includes the plurality of storage capabilities, the plurality of execution efficiencies, and the plurality of priority information of the plurality of groups.

[0006] In an exemplary embodiment of the present invention, the step of generating the plurality of storage capabilities based on the plurality of consumption capacities further includes: calculating the plurality of storage capabilities according to the plurality of consumption capacities and the plurality of initial capacities of the plurality of groups, where the plurality of initial capacities are the capacities of the plurality of groups when the data writing operation starts to be executed.

[0007] In an exemplary embodiment of the present invention, the step of performing the data consolidation operation further includes: if the number of at least one of the groups corresponding to at least one of the storage capabilities is greater than 1, preferentially performing the data consolidation operation on the group corresponding to the lowest storage capability.

[0008] In an exemplary embodiment of the present invention, the step of performing the data consolidation operation further includes: if the number is greater than 1 and at least one of the storage capabilities is the same, calculating at least one execution efficiency of at least one of the groups; and preferentially performing the data consolidation operation on the group corresponding to the highest execution efficiency.

[0009] In an exemplary embodiment of the present invention, the step of performing the data consolidation operation further includes: if at least one of the execution efficiencies is the same, performing the data consolidation operation according to at least one priority information of at least one of the groups.

[0010] In an exemplary embodiment of the present invention, each of the priority information includes fixed priority information and preset priority information. The fixed priority information is determined by the importance of the multiple entity units in each of the groups, and the preset priority information is determined by the urgency of use of the multiple entity units in each of the groups.

[0011] In an exemplary embodiment of the present invention, the multiple entity units in each of the groups are system entity units for storing management information, mapping entity units for storing mapping table information, or data entity units for storing user data.

[0012] Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The connection interface unit is coupled to a host system. The rewritable non-volatile memory module includes multiple groups. Each of the groups includes multiple entity units. During the process of performing a data write operation, whenever a unit capacity of data is written, the memory control circuit unit is used to obtain the multiple consumed capacities of the multiple groups. The memory control circuit unit is further used to generate multiple storage capabilities based on the multiple consumed capacities. If at least one of the storage capabilities is less than a threshold, the memory control circuit unit is further used to determine a control strategy according to the multiple group information corresponding to the multiple groups to perform a data consolidation operation, where the multiple group information includes the multiple storage capabilities, multiple execution efficiencies, and multiple priority information of the multiple groups.

[0013] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to calculate the multiple storage capabilities according to the multiple consumption capacities and the multiple initial capacities of the multiple groups, where the multiple initial capacities are the capacities of the multiple groups when the data writing operation starts to be executed.

[0014] In an exemplary embodiment of the present invention, if the number of at least one of the groups corresponding to at least one of the storage capabilities is greater than 1, the memory control circuit unit is further configured to preferentially perform the data consolidation operation on the group corresponding to the lowest storage capability.

[0015] In an exemplary embodiment of the present invention, if the number is greater than 1 and at least one of the storage capabilities are the same, the memory control circuit unit is further configured to calculate at least one execution efficiency of at least one of the groups, and preferentially perform the data consolidation operation on the group corresponding to the highest execution efficiency.

[0016] In an exemplary embodiment of the present invention, if at least one of the execution efficiencies are the same, the memory control circuit unit is further configured to perform the data consolidation operation according to at least one priority information of at least one of the groups.

[0017] Based on the above, the present invention provides a storage control method and a memory storage device, which can use the consumption capacities (and execution efficiencies, priority information) of various groups (different types of physical units) as the basis for whether to perform the data consolidation operation, and can avoid unnecessary data consolidation operations, thereby effectively improving the performance of the memory storage device.

[0018] To make the above features and advantages of the present invention more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0019] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown according to an exemplary embodiment of the present invention;

[0020] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown according to an exemplary embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of a host system and a memory storage device shown according to an exemplary embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of a memory storage device shown according to an exemplary embodiment of the present invention;

[0023] Figure 5 is a schematic diagram of a memory control circuit unit shown in an exemplary embodiment of the present invention;

[0024] Figure 6 is a schematic diagram of a management rewritable non-volatile memory module shown in an exemplary embodiment of the present invention;

[0025] Figure 7 is a flowchart of a storage control method shown in an exemplary embodiment of the present invention;

[0026] Figure 8 is a flowchart of a storage control method shown in an exemplary embodiment of the present invention. Detailed Description of the Invention

[0027] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0028] Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0029] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown in an exemplary embodiment of the present invention.

[0030] Please refer to Figure 1 and Figure 2 , the host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be coupled to a system bus 110.

[0031] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 through a data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 through a system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0032] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 in a wired or wireless manner.

[0033] In an exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a low energy Bluetooth memory storage device (e.g., iBeacon), etc., which are memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0034] In an exemplary embodiment, the host system 11 is a computer system. In an exemplary embodiment, the host system 11 may be any system that can substantially cooperate with the memory storage device to store data. In an exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include Figure 3 the memory storage device 30 and the host system 31.

[0035] Figure 3 is a schematic diagram of a host system and a memory storage device shown in an exemplary embodiment of the present invention.

[0036] Please refer to Figure 3, the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple a memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0037] Figure 4 is a schematic diagram of the memory storage device shown in the exemplary embodiment of the present invention.

[0038] Please refer to Figure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0039] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be encapsulated in a chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip that includes the memory control circuit unit 42.

[0040] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware form and perform operations such as data writing, reading, and erasing in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0041] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module capable of storing 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0042] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, and thus one or more bits stored in this memory cell can be obtained.

[0043] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may form a plurality of physical programming units, and these physical programming units may form a plurality of physical units. Specifically, the memory cells on the same word line may form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be at least classified into lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in an MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0044] In an exemplary embodiment, the physical programming unit is the smallest unit for programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (such as management data like error correction codes). In this exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can also be larger or smaller. On the other hand, the physical unit is the smallest unit for erasure. That is, each physical unit contains the smallest number of memory cells that are erased together. For example, the physical unit is a physical block.

[0045] Figure 5 It is a schematic diagram of a memory control circuit unit shown in an exemplary embodiment of the present invention.

[0046] Please refer to Figure 5 , the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0047] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions will be executed to perform operations such as data writing, reading, and erasing. When explaining the operation of the memory management circuit 51 below, it is equivalent to explaining the operation of the memory control circuit unit 42.

[0048] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into this read-only memory. When the memory storage device 10 operates, these control instructions will be executed by the microprocessor unit to perform operations such as data writing, reading, and erasing.

[0049] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of the rewritable non-volatile memory module 43 in the form of code (for example, the system area in the memory module dedicated to storing system data). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. After that, the microprocessor unit will execute these control instructions to perform operations such as data writing, reading, and erasing.

[0050] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage units or groups of storage units of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence may each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0051] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 is used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0052] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences can include a write instruction sequence for indicating writing data, a read instruction sequence for indicating reading data, an erase instruction sequence for indicating erasing data, and corresponding instruction sequences for indicating various memory operations (such as changing the read voltage level or performing a garbage collection operation, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on the bus. These signals or data can include instruction codes or codes. For example, in the read instruction sequence, information such as the read identification code and the memory address will be included.

[0053] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correcting circuit 54, a buffer memory 55, and a power management circuit 56.

[0054] The error checking and correcting circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write instruction from the host system 11, the error checking and correcting circuit 54 will generate a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to this write instruction, and the memory management circuit 51 will write the data corresponding to this write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. After that, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it will simultaneously read the corresponding error correcting code and / or error detecting code of this data, and the error checking and correcting circuit 54 will perform error checking and correcting operations on the read data based on this error correcting code and / or error detecting code.

[0055] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0056] In an exemplary embodiment,Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0057] Figure 6 is a schematic diagram showing the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0058] Please refer to Figure 6 , the memory management circuit 51 may logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602. One physical unit refers to one virtual block (VB). One virtual block may include multiple physical programmed units. For example, one virtual block may contain one or more physical units.

[0059] The physical units 610(0) to 610(A) in the storage area 601 are used to store user data (such as user data from Figure 1 the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 may store valid data and invalid data. The physical units 610(A + 1) to 610(B) in the spare area 602 do not store data (such as valid data). For example, if a certain physical unit does not store valid data, this physical unit may be associated (or added) to the spare area 602. In addition, the physical units in the spare area 602 (or the physical units that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store this new data. In an exemplary embodiment, the spare area 602 is also referred to as a free pool.

[0060] The memory management circuit 51 may configure the logical units 612(0) to 612(C) to map the physical units 610(0) to 610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units.

[0061] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data stored in this physical unit currently contains valid data. On the contrary, if a physical unit is not currently mapped by any logical unit, it means that the data stored in this physical unit does not contain any valid data.

[0062] The memory management circuit 51 can record management data (also known as logical-to-physical mapping information) describing the mapping relationship between logical units and physical units in at least one logical-to-physical mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can perform data access operations on the memory storage device 10 according to the information in this logical-to-physical mapping table.

[0063] In an exemplary embodiment, the physical units in the rewritable non-volatile memory module 43 can be divided into multiple groups according to the data types they store, where each group includes one or more physical units.

[0064] Specifically, one or more physical units in each group can include, but are not limited to: one or more system physical units (Log Block) for storing management information, one or more mapping physical units (Mapping Table Block) for storing mapping table information, or one or more data physical units (Data Block) for storing user data.

[0065] In an exemplary embodiment, the garbage collection operation can include the garbage collection operation (Log GC) performed on the system physical units, the garbage collection operation (Mapping Table GC) performed on the mapping garbage collection operation, and the garbage collection operation (Data GC) performed on the data physical units. That is to say, the memory management circuit 51 can perform corresponding garbage collection operations on different groups.

[0066] In an exemplary embodiment, according to the usage status of the memory storage device 10, the garbage collection operation can be divided into background garbage collection operation and foreground garbage collection operation.

[0067] The background garbage collection operation, as the name implies, is the garbage collection operation performed when the memory storage device 10 is in the background state (for example, the idle state). In contrast, the foreground garbage collection operation is the garbage collection operation performed when the memory storage device 10 is in the foreground state (for example, the busy state).

[0068] Generally speaking, the foreground garbage collection operation is performed concurrently with the data writing operation. Specifically, during the execution of the data writing operation, when the number of physical units in the idle area 602 is insufficient, the foreground garbage collection operation is initiated, resulting in a decrease in the writing performance of the memory storage device 10. Accordingly, the present invention provides a storage control method (i.e., Figure 7 the storage control method) that can reduce the occurrence probability of the foreground garbage collection operation, thereby improving the performance of the memory storage device 10.

[0069] Figure 7 is a flowchart of the storage control method shown in an exemplary embodiment of the present invention. Please refer to Figure 7 the specific step content shown:

[0070] In step S701, the memory management circuit 51 can perform the data writing operation. Specifically, when the memory management circuit 51 performs the data writing operation, the memory storage device 10 is in a busy state. As the data writing operation is executed, there is a chance to trigger the foreground garbage collection operation.

[0071] In step S702, the memory management circuit 51 can determine whether the amount of written data reaches the unit capacity (for example, 1 GB). If the amount of written data does not reach the unit capacity, return to step S701 to continue writing data.

[0072] On the contrary, if the amount of written data reaches the unit capacity, proceed to step S703.

[0073] Regarding the unit capacity, it can be designed according to actual needs, and the present invention does not limit it.

[0074] In step S703, the memory management circuit 51 can obtain the consumption capacities of multiple groups and generate multiple storage capabilities based on the multiple consumption capacities.

[0075] Specifically, during the data writing operation, due to different written data, the consumption capacities of physical units in each group are also different. In an exemplary embodiment, whenever the memory management circuit 51 writes 1 GB of data, the memory management circuit 51 can obtain the consumption capacities of each group and use the consumption capacities of each group as a reference basis for performing the garbage collection operation. That is to say, when 1 GB of new data is written, the memory management circuit 51 can obtain the consumption capacities of each group again to update the reference basis for the garbage collection operation.

[0076] In an exemplary embodiment, the memory management circuit 51 can calculate the storage capabilities of each group based on the consumption capacities of each group and the initial capacities of each group, where the initial capacity is the capacity of each group at the start of the data writing operation.

[0077] Specifically, the memory management circuit 51 may first calculate the remaining capacity of each type of group based on the consumed capacity of each type of group, and then calculate the ratio of the remaining capacity of each type of group to the initial capacity (i.e., the storage capacity of each type of group). Accordingly, the memory management circuit 51 may use the storage capacity of each type of group as the basis for determining whether to perform a garbage collection operation on each type of group. That is to say, Figure 7 In the storage control method, the actual situation of each type of group (i.e., the storage capacity) can be used as the basis for determining whether to perform a garbage collection operation, which can avoid unnecessary foreground garbage collection operations.

[0078] Subsequently, in step S704, the memory management circuit 51 may determine whether at least one storage capacity is less than a threshold.

[0079] In an exemplary embodiment, after obtaining the storage capacity of each type of group, the memory management circuit 51 may determine whether the storage capacity of each type of group is less than a threshold.

[0080] Regarding the threshold, it can be designed according to actual needs, and the present invention does not limit it.

[0081] If the storage capacity of each type of group is not less than this threshold, it means that the garbage collection operation has not been triggered, and the data writing operation can continue to be performed.

[0082] On the contrary, if there is at least one storage capacity of at least one type of group less than this threshold, it means that a garbage collection operation needs to be performed on the at least one type of group to maintain the performance of the memory storage device 10.

[0083] Therefore, the memory management circuit 51 may determine a control strategy according to multiple group information respectively corresponding to multiple groups to perform a data consolidation operation (for example, a garbage collection operation). Specifically, the control strategy is used to indicate the execution details of the data consolidation operation. In an exemplary embodiment, the multiple group information includes the multiple storage capacities, multiple execution efficiencies, and multiple priority information of the multiple groups. If there is at least one storage capacity of at least one type of group less than this threshold, the memory management circuit 51 may determine a control strategy according to the multiple group information to perform a data consolidation operation, thereby maintaining the performance of the memory storage device 10.

[0084] That is to say, the memory management circuit 51 may use the storage capacity, execution efficiency, and priority information of each type of group as the basis for determining whether to perform a data consolidation operation, which can avoid unnecessary foreground garbage collection operations. Regarding the memory management circuit 51 determining a control strategy according to multiple group information, reference can be made to Figure 7 Steps S705 to S712 in

[0085] According to the above, if there is no storage capacity less than this threshold, return to step S701. On the contrary, if at least one storage capacity is less than the threshold, enter step S705.

[0086] In step S705, the memory management circuit 51 can determine whether the number of at least one type of group is 1. If the number of at least one type of group is 1, enter step S706.

[0087] In step S706, the memory management circuit 51 can perform a data consolidation operation on this type of group to maintain the performance of the memory storage device 10.

[0088] On the contrary, if the number of at least one type of group is not 1, enter step S707.

[0089] In step S707, the memory management circuit 51 can determine whether at least one storage capacity is the same.

[0090] In an exemplary embodiment, assume that the number of at least one type of group is 2. The memory management circuit 51 can determine which of these 2 types of groups to perform a data consolidation operation on preferentially according to the storage capacities of these 2 types of groups. If the storage capacities of these 2 types of groups are different, enter step S708.

[0091] In step S708, the memory management circuit 51 can preferentially perform a data consolidation operation on the type of group corresponding to the lowest storage capacity.

[0092] Specifically, if a type of group has a lower storage capacity, it means that during the data writing operation, the physical units in this type of group are often written and / or the available capacity of the physical units in this type of group is running out. Therefore, during the data writing operation, the memory management circuit 51 can preferentially perform a foreground garbage collection operation on the type of group corresponding to the lowest storage capacity to maintain the performance of the memory storage device 10.

[0093] That is to say, if the storage capacities of these 2 types of groups are different, the memory management circuit 51 can perform a foreground garbage collection operation on the type of group with the lower storage capacity among these 2 types of groups to avoid unnecessary foreground garbage collection operations.

[0094] Or, the memory management circuit 51 can first perform a foreground garbage collection operation on the type of group with the lower storage capacity among these 2 types of groups, and then perform a foreground garbage collection operation on the other type of group among these 2 types of groups to maintain the performance of the memory storage device 10.

[0095] On the other hand, if the storage capacities of these 2 types of groups are the same, enter step S709.

[0096] In step S709, the memory management circuit 51 may calculate the execution efficiency of at least one group of at least one type.

[0097] Specifically, if the storage capabilities of these two groups are the same, the memory management circuit 51 may further use the execution efficiency of these two groups as a basis for determining whether to perform a garbage collection operation.

[0098] Furthermore, the execution efficiency of each group is used to characterize the number of physical units that can be released after performing a garbage collection operation on each group. The memory management circuit 51 may calculate the execution efficiency of these two groups and accordingly determine which of these two groups to prioritize for data consolidation operations.

[0099] It should be noted that during data write operations, since the usage amount, valid data amount, or invalid data amount of each group changes in real time, the execution efficiency of each group also changes in real time.

[0100] Next, in step S710, the memory management circuit 51 may determine whether at least one execution efficiency is the same.

[0101] Specifically, the memory management circuit 51 may determine whether the execution efficiency of these two groups is the same. If the execution efficiency of these two groups is different, it proceeds to step S711.

[0102] In step S711, the memory management circuit 51 may prioritize performing data consolidation operations on the group corresponding to the highest execution efficiency.

[0103] Specifically, the memory management circuit 51 may prioritize performing foreground garbage collection operations on the group with the higher execution efficiency among these two groups to avoid unnecessary foreground garbage collection operations.

[0104] Or, the memory management circuit 51 may first perform foreground garbage collection operations on the group with the higher execution efficiency among these two groups, and then perform foreground garbage collection operations on the other group among these two groups to maintain the performance of the memory storage device 10.

[0105] On the other hand, if the execution efficiency of these two groups is the same, it proceeds to step S712.

[0106] In step S712, the memory management circuit 51 may perform data consolidation operations according to at least one priority information of at least one group.

[0107] In an exemplary embodiment, each priority information is used to indicate the execution order of foreground garbage collection operations performed on each group in the case where the storage capabilities and execution efficiencies are the same. Specifically, each priority information includes fixed priority information and preset priority information.

[0108] In an exemplary embodiment, the fixed priority information is determined by the importance levels of multiple entity units in each group. Further elaborating, one or more entity units in each group may be, for example, one or more system entity units for storing management information, one or more mapping entity units for storing mapping table information, or one or more data entity units for storing user data. Among them, the importance level of the management information stored by the system entity units is higher than that of the mapping table information stored by the mapping entity units, and the importance level of the mapping table information is higher than that of the user data stored by the data entity units.

[0109] That is to say, the fixed priority information can be used to indicate that the foreground garbage collection operation for the group composed of one or more system entity units needs to be preferentially executed, then the foreground garbage collection operation for the group composed of one or more mapping entity units is executed, and finally the foreground garbage collection operation for the group composed of one or more data entity units is executed.

[0110] For example, assume that these two groups are respectively the group composed of one or more system entity units and the group composed of one or more data entity units. The memory management circuit 51 can preferentially execute the foreground garbage collection operation for the group composed of one or more system entity units to avoid unnecessary foreground garbage collection operations.

[0111] Or, the memory management circuit 51 can first execute the foreground garbage collection operation for one or more system entity units, and then execute the foreground garbage collection operation for the group composed of one or more data entity units to maintain the performance of the memory storage device 10.

[0112] In an exemplary embodiment, the preset priority information is determined by the usage urgency levels of multiple entity units in each group. Further elaborating, the memory management circuit 51 can set the preset priority information according to different actual usage scenarios.

[0113] For example, in a usage scenario where the amount of data (chunk size) written continuously at one time is relatively large, the memory management circuit 51 will continuously write a large amount of user data into the data entity units, and the consumption speed of the data entity units will be faster than that of the system entity units and the mapping entity units. Therefore, the preset priority information (control strategy) will be more biased towards the garbage collection operation executed for the data entity units to reduce the memory fragmentation problem and improve the utilization rate of the rewritable non-volatile memory module 43. In other words, the memory management circuit 51 can set a higher priority for the group composed of the data entity units to enhance the performance of the memory storage device 10.

[0114] For example, in a usage scenario where the amount of data written continuously in a single instance is small, the memory management circuit 51 will randomly write user data into data entity units. In the case of performing a random write operation, the consumption speed of mapped entity units will be faster than that of data entity units and system entity units. Therefore, the preset priority information (control policy) will be more inclined towards the garbage collection operation performed on mapped entity units to optimize the management of the mapping table, thereby reducing the fragmentation problem of the mapping table and improving the query efficiency of the mapping table. In other words, the memory management circuit 51 can set a higher priority for the group composed of mapped entity units to enhance the performance of the memory storage device 10.

[0115] According to the above, Figure 7 The storage control method provides a three-stage (i.e., storage capacity, execution efficiency, and priority information) judgment basis for the foreground garbage collection operation, and determines whether to perform data consolidation operations during the data write operation by matching the actual usage status of each group with the above three-stage judgment basis, which can avoid unnecessary foreground garbage collection operations and effectively improve the performance of the memory storage device 10. Additionally, Figure 7 The storage control method described above records the consumption capacity of each group and calculates the storage capacity of each group based on this, thereby optimizing the judgment basis for data consolidation operations from the original number of remaining available physical units (physical erasure units) to the number of remaining available physical programming units, which can effectively improve the accuracy and efficiency of data consolidation operations.

[0116] Figure 8 is a flowchart of the storage control method shown in an exemplary embodiment of the present invention. Please refer to Figure 8 the following operation process:

[0117] In step S801, during the execution of the data write operation, whenever a unit capacity of data is written, the consumption capacities of multiple groups are obtained.

[0118] In step S802, multiple storage capacities are generated based on the multiple consumption capacities.

[0119] In step S803, if at least one storage capacity is less than the threshold, a control policy is determined according to the multiple group information corresponding to the multiple groups to perform data consolidation operations, where the multiple group information includes the multiple storage capacities, multiple execution efficiencies, and multiple priority information of the multiple groups.

[0120] However, Figure 8 each step has been described in detail above and will not be elaborated here. It should be noted that Figure 8 each step can be implemented as multiple program codes or circuits, and the present invention does not limit this. Additionally,Figure 8 The method can be used in combination with the above embodiments or alone, and the present invention does not impose any restrictions thereon.

[0121] In summary, the storage control method and the memory storage device proposed by the exemplary embodiments of the present invention can monitor the actual usage status of various groups during the data writing operation to calculate the storage capacity of various groups, trigger a data consolidation operation when the storage capacity of at least one group is insufficient, and provide a three-stage (i.e., storage capacity, execution efficiency, and priority information) judgment basis for the data consolidation operation in the foreground state, which can avoid unnecessary data consolidation operations and thus effectively improve the performance of the memory storage device 10.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A storage control method, characterized in that, For a rewritable non-volatile memory module, the rewritable non-volatile memory module includes a plurality of groups, and each of the groups includes a plurality of physical units. The storage control method includes: During the execution of a data write operation, whenever a unit capacity of data is written, obtain the consumption capacities of the plurality of groups; Generate a plurality of storage capabilities based on the plurality of consumption capacities; and If at least one of the storage capabilities is less than a threshold, determine a control strategy according to the plurality of group information corresponding to the plurality of groups to perform a data consolidation operation, where the plurality of group information includes the plurality of storage capabilities, the plurality of execution efficiencies, and the plurality of priority information of the plurality of groups.

2. The storage control method according to claim 1, wherein the step of generating the plurality of storage capabilities based on the plurality of consumption capacities further includes: Calculate the plurality of storage capabilities according to the plurality of consumption capacities and the plurality of initial capacities of the plurality of groups, where the plurality of initial capacities are the capacities of the plurality of groups when the data write operation starts to be executed.

3. The storage control method according to claim 1, wherein the step of performing the data consolidation operation further includes: If the number of at least one of the groups corresponding to at least one of the storage capabilities is greater than 1, preferentially perform the data consolidation operation on the group corresponding to the lowest storage capability.

4. The storage control method according to claim 3, wherein the step of performing the data consolidation operation further includes: If the number is greater than 1 and at least one of the storage capabilities are the same, calculate the at least one execution efficiency of the at least one group; and Preferentially perform the data consolidation operation on the group corresponding to the highest execution efficiency.

5. The storage control method according to claim 4, wherein the step of performing the data consolidation operation further includes: If at least one of the execution efficiencies are the same, perform the data consolidation operation according to the at least one priority information of the at least one group.

6. The storage control method according to claim 5, wherein each of the priority information includes fixed priority information and preset priority information. The fixed priority information is determined by the importance level of the plurality of physical units in each of the groups, and the preset priority information is determined by the usage urgency of the plurality of physical units in each of the groups.

7. The storage control method according to claim 1, wherein the plurality of physical units in each of the groups are one of a system physical unit for storing management information, a mapping physical unit for storing mapping table information, and a data physical unit for storing user data.

8. A memory storage device, characterized in that, Including: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module including a plurality of groups, and each of the groups includes a plurality of physical units; and A memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module, where the memory control circuit unit is used to: During the process of performing a data writing operation, whenever a unit capacity of data is written, obtain the consumption capacities of the multiple groups; generate multiple storage capabilities based on the multiple consumption capacities, and if at least one of the storage capabilities is less than a threshold, determine a control policy according to multiple group information respectively corresponding to the multiple groups to perform a data consolidation operation, where the multiple group information includes the multiple storage capabilities, multiple execution efficiencies, and multiple priority information of the multiple groups.

9. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to calculate the multiple storage capabilities according to the multiple consumption capacities and the multiple initial capacities of the multiple groups, where the multiple initial capacities are the capacities of the multiple groups when the data writing operation starts to be executed.

10. The memory storage device according to claim 8, wherein if the number of at least one of the groups corresponding to at least one of the storage capabilities is greater than 1, the memory control circuit unit is further configured to preferentially perform the data consolidation operation on the group corresponding to the lowest storage capability.

11. The memory storage device according to claim 10, wherein if the number is greater than 1 and at least one of the storage capabilities are the same, the memory control circuit unit is further configured to calculate at least one of the execution efficiencies of at least one of the groups, and preferentially perform the data consolidation operation on the group corresponding to the highest execution efficiency.

12. The memory storage device according to claim 11, wherein if at least one of the execution efficiencies are the same, the memory control circuit unit is further configured to perform the data consolidation operation according to at least one of the priority information of at least one of the groups.

13. The memory storage device according to claim 12, wherein each of the priority information includes fixed priority information and preset priority information, the fixed priority information is determined by the importance degree of the multiple physical units in each of the groups, and the preset priority information is determined by the usage urgency degree of the multiple physical units in each of the groups.

14. The memory storage device according to claim 8, wherein the multiple physical units in each of the groups are one of a system physical unit for storing management information, a mapping physical unit for storing mapping table information, and a data physical unit for storing user data.

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