A dual-branch prediction BTB design method

Abstract

The application provides a novel double-branch prediction BTB structure, belonging to the technical field of BTB structure, and comprising the following steps: S1, an improved BTB structure design step, which comprises a multi-path group association structure link and a multi-target address storage link, and further comprises branch information association, each branch instruction is associated with a corresponding Tgt and a label field according to its position in an instruction block; S2, a BTB query and data reading step, which comprises an input PC processing link, a Tag matching and hit determination link and a data reading link; S3, a parallel branch prediction step, which comprises a branch predictor cooperative working link and a prediction result output link; in view of the problem that the traditional method can only predict a single branch or has limitations on the prediction of multiple branches, the application can generate at most two jump target addresses in the same period, thereby improving the branch prediction throughput.

Description

Technical Field

[0001] This invention relates to the field of BTB structure technology, and more specifically to a BTB design method based on bi-branch prediction. Background Technology

[0002] BTB: Branch Target Buffer is a cache used to store the target address of predicted branch instructions.

[0003] As processor microarchitectures continue to evolve, CPU issue width and pipeline depth are constantly increasing, placing higher demands on front-end fetch bandwidth. To reduce pipeline stalls caused by branch jumps, branch predictors typically need to provide the predicted location of the next instruction (PC) within a very short time. Traditional branch prediction units mostly support only one branch prediction per cycle, or can only predict two branches under very limited conditions. When the CPU needs to process multiple branches in the same cycle, if current technology cannot accurately and quickly provide the target address after consecutive branch jumps, it will reduce front-end fetch efficiency, thus affecting overall throughput.

[0004] Therefore, designing and optimizing a front-end branch prediction structure capable of handling two (or more) branch jumps within a single cycle has become one of the key technologies for improving the performance of high-end processors. This invention addresses this problem by proposing a novel hardware structure and method based on BTB (Border Branch Prediction). By improving the BTB data storage and multi-objective selection methods, it achieves parallel prediction for two conditional branches simultaneously, thus meeting the instruction fetch bandwidth requirements of wide-issue processors.

[0005] Current CPUs typically only predict one branch per cycle, or two branches, but this is limited by their application scenarios. As processor issue width and fetch bandwidth continue to increase, the need for predicting multiple branches per cycle is becoming increasingly prominent. However, conventional branch predictors and their corresponding branch target buffers (BTB) structures struggle to unconditionally support the generation of prediction targets for two jump instructions within a single cycle, resulting in underutilization of the front-end fetch unit's bandwidth and impacting overall processor performance.

[0006] The shortcomings of existing BTB technology:

[0007] 1. Limited to predicting only a single branch or multiple branches: Most processors only provide one jump prediction per cycle. If two consecutive conditional branches are encountered, additional cycles or logic are required for serial processing.

[0008] 2. Unable to truly achieve parallel prediction of two branches: Even if some architectures claim to support prediction of two branches, there are many limitations in the actual implementation, making it difficult to adapt to more common consecutive two-hop branches.

[0009] 3. Wasted front-end bandwidth: As the CPU issue width increases, if the front end cannot provide enough instruction streams to the back end at once, it will cause pipeline waiting and reduce processor throughput.

[0010] To address the aforementioned issues, this invention provides a novel BTB design that can predict two consecutive conditional branches within the same cycle and output the corresponding target address, thereby significantly improving the bandwidth utilization of the front-end instruction fetch unit and the overall performance of the processor.

[0011] This invention proposes a bi-branch prediction BTB design method to solve this problem. Summary of the Invention

[0012] The purpose of this invention is to unconditionally predict two conditional branches for jumps within a single cycle and provide the corresponding target addresses. By improving the BTB data structure, it can output multiple potential target addresses in the same query. Combined with a branch predictor, it simultaneously predicts whether two branches will jump, thereby quickly determining the next instruction fetch address. In terms of hardware structure, it realizes parallel prediction of "at most two conditional branches" to fully match the instruction fetch bandwidth of the wide-issue processor and reduce instruction starvation caused by insufficient branch prediction, thereby overcoming the problems in the background art.

[0013] Based on the above technical concept, the technical solution adopted by this invention is as follows:

[0014] A bi-branch prediction BTB design method includes the following steps:

[0015] S1 improves the BTB structure design steps, which include a multi-way group associative structure and a multi-target address storage step. It also includes branch information association, where each branch instruction is associated with the corresponding Tgt and tag field according to its position in the instruction block.

[0016] The S2BTB query and data reading steps include the input PC processing stage, the tag matching and hit judgment stage, and the data reading stage.

[0017] The S3 parallel branch prediction step includes a branch predictor collaborative work phase and a prediction result output phase.

[0018] The S4 target address selection logic step includes a multiplexer configuration stage and a dual FetchBlock generation stage. It also includes bandwidth matching, which meets the high instruction fetch bandwidth requirements of wide-issue processors by fetching two cache lines in parallel.

[0019] The S5 dynamic update and replacement strategy steps include the BTB entry update phase and the replacement strategy implementation phase.

[0020] The S6 exception handling and recovery steps include a predictive error recovery step and a miss handling step.

[0021] Further defining the above technical solution, the S1 improved BTB structure design step includes designing the BTB as a multi-way set-associative structure similar to a cache, with each group containing multiple channels, using the high-order bits of the program counter as the index value to determine the BTB group to be queried, and storing the high-order part of the PC of each BTB entry as a tag to match the input PC during the query.

[0022] Further defining the above technical solution, the S1 improved BTB structure design step, in which the multi-target address storage stage includes each BTB entry containing the following fields:

[0023] Tgt0, Tgt1, and Tgt2 store the predicted target addresses for different branch combinations, respectively.

[0024] Label 0, label 1, and label 2 identify the branch type;

[0025] The LRU field records recently used information and supports replacement algorithms.

[0026] Further defining the above technical solution, the S2BTB query and data reading step includes an input PC processing stage where the index fetching unit inputs the current PC value into the BTB, extracts the high-order bits of the PC as an index, and locates the target group in the BTB.

[0027] Further defining the above technical solution, the S2BTB query and data reading step includes a tag matching and hit determination step that involves parallel matching of the tag fields of all channels within the group with the high-order part of the input PC. If a tag matching entry exists, it is determined to be a BTB hit; otherwise, it is a miss.

[0028] Further defining the above technical solution, the S2BTB query and data reading step includes the following steps: when a match is found, reading Tgt0, Tgt1, Tgt2 and their corresponding tag information from the matched BTB entries; when a match is not found, using the default sequential address as the next fetch address.

[0029] Further defining the above technical solution, the S3 parallel branch prediction step includes a branch predictor and BTB working together within the same clock cycle to independently predict the jump results of two consecutive branches. Br0 corresponds to the first conditional branch in the instruction block, and Br1 corresponds to the second conditional branch. The prediction result is a binary combination representing the jump state of the two branches. The prediction result output step includes the branch predictor outputting the prediction results of Br0 and Br1 to the target address selection module.

[0030] Further defining the above technical solution, the S4 target address selection logic step includes a multiplexer configuration step that selects the corresponding target address based on the combination of Br0 and Br1:

[0031] No jump, select sequential address;

[0032] Tgt0 is selected as the next instruction fetch address;

[0033] Select Tgt1 as NextPC;

[0034] Select both Tgt1 and Tgt2 to generate two FetchBlock requests.

[0035] Further defining the above technical solution, the S4 target address selection logic step includes a dual FetchBlock generation process where, when both Br0 and Br1 are jumps (1,1), the instruction fetch unit simultaneously sends two requests to the instruction cache:

[0036] Request 1: An instruction block with Tgt1 as the target address;

[0037] Request 2: Instruction block with Tgt2 as the target address.

[0038] Further defining the above technical solution, the S5 dynamic update and replacement strategy step includes updating the BTB entry when the actual execution result of a branch is inconsistent with the prediction:

[0039] Add or replace entries: Select the channel to be replaced within the group according to the LRU policy;

[0040] Write the new Tag, Tgt, and tag information, overwriting the old data.

[0041] Compared with the prior art, the beneficial effects of the present invention are:

[0042] 1. Up to two jump target addresses can be generated within the same cycle, improving branch prediction throughput.

[0043] 2. It adopts a multi-way BTB structure similar to a cache, which is highly scalable and easy to adjust the indexing method and number of paths according to processor requirements.

[0044] 3. It can effectively reduce the latency caused by traditional serial branch prediction and improve the prediction accuracy and performance in high-concurrency branch scenarios. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a flowchart illustrating a bi-branch prediction BTB design method according to the present invention. Detailed Implementation

[0047] The following is in conjunction with the appendix Figure 1 The present invention will be described in further detail below.

[0048] Example 1: This example provides a BTB design method for bi-branch prediction, such as... Figure 1 As shown, it includes the following steps:

[0049] S1 improves the BTB structure design steps, which include a multi-way group associative structure and a multi-target address storage step. It also includes branch information association, where each branch instruction is associated with the corresponding Tgt and tag field according to its position in the instruction block.

[0050] The S2BTB query and data reading steps include the input PC processing stage, the tag matching and hit judgment stage, and the data reading stage.

[0051] The S3 parallel branch prediction step includes a branch predictor collaborative work phase and a prediction result output phase.

[0052] The S4 target address selection logic step includes a multiplexer configuration stage and a dual FetchBlock generation stage. It also includes bandwidth matching, which meets the high instruction fetch bandwidth requirements of wide-issue processors by fetching two cache lines in parallel.

[0053] The S5 dynamic update and replacement strategy steps include the BTB entry update phase and the replacement strategy implementation phase.

[0054] The S6 exception handling and recovery steps include a predictive error recovery step and a miss handling step.

[0055] S1 Improves the BTB structure design step. In this step, the multi-way set-associative structure component includes designing the BTB as a cache-like multi-way set-associative structure. Each group contains multiple channels. The high-order bits of the program counter are used as index values ​​to determine the BTB group to be queried. Each BTB entry stores the high-order part of the PC as a tag, which is used to match the input PC during the query.

[0056] S1 improves the BTB structure design step, in which the multi-target address storage stage includes each BTB table entry containing the following fields:

[0057] Tgt0, Tgt1, and Tgt2 store the predicted target addresses for different branch combinations, respectively.

[0058] Label 0, label 1, and label 2 identify the branch type;

[0059] The LRU field records recently used information and supports replacement algorithms.

[0060] The S2BTB query and data reading steps include the input PC processing step, which involves the instruction fetching unit inputting the current PC value into the BTB, extracting the high-order bits of the PC as an index, and locating the target group in the BTB.

[0061] The S2BTB query and data reading steps include a tag matching and hit determination step. This step involves parallel matching of the tag fields of all channels in the group with the high-order part of the input PC. If a tag matching entry exists, it is determined to be a BTB hit; otherwise, it is a miss.

[0062] The S2BTB query and data reading steps include the following steps: when a match is found, Tgt0, Tgt1, Tgt2 and their corresponding tag information are read from the matched BTB entries; when a match is not found, the default sequential address (PC + instruction block length) is used as the next instruction fetch address.

[0063] The S3 parallel branch prediction step involves the branch predictor and BTB working together within the same clock cycle to independently predict the jump results of two consecutive branches. Br0 corresponds to the first conditional branch in the instruction block, and Br1 corresponds to the second conditional branch. The prediction result is a binary combination representing the jump status of the two branches. The prediction result output step includes the branch predictor outputting the prediction results of Br0 and Br1 to the target address selection module.

[0064] The S4 target address selection logic step includes a multiplexer configuration step that selects the corresponding target address based on the combination of Br0 and Br1:

[0065] No jump, select sequential address;

[0066] Tgt0 is selected as the next instruction fetch address;

[0067] Select Tgt1 as NextPC;

[0068] Select both Tgt1 and Tgt2 to generate two FetchBlock requests.

[0069] The S4 target address selection logic step, in which the double FetchBlock generation process includes, when both Br0 and Br1 are jumps (1,1), the instruction fetch unit simultaneously sends two requests to the instruction cache:

[0070] Request 1: An instruction block with Tgt1 as the target address;

[0071] Request 2: Instruction block with Tgt2 as the target address.

[0072] The S5 dynamic update and replacement strategy steps include updating BTB entries when the actual execution result of a branch is inconsistent with the prediction.

[0073] Add or replace entries: Select the channel to be replaced within the group according to the LRU policy;

[0074] Write the new Tag, Tgt, and tag information, overwriting the old data.

[0075] The S5 dynamic update and replacement strategy steps include updating the LRU counter each time the BTB is accessed, marking the most recently used item, and selecting the item with the largest LRU value in the group for replacement when replacement is needed.

[0076] The S6 exception handling and recovery steps include prediction error recovery, which involves clearing the pipeline and re-fetching instructions from the correct address if the actual branch result does not match the prediction, and the BTB correcting the entry content according to the actual branch result; the miss handling step includes sequentially fetching instructions and monitoring branch instructions when the BTB misses, and dynamically inserting the information of the new branch instruction into the BTB after detecting it.

[0077] This method achieves zero additional latency through hardware parallelization by using single-cycle dual-branch prediction; the dual FetchBlock mechanism makes full use of ICache bandwidth to avoid pipeline starvation; the number of paths and index bit width of BTB can be adjusted to adapt to different processor scales.

[0078] Example 2: This example provides a BTB design method for bi-branch prediction, such as... Figure 1 As shown, structural improvements to the BTB are also included:

[0079] Cache-like organization: This invention designs the BTB as a cache-like structure, using a portion of the high-order bits of the PC (e.g., bit 5 and above) as an index, while storing multiple branch information in each entry. Each index has multiple channels, such as 4-way, to facilitate high-parallelism storage and retrieval.

[0080] Multi-destination address storage: In each BTB table entry, the storage includes:

[0081] Tag: Used to match the input PC (or its high-order part).

[0082] Src0, Src1, Src2: Record the source information corresponding to this branch, or additional information required for a specific branch type.

[0083] Tgt0, Tgt1, Tgt2: These correspond to the target addresses under different branch prediction combinations.

[0084] Label 0, Label 1, Label 2: Can be used to distinguish the type of branch (conditional / unconditional / call / return, etc.) or other control information.

[0085] LRU: Records the information required by the replacement strategy (or other replacement algorithm).

[0086] Two-branch prediction adaptation: To adapt the prediction of two consecutive conditional branches, a single BTB lookup can obtain three target addresses (tgt0, tgt1, tgt2). The branch predictor simultaneously provides taken / not-taken combinations of two branches (Br0 and Br1). The next instruction fetch address (Next PC) is selected from tgt0, tgt1, and tgt2 through a simple multiplexer (MUX).

[0087] Branch prediction process:

[0088] BTB lookup: The PC generated by the instruction fetch unit searches for the BTB by comparing the index and tag. If a match is found, tgt0, tgt1, and tgt2 are read. If a match is not found, the default instruction fetch address order is used.

[0089] Branch predictor output: Within the same period, the branch predictor provides the prediction results of Br0 and Br1 in parallel. For example, (Br0=1, Br1=0) indicates that the first branch jumps and the second branch does not jump.

[0090] Target address selection:

[0091] (Br0=0, Br1=0) → indicates no jump, continue to the next sequential address.

[0092] (Br0=0, Br1=1) → Select tgt0

[0093] (Br0=1, Br1=0) → Select tgt1

[0094] (Br0=1, Br1=1) → Select tgt1 and tgt2

[0095] Dual Fetch Block Construction: Since two branches can be predicted in the same cycle, this invention can issue two possible fetch requests at the same time to meet the needs of wide-issue processors to fetch multiple cachelines at once, thereby improving front-end throughput.

[0096] This improved embodiment supports parallel prediction of a single cycle and two branches: by storing multi-target branch paths in the BTB, the next or next two fetch addresses are given at once in conjunction with the dual-branch prediction results; the BTB's multi-way parallel query structure: using a multi-way organization method similar to the cache, different branch paths are stored; high fetch bandwidth matching for wide-issue CPUs: dual-way fetch requests can be generated on the hardware, thereby truly leveraging the advantages of multi-issue pipelines.

[0097] It can truly achieve parallel prediction of two branches: for continuous conditional branches, it can output two jump target addresses without additional logic or delay; the instruction fetch bandwidth is significantly improved: it greatly increases the number of instructions fetched by the front end at one time, matching or exceeding the instruction throughput requirements of a wide issue pipeline; it has strong scalability: it adopts a BTB with a cache-like structure, and the number of paths and index bit width can be flexibly configured according to the processor scale; the hardware cost is controllable: it expands on the basis of retaining the basic functions of the original BTB, and the impact on chip area and power consumption is relatively acceptable.

[0098] Example 3: This example provides a BTB design method for bi-branch prediction, such as... Figure 1 As shown, an improvement is also provided for embodiment 2:

[0099] In terms of implementation, the number or logic of tgt0, tgt1, and tgt2 can be expanded or simplified. For example, it can be designed to predict only one conditional branch and one unconditional jump, or more target addresses can be added to support more complex branching scenarios.

[0100] By expanding the way, branch paths for records can be added.

[0101] Improvements to the indexing algorithm allow for the use of more complex hash algorithms to calculate the index.

[0102] If only single-branch jumps need to be predicted, this scheme can be degraded and still retain the advantages of high hit rate and flexible update mechanism.

[0103] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention, enabling those skilled in the art to understand and apply the invention. However, it should not be construed that the specific implementation of the invention is limited to these descriptions.

Claims

1. A bi-branch prediction BTB design method, characterized in that, Includes the following steps: S1, Improved BTB structure design steps. S1 includes a multi-way group associative structure design stage and a multi-target address storage stage. S1 also includes branch information association. Each branch instruction is associated with the corresponding Tgt and tag field according to its position in the instruction block. S2, BTB query and data reading steps, S2 includes input PC processing, tag matching and hit judgment and data reading; S3, Parallel branch prediction step, includes the branch predictor collaborative work step and the prediction result output step; S4, the target address selection logic step, includes a multiplexer configuration stage and a dual FetchBlock generation stage. S4 also includes bandwidth matching, which meets the high instruction fetch bandwidth requirements of wide-issue processors by fetching two cachelines in parallel. S5, Dynamic Update and Replacement Strategy Steps, S5 includes the BTB entry update step and the replacement strategy implementation step; S6, Error Handling and Recovery Steps, S6 includes the error prediction recovery step and the miss handling step; In S1, the design of the multi-group associative structure includes designing the BTB as a cache-like multi-group associative structure, with each group containing multiple channels. The high-order bits of the program counter are used as the index value to determine the BTB group to be queried. Each BTB entry stores the high-order part of the PC as a Tag to match the input PC during the query. In S2, the tag matching and hit determination step includes parallel matching of the tag field of all channels in the group and the high-order part of the input PC. If there is a tag matching entry, it is determined to be a BTB hit; otherwise, it is a miss. In S2, the data reading step includes, when a match is found, reading Tgt0, Tgt1, Tgt2 and their corresponding tag information from the matched BTB entries; when a match is not found, using the default sequential address as the next fetch address.

2. The BTB design method for bi-branch prediction according to claim 1, characterized in that, In step S1, the multi-target address storage stage includes each BTB table entry containing the following fields: Tgt0, Tgt1, and Tgt2 store the predicted target addresses for different branch combinations, respectively. Label 0, label 1, and label 2 identify the branch type; The LRU field records recently used information and supports replacement algorithms.

3. The BTB design method for bi-branch prediction according to claim 2, characterized in that, In S2, the input PC processing step includes an instruction fetching unit that inputs the current PC value into BTB, extracts the high-order bits of PC as an index, and locates the target group in BTB.

4. The BTB design method for bi-branch prediction according to claim 3, characterized in that, In S3, the branch predictor collaborative operation includes the branch predictor and BTB working in the same clock cycle, independently predicting the jump results of two consecutive branches. Br0 corresponds to the first conditional branch in the instruction block, and Br1 corresponds to the second conditional branch. The prediction result is a binary combination representing the jump state of the two branches. The prediction result output stage includes the branch predictor outputting the prediction results of Br0 and Br1 to the target address selection module.

5. The BTB design method for bi-branch prediction according to claim 4, characterized in that, In step S4, the multiplexer configuration step includes selecting the corresponding target address based on the combination of Br0 and Br1: No jump, select sequential address; Tgt0 is selected as the next instruction fetch address; Select Tgt1 as NextPC; Select both Tgt1 and Tgt2 to generate two FetchBlock requests.

6. The BTB design method for bi-branch prediction according to claim 5, characterized in that, In S4, the dual FetchBlock generation process includes, when both Br0 and Br1 are jump addresses 1, the instruction fetch unit simultaneously sends two requests to the instruction cache: Request 1: An instruction block with Tgt1 as the target address; Request 2: Instruction block with Tgt2 as the target address.

7. The BTB design method for bi-branch prediction according to claim 6, characterized in that, In S5, the BTB entry update step includes updating the BTB entry when the actual execution result of the branch is inconsistent with the prediction: Add or replace entries: Select the channel to be replaced within the group according to the LRU policy; Write the new Tag, Tgt, and tag information, overwriting the old data.

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