Memory processing method and device, electronic equipment and storage medium
By allocating large amounts of memory and updating cached data addresses, the problem of low query performance of virtual machines during interpretation of code execution is solved, and the execution efficiency of the interpreter is improved.
Patent Information
- Application Number
- CN202410045023.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-11
- Publication Date
- 2025-07-11
AI Technical Summary
During the interpretation of code execution, the virtual machine frequently searches for memory variable information lead to low query performance and cannot effectively utilize cached data.
By allocating target memory that is larger than the original memory capacity, updating the cached data memory address managed by the virtual machine, and copying the cached data to the target memory, determining the location information of the cached data in the target memory.
It improves the query success rate of virtual machines during the interpretation of code execution and increases the execution efficiency of interpreter.
Smart Images
Figure CN120295747A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to computer technologies, and in particular, to a memory processing method, apparatus, electronic device, and storage medium. Background Art
[0002] An application project refers to a software project developed to achieve specific functions or goals. In an application project, to improve the performance of an App, it is necessary to improve the performance of a virtual machine. And the virtual machine interprets and executes most code using an interpreter. During the process of interpreting and executing code by the virtual machine, it is necessary to continuously search for information of memory variables, and this search process is generally time-consuming.
[0003] To improve the query performance, information of memory variables is cached, but in most cases, there is still a situation where the required information cannot be found in the cache, resulting in low execution efficiency of the interpreter. Summary of the Invention
[0004] The present disclosure provides a memory processing method, apparatus, electronic device, and storage medium to improve the success rate of querying during the process of interpreting and executing code by a virtual machine.
[0005] In a first aspect, embodiments of the present disclosure provide a memory processing method, including:
[0006] Allocating a target memory of a set size through a memory block allocation function of a memory allocation class;
[0007] Updating the memory address of the cache data managed by the virtual machine;
[0008] Copying the cache data stored in the original memory to the target memory, where the capacity of the original memory is smaller than that of the target memory;
[0009] Determining the position information of the cache data in the target memory.
[0010] In a second aspect, embodiments of the present disclosure further provide a memory processing apparatus, including:
[0011] An allocation module, configured to allocate a target memory of a set size through a memory block allocation function of a memory allocation class;
[0012] A first update module, configured to update the memory address of the cache data managed by the virtual machine;
[0013] A copy module, configured to copy the cache data stored in the original memory to the target memory, where the capacity of the original memory is smaller than that of the target memory;
[0014] A second update module, configured to determine the position information of the cache data in the target memory.
[0015] In a third aspect, embodiments of the present disclosure further provide an electronic device, where the electronic device includes:
[0016] One or more processing devices;
[0017] A storage device for storing one or more programs,
[0018] When the one or more programs are executed by the one or more processing devices, the one or more processing devices implement the memory processing method provided by the present disclosure.
[0019] In a fourth aspect, embodiments of the present disclosure further provide a storage medium containing computer-executable instructions, and the computer-executable instructions are used to execute the memory processing method provided by the present disclosure when executed by a computer processor.
[0020] In the embodiments of the present disclosure, a target memory of a set size is allocated through a memory block allocation function of a memory allocation class; the memory address of the cache data managed by the virtual machine is updated; the cache data stored in the original memory is copied to the target memory, and the capacity of the original memory is smaller than the capacity of the target memory; the position information of the cache data in the target memory is determined. The problem of being unable to query the required information in the cache is solved. By allocating a target memory larger than the capacity of the original memory and storing the cache data in the target memory, the success rate of querying during the process of the virtual machine interpreting and executing code is improved, and the execution efficiency of the interpreter is increased. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In combination with the accompanying drawings and with reference to the following specific embodiments, the above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic, and the original and elements are not necessarily drawn to scale.
[0022] Figure 1 is a flowchart of a memory processing method provided by an embodiment of the present disclosure;
[0023] Figure 2 is a flowchart of another memory processing method provided by an embodiment of the present disclosure;
[0024] Figure 3 is a schematic diagram of a cache data copying process provided by an embodiment of the present disclosure;
[0025] Figure 4 is a schematic diagram of the structure of a memory processing device provided by an embodiment of the present disclosure;
[0026] Figure 5It is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. Detailed implementation manners
[0027] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not used to limit the protection scope of the present disclosure.
[0028] It should be understood that the various steps recorded in the method embodiments of the present disclosure can be executed in different orders and / or executed in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this regard.
[0029] As used herein, the term "including" and its variations are open-ended, that is, "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.
[0030] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order of functions executed by these devices, modules or units or their interdependent relationships.
[0031] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly stated in the context, it should be understood as "one or more".
[0032] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only for illustrative purposes and are not used to limit the scope of these messages or information.
[0033] Figure 1 It is a schematic flowchart of a memory processing method provided by an embodiment of the present disclosure. The embodiments of the present disclosure are applicable to the situation of processing memory. This method can be executed by a memory processing device, which can be implemented in the form of software and / or hardware. Optionally, it can be implemented by an electronic device, which can be a mobile terminal, a PC or a server, etc.
[0034] As Figure 1 shown, the method includes:
[0035] S110. Allocate a target memory of a set size through a memory block allocation function of a memory allocation class.
[0036] The memory allocation class can be considered as a class for implementing memory allocation, such as the LinearAlloc class. The LinearAlloc class is a class for memory allocation that provides a way to allocate memory linearly. The memory block allocation function can be a function for implementing memory block allocation, such as the Alloc function. The Alloc function is a member function of the LinearAlloc class and is used to allocate a memory block of a specified size. The set size can be a pre-set size, and the set size is not limited here. The target memory can be a re-allocated memory for storing cached data, such as caching memory variables managed by a virtual machine.
[0037] This operation can allocate a target memory of a set size through a memory block allocation function. For example, by calling the memory block allocation function to allocate a target memory of a set size through the memory block allocation function.
[0038] The means of calling is not limited. For example, it can be called through the address of the memory block allocation function. Also, if the memory block allocation function is an exported function, the exported function can be exported to implement the call to the exported function (such as exporting the Alloc function of the LinearAlloc class and calling the Alloc function to allocate a cached memory of 4096 sizes, that is, the target memory). The exported function can have special symbols or identifiers to indicate that they can be used by other modules or code. The symbol identifying the exported function can indicate to the compiler or linker that the corresponding exported function can be called by external code.
[0039] During the process of interpreting and executing code by the Android Run Time (ART) virtual machine, it is necessary to continuously search for information on memory variables such as class method objects (i.e., ArtMethod) and class member variable objects (i.e., ArtField). This search process is generally time-consuming. To improve the search performance, the virtual machine uses an object of a cached data class (i.e., the DexCache class) to manage the cache of this information, that is, the cached data. However, the virtual machine only caches 1024 objects by default. For large Apps, in most cases, the cache cannot be hit, so the execution efficiency of the interpreter is low. To optimize this problem, the present disclosure allocates a target memory to modify the cache capacity and increase the probability of cache hit. Among them, the cached data class can be considered as a class for implementing cached data management.
[0040] In Android, the virtual machine is a program used to execute and run applications. It contains an interpreter for interpreting and executing Dex bytecode. In Android development, Dex is an abbreviation for Dalvik Executable, which is an intermediate format that converts Java bytecode (also known as Java bytecode) into an executable format for the Dalvik virtual machine (VM).
[0041] The cache data class can manage the cache. The cache data class stores relevant information about the loaded Dex files in the cache, including the path, hash value, loading time, etc. of the Dex files. When the application starts again, if the same Dex file needs to be loaded, the system can directly obtain the relevant information from the cache data class without parsing the Dex file again, thereby improving the startup speed.
[0042] S120. Update the memory address of the cache data managed by the virtual machine.
[0043] The cache data managed by the virtual machine can be the data cached for interpreting and executing code during the process of the virtual machine interpreting and executing code. For example, the virtual machine uses an object of the cache data class (i.e., the DexCache class) to manage the cache for querying.
[0044] In this embodiment, since the target memory is allocated, for the convenience of managing the cache data, the memory address of the cache data can be updated. For example, the address indicating the memory where the cache data is located can be updated.
[0045] S130. Copy the cache data stored in the original memory to the target memory.
[0046] The capacity of the original memory is smaller than the capacity of the target memory, realizing the expansion of the memory by allocating the target memory. The amount of cache data that can be stored after the expansion will increase. Furthermore, during the process of the virtual machine interpreting and executing code, the query hit rate can be improved, increasing the execution efficiency of the interpreter.
[0047] The original memory can be considered as the memory where the cache data is originally stored. The cache data can be transferred from the original memory to the target memory to realize copying the old cached data to the new memory address.
[0048] In this operation, when copying the cache data, the cache data can be copied at least one copy to the target memory.
[0049] S140. Determine the location information of the cache data in the target memory.
[0050] The location information can indicate the location of the cache data in the target memory. Since the cache data is transferred to the target memory, this operation needs to determine the location information of the cache data in the target memory.
[0051] When determining the location information of cached data in the target memory, this operation can determine the location of the cached data in the target memory based on the size of the target memory. For example, the location information of the cached data in the target memory can be determined according to the size of the target memory and the index position of the cached data in the bytecode.
[0052] After determining the location information of the cached data in the target memory, all the location information of the cached data in the machine code in the target memory can be modified. For example, the original location information of the cached data stored in the machine code in the original memory can be modified to the location information of the cached data in the target memory in this embodiment. Calculate the index of the cached data in the memory.
[0053] The technical solution of the embodiment of the present disclosure allocates a target memory of a set size through a memory block allocation function of the memory allocation class; updates the memory address of the cached data managed by the virtual machine; copies the cached data stored in the original memory to the target memory, where the capacity of the original memory is smaller than the capacity of the target memory; determines the location information of the cached data in the target memory. It solves the problem that the required information cannot be queried in the cache. By allocating a target memory larger than the capacity of the original memory and storing the cached data in the target memory, the success rate of querying during the process of the virtual machine interpreting and executing code is improved, and the execution efficiency of the interpreter is increased.
[0054] Based on the above embodiment, a variant embodiment of the above embodiment is proposed. Here, it should be noted that for the sake of brief description, only the differences from the above embodiment are described in the variant embodiment.
[0055] In one embodiment, the updating the memory address of the cached data managed by the virtual machine includes:
[0056] Updating the member variables of the cached data class in the Java layer to the address of the target memory.
[0057] After allocating the target memory, this embodiment can update the memory address based on the address of the target memory. For example, the member variables of the cached data class in the Java layer are modified to the address of the newly allocated target memory through reflection.
[0058] When updating the member variables in this embodiment, the member variables of the cached data class can be directly modified to the address of the target memory, or the member variables of the cached data class can be indirectly modified to the address of the target memory. When indirectly modifying to the address of the target memory, the member variables can be modified to the native layer address, and the native layer address can indicate the location in the native layer where the address of the target memory is stored.
[0059] In one embodiment, updating the member variable of the cache data class in the Java layer to the address of the target memory includes:
[0060] Updating the member variable of the cache data class in the Java layer to the native layer address, where the address of the target memory is stored at the position corresponding to the native layer address.
[0061] In this embodiment, when updating the member variable of the cache data class, the mapping of the target memory address can be achieved through the native layer address. The member variable is updated to the native layer address, such as the starting address of an array in the native layer that stores the address of the target memory, and then based on the address of the target memory stored at the position indicated by the native layer address, the update of the member variable of the cache data class in the Java layer is realized.
[0062] The member variable of the cache data class can be a parsing field, such as resolveFields.
[0063] In one embodiment, determining the position information of the cache data in the target memory includes:
[0064] Setting the memory size to the size of the target memory;
[0065] Based on the memory size and the index position of the cache data in the bytecode, determining the position information of the cache data in the target memory.
[0066] The memory size can be a parameter used to determine the position information of the cache data in the target memory. In this embodiment, the memory size is set to the size of the target memory to realize determining the position information of the cache data in the target memory based on the size of the target memory. The index position in the bytecode usually refers to the offset or index value in the bytecode instruction. Each bytecode instruction has a fixed length, usually one byte or multiple bytes. In the bytecode instruction, the index position may be used to represent the position of the data.
[0067] The position of the cache data in the original memory is determined based on the index position of the cache data in the bytecode and the size of the original memory. After replacing the original memory with the target memory, the size of the original memory can be replaced with the size of the target memory to determine the position information of the cache data in the target memory.
[0068] In this embodiment, the position information of the cache data in the target memory can be determined by the index position of the cache data in the bytecode % the size of the target memory. The position information in the target memory can also be represented by an index identifier, which is not limited here.
[0069] In one embodiment, the target memory is a continuous memory block, and the size of the target memory is a multiple of a set value of the size of the original memory.
[0070] To improve the search efficiency, the target memory allocated in this embodiment is a continuous memory block. And the size of the target memory is a multiple of a set value of the size of the original memory. The set value is not limited here, for example, it can be 2.
[0071] Figure 2 It is a flowchart of another memory processing method provided by an embodiment of the present disclosure. In this embodiment, the operation of copying cached data is refined, such as Figure 2 As shown, the memory processing method includes the following steps:
[0072] S210. Allocate a target memory of a set size through the memory block allocation function of the memory allocation class.
[0073] S220. Update the memory address of the cached data managed by the virtual machine.
[0074] S230. Copy at least two copies of the cached data stored in the original memory to the target memory.
[0075] In this embodiment, the means of copying cached data is refined. In this embodiment, at least two copies of the cached data are copied to the target memory. The order between each copy of the cached data can remain unchanged, and each copy of the cached data can be adjacent. Start copying the next copy of the cached data at the first position after a copy of the cached data.
[0076] In this embodiment, multiple copies of the cached data are copied to the target memory, so that multiple copies of the cached data are stored on the target memory, which improves the hit rate of data query during the process of the virtual machine interpreting and executing code.
[0077] Multiple copies of the cached data can be copied to the target memory sequentially or simultaneously. When there is newly added cached data, the repeated cached data can be replaced with the newly added cached data.
[0078] S240. Determine the position information of the cached data in the target memory.
[0079] This embodiment refines the operation of copying cached data. By copying multiple copies of the cached data to the target memory, the hit rate of the virtual machine querying cached data is further improved.
[0080] Based on the above embodiment, a variant embodiment of the above embodiment is proposed. Here, it should be noted that in order to make the description brief, only the differences from the above embodiment are described in the variant embodiment.
[0081] In one embodiment, the memory processing method further includes:
[0082] Store the increased cached data at the position of the non-first copy of the cached data in the target memory.
[0083] The non-first cached data can be the cached data in the target memory except for the first cached data. The non-first cached data is the data that is repeatedly stored. When there is new cached data, the non-first cached data will be replaced to store the increased cached data. The first cached data can be the cached data stored starting from the first address of the target memory.
[0084] Figure 3 It is a schematic diagram of a cached data copy process provided by an embodiment of the present disclosure. Refer to Figure 3 , the original memory may include cached data 0, cached data 1... cached data 1023, a total of 1024 cached data are shown in Figure 3 the first row. 1024 cached data can be copied four times to the target memory. When adding cached data, the added cached data can be stored at the position where the bold rectangle is located.
[0085] In a large Android App project, in order to improve the performance of the App, it is necessary to find a way to improve the performance of the virtual machine. And the virtual machine interprets and executes most of the code using an interpreter. Therefore, the present disclosure improves the performance of the Android ART virtual machine by expanding the DexCache capacity.
[0086] Figure 4 It is a schematic structural diagram of a memory processing device provided by an embodiment of the present disclosure. The memory processing device is integrated in an electronic device. The device includes:
[0087] An allocation module 410, configured to allocate a target memory of a set size through a memory block allocation function of a memory allocation class;
[0088] A first update module 420, configured to update the memory address of the cached data managed by the virtual machine;
[0089] A copy module 430, configured to copy the cached data stored in the original memory to the target memory, where the capacity of the original memory is smaller than the capacity of the target memory;
[0090] A second update module 440, configured to determine the position information of the cached data in the target memory.
[0091] The technical solution provided by the embodiment of the present disclosure solves the problem that the required information cannot be queried in the cache. By allocating a target memory larger than the capacity of the original memory and storing the cached data in the target memory, the success rate of querying during the process of the virtual machine interpreting and executing code is improved, and the execution efficiency of the interpreter is increased.
[0092] In one embodiment, the first update module 420 includes:
[0093] An update unit, configured to update a member variable of a cache data class in the Java layer to the address of the target memory.
[0094] In one embodiment, the update unit is specifically configured to:
[0095] Update a member variable of a cache data class in the Java layer to a native layer address, where the address of the target memory is stored at a position corresponding to the native layer address.
[0096] In one embodiment, the copy module 430 is specifically configured to:
[0097] Copy at least two copies of the cache data stored in the original memory to the target memory.
[0098] In one embodiment, the memory management device further includes: an adding module, configured to:
[0099] Store the added cache data at a position other than the first cache data in the target memory.
[0100] In one embodiment, the second update module 440 is specifically configured to:
[0101] Set the memory size to the size of the target memory;
[0102] Determine the position information of the cache data in the target memory based on the memory size and the index position of the cache data in the bytecode.
[0103] In one embodiment, the target memory is a continuous memory block, and the size of the target memory is a multiple of a set value of the size of the original memory.
[0104] The memory processing device provided by the embodiments of the present disclosure can execute the memory processing method provided by any embodiment of the present disclosure, and has functional modules and beneficial effects corresponding to the execution of the method.
[0105] It should be noted that the various units and modules included in the above device are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be realized; in addition, the specific names of the functional units are only for the convenience of mutual distinction, and are not used to limit the protection scope of the embodiments of the present disclosure.
[0106] Figure 5 It is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. Next, refer to Figure 5 , which shows a schematic structural diagram of an electronic device (such as Figure 5 the terminal device or server in) 500 suitable for implementing the embodiments of the present disclosure.
[0107] Electronic device 500
[0108] One or more processing devices 501;
[0109] A storage device 508 for storing one or more programs,
[0110] When the one or more programs are executed by the one or more processing devices 501, the one or more processing devices 501 implement the memory processing method provided in this disclosure.
[0111] The terminal device in the embodiments of this disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 5 The illustrated electronic device is merely an example and should not impose any limitation on the functions and usage scope of the embodiments of this disclosure.
[0112] As Figure 5 As shown, the electronic device 500 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 501, which may perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 502 or the program loaded from the storage device 508 into the random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the electronic device 500 are also stored. The processing device 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. The editing / output (I / O) interface 505 is also connected to the bus 504.
[0113] Generally, the following devices may be connected to the I / O interface 505: an input device 506 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 508 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 509. The communication device 509 may allow the electronic device 500 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 5 The electronic device 500 with various devices is shown, but it should be understood that it is not required to implement or include all the shown devices. More or fewer devices may be alternatively implemented or included.
[0114] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product that includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program code for performing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 509, or installed from a storage device 508, or installed from a ROM 502. When the computer program is executed by a processing device 501, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.
[0115] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only for illustrative purposes and are not used to limit the scope of these messages or information.
[0116] The electronic device provided in the embodiment of the present disclosure and the memory processing method provided in the above embodiment belong to the same inventive concept. Technical details not described in detail in this embodiment can be referred to in the above embodiment, and this embodiment has the same beneficial effects as the above embodiment.
[0117] An embodiment of the present disclosure provides a computer storage medium, on which a computer program is stored, and when the program is executed by a processor, the memory processing method provided in the above embodiment is implemented.
[0118] It should be noted that the above-mentioned computer-readable medium in the present disclosure can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two.
[0119] The computer storage medium can be a storage medium for computer-executable instructions, and the computer-executable instructions are used to execute the method provided by the present disclosure when executed by a computer processor.
[0120] A computer-readable storage medium may, for example, but is not limited to: an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present disclosure, the computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium, and the computer-readable signal medium can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.
[0121] In some embodiments, the client and the server can communicate using any currently known or future-developed network protocol such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communication in any form or medium (e.g., a communication network). Examples of the communication network include a local area network (“LAN”), a wide area network (“WAN”), the Internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future-developed network.
[0122] The above computer-readable medium may be included in the above electronic device; or may exist separately without being assembled into the electronic device.
[0123] The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by the electronic device, the electronic device is caused to:
[0124] The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by the electronic device, the electronic device is caused to: allocate a target memory of a set size through a memory block allocation function of the memory allocation class;
[0125] Update the memory address of the cached data managed by the virtual machine;
[0126] Copy the cached data stored in the original memory to the target memory, where the capacity of the original memory is smaller than that of the target memory;
[0127] Determine the position information of the cached data in the target memory.
[0128] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages or combinations thereof. The above-mentioned programming languages include, but are not limited to, object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., by connecting through the Internet using an Internet service provider).
[0129] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.
[0130] The modules or units involved in the embodiments of the present disclosure may be implemented in software or in hardware. Among them, the name of the module or unit does not constitute a limitation to the unit itself in some cases. For example, the allocation module may also be described as the "target memory allocation module".
[0131] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), Systems on Chip (SOCs), Complex Programmable Logic Devices (CPLDs), and so on.
[0132] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include electrical connections based on one or more wires, portable computer disks, hard disks, Random Access Memory (RAM), Read Only Memory (ROM), Erasable Programmable Read Only Memory (EPROM or flash memory), optical fibers, portable compact disc read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0133] According to one or more embodiments of the present disclosure, [Example 1] provides a memory processing method, including:
[0134] Allocating a target memory of a set size through a memory block allocation function of a memory allocation class;
[0135] Updating the memory address of the cache data managed by the virtual machine;
[0136] Copying the cache data stored in the original memory to the target memory, where the capacity of the original memory is less than the capacity of the target memory;
[0137] Determining the location information of the cache data in the target memory.
[0138] According to one or more embodiments of the present disclosure, [Example 2] provides the method described in Example 1, where the updating the memory address of the cache data managed by the virtual machine includes:
[0139] Updating the member variable of the cache data class in the Java layer to the address of the target memory.
[0140] According to one or more embodiments of the present disclosure, [Example 3] provides the method described in Example 2, where the updating the member variable of the cache data class in the Java layer to the address of the target memory includes:
[0141] Update the member variables of the cache data class in the Java layer to the native layer address, and store the address of the target memory at the position corresponding to the native layer address.
[0142] According to one or more embodiments of the present disclosure, [Example 4] provides the method described in Example 1, and the copying the cache data stored in the original memory to the target memory includes:
[0143] Copy at least two copies of the cache data stored in the original memory to the target memory.
[0144] According to one or more embodiments of the present disclosure, [Example 5] provides the method described in Example 4, and further includes:
[0145] Store the additional cache data at the position where the non-first cache data is located in the target memory.
[0146] According to one or more embodiments of the present disclosure, [Example 6] provides the method described in Example 1, and the determining the position information of the cache data in the target memory includes:
[0147] Set the memory size to the size of the target memory;
[0148] Based on the memory size and the index position of the cache data in the bytecode, determine the position information of the cache data in the target memory.
[0149] According to one or more embodiments of the present disclosure, [Example 7] provides the method described in Example 1, the target memory is a continuous memory block, and the size of the target memory is a multiple of a set value of the size of the original memory.
[0150] According to one or more embodiments of the present disclosure, [Example 8] provides a memory processing device, including:
[0151] An allocation module, configured to allocate a target memory with a set size through a memory block allocation function of a memory allocation class;
[0152] A first update module, configured to update the memory address of the cache data managed by the virtual machine;
[0153] A copy module, configured to copy the cache data stored in the original memory to the target memory, and the capacity of the original memory is smaller than the capacity of the target memory;
[0154] A second update module, configured to determine the position information of the cache data in the target memory.
[0155] According to one or more embodiments of the present disclosure, [Example 9] provides an electronic device, and the electronic device includes:
[0156] One or more processing devices;
[0157] A storage device for storing one or more programs,
[0158] When the one or more programs are executed by the one or more processing devices, the one or more processing devices implement the memory processing method as described in any one of Examples 1-7.
[0159] According to one or more embodiments of the present disclosure, [Example 10] provides a storage medium containing computer-executable instructions that, when executed by a computer processor, are used to execute the memory processing method as described in any one of Examples 1-7.
[0160] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles applied. Those skilled in the art should understand that the scope of the disclosure involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosure concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present disclosure.
[0161] In addition, although the operations are depicted in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or in sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features described in the context of separate embodiments may also be implemented combinatorially in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments.
[0162] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. On the contrary, the specific features and acts described above are merely example forms for implementing the claims.
Claims
1. A memory processing method, characterized in that, Including: Allocating a target memory of a set size through a memory block allocation function of a memory allocation class; Updating the memory address of the cache data managed by the virtual machine; Copying the cache data stored in the original memory to the target memory, where the capacity of the original memory is less than the capacity of the target memory; Determining the position information of the cache data in the target memory.
2. The method according to claim 1, wherein The updating the memory address of the cache data managed by the virtual machine includes: Updating the member variable of the cache data class in the Java layer to the address of the target memory.
3. The method according to claim 2, wherein The updating the member variable of the cache data class in the Java layer to the address of the target memory includes: Updating the member variable of the cache data class in the Java layer to a native layer address, where the address of the target memory is stored at the position corresponding to the native layer address.
4. The method according to claim 1, wherein The copying the cache data stored in the original memory to the target memory includes: Copying at least two copies of the cache data stored in the original memory to the target memory.
5. The method according to claim 4, characterized in that, It further includes: Storing the increased cache data at the position where the non-first cache data is located in the target memory.
6. The method according to claim 1, characterized in that, The determining the position information of the cache data in the target memory includes: Setting the memory size to the size of the target memory; Based on the memory size and the index position of the cache data in the bytecode, determining the position information of the cache data in the target memory.
7. The method according to claim 1, characterized in that, The target memory is a continuous memory block, and the size of the target memory is a multiple of a set value of the size of the original memory.
8. A memory processing device, characterized in that, Including: An allocation module for allocating a target memory of a set size through a memory block allocation function of a memory allocation class; A first update module for updating the memory address of the cache data managed by the virtual machine; A copy module for copying the cache data stored in the original memory to the target memory, where the capacity of the original memory is less than the capacity of the target memory; A second update module for determining the position information of the cache data in the target memory.
9. An electronic device, characterized in that, The electronic device includes: One or more processing devices; A storage device for storing one or more programs, When the one or more programs are executed by the one or more processing devices, enabling the one or more processing devices to implement the memory processing method as described in any one of claims 1-7.
10. A storage medium containing computer-executable instructions, where the computer-executable instructions are used to execute the memory processing method as described in any one of claims 1-7 when executed by a computer processor.