Storage resource allocation method and device, computing device and storage medium

Abstract

The invention discloses a storage resource allocation method and device, a computing device and a storage medium. The storage resource allocation method is used for allocation of shared registers in a processor and comprises the steps that a discontinuous register block list is added into an available register block list, the discontinuous register block list comprises a plurality of discontinuous register blocks with the interval step length being M, and M is a positive integer larger than 1; in response to an allocation request that the current instruction occupies K discontinuous registers, allocating a discontinuous register group to the current instruction, K being a positive integer greater than 1; and updating the state of the distributed discontinuous register block in the discontinuous register block list. According to the storage resource allocation method, the utilization rate of the register can be improved, so that the number of synchronously executed threads is increased, and the program execution parallelism is improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a storage resource allocation method and apparatus, a computing device, and a storage medium. Background Art

[0002] Registers are a small amount of high-speed memories inside hardware such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), etc., and are used to store operands in machine instructions, for example. Limited by high prices, the number of registers is scarce. However, registers are indispensable because of their high-speed access characteristics.

[0003] During the code generation process of a compiler, variables in a program are allocated by the compiler to registers for storage. Variables in a high-level language program can be infinite, but the number of registers in hardware resources is limited. Variables that cannot be stored in registers are stored in external storage units. The access speed of registers is much faster than that of external memories such as memory. If too many variables are stored in external storage units of an external chip, the access speed of the variables will decrease, thus affecting the performance of the entire chip.

[0004] Reasonably using register allocation technology can allocate as many variables as possible to registers, thereby providing shorter access time for hardware and improving the performance of the entire computer system.

[0005] Currently, technologies and methods including register allocation, instruction selection, and instruction scheduling are important components of the compiler backend. A good register allocation algorithm can significantly improve program performance. Summary of the Invention

[0006] At least some embodiments of the present disclosure provide a storage resource allocation method for allocating shared registers in a processor. The storage resource allocation method includes: adding a discontinuous register group list to a list of available register groups, where the discontinuous register group list includes a plurality of discontinuous register groups with an interval step of M, and M is a positive integer greater than 1; in response to an allocation request for K of the discontinuous registers occupied by a current instruction, allocating the discontinuous register group to the current instruction, where K is a positive integer greater than 1; and updating the status of the allocated discontinuous register group in the discontinuous register group list.

[0007] For example, the storage resource allocation method provided by some embodiments of the present disclosure further includes: in response to the variable bit width corresponding to the current instruction being greater than a first threshold, determining whether the instruction type of the current instruction is a matrix instruction.

[0008] For example, the storage resource allocation method provided by some embodiments of the present disclosure further includes: in response to the instruction type of the current instruction being the matrix instruction and the allocation request of the current instruction occupying a discontinuous register group, determining the current instruction as the first instruction.

[0009] For example, in the storage resource allocation method provided by some embodiments of the present disclosure, allocating the discontinuous register group for the current instruction includes: in response to the discontinuous register group including K discontinuous registers in the available register group list, allocating the discontinuous register group for the current instruction.

[0010] For example, the storage resource allocation method provided by some embodiments of the present disclosure further includes: updating the status of the allocated single register in the single register list in the available register group list.

[0011] For example, in the storage resource allocation method provided by some embodiments of the present disclosure, the discontinuous register group list further includes a plurality of discontinuous register groups with an interval step of N, where N is an integer greater than 1 and N≠M.

[0012] For example, the storage resource allocation method provided by some embodiments of the present disclosure further includes: in response to the variable bit width corresponding to the current instruction being less than or equal to the first threshold, determining the current instruction as the second instruction, judging whether the single register list in the available register group list is empty, in response to the single register list not being empty, allocating a single register for the second instruction, updating the status of the allocated single register in the single register list, and in response to the single register list being empty, allocating an external storage unit for the second instruction.

[0013] For example, the storage resource allocation method provided by some embodiments of the present disclosure further includes: in response to the variable bit width corresponding to the current instruction being greater than the first threshold and the instruction type of the second instruction being a non-matrix instruction, determining the current instruction as the second instruction, judging whether the continuous register group list in the available register group list is empty, in response to the continuous register group list not being empty, allocating a continuous register group for the second instruction, and updating the status of the allocated continuous register group in the continuous register group list and the status of the allocated single register in the single register list.

[0014] For example, the storage resource allocation method provided by some embodiments of the present disclosure further includes: in response to the instruction type of the current instruction being a matrix instruction and the allocation request of the current instruction occupying a continuous register group, determining the current instruction as a second instruction, determining whether the continuous register group list in the available register group list is empty, and in response to the continuous register group list not being empty, allocating a continuous register group to the second instruction, and updating the status of the allocated continuous register group in the continuous register group list and the status of the allocated individual register in the single register list.

[0015] For example, the storage resource allocation method provided by some embodiments of the present disclosure further includes: in response to the continuous register group list being empty, allocating an external storage unit to the second instruction.

[0016] At least some embodiments of the present disclosure further provide a storage resource allocation device for allocating shared registers in a processor. The storage resource allocation device includes: a setting module configured to add a discontinuous register group list to the available register group list, where the discontinuous register group list includes a plurality of discontinuous register groups with an interval step of M, and M is a positive integer greater than 1; an allocation module configured to, in response to an allocation request of the current instruction occupying K of the discontinuous registers, allocate the discontinuous register group to the current instruction, where K is a positive integer greater than 1; and an update module configured to update the status of the allocated discontinuous register group in the discontinuous register group list.

[0017] For example, in the storage resource allocation device provided by at least some embodiments of the present disclosure, the allocation module further includes a determination module configured to, in response to the variable bit width corresponding to the current instruction being greater than a first threshold, determine whether the instruction type of the current instruction is a matrix instruction.

[0018] For example, in the storage resource allocation device provided by at least some embodiments of the present disclosure, the determination module is further configured to, in response to the instruction type of the current instruction being the matrix instruction and the allocation request of the current instruction occupying a discontinuous register group, determine the current instruction as a first instruction.

[0019] For example, in the storage resource allocation device provided by at least some embodiments of the present disclosure, the update module is further configured to update the status of the allocated individual register in the single register list in the available register group list.

[0020] For example, in the storage resource allocation device provided by at least some embodiments of the present disclosure, the discontinuous register group list further includes a plurality of discontinuous register groups with an interval step of N, and N is an integer greater than 1 and N≠M.

[0021] At least some embodiments of the present disclosure also provide a storage resource allocation device, which includes: a memory that stores computer-executable instructions non-transiently; a processor configured to run the computer-executable instructions, wherein when the computer-executable instructions are run by the processor, a storage resource allocation method provided by any embodiment of the present disclosure is implemented.

[0022] At least some embodiments of the present disclosure also provide a computing device, which includes: a storage unit including shared registers; a processor configured to execute computer-executable instructions; a storage controller configured to control the storage unit to allocate the shared registers when the computer-executable instructions are executed by the processor, so as to implement the storage resource allocation method provided by any embodiment of the present disclosure.

[0023] At least some embodiments of the present disclosure also provide a computer-readable storage medium, which stores computer-readable instructions non-transiently, wherein when the computer-executable instructions are executed by a computer, a storage resource allocation method provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0025] Figure 1A It is a schematic structural diagram of a data computing processor;

[0026] Figure 1B It is a register allocation flowchart of a compiler in a data computing processor;

[0027] Figure 2 It is a flowchart for specifying physical registers;

[0028] Figure 3 It is a schematic diagram of the steps of the storage resource allocation method provided by the embodiments of the present disclosure;

[0029] Figure 4 It is a flowchart of the storage resource allocation method provided by the embodiments of the present disclosure;

[0030] Figure 5 It is a schematic diagram of the steps of a discontinuous register group allocation method provided by some embodiments of the present disclosure;

[0031] Figure 6 It is a schematic diagram of the steps of a single register or continuous register group allocation method provided by some embodiments of the present disclosure;

[0032] Figure 7A Comparison of the number of registers occupied and the number of parallel threads between the resource allocation method provided by the present disclosure and the existing allocation method for discontinuous register groups with an interval step size of 2;

[0033] Figure 7B Comparison of the number of registers occupied and the number of parallel threads between the resource allocation method provided by the present disclosure and the existing allocation method for discontinuous register groups with an interval step size of 4;

[0034] Figure 8 Schematic structural diagram of a storage resource allocation device provided by some embodiments of the present disclosure;

[0035] Figure 9 Schematic structural diagram of a computing device provided by some embodiments of the present disclosure;

[0036] Figure 10 Schematic structural diagram of an electronic device provided by some embodiments of the present disclosure; and

[0037] Figure 11 Schematic diagram of a storage medium provided by some embodiments of the present disclosure. Detailed implementation manners

[0038] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0039] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure belongs. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0040] The present disclosure will be described below through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components (elements) may be omitted. When any component (element) of an embodiment of the present disclosure appears in more than one drawing, the component is denoted by the same or similar reference numerals in each drawing.

[0041] To keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed descriptions of some known functions and known components.

[0042] Due to the current need for computations such as neural networks, etc., a computing unit or a hardware accelerator dedicated to processing deep learning tasks can be provided, such as a general-purpose graphics processing unit (GPGPU), or a data computing processor. Compared with traditional CPUs or graphics processing units (GPUs), data computing processors generally have higher computing efficiency and lower power consumption in deep learning tasks.

[0043] Figure 1A Schematic diagram of the structure of a data computing processor. As Figure 1A shown, the structure of a data computing processor generally includes a thread block scheduling module, a thread block distribution module, a warp scheduling / distribution module, multiple cores, multiple processors, a register bank (or register file), shared caches (L1, L2), a global cache, a data path (e.g., direct memory access (DMA)), etc. ( Figure 1A not shown in the figure). Among them, the processor is the core component of the data computing processor architecture. A computer program can directly control these processors through a kernel function to execute deep learning-related computing tasks. The DMA unit is responsible for data transfer, ensuring efficient data transfer between the host side and the data computing processor without affecting the host's execution of other instructions.

[0044] In parallel computing, computing tasks are generally executed by multiple threads. As Figure 1AAs shown, before these threads are executed in a data computing processor (or a parallel computing processor), the thread block scheduling module divides them into multiple thread blocks, and then distributes the multiple thread blocks to each processor (e.g., a streaming multi-processor (SM)) via the thread block distribution module. Multiple thread blocks can be executed in the same processor or in different processors. All threads in a thread block must be assigned to the same processor for execution. At the same time, the thread block is split into the smallest execution thread warps (or simply thread warps). A thread warp is the most basic execution unit in the data computing processor, and each thread warp contains a fixed number (or less than this fixed number) of threads. For example, 32 threads or 64 threads. The more thread warps that can run simultaneously, the higher the parallelism of the program execution.

[0045] In each processor, the thread warp scheduling / distribution module schedules and allocates the thread warps so that multiple computing cores (e.g., streaming processors (SP)) of the processor can run the thread warps. Each computing core includes an arithmetic logic unit (ALU), a floating-point computing unit, etc. According to the number of computing cores in the processor, multiple thread warps in a thread block can be executed simultaneously or time-shared. Multiple threads in each thread warp will execute the same instruction. The reading, decoding, and issuing of instructions are all completed in the thread warp scheduling / distribution module. Memory execution instructions are issued to the shared cache (e.g., shared L1 cache) in the processor or further issued to the unified cache for read / write operations, etc.

[0046] For example, in the field of deep learning, the application scenarios of data computing processors are very extensive. For example, it can be used to process a large amount of image data to achieve functions such as image recognition, object detection, image generation, and synthesis. In addition, data computing processors can also be used for tasks such as video analysis and behavior recognition, providing powerful computing capabilities for fields such as autonomous driving and security monitoring.

[0047] Generally speaking, a data computing processor is a hardware accelerator designed for deep learning tasks. It improves computing efficiency and reduces power consumption by optimizing the structure and algorithms, thus promoting the application of deep learning technology in more fields.

[0048] Figure 1B It is a register allocation flowchart of a compiler in a data computing processor. The register allocation process shown in Figure 1 includes steps S10 - S50.

[0049] Step S10, variable lifetime statistics, and calculate the priority according to the weight.

[0050] Among them, the variable lifetime is an interval value of a variable in the program from its definition and use to the end of its use.

[0051] Step S20: Push the variable into the priority queue according to the priority.

[0052] For example, determine its priority according to the weight and activity value of the variable, and add the variables to the priority queue in sequence.

[0053] Step S30: Assign a physical register to the lifetime corresponding to the variable.

[0054] For example, take out variables from the priority queue in sequence and map them to the corresponding physical registers in the list of available physical registers.

[0055] Step S40: Split the lifetime corresponding to the variable.

[0056] Splitting the lifetime corresponding to the variable means further dividing the lifetime of the same variable into multiple parts and mapping them to different physical registers respectively.

[0057] Step S50: Overflow the lifetime corresponding to the variable.

[0058] Among them, lifetime overflow means that after allocating a register for the variable, update the lifetime corresponding to the variable and the lifetime associated with this variable to the overflow state.

[0059] Figure 2 It is a flowchart for specifying physical registers. Figure 2 It shows the flowchart of the stage of specifying physical registers in the above step S30.

[0060] As Figure 2 shown, read the variable from the priority queue, and then judge the variable width to judge the number of registers that may be required to store the variable. For example, the hardware width of a single register storage unit is 32 bits (bit), so take 32 bit as the judgment standard. The following first describes the process when the variable width is less than or equal to 32 bit. When the variable width is less than or equal to 32 bit, using one / single register can meet the storage requirements of the variable. The single register list records the available registers, and it is necessary to query whether the single register list is empty. When the single register list is empty, it means there are no available registers, and the variable needs to be stored in the external storage unit; when the single register list is not empty, it means there are available registers, and a single register can be allocated for the variable. At the same time, it is necessary to update the status of the single register list, update the allocated register to the unavailable state, and make all the registers recorded in the single register list available registers.

[0061] Another case is that the variable width is greater than 32 bit. At this time, using one register cannot meet the storage requirements of the variable, so it is necessary to use consecutive registers with more than one register to complete the storage operation.

[0062] Consecutive registers (also known as consecutive storage units or consecutive memory locations) are a series of adjacent storage locations in a processor used to store a consecutive block of data or instructions. For example, these registers are accessed and operated on by the central processing unit (CPU) through specific addresses. The main feature of consecutive registers is that they are consecutive in memory, i.e., each register has a unique address, and these addresses are consecutive integers. This enables the CPU to access and operate on these registers continuously by incrementing or decrementing the address pointer, thus achieving efficient processing of consecutive blocks of data or instructions.

[0063] Similar to the use of a single register, when using consecutive registers, it is necessary to query whether the consecutive register list is empty. The consecutive register list records the available consecutive registers. When the consecutive register list is empty, it means there are no available consecutive registers, and the variable needs to be stored in an external storage unit; when the consecutive register list is not empty, a consecutive register group can be allocated for the variable. At the same time, it is necessary to update the status of the consecutive register list, updating the allocated consecutive register group to an unavailable state, so that all the consecutive register groups recorded in the consecutive register list are available. It should be noted that at this time, it is also necessary to update the status of the single register list. This is because the consecutive register groups in the consecutive register list are formed by connecting available single registers with consecutive addresses, and these single registers used for connection themselves exist in the single register list. The occupation of a consecutive register group can be understood as the actual occupation of the corresponding single registers that form these consecutive register groups, so it is also necessary to update the status of the single register list.

[0064] However, in some application scenarios, for example, during the process of inference or training using a neural network, matrix instructions (such as matrix multiply-accumulate instructions) are used to process data. For example, the operands of a matrix instruction require a register group composed of 4 registers. The register group composed of these 4 registers can be continuous, or can have a fixed interval and be discontinuous, where the fixed interval can be 2 or 4. For example, v[0:1:2:3] represents a continuous register group with an interval step of 1. When the instruction uses a register group like v[0:1:2:3], it means using 4 continuous registers v0, v1, v2, and v3. Then v[0:2:4:6] represents a discontinuous register group with an interval step equal to 2. When the instruction uses a register group like v[0:2:4:6], it means using 4 discontinuous registers v0, v2, v4, and v6, rather than using 7 discontinuous registers from v0 to v6; similarly, v[0:4:8:12] represents a discontinuous register group with an interval step equal to 4. When the instruction uses a register group like v[0:4:8:12], it means using 4 discontinuous registers v0, v4, v8, and v12, rather than using 13 continuous registers from v0 to v12.

[0065] At this time, using Figure 2 the allocation process of the specified physical registers shown will have the following problems: Since there are no discontinuous register groups with an interval step equal to 2 or 4 in the available register list, the operands of the matrix instruction cannot be allocated to such discontinuous register groups.

[0066] If discontinuous register groups with an interval step equal to 2 or 4 are added to the available register list, since the instruction types are not distinguished, there is a possibility that existing instructions will be allocated to discontinuous register groups with an interval step equal to 2 or 4. And if discontinuous register groups with an interval step equal to 2 or 4 are added to the available register list, the existing register allocation algorithm will allocate more registers in the available register list than required. For example, allocating a register group like v[0:2:4:6] will occupy 7 registers from v0 to v6, rather than 4 registers v0, v2, v4, and v6, making 3 registers v1, v3, and v5 unavailable; similarly, after allocating a register group like v[0:4:8:12], it will occupy 13 registers from v0 to v12, rather than 4 registers v0, v4, v8, and v12, making 9 registers v1, v2, v3, v5, v6, v7, v9, v10, and v11 unavailable, resulting in a decrease in the availability rate of registers.

[0067] Therefore, if the current register allocation algorithm continues to be used, when facing matrix instructions that require the use of spaced registers, it will either affect the normal use of newly added matrix instructions, or adding discontinuous register groups to the available register list will cause redundant occupation of register resources, reduce the number of available registers for variables, resulting in a decrease in the variable access rate, and a decrease in the number of parallel warps in which the program is executed in the data computing processor, reducing the parallelism of the program running in the data computing processor. This particularly affects convolution and matrix calculations in high-performance computing (HPC) and artificial intelligence (AI).

[0068] Based on this, the embodiments of the present disclosure provide a storage resource allocation method for allocating shared registers in a processor. The storage resource allocation method includes: adding a discontinuous register group list to the available register group list, where the discontinuous register group list includes multiple discontinuous register groups with an interval step of M, and M is a positive integer greater than 1; in response to an allocation request for the current instruction to occupy K discontinuous registers, allocating a discontinuous register group to the current instruction, where K is a positive integer greater than 1; and updating the status of the allocated discontinuous register group in the discontinuous register group list.

[0069] By adding a discontinuous register list to the specified physical register allocation algorithm and allocating a discontinuous register group to an instruction in response to an allocation request for the instruction to occupy a discontinuous register group, this method can provide appropriate registers or register groups for instruction operands, improve the utilization rate of registers, increase the number of warps synchronously executed in the data computing processor, improve the parallelism of program execution, and thus improve the overall execution performance of the data computing processor.

[0070] Figure 3 It is a schematic diagram of the steps of the storage resource allocation method provided by some embodiments of the present disclosure. The storage resource allocation method includes steps S100 - S300.

[0071] Step S100, adding a discontinuous register group list to the available register group list, where the discontinuous register group list includes multiple discontinuous register groups with an interval step of M, and M is a positive integer greater than 1.

[0072] As mentioned above, for example, M can be 2, so that the discontinuous register group includes multiple discontinuous register groups with an interval step of 2, such as v[0:2:4:6], v[1:3:5:7], etc. For example, M can also be 4, so that the discontinuous register group includes multiple discontinuous register groups with an interval step of 4, such as v[0:4:8:12], v[1:5:9:13], etc.

[0073] Step S200: In response to an allocation request for the current instruction to occupy K discontinuous registers, allocate a discontinuous register group for the current instruction, where K is a positive integer greater than 1.

[0074] In response to an allocation request for the current instruction to occupy K discontinuous registers, if there is an available discontinuous register group in the current list of discontinuous register groups, then a discontinuous register group can be allocated for the current instruction.

[0075] Step S300: Update the status of the allocated discontinuous register group in the discontinuous register group list.

[0076] After completing the allocation of the discontinuous register group, it is necessary to update the status of the discontinuous register group in the discontinuous register group list and update the allocated discontinuous register group to an unavailable state. It should be noted that there is no strict time sequence limit for the execution of Step S200 and Step S300. For example, the update of the discontinuous register group list can be performed while allocating the discontinuous register group for the current instruction in Step S200.

[0077] The storage resource allocation method provided in the above embodiments of the present disclosure enables instructions that need to occupy discontinuous register groups to use discontinuous register groups, while the registers will not be redundantly occupied, thereby improving the availability and utilization rate of the registers, increasing the number of warps executed in parallel in the data computing processor, and improving the parallelism of program execution.

[0078] Figure 4 It is a schematic flowchart of a storage resource allocation method provided in an embodiment of the present disclosure. Figure 5 It is a schematic diagram of steps of a discontinuous register group allocation method provided in some embodiments of the present disclosure, including steps S110 - S180. The following combines Figure 4 the process to first describe the discontinuous register group allocation method provided in the embodiments of the present disclosure. Figure 5 shown in the discontinuous register group allocation method.

[0079] Step S110: Add a discontinuous register group list to the available register group list.

[0080] Before starting the storage resource allocation, add discontinuous memories according to requirements. For example, add a discontinuous register group list with a step interval of 2 or a step interval of 4 to the available memory group list.

[0081] For example, when the current instruction is a matrix instruction that needs to use a discontinuous register group, as Figure 5 shown, the above storage resource allocation method may further include the following steps S120 - S180.

[0082] Step S120: For the current instruction, read variables from the priority queue.

[0083] Step S120 is the same as Figure 1B the allocation process of registers in the data calculation processor.

[0084] Step S130: Determine the variable width.

[0085] The variable width can be judged by the first threshold to determine the number of registers that may be needed to store the variable. For example, the hardware width of a single register storage unit is 32bit, so the first threshold can be set to 32bit. For example, when the variable width corresponding to the current instruction is greater than the first threshold of 32bit, at least 2 registers are needed to store the variable. Here, 32bit is taken as an example for illustration, and the embodiments of the present disclosure are not limited thereto.

[0086] In response to the variable bit width corresponding to the current instruction being greater than the first threshold, step S140 needs to be executed next to determine whether the instruction type of the current instruction is a matrix instruction.

[0087] When it is determined that the instruction type of the current instruction is a matrix instruction, it is only possible to use a discontinuous register group. For example, matrix instructions can be matrix addition instructions, matrix multiplication instructions, matrix multiply-accumulate instructions, etc., and the embodiments of the present disclosure do not limit this. For the case of non-matrix instruction types, it will be described in combination with the following Figure 6 description.

[0088] Step S150: Determine whether the register group interval step size corresponding to the current instruction is equal to 1.

[0089] As mentioned above, for example, the operands of a matrix instruction require a register group composed of 4 registers. The register group can be continuous, that is, the register group interval step size is 1; it can also be a discontinuous register with an interval step size of 2 or 4. Therefore, not all matrix-type instructions require the use of discontinuous register groups. When the instruction type of the current instruction is a matrix instruction, it is necessary to determine whether the register group to be occupied by the current instruction has an interval step size other than 1, that is, to determine whether the current instruction needs to use a discontinuous register group. When it is determined that the current instruction needs to use a discontinuous register group, the current instruction is determined as the first instruction.

[0090] Step S160: In response to the allocation request of the first instruction occupying K discontinuous registers, allocate a discontinuous register group for the first instruction. Wherein, K is a positive integer greater than 1.

[0091] In step S160, allocating a discontinuous register group for the first instruction may include step S161 ( Figure 5 not shown in the figure):

[0092] Step S161: Determine whether the discontinuous register group list is empty.

[0093] The discontinuous register group list indicates the currently available discontinuous register groups. An empty discontinuous register group list means that there are no available discontinuous register groups currently, and variables need to be stored in an external storage unit. Therefore, after determining whether the discontinuous register group list is empty, when the register group list includes a register group of K discontinuous registers, it can meet the allocation request of the current instruction, and discontinuous register groups can be allocated for the current instruction. For example, allocate a register group of K discontinuous registers for an allocation request that occupies K discontinuous registers. Otherwise, the variable will be stored in the external storage unit.

[0094] Step S170: Update the status of the allocated discontinuous register groups in the discontinuous register group list.

[0095] By executing Step S170, update the status of the allocated discontinuous register groups to unavailable, so that the discontinuous register list always records available discontinuous register groups.

[0096] The above storage resource allocation method may further include Step S180:

[0097] Step S180: Update the status of the allocated single registers in the single register list of the available register group list.

[0098] The discontinuous register groups in the discontinuous register list are composed of available single registers selected according to addresses, for example, to form discontinuous register groups. Therefore, these selected single registers themselves exist in the single register list. When a discontinuous register group is occupied, it can be understood that in fact, the single registers corresponding to those used to form these discontinuous register groups are occupied. Therefore, the status of the single register list also needs to be updated.

[0099] For the matrix instructions that need to use discontinuous register groups, the storage resource allocation method provided in the above embodiments of the present disclosure can allocate discontinuous register groups for matrix instructions by adding a discontinuous register group list to the available register group list and in response to the allocation request that the current instruction occupies K discontinuous registers. At the same time, the registers will not be redundantly occupied, improving the availability rate of the registers.

[0100] It should be noted that the foregoing matrix instructions using discontinuous register groups with an interval step of 2 or 4 are merely examples, and the interval step value can also be any positive integer other than 1. In addition, in the storage resource allocation method provided by the embodiments of the present disclosure, in addition to the discontinuous register groups with an interval step of M, the discontinuous register group list may further include multiple discontinuous register groups with an interval step of N, where N is an integer greater than 1 and N≠M. For example, matrix instructions can simultaneously use discontinuous register groups including an interval step of 2 and 4.

[0101] Figure 6 is a schematic diagram of the steps of a method for allocating a single register and a continuous register group provided by some embodiments of the present disclosure, including steps S210 - S240. Next, in combination with Figure 4 and Figure 6 describe the method for allocating a single register and a continuous register group in the embodiments of the present disclosure.

[0102] Step S210, for the second instruction, read the variable from the priority queue.

[0103] The current instruction includes a first instruction and a second instruction. When the variable bit width of the current instruction is greater than the first threshold, the instruction type of the current instruction is a matrix instruction, and the current instruction needs to occupy a discontinuous register group, the current instruction can be determined as the first instruction. Otherwise, for example, in the following three cases, the current instruction can be determined as the second instruction: the variable bit width corresponding to the current instruction is less than or equal to the first threshold, the variable bit width corresponding to the current instruction is greater than the first threshold and the instruction type of the current instruction is a non - matrix type, or the instruction type of the current instruction is a matrix instruction and the current instruction needs to occupy a continuous register group.

[0104] Step S220, determine the variable width.

[0105] As Figure 6 shown, as described above, the variable width can be determined with the first threshold as a standard to determine the number of registers that may be used to store the variable. For example, the hardware width of a single - register storage unit is 32bit, then the first threshold can be set to 32bit. For example, when the variable width corresponding to the current instruction is less than the first threshold of 32bit, the current instruction is determined as the second instruction, and 1 register is needed to store the variable corresponding to the second instruction. Here, 32bit is taken as an example for illustration, and the embodiments of the present disclosure are not limited thereto.

[0106] When the variable bit width of the second instruction is less than or equal to the first threshold, execute step S230 to determine whether the single - register list in the available register group list is empty.

[0107] In response to the single register list not being empty, that is, there is currently an available single register, allocate a single register for the second instruction and update the status of the allocated single register in the single register list.

[0108] In response to the single register list being empty, that is, there is currently no available single register, allocate an external storage unit for the second instruction.

[0109] When the variable bit width corresponding to the current instruction is greater than the first threshold and the instruction type of the current instruction is a non-matrix instruction, determine the current instruction as the second instruction. It can be seen that the variables corresponding to the second instruction need to be stored using a continuous register group. At this time, execute step S240 to determine whether the continuous register group list in the available register group list is empty.

[0110] In response to the continuous register group list not being empty, a continuous register group can be allocated for the second instruction. Since the continuous register groups in the continuous register list are formed by connecting single registers with consecutive addresses, these single registers used for connection also exist in the single register list. It is necessary to update the status of the allocated continuous register group in the continuous register group list and the status of the allocated single register in the single register list.

[0111] When the second instruction needs to use a continuous register group, if the continuous register group list is empty, allocate an external storage unit for the second instruction.

[0112] In response to the instruction type of the current instruction being a matrix instruction and the allocation request of the current instruction occupying a continuous register group, determine the current instruction as the second instruction. It can be understood that the second instruction is a matrix instruction and the required register group interval step size is 1, that is, in the case of needing to use a continuous register group, it is still necessary to execute step S240 to determine whether the continuous register group list in the available register group list is empty. The subsequent execution steps are the same as when the variable bit width of the second instruction is greater than the first threshold and the instruction type is a non-matrix instruction, and will not be elaborated here.

[0113] The storage resource allocation method provided by the above embodiments of the present disclosure can allocate a discontinuous register group for the first instruction when the first instruction needs to occupy a discontinuous register group by adding a discontinuous register group list to the available register group list; when the second instruction needs to occupy a single register or a continuous register group, it can allocate a single register or a continuous register group for the second instruction, so as to provide a suitable register or register group for the instruction operand, improve the availability of the register, and improve the parallelism of program execution.

[0114] Figure 7A For discontinuous register groups with an interval step size of 2, compare the register occupancy and the number of parallel threads of the resource allocation method provided by the present disclosure with the existing allocation method.

[0115] In Figure 7A it, the first line represents the convolution kernel matrix operation program commonly used in high-performance computing (HPC) and artificial intelligence (AI) programs. For example, the 1×1 convolution operation represents a convolution operation program with a core function length and width of 1. When using the existing register allocation method to allocate registers for it, 130 registers are required. In the case where the total number of registers is 256, only one warp can run on the data computing processor. After using the resource allocation method provided by the present disclosure, for the 1×1 convolution operation program, the number of registers occupied is 112, and the register occupancy rate is reduced by 13.8% compared with the existing allocation method. Moreover, in the case where the total number of registers is 256, the number of warps that can be parallelized increases from one to two. After using the resource allocation method provided by the embodiments of the present disclosure for the remaining four programs, the number of registers occupied has also been reduced to varying degrees compared with using the existing allocation method. Especially for the 64×64 matrix operation program and the 128×128 matrix operation program, the number of warps that can be parallelized increases from one to two, and the parallelism of program operation has been significantly improved. Therefore, the resource allocation method provided by the embodiments of the present disclosure improves the parallelism of program operation, thereby improving the performance of the data computing processor.

[0116] Figure 7B For the discontinuous register group with an interval step of 4, the comparison of the register occupancy and the number of parallel threads between the resource allocation method provided by the present disclosure and the existing allocation method is shown. The data therein is similar to that of the discontinuous register group with an interval step of 2 shown in Figure 7A and will not be elaborated here. It should be noted that for the program that requires a discontinuous register group with an interval step of 4, after using the resource allocation method provided by the present disclosure, the number of registers occupied is reduced more than using the existing register allocation method, and the performance improvement of the data computing processor is more obvious.

[0117] The embodiments of the present disclosure also provide a storage resource allocation device. As Figure 8 shown, the storage resource allocation device 100 includes a setting module 110, an allocation module 120, and an update module 130. The setting module 10 is configured to add a discontinuous register group list to the available register group list, where the discontinuous register group list includes a plurality of discontinuous register groups with an interval step of M, and M is a positive integer greater than 1. The allocation module 120 is configured to, in response to an allocation request for K discontinuous registers occupied by the current instruction, allocate a discontinuous register group for the current instruction, where K is a positive integer greater than 1. The update module 130 is configured to update the status of the allocated discontinuous register group in the discontinuous register group list.

[0118] The storage resource allocation device provided by the embodiments of the present disclosure can improve the utilization rate of registers, reduce the use of external storage units, increase the access rate of variables, and increase the number of threads executed synchronously, thereby improving the parallelism of program execution.

[0119] The allocation module 120 in the above embodiment may further include a determination module 140, and the determination module 140 is configured to, in response to the variable bit width corresponding to the current instruction being greater than a first threshold, determine whether the instruction type of the current instruction is a matrix instruction.

[0120] The determination module 140 in the above embodiment is further configured to, in response to the instruction type of the current instruction being a matrix instruction and the allocation request of the current instruction occupying a discontinuous register group, determine the current instruction as a first instruction.

[0121] In the above embodiment, the allocation module 120 performs allocating a discontinuous register group for the current instruction, including: in response to a discontinuous register group including K discontinuous registers in the available register group list, allocating a discontinuous register group for the current instruction.

[0122] In the above embodiment, the update module 130 is further configured to update the status of the allocated single register in the single register list in the available register group list.

[0123] In the storage resource allocation device provided by the above embodiment, the discontinuous register group list further includes a plurality of discontinuous register groups with an interval step of N, where N is an integer greater than 1 and N≠M.

[0124] In the storage resource allocation device provided by the above embodiment, the determination module 140 is further configured to, in response to the variable bit width corresponding to the current instruction being less than or equal to the first threshold, determine the current instruction as a second instruction, determine whether the single register list in the available register group list is empty, and in response to the single register list not being empty, the allocation module 120 further allocates a single register for the second instruction, and the update module 130 updates the status of the allocated single register in the single register list. In response to the single register list being empty, the configuration module allocates an external storage unit for the second instruction.

[0125] In the storage resource allocation device provided by the above embodiment, the determination module 140 is further configured to, in response to the variable bit width corresponding to the current instruction being greater than the first threshold and the instruction type of the current instruction being a non-matrix instruction, determine the current instruction as a second instruction, determine whether the continuous register group list in the available register group list is empty, and in response to the continuous register group list not being empty, the allocation module 120 allocates a continuous register group for the second instruction, and the update module 130 updates the status of the allocated continuous register group in the continuous register group list and the status of the allocated single register in the single register list.

[0126] In the storage resource allocation device provided in the above embodiment, the determination module 140 is further configured to, in response to the instruction type of the current instruction being a matrix instruction and the allocation request of the current instruction occupying a continuous register group, determine the current instruction as a second instruction, determine whether the continuous register group list in the available register group list is empty, and in response to the continuous register group list not being empty, the allocation module 120 allocates a continuous register group to the second instruction, and the update module 130 updates the status of the allocated continuous register group in the continuous register group list and the status of the allocated individual register in the single register list.

[0127] In the storage resource allocation device provided in the above embodiment, in response to the continuous register group list being empty, the allocation module 120 allocates an external storage unit to the second instruction.

[0128] For the storage resource allocation device provided in the above embodiments of the present disclosure, it can be understood in combination with Figure 4 、 Figure 5 and Figure 6 the provided storage resource allocation method and related descriptions, which will not be elaborated here.

[0129] Some embodiments of the present disclosure also provide a computing device, as Figure 9 shown, the computing device 200 includes a storage unit 210, one or more processors 220, and a storage controller 230. The storage unit 210 includes a shared memory, and the shared memory includes a plurality of registers, and the plurality of registers may include register groups. The processor 220 may include, for example, a CPU, a GPU, a deep computing processor, etc., and is capable of executing computer-executable instructions to perform fixed-point calculations, floating-point calculations, etc., and multiple processors 220 may execute multiple threads in parallel. The storage controller 230 is coupled to the storage unit 210 and the processor 220, and is configured to control the storage unit 210 to allocate shared registers by implementing the storage resource allocation method provided in any embodiment of the present disclosure when the computer-executable instructions are executed by the processor 220.

[0130] For example, the computing device may be combined with a central processing unit to form a heterogeneous computing system.

[0131] Some embodiments of the present disclosure also provide a computing device, including a processor and a memory, and the memory stores computer-readable instructions non-temporarily, wherein when the computer-executable instructions are executed by the processor, the storage resource allocation method according to the embodiments of the present disclosure is implemented. For example, the processor and the memory as a whole implement the above storage controller.

[0132] Figure 10A schematic structural diagram of an electronic device provided by some embodiments of the present disclosure. The electronic device according to the embodiments of the present disclosure can be used to implement the storage resource allocation method according to any embodiment of the present disclosure. The electronic device may include at least one memory and at least one processor. Among them, the memory stores computer-executable instructions non-transiently, and the processor is configured to run the computer-executable instructions. For example, the electronic device according to the embodiments of the present disclosure can be implemented as, but not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc.

[0133] Figure 10 The electronic device shown is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.

[0134] As Figure 10 shown, the electronic device 300 may include a processing device (such as one or more central processing units, one or more graphics processing units, etc.) 310. The processing device includes the computing device that can implement the storage resource allocation method described above in the present disclosure. It can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 320 or the program loaded from the storage device 380 into the random access memory (RAM) 330. In the RAM 330, various executable programs and data required for the operation of the electronic device 300 are also stored. The processing device 310, the ROM 320, and the RAM 330 are connected to each other through a bus 340. The input / output (I / O) interface 350 is also connected to the bus 340.

[0135] Generally, the following devices may be connected to the I / O interface 350: an input device 360 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, or a gyroscope, etc.; an output device 370 including, for example, a liquid crystal display (LCD), a speaker, or a vibrator, etc.; a storage device 380 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 390. The communication device 390 can allow the electronic device 300 to communicate with other electronic devices wirelessly or wiredly to exchange data. Although Figure 10 the electronic device 300 including various devices is shown, it should be understood that it is not required to implement or have all the shown devices. The electronic device 300 can alternatively implement or have more or fewer devices.

[0136] For example, according to an embodiment of the present disclosure, the above storage resource allocation method can be implemented as a computer software program product. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program code for executing the above integrated circuit verification system configuration method or integrated circuit verification method. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 390, or installed from a storage device 380, or installed from a ROM 320. When the computer program is executed by a processing device 310, the functions defined in the storage resource allocation method provided by the embodiments of the present disclosure can be executed.

[0137] Some embodiments of the present disclosure also provide a storage medium for storing non-transitory computer program executable code (such as computer executable instructions), which can implement the storage resource allocation method of any embodiment of the present disclosure when the non-transitory computer program executable code is executed by a computer (such as including one or more processors); or, when the non-transitory computer program executable code is executed by a computer, it can implement the storage resource allocation method provided by the embodiments of the present disclosure.

[0138] Figure 11 A schematic diagram of a storage medium provided by some embodiments of the present disclosure. As Figure 11 shown, the storage medium 400 non-transitorily stores computer-readable instructions 401. For example, when the computer program-readable instructions 401 are executed by a computer (such as including one or more processors), the storage resource allocation method provided by the embodiments of the present disclosure can be executed.

[0139] For example, the storage medium 400 can be applied to the above electronic device 300. For example, the storage medium 400 can be Figure 10 the memory 320 in the electronic device 300 shown. For example, the relevant description of the storage medium 400 can refer to Figure 10 the corresponding description of the memory 320 in the electronic device 300 shown, which will not be elaborated here.

[0140] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, based on the embodiments of the present disclosure, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present disclosure all fall within the scope of protection required by the present disclosure.

[0141] In addition to the above exemplary descriptions, the following points need to be noted for the present disclosure:

[0142] (1) The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0143] (2) For clarity, in the accompanying drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn to actual scale.

[0144] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0145] As mentioned above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A storage resource allocation method for allocating shared registers in a processor, the storage resource allocation method comprising: Adding a discontinuous register group list to the available register group list, wherein the discontinuous register group list includes a plurality of discontinuous register groups with an interval step of M, and M is a positive integer greater than 1; In response to an allocation request for the current instruction to occupy K discontinuous registers, allocating the discontinuous register group to the current instruction, wherein K is a positive integer greater than 1; Updating the status of the allocated discontinuous register group in the discontinuous register group list.

2. The storage resource allocation method according to claim 1, further comprising: In response to the variable bit width of the current instruction being greater than a first threshold, determining whether the instruction type of the current instruction is a matrix instruction.

3. The storage resource allocation method according to claim 2, further comprising: In response to the instruction type of the current instruction being the matrix instruction and an allocation request for the current instruction to occupy a discontinuous register group, determining the current instruction as a first instruction.

4. The storage resource allocation method according to claim 1, wherein, Allocating the discontinuous register group to the current instruction includes: In response to the available register group list including a discontinuous register group with K discontinuous registers, allocating the discontinuous register group to the current instruction.

5. The storage resource allocation method according to claim 1, further comprising: Updating the status of the allocated single register in the single register list of the available register group list.

6. The storage resource allocation method according to claim 1, wherein, The discontinuous register group list further includes a plurality of discontinuous register groups with an interval step of N, and N is an integer greater than 1 and N≠M.

7. The storage resource allocation method according to claim 1, further comprising: In response to the variable bit width of the current instruction being less than or equal to the first threshold, determining the current instruction as a second instruction, and determining whether the single register list in the available register group list is empty, In response to the single register list not being empty, allocating a single register to the second instruction, Updating the status of the allocated single register in the single register list, In response to the single register list being empty, allocating an external storage unit to the second instruction.

8. The storage resource allocation method according to claim 1, further comprising: In response to the variable bit width of the current instruction being greater than the first threshold and the instruction type of the current instruction being a non - matrix instruction, determining the current instruction as a second instruction, and determining whether the continuous register group list in the available register group list is empty, In response to the continuous register group list not being empty, allocating a continuous register group to the second instruction, Updating the status of the allocated continuous register group in the continuous register group list and the status of the allocated single register in the single register list.

9. The storage resource allocation method according to claim 1, further comprising: In response to the instruction type of the current instruction being a matrix instruction and an allocation request for the current instruction to occupy a continuous register group, determining the current instruction as a second instruction, and determining whether the continuous register group list in the available register group list is empty, In response to the continuous register group list not being empty, allocate continuous register groups for the second instruction. Update the status of the allocated continuous register groups in the continuous register group list and the status of the allocated individual registers in the single register list.

10. The storage resource allocation method according to claim 8 or 9, further comprising: In response to the continuous register group list being empty, allocate an external storage unit for the second instruction.

11. A storage resource allocation device for allocating shared registers in a processor, the storage resource allocation device comprising: A setting module configured to add a discontinuous register group list to the available register group list, wherein the discontinuous register group list includes a plurality of discontinuous register groups with an interval step of M, and M is a positive integer greater than 1; An allocation module configured to, in response to an allocation request for the current instruction to occupy K discontinuous registers, allocate the discontinuous register groups for the current instruction, wherein K is a positive integer greater than 1; An update module configured to update the status of the allocated discontinuous register groups in the discontinuous register group list.

12. The storage resource allocation device according to claim 11, wherein, The allocation module further includes a determination module configured to, in response to the variable bit width corresponding to the current instruction being greater than a first threshold, determine whether the instruction type of the current instruction is a matrix instruction.

13. The storage resource allocation device according to claim 12, wherein, The determination module is further configured to, in response to the instruction type of the current instruction being the matrix instruction and an allocation request for the current instruction to occupy discontinuous register groups, determine the current instruction as a first instruction.

14. The storage resource allocation device according to claim 11, wherein, The update module is further configured to update the status of the allocated individual registers in the single register list in the available register group list.

15. The storage resource allocation device according to claim 11, wherein, The discontinuous register group list further includes a plurality of discontinuous register groups with an interval step of N, and N is an integer greater than 1 and N≠M.

16. A storage resource allocation device, comprising: A memory that non-transiently stores computer-executable instructions; A processor configured to run the computer-executable instructions, wherein the computer-executable instructions, when run by the processor, implement the storage resource allocation method according to any one of claims 1-10.

17. A computing device, comprising: A storage unit including shared registers; A processor configured to execute computer-executable instructions; A storage controller configured to, when the computer-executable instructions are executed by the processor, control the storage unit to allocate the shared registers by implementing the storage resource allocation method according to any one of claims 1-10.

18. A computer-readable storage medium that non-transitorily stores computer-executable instructions, wherein, When the computer-executable instructions are executed by a computer, execute the storage resource allocation method according to any one of claims 1-10.

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