Managing integrated circuit memory controller interrupts

Abstract

The invention relates to managing integrated circuit memory controller interrupts. The present disclosure provides an integrated circuit including a memory controller configured to transfer information stored in a memory to a processing unit. An example memory controller includes an error detection circuit configured to detect an error in the information by implementing an error correction code algorithm, and generate an interrupt signal if at least one error is detected in the information, the transmission control circuit is configured to transmit an interrupt signal to the processing unit only when the error detection circuit detects an error for the first time in the information.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to French Patent Application FR2400264, entitled "GESTION DES INTERRUPTIONSD'UN DE DE CIRCUIT ", filed on January 11, 2024, which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments and implementations relate to integrated circuit memory controllers, and more particularly to the management of memory controller interrupts within an integrated circuit. Background Art

[0004] A memory controller enables a processor to access information stored in a memory, such as instructions or data. The memory controller can detect errors in the information, in particular by implementing an error correction code during the transfer of the information to the processor.

[0005] When the memory controller detects an error in the information, the memory controller can generate an interrupt, so that the processor can be informed that the transferred information contains an error.

[0006] However, it is possible to correct errors in the information read by the memory controller, rather than correcting the error directly in the memory. In fact, correcting an error in the memory may require erasing and rewriting the information, which can be a relatively long operation, especially in the case of non-volatile memory. Therefore, error correction performed by the memory controller is generally faster and more preferred, especially in the case of real-time applications.

[0007] In addition, when a memory stores multiple instructions in an instruction sequence, the processor can provide a preloading mechanism to enable each of these instructions to be pre-read in the memory while other instructions in the instruction sequence are being executed, in order to improve the performance of the processor.

[0008] More specifically, when a pre-read instruction contains an error, this preloading mechanism can trigger an interrupt, thus temporarily halting the execution of the instruction sequence.

[0009] As long as the instruction has not been executed before the interruption of the instruction sequence, the processor will continue to read the same instruction after processing the interrupt.

[0010] Therefore, as long as the error contained in the instruction has not been corrected in the memory, the preloading mechanism will generate repeated triggering of the interrupt.

[0011] In other words, the repeated triggering of an interruption prevents the processor from continuing the execution of the instruction sequence because the processor always attempts to access the faulty instruction at the same location in the memory after each interruption.

[0012] In this regard, the interruption can be deactivated to prevent the repeated triggering of the interruption for the same error included in the instruction, but this solution does not allow determining the location of the faulty instruction in the memory. Thus, when this solution is viable, the faulty instruction whose location in the memory cannot be found by the processing unit cannot be corrected.

[0013] Therefore, solutions need to be proposed to enable the detection and correction of errors in the information while preventing the processor from repeatedly accessing the same location in the memory during an interruption generated by the memory controller. SUMMARY OF THE INVENTION

[0014] According to one aspect, an integrated circuit is proposed, the integrated circuit comprising a memory controller configured to transmit information, instructions or data stored in a memory to a processing unit (such as a processor), the memory controller comprising:

[0015] - an error detection circuit configured to detect an error or optionally multiple errors in the information by implementing an error correction code algorithm and to generate an interruption signal in the case where an error is detected in the information,

[0016] - a transmission control circuit configured to transmit the interruption signal to the processing unit only if the error detection circuit first detects an error in the information.

[0017] By transmitting the interruption signal to the processing unit only when the error is first detected, this can prevent the repeated triggering of the interruption signal from causing the processing unit to re-enter an infinite loop in which the processing unit processes the same interruption signal.

[0018] Thus, in the absence of the repeated triggering of the interruption signal, it is no longer necessary to deactivate the interruption to end this infinite loop, and the errors in the instructions stored in the memory can be corrected during maintenance operations.

[0019] According to one embodiment, the transmission control circuit comprises a memory circuit and a logic circuit, the memory circuit being configured to store the address of the location in the memory of the last information for which the transmission of the interruption signal has been triggered, the logic circuit being configured to compare the address stored by the memory circuit with the address of the location in the memory of the next information detected with an error transmitted by the memory controller after the last information, so as to transmit the interruption signal to the processing unit only if the address of the location in the memory of the next information does not correspond to the address stored by the memory circuit.

[0020] "Next information" refers to any information or data stored in a memory, which is transmitted to a processing unit after the last information in the order of information transmission. For example, this order can be the same as the order of the instruction sequence executed by the processing unit.

[0021] The next information and the last information can be the same information stored at a certain location in the memory. For example, if the same instruction is transmitted to the processing unit twice in a row, or two pieces of information stored at two different locations in the memory.

[0022] The memory circuit is configured to store one address at a time, so that the logic circuit can compare the address of the location of the next information in the memory with only one storage address (which is the address of the location of the last information in the memory).

[0023] The address of the location of the last information that has triggered the transmission of an interrupt signal in the memory is stored to prevent each new interrupt generated during the detection of an error in that information from being transmitted to the processing unit.

[0024] Advantageously, the transmission control circuit has a logic circuit that can transmit an interrupt if the address of the next information is different from the storage address, or can block the interrupt if the address of the next information and the storage address correspond.

[0025] According to one embodiment, the memory circuit includes: a first register configured to store the address of the location of the information in the memory in the case where an error detection circuit detects an error in the information,

[0026] - a second register configured to store the address contained in the first register before an error is detected in the next information.

[0027] Thus, for example, such a memory circuit can be easily produced from two registers.

[0028] The logic circuit includes a comparison circuit and a conditional transmission circuit. The comparison circuit is configured to generate a control signal having a value corresponding to the result of the comparison between the address contained in the first register and the address contained in the second register. The conditional transmission circuit is configured to transmit an interrupt signal only when the address stored in the first register does not correspond to the address stored in the second register.

[0029] The conditional transmission circuit (e.g., an "AND" logic gate) enables filtering of the interrupts generated by the error detection circuit according to the comparison result of the comparison circuit, so as to transmit only the interrupts generated when an error is first detected in the information.

[0030] According to one embodiment, the processing unit is configured to control the logic circuit such that, after the address where the memory circuit stores the last information, the logic circuit immediately compares the stored address with the address of the location of the next information in the memory.

[0031] Thus, when the memory circuit has not yet stored the address of the last information, the new transmission of the interrupt signal by the logic circuit is blocked. For example, the same stored address compared multiple times before an update may trigger the transmission of multiple interrupt signals generated for the same error, such as an error in the same information transmitted multiple times before updating the stored address.

[0032] According to one embodiment, the memory controller includes an additional conditional transmission circuit configured to block the transmission of the interrupt signal by the transmission control circuit as long as the memory circuit has not stored the address of the last information.

[0033] The additional conditional transmission circuit can be particularly considered when the conditional transmission circuit can no longer ensure the blocking of certain interrupts.

[0034] According to one embodiment, the processing unit is configured to read the address contained in the second register during the reception of the interrupt signal and store the read address in an additional memory.

[0035] Thus, the additional memory makes it possible to store a single address for each piece of information for which an error is detected during the execution of the instruction sequence by the processing unit.

[0036] According to one embodiment, the integrated circuit further includes a correction circuit, which can be, for example, the processing unit, configured to correct the information stored in the memory at the corresponding address stored in the additional memory.

[0037] These addresses, after being stored in the additional memory, make it possible to directly find all the error information in the memory and correct it during maintenance operations, and thus prevent the correction of this information during each interrupt.

[0038] According to one embodiment, the processing unit is configured to erase the content of the second register after the correction of the information stored in the memory by the processing unit.

[0039] Thus, after a maintenance operation, for example, during a restart of the integrated circuit, the content of the second register can be erased. This prevents the addresses of the information that has been corrected during the maintenance operation from remaining stored in the second register after the maintenance operation.

[0040] According to another aspect, a method for transmitting at least one piece of information stored in a memory to a processing unit is proposed, the method comprising:

[0041] - Detect errors in the information by implementing an error correction code algorithm, and generate an interrupt signal in the event of an error being detected in the information. The interrupt signal is transmitted only when the error detection circuit first detects an error in the information.

[0042] According to one implementation, the method includes storing the address of the location in the memory of the last information for which the transmission of the interrupt signal has been triggered, and comparing the stored address with the address of the location in the memory of each information with an error detected after the last information, so as to transmit an interrupt signal to the processing unit only when the address of the location of the information in the memory does not correspond to the address stored by the memory circuit.

[0043] According to one implementation, the memory includes:

[0044] - When an error is detected in the information, store the address of the location of the information in the memory in a first register,

[0045] - Before an error is detected in the next information, store the address contained in the first register in a second register.

[0046] The comparison includes generating a control signal having a value corresponding to the result of the comparison between the address contained in the first register and the address contained in the second register, and transmitting an interrupt signal only when the address stored in the first register does not correspond to the address stored in the second register.

[0047] According to one implementation, the comparison of the stored address with the address of the location in the memory of the next information is performed immediately after the address of the last information is stored.

[0048] According to one implementation, the method includes blocking the transmission of the interrupt signal as long as the address of the last information has not been stored.

[0049] According to one implementation, the method includes, during the reception of the interrupt signal by the processing unit, the processing unit reads the address stored in the second register and stores the address read by the processing unit in an additional memory.

[0050] According to one implementation, the method includes erasing the content of the second register after the processing unit corrects the information stored in the memory. Description of the Drawings

[0051] After examining the detailed description of the non-limiting embodiments and implementations and the drawings, other advantages and features of the present disclosure will become apparent, in the drawings:

[0052] Figure 1 、 Figure 2 and Figure 3Illustrates schematically implementations and embodiments of the present disclosure. Detailed implementation manners

[0053] Figure 1 Schematically illustrates an integrated circuit IC according to an embodiment of the present disclosure. The integrated circuit IC includes, for example, a memory ECC_MEM (such as a non-volatile memory) and an additional memory MEM (such as a random access memory (RAM)).

[0054] The integrated circuit IC further includes a memory controller MEM_CTRL and a processing unit UT, such as a processor.

[0055] The memory ECC_MEM can generally enable storage of information (such as instructions or data) and an error correction code (ECC).

[0056] The memory controller MEM_CTRL is configured to transmit the information stored in the memory ECC_MEM to the processing unit UT.

[0057] The information stored in the memory ECC_MEM (e.g., an instruction MEM_DAT of an instruction sequence executed by the processing unit UT, or data) may contain errors.

[0058] In this regard, the memory controller MEM_CTRL includes an error detection circuit ECC_CTRL, which is configured to detect an error or errors in the information by implementing an error correction code algorithm, and generate an interrupt signal INT in the case where an error is detected in the information MEM_DAT.

[0059] Such an error detection circuit ECC_CTRL is well-known to those skilled in the art, and they will know how to determine the error correction code so that the presence of an error in an instruction or data can be detected based on the error correction code included in the memory MEM_ECC. These error correction code algorithms can be algorithms based on Hamming codes or Gray codes, although these examples of algorithms are not exhaustive.

[0060] The error detection circuit ECC_CTRL enables, for example, reading of the instruction MEM_DAT in the memory ECC_MEM and correcting the instruction MEM_DAT before transmitting it to the processing unit UT.

[0061] The error detection circuit ECC_CTRL is configured to generate an interrupt signal INT during detection of an error in the information.

[0062] When the error detection circuit ECC_CTRL detects an error, the interrupt signal INT can be generated in the form of a pulse corresponding to a "high" logic level for a given duration.

[0063] The interrupt signal INT temporarily interrupts the execution of the instruction sequence by the processing unit UT so that the processing unit UT can react when an error is detected in the information MEM_DAT.

[0064] The memory controller MEM_CTRL further includes a transmission control circuit INT_CTRL. The transmission control circuit INT_CTRL is configured to transmit the interrupt signal INT only when the error detection circuit ECC_CTRL first detects an error in the information.

[0065] For example, when the error detection circuit ECC_CTRL first detects an error in the information MEM_DAT, the transmission control circuit INT_CTRL transmits the interrupt signal INT to the processing unit UT, but blocks the transmission of subsequent interrupt signals that may be generated in the case of detecting an error in the same information MEM_DAT.

[0066] Therefore, when the error detection circuit ECC_CTRL detects an error again for the same information, the transmission control circuit INT_CTRL makes it possible to prevent the transmission of an interrupt to the processing unit UT.

[0067] By transmitting the interrupt signal INT to the processing unit UT only when the error is first detected, this prevents an infinite loop in which the processing unit re-enters the processing of the same interrupt signal due to repeated triggering of the interrupt signal.

[0068] Therefore, the processing unit UT having, for example, the above preloading mechanism can continue the execution of the instruction sequence without being affected by repeated triggering of the interrupt.

[0069] Figure 2 Schematically illustrates the transmission control circuit INT_CTRL of the memory controller MEM_CTRL, as described above with respect to Figure 1 described.

[0070] The transmission control circuit INT_CTRL includes a memory circuit MEM_REG and a logic circuit LOG_TX.

[0071] The memory circuit MEM_REG is configured to store the address of the location in the memory ECC_MEM of the last information for which the transmission of the interrupt signal INT has been triggered.

[0072] The memory circuit MEM_REG includes hardware elements to enable, for example, the error detection circuit ECC_CTRL to read the address ADD of the information in which an error has been detected and store the address ADD.

[0073] The logic circuit LOG_TX is configured to compare the address stored by the memory circuit MEM_REG with the address of the position in the memory ECC_MEM of the next information, which is transmitted after the last information and in which an error is detected.

[0074] During the comparison by the logic circuit LOG_TX, if the address of the position of the next information in the memory ECC_MEM does not correspond to the address stored by the memory circuit MEM_REG, an interrupt signal INT is transmitted to the processing unit UT.

[0075] In other words, in the case where an error is detected in the information, the logic circuit LOG_TX uses the address stored by the memory circuit as a comparison base for each address transmitted by the error detection circuit ECC_CTRL, so as to prevent the interrupt signal INT from being transmitted again for the error detected in the same information.

[0076] The transmission control circuit INT_CTRL further includes a control register ENB_CTRL. The processing unit UT is configured to control the logic circuit LOG_TX according to the value stored in the control register ENB_CTRL.

[0077] More specifically, the processing unit UT is configured to modify the value of the control register ENB_CTRL when the address of the last information for which the interrupt signal INT has been triggered is stored by the memory circuit MEM_REG. The processing unit UT generates an activation signal ENB according to the value stored in the control register ENB_CTRL, so that the logic circuit LOG_TX can perform the comparison immediately after the memory circuit MEM_REG stores the address of the last signal.

[0078] The memory circuit MEM_REG includes a first register ERR_ADD_REG and a second register ADD_TAG_REG.

[0079] The first register ERR_ADD_REG is configured to store the address ADD of the position of the information in the memory ECC_MEM when the error detection circuit ECC_CTRL detects an error in the information. When an error is detected in the information, each new address transmitted by the error detection circuit ECC_CTRL can be automatically stored in the first register ERR_ADD_REG, for example, by replacing the address contained in the first register ERR_ADD_REG with the new address.

[0080] The second register ADD_TAG_REG is configured to store the address contained in the first register ERR_ADD_REG before an error is detected in the next information.

[0081] For example, the storage of the address in the second register ADD_TAG_REG can be performed by the processing unit UT in response to the interrupt signal INT.

[0082] During the initialization of the integrated circuit IC, the initialization value stored in the second register ADD_TAG_REG can be different from the value of the address of the memory ECC_MEM.

[0083] The logic circuit LOG_TX includes a comparison circuit COMP, which is configured to generate a control signal COMP_CTRL having a value corresponding to the result of the comparison between the address included in the first register ERR_ADD_REG and the address included in the second register ADD_TAG_REG.

[0084] The comparison circuit COMP can be a digitally - comparator of a conventional design such that a bit - by - bit comparison can be performed between the address stored in the first register ERR_ADD_REG and the address stored in the second register ADD_TAG_REG.

[0085] The control signal COMP_CTRL generated by such a comparator COMP can be a signal whose voltage value corresponds to different logic levels according to the result of the comparison. For example, if the addresses stored in the first register ERR_ADD_REG and the second register ADD_TAG_REG are the same, the control signal COMP_CTRL can have a "high" logic level, while if these addresses are different, the control signal COMP_CTRL can have a "low" logic level.

[0086] The logic circuit LOG_TX also includes a conditional transmission circuit AND2, which is configured to transmit the interrupt signal INT only when the address stored in the first register ERR_ADD_REG does not correspond to the address stored in the second register ADD_TAG_REG.

[0087] The conditional transmission circuit can be a logic gate configured to perform an "AND" logic operation between the interrupt signal INT and the control signal COMP_CTRL. In particular, an inverter can be connected to the input of the logic gate AND2 to transmit the inverted logic level of the control signal COMP_CTRL to the logic gate AND2.

[0088] Then, according to the logic level of the control signal COMP_CTRL, the interrupt signal INT is retransmitted as the output of the logic gate AND2. More specifically, if the inverted logic level of the control signal COMP_CTRL, which is an input to the logic gate AND2, is a "high" level, for example when the address ADD of the information MEM_DAT is different from the stored address, then the interrupt signal INT is transmitted to the processing unit UT. In the opposite case, that is, if the inverted logic level of the control signal COMP_CTRL, which is an input to the logic gate AND2, is a "low" level, then the interrupt signal INT is not transmitted to the processor UT.

[0089] The memory controller MEM_CTRL includes an additional condition transmission circuit AND1, which is configured to prevent the transmission control circuit INT_CTRL from transmitting the interrupt signal INT as long as the memory circuit MEM_REG does not store the address of the last information.

[0090] The additional condition transmission circuit AND1 can be a logic gate, which is configured to perform an "AND" logic operation between the interrupt signal INT and the activation signal ENB.

[0091] Upon receiving the interrupt signal INT, the processing unit UT can read the address stored in the second register ADD_TAG_REG and store this address in the additional memory MEM.

[0092] The additional memory MEM makes it possible to store the address of each piece of information for which an error is detected during the execution of the instruction sequence by the processing unit UT. These addresses can be used to perform a maintenance operation after being stored in the additional memory, during which each error message stored in the memory ECC_MEM is corrected.

[0093] In this regard, the integrated circuit further includes a correction circuit, which can be, for example, the processing unit UT, and is configured to correct the information stored in the memory at the corresponding address stored in the additional memory.

[0094] During the maintenance operation, the processing unit UT can find all the error messages stored in the memory ECC_MEM from the addresses stored in the additional memory MEM and correct this information. Such a maintenance operation can occur particularly after the execution of the instruction sequence by the processing unit UT, for example to prevent correcting this information during each interruption.

[0095] Then, the integrated circuit IC can be restarted after a maintenance operation. However, when the last information for which the interrupt signal INT has been triggered is corrected during the maintenance operation, after the integrated circuit IC is restarted, the address of this information is also stored in the second register ADD_TAG_REG. If the address of this information is also stored in the second register ADD_TAG_REG, there is a risk that the interrupt signal INT generated by the error detection circuit ECC_CTRL during the detection of new errors in this information will not be transmitted to the processing unit UT.

[0096] To prevent this risk, the processing unit UT is configured to erase the content of the second register ADD_TAG_REG after the processing unit UT corrects the information stored in the memory ECC_MEM.

[0097] In particular, the transmission control circuit INT_CTRL includes an erase register CLR_REG configured to store a user-defined value.

[0098] For example, during the first use of the integrated circuit IC, an initial value can be stored in the erase register CLR_REG such that during each restart of the integrated circuit IC, the processing unit UT reads the initial value stored in the erase register CLR_REG and replaces the value stored in the second register ADD_TAG_REG with this initial value.

[0099] Figure 3 A method for transmitting at least one piece of information stored in the memory ECC_MEM to the processing unit UT is schematically illustrated.

[0100] The method includes step 100: detecting an error in the information by implementing an error correction code algorithm and generating an interrupt signal INT in the case where one or more errors are detected in the information.

[0101] The method includes step 101: transmitting the interrupt signal INT (e.g., by the transmission control circuit INT_CTRL) only when the error detection circuit first detects an error in the information, as described above with respect to Figure 1 and Figure 2 stated.

[0102] The method further includes step 102: storing the address of the location in the memory ECC_MEM of the last information for which the transmission of the interrupt signal INT has been triggered.

[0103] Step 102 includes, in the case where an error is detected in the information, storing the address of the location of the information in the memory ECC_MEM in the first register ERR_ADD_REG.

[0104] Step 102 further includes storing the address contained in the first register ERR_ADD_REG in the second register ADD_TAG_REG before an error is detected in the next information. If, for example, the address of the memory ECC_MEM is not stored during the initialization of the integrated circuit IC, by default, an initialization value that can be a value different from the address of the memory ECC_MEM can be stored in the second register ADD_TAG_REG.

[0105] The method includes step 103: comparing, by, for example, the logic circuit LOG_TX, the stored address with the address of the position of the next information, in which an error is detected, transmitted after the last information in the memory ECC_MEM. If, after this comparison, the address of the position of the next information in the memory ECC_MEM does not correspond to the address stored by the memory circuit MEM_REG, an interrupt signal INT is transmitted to the processing unit UT.

[0106] Step 103 includes detecting the storage of the address of the last information that has triggered the transmission of the interrupt signal INT, and generating an activation signal ENB according to the value stored in the control register ENB_CTRL, so that the logic circuit LOG_TX can perform the comparison immediately after the memory circuit MEM_REG stores the address of the last information.

[0107] Step 103 includes generating a control signal COMP_CTRL. The control signal COMP_CTRL has a value corresponding to the result of the comparison between the address contained in the first register ERR_ADD_REG and the address contained in the second register ADD_TAG_REG.

[0108] Step 103 further includes transmitting the interrupt signal INT only if the address stored in the first register ERR_ADD_REG does not correspond to the address in the second register ADD_TAG_REG.

[0109] The method includes step 104: the transmission control circuit INT_CTRL blocks the transmission of the interrupt signal INT as long as the address of the last information is not stored.

[0110] The method includes step 105: receiving the interrupt signal INT by the processing unit UT.

[0111] Step 105 includes reading, by the processing unit UT, the address stored in the second register ADD_TAG_REG, and storing the address read by the processing unit UT in the additional memory MEM.

[0112] The method further includes step 106: correcting information stored in the memory ECC_MEM at a corresponding address stored in the additional memory. The correction of step 107 can be performed, for example, by the processing unit UT.

[0113] The method includes step 107: after the processing unit UT corrects the information stored in the memory ECC_MEM, erasing the content of the second register ADD_TAG_REG. Such erasing can include, for example, reading an initialization value stored in the erase register CLR_REG and replacing the address stored in the second register ADD_TAG_REG with the initialization value.

Claims

1. An integrated circuit includes a memory controller configured to transmit information stored in a memory to a processing unit. The memory controller includes: An error detection circuit configured to detect an error in the information by implementing an error correction code algorithm and generate an interrupt signal when an error is detected in the information; And A transmission control circuit configured to transmit the interrupt signal to the processing unit only when the error detection circuit first detects the error in the information.

2. The integrated circuit according to claim 1, wherein the transmission control circuit includes a memory circuit and a logic circuit. The memory circuit is configured to store an address of a location in the memory of the last information that has triggered transmission of the interrupt signal. The logic circuit is configured to compare the address stored by the memory circuit with an address of a location in the memory of the next information that is transmitted after the last information and in which an error is detected, so as to transmit the interrupt signal to the processing unit only when the address of the location of the next information in the memory does not correspond to the address stored by the memory circuit.

3. The integrated circuit according to claim 2, wherein the memory circuit includes: A first register configured to store the address of the location in the memory of the information when the error detection circuit detects an error in the information; A second register configured to store the address contained in the first register before an error is detected in the next information; And Wherein the logic circuit includes a comparison circuit and a conditional transmission circuit. The comparison circuit is configured to generate a control signal having a value corresponding to a result of a comparison between the address contained in the first register and the address contained in the second register. The conditional transmission circuit is configured to transmit the interrupt signal only when the address stored in the first register does not correspond to the address stored in the second register.

4. The integrated circuit according to claim 2, wherein the processing unit is configured to control the logic circuit such that after the memory circuit stores the address of the last information, the logic circuit immediately compares the stored address with the address of the location in the memory of the next information.

5. The integrated circuit according to claim 2, wherein the memory controller includes an additional conditional transmission circuit configured to prevent the transmission control circuit from transmitting the interrupt signal as long as the memory circuit does not store the address of the last information.

6. The integrated circuit according to claim 3, wherein the processing unit is further configured to read the address stored in the second register during reception of the interrupt signal and store the address read by the processing unit in an additional memory.

7. The integrated circuit according to claim 6 further includes a correction circuit configured to correct the information stored in the memory at a corresponding address stored in the additional memory.

8. The integrated circuit according to claim 7, wherein the processing unit is further configured to erase the content of the second register after correction of the information stored in the memory.

9. A method for transmitting information stored in a memory to a processing unit, comprising: detecting an error in the information by implementing an error correction code algorithm; generating an interrupt signal in case an error is detected in the information; and transmitting the interrupt signal to the processing unit only when the error detection circuit first detects the error in the information.

10. The method according to claim 9, further comprising: storing an address of a location in the memory where the last information that has triggered transmission of the interrupt signal is stored, and comparing the stored address with an address of a location in the memory of the next information detected with an error, which is transmitted after the last information, so as to transmit the interrupt signal to the processing unit only when the address of the location in the memory of the next information does not correspond to the stored address.

11. The method according to claim 10, wherein storing the address comprises: storing, in case an error is detected in the information, the address of the location in the memory of the information in a first register; storing, before an error is detected in the next information, the address contained in the first register in a second register; and wherein the comparison comprises generating a control signal having a value corresponding to a result of a comparison between the address contained in the first register and the address contained in the second register, and transmitting the interrupt signal only when the address stored in the first register does not correspond to the address stored in the second register.

12. The method according to claim 10, wherein the comparison of the stored address with the address of the location in the memory of the next information is performed immediately after the address of the last information is stored.

13. The method according to claim 10, further comprising blocking the transmission of the interrupt signal as long as the address of the last information is not stored.

14. The method according to claim 10, further comprising, during reception of the interrupt signal by the processing unit, the processing unit reading the address stored in the second register and storing the address read by the processing unit in an additional memory.

15. The method according to claim 14, further comprising correcting the information stored in the memory at a corresponding address stored in the additional memory.

16. The method according to claim 15, further comprising erasing the content of the second register after correction of the information stored in the memory by the processing unit.

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