Data storage method, system, device, debugger, medium and product

Abstract

This application relates to a data storage method, system, apparatus, debugger, medium, and product. The method includes: converting real-time program execution data conforming to a first communication protocol output by the device under test (DUT) into program execution data conforming to a second communication protocol; the first communication protocol is a protocol for testing the DUT, and the second communication protocol is a protocol adapted to a computer device; the program execution data is execution data fed back by stub programs in the test program of the DUT, and multiple stub programs are pre-set at key program locations in the test program of the DUT through stub insertion; storing the program execution data conforming to the second communication protocol in a storage module, so that a computer device can obtain the program execution data conforming to the second communication protocol stored in the storage module. This method can improve the reliability of DUT testing.

Description

Technical Field

[0001] This application relates to the field of hardware-in-the-loop testing technology, and in particular to a data storage method, system, device, debugger, medium, and product. Background Technology

[0002] Hardware-in-the-Loop (HiL) testing is a testing method that combines the device under test (DUT) with a virtual simulation environment. It is mainly used to verify the functionality, performance, and reliability of the DUT in complex real-world environments.

[0003] Taking hardware-in-the-loop (HIL) testing in automotive electronics as an example, HIL testing in automotive electronics involves monitoring the program execution data of the device under test (DUT) (such as a vehicle or a device within a vehicle) to determine the operational status of the test program within the DUT. In related technologies, a computer is often connected to the DUT so that the DUT can transmit the program execution data of its test program to the computer in real time. The computer then monitors the program execution status during the testing process based on the received data to determine whether the HIL test of the DUT has passed.

[0004] However, in hardware-in-the-loop testing of related technologies, computer equipment often cannot monitor the complete program execution status of the test program in the device under test during the testing process, resulting in low reliability of the device under test. Summary of the Invention

[0005] Based on this, this application provides a data storage method, system, device, debugger, medium, and product, which can improve the completeness of the computer equipment's acquisition of the program running status of the test program in the device under test during the test process, thereby improving the reliability of the test of the device under test.

[0006] In a first aspect, this application provides a data storage method applied to a data processing chip in a debugger for hardware-in-the-loop testing. The debugger is further configured with a storage module connected to the data processing chip. The method includes: converting program execution data output in real time by the device under test (DUT) conforming to a first communication protocol into program execution data conforming to a second communication protocol; the first communication protocol is a protocol for testing the DUT, and the second communication protocol is a protocol adapted to a computer device; the program execution data is the execution data fed back by stub programs in the test program of the DUT, and multiple stub programs are pre-set at key program positions in the test program of the DUT by instrumentation; storing the program execution data conforming to the second communication protocol in the storage module so that the computer device can obtain the program execution data conforming to the second communication protocol stored in the storage module.

[0007] In the technical solution provided in this application embodiment, after the debugger obtains the program running data, it stores the program running data in the storage module. Thus, even if the computer device lags or does not support real-time acquisition of program running data, the computer device can still obtain the program running data stored in the storage module. This improves the completeness of the computer device's acquisition of the program running status of the test program in the device under test during the testing process, thereby improving the reliability of the device under test testing. Furthermore, the debugger is connected between the device under test and the computer device. The data processing chip in the debugger can perform communication protocol conversion, effectively solving the protocol incompatibility problem between the device under test and the computer device. No additional configuration is required for the computer device to support the first communication protocol, expanding the application scope of the debugger. Moreover, the storage module stores program running data conforming to the second communication protocol. Therefore, when the computer device needs to read program running data, it forwards the stored program running data of the second communication protocol without performing the protocol conversion step, reducing the latency for the computer device to read the program running data of the second communication protocol.

[0008] In some embodiments, the storage module includes multiple types of storage units; storing program execution data conforming to the second communication protocol in the storage module includes: receiving transmission configuration information sent by a computer device; the transmission configuration information is used to indicate the transmission path of the program execution data conforming to the second communication protocol; determining the target type of the storage unit storing the program execution data conforming to the second communication protocol according to the transmission configuration information; and storing the program execution data conforming to the second communication protocol in the storage unit of the target type.

[0009] In the technical solution provided in this application embodiment, the transmission path of the second communication protocol program running data is represented by the transmission configuration information sent by the computer device, and the target type of the storage unit is accurately matched accordingly for data storage. In this way, the corresponding storage unit can be adapted to the characteristics of different transmission paths, and data classification storage can be achieved. This not only improves the efficiency of storage resource utilization, but also ensures data integrity and storage stability, avoids problems such as data loss and transmission delay caused by improper selection of storage units, and significantly improves the flexibility and reliability of data storage for different transmission paths.

[0010] In some embodiments, determining the target type of a storage unit storing program execution data conforming to the second communication protocol based on transmission configuration information includes at least one of the following: when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted via random access memory, determining the target type of the storage unit to be random access memory type; when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted in real time, determining the target type of the storage unit to be cache type; when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted via read-only memory, determining the target type of the storage unit to be read-only memory type.

[0011] In the technical solution provided in this application embodiment, the appropriate memory type is dynamically selected according to the transmission configuration information, which can achieve optimal allocation of storage resources and avoid the problems of waste of storage resources and reduced data transmission efficiency caused by using inappropriate memory types. For example, data that needs to be transmitted in real time is stored in a small-capacity but fast cache, data that needs to be stored without power is stored in a large-capacity read-only memory, and data that needs a certain amount of storage and needs to be read quickly is stored in a moderate-capacity random access memory. Thus, the corresponding memory type can be flexibly selected according to the reliability and speed of data transmission, thereby improving the efficiency of storage resource utilization.

[0012] In some embodiments, storing program execution data conforming to the second communication protocol in a target type storage unit includes at least one of the following: when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted via random access memory in the storage module, storing the program execution data conforming to the second communication protocol in a cache in the storage module, and transferring the program execution data conforming to the second communication protocol in the cache to the random access memory; when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted in real time, storing the program execution data conforming to the second communication protocol in a cache in the storage module; when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted via read-only memory in the storage module, storing the program execution data conforming to the second communication protocol in a cache in the storage module, transferring the program execution data conforming to the second communication protocol in the cache to the random access memory in the storage module, and transferring the program execution data conforming to the second communication protocol in the random access memory to the read-only memory.

[0013] In the technical solution provided by the embodiments of this application, the data after the data processing chip converts the protocol is first written to a cache, and then read from the cache and written to random access memory. The write latency of the cache is lower than that of the random access memory, and the write latency of the random access memory is lower than that of the read-only memory. Therefore, the cache can respond immediately to the data storage of the data processing chip. Compared with the solution of directly writing the data after the data processing chip converts the protocol to the random access memory, or compared with the solution of directly writing the data after the data processing chip converts the protocol to the read-only memory, the data processing... The chip does not need to wait for the data to be written to be completed before it can perform the next operation, which improves the processing efficiency of the data processing chip. Furthermore, by writing random access memory to read-only memory, and since read-only memory needs to be written page by page, multiple small data stored in random access memory can be merged into a complete page and written to read-only memory page by page. Compared with the solution of writing cached data directly to read-only memory, this reduces the number of read-only memory writes. This not only reduces the risk of read-only memory aging caused by the write count limit of read-only memory and improves the lifespan of read-only memory, but also improves the write efficiency of read-only memory.

[0014] In some embodiments, transferring cached program execution data conforming to the second communication protocol to random access memory includes: receiving a clock signal sent by a computer device; the clock signal being a waveform signal of a preset frequency; transferring the cached program execution data conforming to the second communication protocol to random access memory at a preset frequency according to the waveform signal of the preset frequency and a pre-configured number of bytes written to random access memory each time; the method further includes: sending the program execution data conforming to the second communication protocol in random access memory to the computer device at a preset frequency according to the waveform signal of the preset frequency and a pre-configured number of bytes read from random access memory each time.

[0015] In the technical solution provided in this application embodiment, a waveform signal with a preset frequency is used as a reference to precisely control the rhythm of data transfer to random access memory (RAM), avoiding data loss and misalignment caused by timing disorder, ensuring that program running data is transferred to RAM completely and orderly, and improving the accuracy of data transfer from cache to RAM; transferring data to RAM according to the number of bytes written can fully utilize the high-speed read and write characteristics of RAM, reduce the number of data transfer interactions, reduce transfer latency, and improve the timeliness of data transfer; and sending data to the computer device according to the waveform signal with the preset frequency and the pre-configured number of bytes read from RAM each time, thereby improving the correctness and synchronization of data sent by the data processing chip to the computer device, and thus improving the reliability of data transmission.

[0016] In some embodiments, transferring program execution data conforming to a second communication protocol from random access memory to read-only memory includes: receiving a clock signal sent by a computer device; the clock signal being a waveform signal of a preset frequency; transferring program execution data conforming to the second communication protocol from random access memory to read-only memory at a preset frequency according to the waveform signal of the preset frequency and a pre-configured number of bytes written to read-only memory each time; the method further includes: sending program execution data conforming to the second communication protocol from read-only memory to computer device at a preset frequency according to the waveform signal of the preset frequency and a pre-configured number of bytes read from read-only memory each time.

[0017] In the technical solution provided in this application embodiment, based on a waveform signal of a preset frequency, the rhythm of data transfer to read-only memory can be precisely controlled, avoiding data loss and misalignment caused by timing disorder. This ensures that program running data is transferred to read-only memory completely and orderly, improving the accuracy of data transfer from random access memory to read-only memory. Furthermore, transferring data to read-only memory according to the number of bytes written can fully utilize the high-speed read / write characteristics of read-only memory, reducing the number of data transfer interactions, lowering transfer latency, and improving the timeliness of data transfer. Moreover, based on the waveform signal of the preset frequency and the pre-configured number of bytes read from read-only memory each time, data is sent to the computer device, thereby improving the correctness and synchronization of data transmission from the data processing chip to the computer device, and thus improving the reliability of data transmission.

[0018] In some embodiments, the method further includes: when program execution data conforming to the second communication protocol is configured to be transmitted through a target memory in the storage module, during hardware-in-the-loop testing, reading program execution data conforming to the second communication protocol from the target memory according to each received target data read request; the target memory includes random access memory or read-only memory; and sending the read program execution data conforming to the second communication protocol to a computer device.

[0019] In the technical solution provided in this application embodiment, when the target memory is random access memory (RAM), the capacity of the RAM is moderate. This avoids the problem of insufficient data storage due to insufficient storage capacity, which would prevent the computer device from intermittently sending target data read requests. It also prevents resource waste due to excessive capacity. Furthermore, the fast read performance of RAM allows the data processing chip to quickly read data from RAM and send it to the computer device after receiving the target data read request from the computer device, greatly improving the timeliness of data interaction and ensuring the efficiency of data transmission during the testing process. When the target memory is read-only memory (ROM), the program execution data stored in ROM can also be obtained during hardware-in-the-loop testing, avoiding the inability to read program execution data in ROM during hardware-in-the-loop testing and improving the timeliness of data transmission.

[0020] In some embodiments, reading program execution data conforming to the second communication protocol from the target memory according to each received target data read request includes: determining the target read address of the program execution data conforming to the second communication protocol in the target memory based on the latest execution time of the program execution data already acquired by the computer device carried in each received target data read request; and reading the program execution data conforming to the second communication protocol from the target memory according to the target read address.

[0021] In the technical solution provided in this application embodiment, by carrying the latest running time of the program running data already acquired by the computer device in the target data reading request, not only does the data processing chip not need to record the latest time of the program running data sent each time, reducing the internal resource occupation of the data processing chip and avoiding the computational overhead caused by frequent recording and updating of time; it also avoids the problem that the computer device does not acquire the program running data even though the data processing chip has sent the program running data, thus improving the reliability of data transmission.

[0022] In some embodiments, the method further includes: upon receiving a data reception success instruction sent by a computer device, determining that the transmission of each batch of program running data conforming to the second communication protocol has been completed; upon receiving a retransmission instruction for program running data for at least one runtime sent by a computer device, determining a set read address for the program running data for at least one runtime; and according to the set read address, reading the program running data conforming to the second communication protocol for at least one runtime from a target memory, and sending the program running data conforming to the second communication protocol for at least one runtime to the computer device.

[0023] In the technical solution provided in this application embodiment, the successful data reception instruction confirms that the transmission of program running data conforming to the second communication protocol has been completed each time. The retransmission instruction for program running data at least one running time can accurately determine the set read address, read from the target memory and retransmit program running data at least one running time, thereby realizing reliable confirmation and efficient retransmission of program running data transmission, effectively ensuring the integrity and accuracy of data transmission, and improving the reliability of program running data transmission.

[0024] In some embodiments, the method further includes: when the program execution data conforming to the second communication protocol is configured for real-time transmission, sending the program execution data of the second communication protocol stored in the cache of the storage module to the computer device in real time; wherein the storage module includes a random access memory, a cache, and a read-only memory; the capacity of the random access memory is greater than the capacity of the cache and less than the capacity of the read-only memory.

[0025] In the technical solution provided in this application embodiment, when the program running data conforming to the second communication protocol is configured for real-time transmission, the program running data cached in the storage module can be sent to the computer device in real time, which greatly shortens the data transmission delay time, realizes real-time data interaction and processing, and improves data transmission efficiency. Furthermore, real-time transmission of program running data is only performed when the program running data conforming to the second communication protocol is configured for real-time transmission, avoiding real-time transmission when it is not configured for real-time transmission. This not only reduces the operating load of the data processing chip, but also avoids the problem of data loss caused by the computer device not supporting real-time acquisition, thus improving the reliability of data transmission.

[0026] In some embodiments, the method further includes: when program execution data conforming to the second communication protocol is configured to be transmitted via read-only memory, detecting the connection status between the debugger and the computer device; when the connection status is that the debugger and the computer device are disconnected during hardware-in-the-loop testing and successfully reconnected after the hardware-in-the-loop testing process, reading all the program execution data conforming to the second communication protocol stored in the read-only memory according to a predetermined data read request received from the computer device; and sending all the stored program execution data conforming to the second communication protocol to the computer device.

[0027] In the technical solution provided in this application embodiment, when the program running data is configured to be transmitted through a read-only memory, even if the debugger and the computer device are disconnected during hardware-in-the-loop testing, the program running data conforming to the second communication protocol can be completely retained by relying on the stable storage performance of the read-only memory. After the test is completed and the connection between the debugger and the computer device is restored, all the stored program running data is accurately transmitted back according to the predetermined data reading request of the computer device, which effectively avoids the risk of data loss and improves the comprehensiveness of the program running data obtained by the computer device.

[0028] Secondly, this application provides a hardware-in-the-loop testing system, comprising: a device under test (DUT), a computer device, and a debugger; the debugger includes a data processing chip and a storage module; the DUT is used to send program execution data conforming to a first communication protocol to the data processing chip; the first communication protocol is a protocol for testing the DUT; the program execution data is the execution data fed back by stub programs in the test program of the DUT, and multiple stub programs are pre-set at key program locations in the test program of the DUT by instrumentation; the data processing chip is used to convert the program execution data conforming to the first communication protocol into program execution data conforming to a second communication protocol, and to store the program execution data conforming to the second communication protocol in a storage device; the second communication protocol is a protocol adapted to the computer device; the data processing chip is also used to read the program execution data conforming to the second communication protocol from the storage device, so that the computer device can obtain the program execution data conforming to the second communication protocol stored in the storage module.

[0029] Thirdly, this application provides a data storage device, comprising: a protocol conversion module for converting program execution data conforming to a first communication protocol, which is output in real time by the device under test (DUT), into program execution data conforming to a second communication protocol; the first communication protocol is a protocol for testing the DUT, and the second communication protocol is a protocol adapted to a computer device; the program execution data is the execution data fed back by stub programs in the test program of the DUT, and multiple stub programs are pre-set at key program positions in the test program of the DUT by stub insertion; and a storage control module for storing the program execution data conforming to the second communication protocol in a storage module for use by a computer device to obtain the program execution data conforming to the second communication protocol stored in the storage module.

[0030] Fourthly, this application provides a debugger, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method of any one of the first aspects.

[0031] Fifthly, this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method of any one of the first aspects.

[0032] In a sixth aspect, this application provides a computer program product, including a computer program, wherein when the computer program is executed by a processor, it implements the steps of the method of any one of the first aspects. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the hardware-in-the-loop test system provided in the first embodiment;

[0035] Figure 2 A flowchart illustrating the data storage method provided in the first embodiment;

[0036] Figure 3 A flowchart illustrating the data storage method provided in the second embodiment;

[0037] Figure 4 A flowchart illustrating the data storage method provided in the third embodiment;

[0038] Figure 5 A flowchart illustrating the data storage method provided in the fourth embodiment;

[0039] Figure 6 A flowchart illustrating the data storage method provided in the fifth embodiment;

[0040] Figure 7 This is a schematic diagram of the hardware-in-the-loop test system provided in the second embodiment;

[0041] Figure 8 This is a schematic diagram of the hardware-in-the-loop test system provided in the third embodiment;

[0042] Figure 9 A schematic diagram of the structure of a data storage device provided for some embodiments;

[0043] Figure 10 A schematic diagram of the structure of a debugger provided for some embodiments. Detailed Implementation

[0044] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0046] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined. In the description of the embodiments of this application, "each" means each of the multiple options, unless otherwise explicitly defined.

[0047] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0048] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0049] Figure 1 This is a schematic diagram of the hardware-in-the-loop test system provided in the first embodiment, as shown below. Figure 1 As shown, the hardware-in-the-loop test system includes a computer device, a communication device, a debugger, a device under test (DUT), and a test bench. The computer device is connected to the DUT via the communication device, and also to the test bench via the communication device. The DUT is further connected to the test bench via the debugger. In some embodiments, the debugger may include a data parser.

[0050] For example, the computer equipment may include one of the following: a test host, a computer, an industrial control computer, or a server. For example, the communication equipment may include a CAN communication device or a satellite communication device. For example, the device under test may be a vehicle or a processing device within a vehicle; for example, the processing device may include a Battery Management System (BMS) or an Electronic Control Unit (ECU).

[0051] The test bench is connected to the device under test (DUT). The computer equipment is also used to send the operating condition parameters of each operating condition to the test bench connected to the DUT via the communication equipment in response to the test start command to start the test program. The test bench is used to simulate an environment that matches the operating condition parameters of each operating condition so that the DUT can operate in each operating condition.

[0052] Test benches are used to simulate the real-world operating environment of the device under test (DUT). For example, a test bench can provide high and low voltage to the DUT to enable its operation. Alternatively, a test bench can provide the DUT with simulated signals of an engine operating at different speeds and loads, thus providing the DUT with an operating environment under varying speeds and loads.

[0053] Computer equipment can acquire operational data from the device under test (DUT) via communication equipment and determine whether the DUT has passed the test based on whether the operational data is abnormal. For example, the computer equipment may have testing software installed to acquire the DUT's operational data. For example, the DUT outputs CAN messages to the communication equipment, causing the communication equipment to send CAN messages to the computer equipment. The CAN messages include operational data of the DUT under various operating conditions.

[0054] For example, the device under test (DUT) can output program execution data to a debugger, which includes the location and / or execution time of stubs. The debugger then transmits this program execution data to a computer. The DUT can also send its status execution data to the computer via a communication device. For example, this status execution data may include operating data such as voltage, current, temperature, and power consumption.

[0055] In some solutions, a trace debugger can be used, which exports data to an external trace buffer or storage device via a dedicated trace interface. However, trace debuggers are expensive and have limited applicability to hardware-in-the-loop testing.

[0056] Furthermore, during the use of the debugger, the debugger acquires the program execution data of the device under test (DUT) in real time and transmits this data to the computer device in real time. However, the computer device often experiences lag during testing, or it may not support real-time acquisition of program execution data (i.e., the debugger and computer device cannot interact in real time, such as receiving program execution data at preset time points). The computer device may not be able to obtain the program execution data set sent by the debugger during lag, or it may be unable to obtain program execution data outside of the preset time points. This results in the computer device not being able to obtain complete program execution data from the DUT, and often cannot monitor the complete program execution status of the test program on the DUT during testing, leading to low reliability of the DUT test.

[0057] To alleviate the above problems, a new debugger will be provided. This new debugger is not a trace debugger. Research has shown that when the debugger obtains program execution data, it stores the program execution data. In this way, even if the computer device is slow or does not support real-time acquisition of program execution data, the debugger can still send the program execution data stored in its internal storage module to the computer device. This improves the completeness of the computer device's acquisition of the program execution status of the test program in the device under test, thereby improving the reliability of the test of the device under test.

[0058] Based on the above considerations, this application provides a data storage method applied to a data processing chip in a debugger for hardware-in-the-loop testing. The debugger is further configured with a storage module connected to the data processing chip. The method includes: converting program execution data output in real time by the device under test (DUT) conforming to a first communication protocol into program execution data conforming to a second communication protocol; the first communication protocol is a protocol for testing the DUT, and the second communication protocol is a protocol adapted to a computer device; the program execution data is the execution data fed back by stub programs in the test program of the DUT, and multiple stub programs are pre-set at key program positions in the test program of the DUT by instrumentation; storing the program execution data conforming to the second communication protocol in the storage module so that the computer device can obtain the program execution data conforming to the second communication protocol stored in the storage module.

[0059] In this way, after the debugger obtains the program execution data, it stores the program execution data in the storage module. This ensures that even if the computer device lags or does not support real-time acquisition of program execution data, it can still access the stored data. This improves the completeness of the computer device's acquisition of the program's execution status during testing, thereby enhancing the reliability of the test. Furthermore, the debugger connects between the device under test and the computer. Its data processing chip can convert communication protocols, effectively resolving protocol incompatibility issues between the device under test and the computer. No additional configuration is needed to enable the computer to support the first communication protocol, expanding the debugger's application scope. Moreover, the storage module stores program execution data conforming to the second communication protocol. Therefore, when the computer device needs to read program execution data, it forwards the stored second-protocol program execution data without requiring protocol conversion, reducing the latency of the computer device reading the second-protocol program execution data.

[0060] Figure 2 A flowchart illustrating the data storage method provided in the first embodiment is shown below. Figure 2 As shown, this method is applied to a data processing chip in a debugger for hardware-in-the-loop testing. The method includes:

[0061] S201. Convert the program execution data that conforms to the first communication protocol and is output in real time by the device under test into program execution data that conforms to the second communication protocol.

[0062] Among them, the first communication protocol is the protocol for testing the device under test, and the second communication protocol is the protocol adapted to the computer equipment; the program running data is the running data fed back by the stub program in the test program of the device under test, and multiple stub programs are pre-set at the key program positions in the test program of the device under test by inserting stubs.

[0063] For example, a hardware-in-the-loop (HIL) test system can be used to perform HIL testing on the device under test (DUT). During HIL testing of the DUT, multiple operating conditions can be tested. For example, taking a Battery Management System (BMS) as the DUT, these multiple operating conditions can cover various scenarios from battery charging and discharging to fault handling. For instance, these multiple operating conditions may include at least two of the following: slow charging condition, fast charging condition, discharging condition, high temperature condition, low temperature condition, high altitude condition, overvoltage fault condition, overcurrent fault condition, thermal runaway warning condition, battery balancing condition, hibernation condition, and wake-up condition, etc. This application embodiment does not impose any limitations on these conditions.

[0064] For example, the first communication protocol may include a protocol for on-chip testing. Exemplarily, the first communication protocol includes a Joint Test Action Group (JTAG) protocol.

[0065] For example, the second communication protocol may include one of the following: Universal Serial Bus (USB), Video Graphics Array (VGA), High Definition Multimedia Interface (HDMI), etc. For example, the target protocol data includes the USB communication protocol.

[0066] The device under test (DUT) outputs program execution data conforming to a first communication protocol in real time. The data processing chip receives this program execution data in real time, converts it into program execution data conforming to a second communication protocol, and stores the program execution data conforming to the second communication protocol in a storage module. For example, the data processing chip may include a protocol conversion module, which converts the received program execution data conforming to the first communication protocol into program execution data conforming to the second communication protocol and stores the program execution data conforming to the second communication protocol in the storage module.

[0067] In some embodiments, the running data fed back by the piling program may include the running location and running time of the piling program.

[0068] In some embodiments, the execution position of a stub can be the identifier and / or location of the basic test block associated with the stub. In other embodiments, the execution position of a stub can be the line of code in the test program where the stub is located. In some embodiments, a stub can be a program used to report the execution position of the stub. In other embodiments, a stub can be a program used to report the execution position and execution time of the stub.

[0069] In some embodiments, the runtime of the stub program can be the time recorded by a timer in the device under test (DUT). In other embodiments, the runtime of the stub program can be a standard time recorded after the DUT and the computer device have synchronized their times.

[0070] For example, a test program may include several basic test blocks, with a stub program set at the input point (also called the in point or program start point) of each basic test block and a stub program set at the output point (also called the out point or program end point) of each basic test block. Alternatively, the test program can be divided according to the variables to be tested, resulting in multiple basic test blocks, with a stub program set before, after, or both before and after each basic test block.

[0071] For example, critical program locations in a test program typically refer to code segments that have a significant impact on the overall performance and functionality of the program. For example, critical program locations in a test program may include at least one of the following: the location of the core data processing function, the location of the program that outputs the runtime data of the variable under test, the location of the input / output interface, the location of conditional statements, the position before and after loop structures, the location of function calls, the location of exception handling, etc., and this application embodiment does not impose any limitations on this.

[0072] Instrumentation (also known as program instrumentation) involves inserting probes into the program under test while maintaining its original logical integrity. A probe is essentially a code segment (i.e., a stub program) that collects information. It can be an assignment statement or a function call that collects coverage information. By executing the probe, characteristic data of the program's operation (such as the operating data of the device under test) can be emitted. By analyzing this data, the control flow and data flow information of the program can be obtained, and dynamic information such as logical coverage can be obtained, thereby achieving the testing purpose.

[0073] In any embodiment of this application, inserting at least one stub program in a program segment or a location may include inserting the stub program at at least one location before, after, or among several intermediate locations of the program segment or location.

[0074] In some embodiments, a computer device can send the type of the variable to be tested to the device under test (DUT) via a communication device, so that the DUT can determine the critical program location based on the type of the variable and activate the stub program at the critical program location. Exemplarily, the type of the variable to be tested may include temperature, voltage, current, power, and battery state of charge, etc., and this application embodiment does not limit this. In some embodiments, the running data fed back by the stub program in the test program of the DUT may include the running data fed back by the stub program activated in the test program of the DUT. In some embodiments, the type of the variable to be tested can be adjusted according to different operating conditions of the DUT.

[0075] In some embodiments, by providing feedback on the location of the stub program, the computer device can obtain the execution order of the basic test blocks in the stub program's test program. In some embodiments, by providing feedback on the execution time of the stub program, the computer device can obtain the execution timing of the basic test blocks in the stub program's test program.

[0076] S202. The program execution data conforming to the second communication protocol is stored in the storage module so that the computer device can obtain the program execution data conforming to the second communication protocol stored in the storage module.

[0077] In some embodiments, program execution data conforming to the second communication protocol can be stored in the storage module according to a clock signal configured in the computer device. In other embodiments, program execution data conforming to the second communication protocol can be stored in the storage module according to a clock signal pre-configured in the data processing chip. The clock signal can be a waveform signal of a preset frequency, and the storage speed of storing program execution data conforming to the second communication protocol in the storage module can be adjusted by configuring the clock period.

[0078] In some embodiments, the data processing chip may have data interaction capabilities. For example, the data processing chip may include a communication module (e.g., a communication module for a second communication protocol). The communication module is used to read program execution data conforming to the second communication protocol from the storage module and send program execution data conforming to the second communication protocol to the computer device. In the following description, the interaction between the data processing chip and the computer device, such as the data processing chip receiving instructions from the computer device or the data processing chip sending program execution data conforming to the second communication protocol to the computer device, may include the interaction between the communication module and the computer device.

[0079] In some embodiments, the communication bandwidth of the first communication protocol may be less than the communication bandwidth of the second communication protocol. Communication bandwidth refers to the number of bits that can be transmitted per unit time; a larger communication bandwidth allows for the transmission of more data per unit time and supports a faster transmission rate. In other embodiments, the communication bandwidth of the first communication protocol may be equal to the communication bandwidth of the second communication protocol.

[0080] In some embodiments, the data processing chip can actively read program execution data conforming to the second communication protocol and send the program execution data conforming to the second communication protocol to the computer device. For example, the data processing chip can read program execution data conforming to the second communication protocol in real time and send the read program execution data conforming to the second communication protocol to the computer device in real time. As another example, the data processing chip can read program execution data conforming to the second communication protocol stored within a preset time interval and send the program execution data conforming to the second communication protocol stored within the preset time interval to the computer device at preset time intervals.

[0081] In other embodiments, the data processing chip can read program execution data conforming to the second communication protocol according to data read instructions from the computer device, and then send the program execution data conforming to the second communication protocol to the computer device. For example, during hardware-in-the-loop testing, each time the data processing chip receives a data read instruction from the computer device, it can read program execution data that has not yet been read from the storage module and send the read program execution data to the computer device. As another example, after the hardware-in-the-loop test is completed, the data processing chip can receive a data read instruction from the computer device, read all program execution data stored in the storage module, and send the read program execution data to the computer device.

[0082] In this embodiment, data reading and data transmission are performed synchronously. For example, each time the data processing chip reads a preset number of bits of data, it sends that preset number of bits of data to the computer device, and then continues to read the next preset number of bits of data and send that next preset number of bits of data to the computer device, until data reading and transmission are completed.

[0083] For example, the number of bits occupied by program execution data in different stub programs or different feedback cycles of the same stub program is the same. For instance, the number of bits occupied by the execution position of different stub programs or different feedback cycles of the same stub program is the same, while the execution time of different stub programs or different feedback cycles of the same stub program is different, but the number of bits occupied is the same.

[0084] For example, the program execution data of the second communication protocol can be stored in a row-oriented manner. For instance, based on the bandwidth corresponding to the second communication protocol and the clock signal sent by the computer device (the clock signal is a waveform signal of a preset frequency), the maximum number of bits transmitted per cycle in the waveform signal can be determined. The number of data packets of the second communication protocol transmitted each time is determined based on the maximum number of bits transmitted per cycle, and the number of data packets of the second communication protocol transmitted each time is defined as a data block. The number of data packets transmitted each time may include at least one or more feedback program execution data. For example, different data packets may contain the same amount of program execution data.

[0085] In the technical solution provided in this application embodiment, after the debugger obtains the program running data, it stores the program running data in the storage module. Thus, even if the computer device lags or does not support real-time acquisition of program running data, the computer device can still obtain the program running data stored in the storage module. This improves the completeness of the computer device's acquisition of the program running status of the test program in the device under test during the testing process, thereby improving the reliability of the device under test testing. Furthermore, the debugger is connected between the device under test and the computer device. The data processing chip in the debugger can perform communication protocol conversion, effectively solving the protocol incompatibility problem between the device under test and the computer device. No additional configuration is required for the computer device to support the first communication protocol, expanding the application scope of the debugger. Moreover, the storage module stores program running data conforming to the second communication protocol. Therefore, when the computer device needs to read program running data, it forwards the stored program running data of the second communication protocol without performing the protocol conversion step, reducing the latency for the computer device to read the program running data of the second communication protocol.

[0086] Figure 3 A flowchart illustrating the data storage method provided in the second embodiment is shown below. Figure 3 As shown, this method is applied to the data processing chip in the debugger of hardware-in-the-loop testing. Figure 3 Compared to the example Figure 2 The difference in the embodiments is that the storage module includes multiple types of storage units; S202 includes S2021 to S2023.

[0087] S2021. Receive transmission configuration information sent by computer equipment; the transmission configuration information is used to indicate the transmission path of program running data conforming to the second communication protocol.

[0088] In some embodiments, the transmission path may include at least one of the following: a transmission path via random access memory, a real-time transmission path, a transmission path via read-only memory, etc.

[0089] In some embodiments, the transmission configuration information may be sent by the computer device to the data processing chip before the hardware-in-the-loop testing process. For example, the data processing chip can determine, based on the transmission configuration information, that during the hardware-in-the-loop testing process, it will always store and transmit program execution data according to the transmission configuration information.

[0090] In other embodiments, the transmission configuration information may be sent to the data processing chip before and during the hardware-in-the-loop (HIL) testing process. For example, the computer device may dynamically send transmission configuration information to the data processing chip based on its current computing load and / or its transmission needs, so that the data processing chip stores and transmits program execution data according to the latest transmission configuration information of the computer device. For instance, when the computer device needs to focus on processing other tasks, the acquisition of program execution data can be postponed.

[0091] For example, if a computer device's computing load is greater than or equal to a preset load, it indicates severe lag, and it can send transmission configuration information via read-only memory to the data processing chip; if its computing load is less than the preset load but greater than or equal to the set load, it indicates moderate lag, and it can send transmission configuration information via random access memory to the data processing chip; if its computing load is less than the set load, it indicates smooth operation, and it can send transmission configuration information for real-time transmission of program execution data to the data processing chip.

[0092] S2022. Based on the transmission configuration information, determine the target type of the storage unit that stores program execution data conforming to the second communication protocol.

[0093] For example, different transmission configuration information can correspond to different target types. For example, the target type of the storage unit may include Random Access Memory (RAM), cache type, and Read Only Memory (ROM).

[0094] Random access memory can be volatile memory. For example, random access memory can take many forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0095] Read-only memory can be non-volatile memory. For example, read-only memory may include one of the following: Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Ferromagnetic Random Access Memory (FRAM), Flash Memory, Magnetic Surface Memory, Optical Disc, Compact Disc Read-Only Memory (CD-ROM), Magnetic Tape, Floppy Disk, Flash Memory, Optical Memory, High-Density Embedded Non-Volatile Memory, Resistive Random Access Memory (ReRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Graphene Memory, Volatile Memory, etc.

[0096] S2023. Store program execution data conforming to the second communication protocol in the target type storage unit.

[0097] In the technical solution provided in this application embodiment, the transmission path of the second communication protocol program running data is represented by the transmission configuration information sent by the computer device, and the target type of the storage unit is accurately matched accordingly for data storage. In this way, the corresponding storage unit can be adapted to the characteristics of different transmission paths, and data classification storage can be achieved. This not only improves the efficiency of storage resource utilization, but also ensures data integrity and storage stability, avoids problems such as data loss and transmission delay caused by improper selection of storage units, and significantly improves the flexibility and reliability of data storage for different transmission paths.

[0098] In some embodiments, determining the target type of the storage unit storing program execution data conforming to the second communication protocol based on the transmission configuration information may include: determining the target type of the storage unit as a random access memory type when the transmission configuration information indicates that the program execution data conforming to the second communication protocol is transmitted via random access memory.

[0099] For example, the data write rate of the read-only memory should be greater than or equal to the data write rate of the random access memory. For example, the data write rate in the read-only memory should be greater than or equal to the data read rate of the random access memory.

[0100] For example, in the storage module of the debugger, the capacity of the random access memory is greater than the capacity of the cache, and the capacity of the random access memory is less than the capacity of the read-only memory.

[0101] In this way, because the capacity of the random access memory (RAM) is moderate enough to meet the needs of fast storage and retrieval of a certain amount of data, and because of its characteristics, the retrieval speed can also be maintained at a high level, the RAM can satisfy the storage operation of a certain amount of program running data, and meet the situation where the computer device cannot obtain program running data in real time. This allows the computer device to intermittently obtain program running data from the RAM, improving the completeness of the program running data obtained by the computer device, thereby improving the reliability of program running data transmission, and also improving the efficiency of program running data transmission by quickly reading data.

[0102] In some embodiments, determining the target type of a storage unit storing program execution data conforming to the second communication protocol based on transmission configuration information may include: determining the target type of the storage unit as a cache type when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted in real time.

[0103] In this way, the cache has extremely fast read and write speeds. Although its capacity is relatively small, it is sufficient for temporary storage and fast access of real-time data. By storing real-time data in the cache, it can be ensured that the data can be processed and responded to in a timely manner, avoiding system lag or errors caused by data transmission delays, and providing stable and reliable support for applications with extremely high real-time requirements.

[0104] In some embodiments, determining the target type of the storage unit storing program execution data conforming to the second communication protocol based on the transmission configuration information may include: determining the target type of the storage unit as a read-only memory type when the transmission configuration information indicates that the program execution data conforming to the second communication protocol is transmitted via a read-only memory.

[0105] In some embodiments, the capacity of the read-only memory (ROM) can be greater than or equal to the total program execution data of the second communication protocol in a single hardware-in-the-loop test. In this approach, during the hardware-in-the-loop test, the computer device does not need to acquire the program execution data; the computer device can be powered off, and after powering on, it can acquire the program execution data conforming to the second communication protocol from the ROM. This approach is applicable to scenarios where, as an engineer is about to leave work, they can send transmission configuration information indicating that the program execution data conforming to the second communication protocol is being transmitted via ROM to the data processing chip in the debugger through the computer device. The engineer can then shut down the computer device, and the program execution data of the second communication protocol will remain stored in the ROM and will not be lost due to the power outage. The next day, after powering on the computer device, the engineer can send a data read request to the data processing chip in the debugger, causing the data processing chip to read the program execution data of the second communication protocol from the ROM and transmit it back to the computer device.

[0106] In this way, the advantages of high data stability and no data loss when power is off in read-only memory can be fully utilized, thereby improving the reliability of data storage for program execution data of the second communication protocol.

[0107] In the technical solution provided in this application embodiment, the appropriate memory type is dynamically selected according to the transmission configuration information, which can achieve optimal allocation of storage resources and avoid the problems of waste of storage resources and reduced data transmission efficiency caused by using inappropriate memory types. For example, data that needs to be transmitted in real time is stored in a small-capacity but fast cache, data that needs to be stored without power is stored in a large-capacity read-only memory, and data that needs a certain amount of storage and needs to be read quickly is stored in a moderate-capacity random access memory. Thus, the corresponding memory type can be flexibly selected according to the reliability and speed of data transmission, thereby improving the efficiency of storage resource utilization.

[0108] In some embodiments, storing program execution data conforming to the second communication protocol in a target type storage unit includes: when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted through random access memory in the storage module, storing the program execution data conforming to the second communication protocol in a cache in the storage module, and transferring the program execution data conforming to the second communication protocol in the cache to the random access memory.

[0109] In some implementations, data read from the cache can be validated, reducing the accuracy of data transmission.

[0110] In some embodiments, storing program execution data conforming to the second communication protocol in a target type storage unit includes: storing the program execution data conforming to the second communication protocol in a cache in a storage module when the transmission configuration information indicates that the program execution data conforming to the second communication protocol is transmitted in real time.

[0111] In some embodiments, storing program execution data conforming to the second communication protocol in a target type storage unit includes: when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted through a read-only memory in the storage module, storing the program execution data conforming to the second communication protocol in a cache in the storage module, transferring the program execution data conforming to the second communication protocol in the cache to a random access memory in the storage module, and transferring the program execution data conforming to the second communication protocol in the random access memory to a read-only memory.

[0112] In some embodiments, the read-only memory may include a ferroelectric memory, the read / write speed of which is greater than or equal to the read / write speed of the random access memory.

[0113] In the technical solution provided in this application embodiment, the data after the data processing chip converts the protocol is first written to a cache, and then read from the cache and written to the random access memory (RAM). The write latency of the cache is lower than that of the RAM, and the write latency of the RAM is lower than that of the read-only memory (ROM). Therefore, the cache can immediately respond to the data storage of the data processing chip. Compared to the solution of directly writing the data after the data processing chip converts the protocol to the RAM, or compared to the solution of directly writing the data after the data processing chip converts the protocol to the ROM, the data processing chip does not require high latency. By waiting for the data to be written to be completed before proceeding to the next operation, the processing efficiency of the data processing chip is improved. Furthermore, by writing random access memory (RAM) data into read-only memory (ROM), which requires page-by-page writing, multiple small data items stored in RAM can be merged into a complete page and written to ROM page by page. Compared to directly writing cached data to ROM, this reduces the number of ROM writes. This not only reduces the risk of ROM aging caused by the ROM write count limitation and improves ROM lifespan, but also increases ROM write efficiency.

[0114] In some embodiments, transferring cached program execution data conforming to the second communication protocol to random access memory includes: receiving a clock signal sent by a computer device; the clock signal being a waveform signal of a preset frequency; and transferring the cached program execution data conforming to the second communication protocol to random access memory at a preset frequency according to the waveform signal of the preset frequency and a pre-configured number of bytes written to random access memory each time. The method further includes: sending the program execution data conforming to the second communication protocol from random access memory to the computer device at a preset frequency according to the waveform signal of the preset frequency and a pre-configured number of bytes read from random access memory each time.

[0115] In some implementations, the clock signal may include a Serial Peripheral Interface (SPI) clock signal. For example, both the computer device and the debugger may include an SPI interface to allow the computer device to send an SPI clock signal to the debugger. For example, the computer device may implement the SPI interface via an expansion card or a USB adapter.

[0116] The SPI clock signal is a periodic signal generated by the master device (i.e., the computer device) to synchronize data transmission between the master and slave devices (i.e., the debugger). The SPI clock signal controls the rhythm and timing of data transmission between the master and slave devices, ensuring that both parties can accurately send and receive data.

[0117] A waveform signal with a preset frequency may include a periodic waveform signal with a preset frequency. For example, the waveform signal may include a square wave signal.

[0118] In some embodiments, the data processing chip may include a random access transfer processing module. When the communication module of the data processing chip receives transmission configuration information indicating that program execution data conforming to a second communication protocol is being transmitted through random access memory, it may send a data transfer instruction to the random access transfer processing module, causing the module to transfer data from its cache to the random access memory. In some embodiments, the SPI interface may transmit a clock signal to the random access transfer processing module.

[0119] In some embodiments, data can be written to the random access memory at each rising or falling edge of a waveform signal at a preset frequency, according to the number of bytes written to the random access memory each time.

[0120] In the technical solution provided in this application embodiment, a waveform signal with a preset frequency is used as a reference to precisely control the rhythm of data transfer to random access memory (RAM), avoiding data loss and misalignment caused by timing disorder, ensuring that program running data is transferred to RAM completely and orderly, and improving the accuracy of data transfer from cache to RAM; transferring data to RAM according to the number of bytes written can fully utilize the high-speed read and write characteristics of RAM, reduce the number of data transfer interactions, reduce transfer latency, and improve the timeliness of data transfer; and sending data to the computer device according to the waveform signal with the preset frequency and the pre-configured number of bytes read from RAM each time, thereby improving the correctness and synchronization of data sent by the data processing chip to the computer device, and thus improving the reliability of data transmission.

[0121] In some embodiments, transferring program execution data conforming to a second communication protocol from random access memory to read-only memory includes: receiving a clock signal sent by a computer device; the clock signal being a waveform signal of a preset frequency; and transferring the program execution data conforming to the second communication protocol from random access memory to read-only memory at a preset frequency according to the waveform signal of the preset frequency and a pre-configured number of bytes written to read-only memory each time. The method further includes: sending the program execution data conforming to the second communication protocol from read-only memory to the computer device at a preset frequency according to the waveform signal of the preset frequency and a pre-configured number of bytes read from read-only memory each time.

[0122] In some embodiments, the data processing chip may include a read-only transfer processing module. When the communication module of the data processing chip receives transmission configuration information indicating that program execution data conforming to a second communication protocol is being transmitted via read-only memory, it may send data transfer instructions to both the random access transfer processing module and the read-only memory. This causes the random access transfer processing module to transfer data from its cache to the random access memory, and the read-only transfer processing module to transfer data from the random access memory to the read-only memory. In some embodiments, the SPI interface may transmit a clock signal to the read-only transfer processing module.

[0123] In some implementations, data can be written to the read-only memory at each rising or falling edge of a waveform signal at a preset frequency, according to the number of bytes written to the read-only memory each time.

[0124] In some implementations, the number of bytes written to the read-only memory each time can be the same as the number of bytes written to the random access memory each time. This ensures a stable and synchronized transmission rhythm for data flow between different storage media by maintaining a uniform preset frequency waveform signal. This effectively avoids timing errors, data loss, or misalignment during data transmission, greatly guaranteeing data integrity and accuracy. Furthermore, the design of writing the same number of bytes simplifies the control logic and configuration management of data transmission, reducing the complexity of system design and development costs.

[0125] In the technical solution provided in this application embodiment, based on a waveform signal of a preset frequency, the rhythm of data transfer to read-only memory can be precisely controlled, avoiding data loss and misalignment caused by timing disorder. This ensures that program running data is transferred to read-only memory completely and orderly, improving the accuracy of data transfer from random access memory to read-only memory. Furthermore, transferring data to read-only memory according to the number of bytes written can fully utilize the high-speed read / write characteristics of read-only memory, reducing the number of data transfer interactions, lowering transfer latency, and improving the timeliness of data transfer. Moreover, based on the waveform signal of the preset frequency and the pre-configured number of bytes read from read-only memory each time, data is sent to the computer device, thereby improving the correctness and synchronization of data transmission from the data processing chip to the computer device, and thus improving the reliability of data transmission.

[0126] In some embodiments, after S202, the following steps may also be performed: reading program execution data conforming to the second communication protocol from the storage module, and sending program execution data conforming to the second communication protocol to the computer device. In some embodiments, when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted via random access memory, data is read from random access memory; when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted in real time, data is read from a cache; when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted via read-only memory, data is read from read-only memory.

[0127] In some embodiments, any two of the following can be the same: the number of bytes written to read-only memory each time, the number of bytes written to random access memory each time, and the number of bytes transferred to computer device each time.

[0128] the following Figures 4 to 6 The following embodiment illustrates the process of transmitting program execution data conforming to the second communication protocol:

[0129] Figure 4 A flowchart illustrating the data storage method provided in the third embodiment is shown below. Figure 4As shown, this method is applied to the data processing chip in the debugger of hardware-in-the-loop testing. Figure 4 Compared to the example Figure 2 The difference in the embodiments is that S203 to S204 are included after S202.

[0130] S203. When the program execution data conforming to the second communication protocol is configured to be transmitted through the target memory in the storage module, during the hardware-in-the-loop test, the program execution data conforming to the second communication protocol in the target memory is read according to each received target data read request.

[0131] The target memory includes random access memory or read-only memory.

[0132] In some implementations, the storage module includes random access memory, a cache, and read-only memory; the capacity of the random access memory is greater than the capacity of the cache but less than the capacity of the read-only memory.

[0133] In some implementations, the computer can send target data read requests periodically or aperiodically, and correspondingly, the data processing chip can receive target data read requests periodically or aperiodically.

[0134] In some implementations, the data processing chip can record the latest running time in the transmitted program running data each time it transmits program running data conforming to the second communication protocol. The recorded latest running time is updated as the number of transmissions increases, so that when transmitting program running data conforming to the second communication protocol for the next time, the program running data between the next running time of the recorded latest running time and the latest running time in the storage module is determined as the program running data to be transmitted next time.

[0135] In other implementations, the data processing chip can record the last read address of the transmitted program execution data each time it transmits program execution data conforming to the second communication protocol. The recorded last read address is updated as the number of transmissions increases, so that when transmitting program execution data conforming to the second communication protocol for the next time, the program execution data between the next address of the recorded last read address and the address last written in the storage module is determined as the program execution data to be transmitted next time.

[0136] S204. Send the read program execution data conforming to the second communication protocol to the computer device.

[0137] In the technical solution provided in this application embodiment, when the target memory is random access memory (RAM), the capacity of the RAM is moderate. This avoids the problem of insufficient data storage due to insufficient storage capacity, which would prevent the computer device from intermittently sending target data read requests. It also prevents resource waste due to excessive capacity. Furthermore, the fast read performance of RAM allows the data processing chip to quickly read data from RAM and send it to the computer device after receiving the target data read request from the computer device, greatly improving the timeliness of data interaction and ensuring the efficiency of data transmission during the testing process. When the target memory is read-only memory (ROM), the program execution data stored in ROM can also be obtained during hardware-in-the-loop testing, avoiding the inability to read program execution data in ROM during hardware-in-the-loop testing and improving the timeliness of data transmission.

[0138] In some embodiments, reading program execution data conforming to the second communication protocol from the target memory according to each received target data read request includes: determining the target read address of the program execution data conforming to the second communication protocol in the target memory based on the latest execution time of the program execution data already acquired by the computer device carried in each received target data read request; and reading the program execution data conforming to the second communication protocol from the target memory according to the target read address.

[0139] In some implementations, the latest execution time in the program execution data already acquired by the computer device can be used to determine the end address of the program execution data corresponding to the latest execution time. The target read address can then be determined based on this end address of the program execution data corresponding to the latest execution time and the end address of the most recently stored program execution data. For example, all addresses between these two end addresses can be determined as the target read address, or both end addresses can be used as the target read address.

[0140] In some implementations, the program running data between the end address of the program running data corresponding to the latest running time and the end address of the latest stored program running data can be determined as the program running data that conforms to the second communication protocol read this time.

[0141] In the technical solution provided in this application embodiment, by carrying the latest running time of the program running data already acquired by the computer device in the target data reading request, not only does the data processing chip not need to record the latest time of the program running data sent each time, reducing the internal resource occupation of the data processing chip and avoiding the computational overhead caused by frequent recording and updating of time; it also avoids the problem that the computer device does not acquire the program running data even though the data processing chip has sent the program running data, thus improving the reliability of data transmission.

[0142] In some embodiments, after receiving a target data read request and sending the read program running data conforming to the second communication protocol to the computer device, the data processing chip may perform the following steps: upon receiving a data reception success instruction sent by the computer device, determine that the transmission of each program running data conforming to the second communication protocol has been completed; upon receiving a retransmission instruction for program running data for at least one runtime sent by the computer device, determine a set read address for the program running data for at least one runtime; according to the set read address, read the program running data conforming to the second communication protocol for at least one runtime from the target memory, and send the program running data conforming to the second communication protocol for at least one runtime to the computer device.

[0143] For example, each runtime in at least one runtime can be a runtime in each program runtime data. If the computer device sends a retransmission instruction for program runtime data for at least one runtime, it indicates that the computer device has failed to receive program runtime data for at least one runtime. In this case, a retransmission mechanism can be used to cause the data processing chip to retransmit the program runtime data for at least one runtime to the computer device.

[0144] In the technical solution provided in this application embodiment, the successful data reception instruction confirms that the transmission of program running data conforming to the second communication protocol has been completed each time. The retransmission instruction for program running data at least one running time can accurately determine the set read address, read from the target memory and retransmit program running data at least one running time, thereby realizing reliable confirmation and efficient retransmission of program running data transmission, effectively ensuring the integrity and accuracy of data transmission, and improving the reliability of program running data transmission.

[0145] Figure 5 A flowchart illustrating the data storage method provided in the fourth embodiment is shown below. Figure 5 As shown, this method is applied to the data processing chip in the debugger of hardware-in-the-loop testing. Figure 5 Compared to the example Figure 2The difference in the embodiment is that S205 is included after S202.

[0146] S205. When the program execution data conforming to the second communication protocol is configured for real-time transmission, the program execution data of the second communication protocol stored in the cache of the storage module is sent to the computer device in real time.

[0147] In the technical solution provided in this application embodiment, when the program running data conforming to the second communication protocol is configured for real-time transmission, the program running data cached in the storage module can be sent to the computer device in real time, which greatly shortens the data transmission delay time, realizes real-time data interaction and processing, and improves data transmission efficiency. Furthermore, real-time transmission of program running data is only performed when the program running data conforming to the second communication protocol is configured for real-time transmission, avoiding real-time transmission when it is not configured for real-time transmission. This not only reduces the operating load of the data processing chip, but also avoids the problem of data loss caused by the computer device not supporting real-time acquisition, thus improving the reliability of data transmission.

[0148] Figure 6 A flowchart illustrating the data storage method provided in the fifth embodiment is shown below. Figure 6 As shown, this method is applied to the data processing chip in the debugger of hardware-in-the-loop testing. Figure 6 Compared to the example Figure 2 The difference in the embodiments is that S206 to S208 are included after S202.

[0149] S206. When the program execution data conforming to the second communication protocol is configured to be transmitted via read-only memory, detect the connection status between the debugger and the computer device.

[0150] In some embodiments, the connection status between the debugger and the computer device can be detected starting when hardware-in-the-loop testing begins. In other embodiments, the connection status between the debugger and the computer device can be detected starting when the debugger is enabled.

[0151] S207. When the connection status is that the debugger is disconnected from the computer device during the hardware-in-the-loop test and successfully reconnects to the computer device after the hardware-in-the-loop test is completed, read all the program execution data stored in the read-only memory that conforms to the second communication protocol according to the predetermined data read request sent by the computer device.

[0152] In some implementations, an indicator light can be set in the debugger to determine that the hardware-in-the-loop test has ended if the data processing chip does not receive program execution data conforming to the first communication protocol within a set time period, or if the position of the stub program in the program execution data received by the data processing chip has a preset number of loops. The data processing chip can control the indicator light to turn on when the hardware-in-the-loop test ends.

[0153] S208. Send all stored program execution data conforming to the second communication protocol to the computer device.

[0154] In this implementation, a predetermined data read request can be used to transmit all program execution data stored in the read-only memory that conforms to the second communication protocol, simplifying the data acquisition process and improving data transmission efficiency.

[0155] In the technical solution provided in this application embodiment, when the program running data is configured to be transmitted through a read-only memory, even if the debugger and the computer device are disconnected during hardware-in-the-loop testing, the program running data conforming to the second communication protocol can be completely retained by relying on the stable storage performance of the read-only memory. After the test is completed and the connection between the debugger and the computer device is restored, all the stored program running data is accurately transmitted back according to the predetermined data reading request of the computer device, which effectively avoids the risk of data loss and improves the comprehensiveness of the program running data obtained by the computer device.

[0156] Figure 7 A schematic diagram of the hardware-in-the-loop test system provided in the second embodiment is shown below. Figure 7 As shown, the hardware-in-the-loop test system includes a device under test (DUT), a computer device, and a debugger. The debugger includes a data processing chip and a storage module. Exemplarily, the data processing chip is configured to perform the methods of any of the above embodiments.

[0157] In some embodiments, the device under test (DUT) sends program execution data conforming to a first communication protocol to the data processing chip; the first communication protocol is a protocol for testing the DUT; the program execution data is the execution data fed back by stub programs in the test program of the DUT, and multiple stub programs are pre-set at key program positions in the test program of the DUT by stubs; the data processing chip can convert the program execution data conforming to the first communication protocol into program execution data conforming to a second communication protocol, and store the program execution data conforming to the second communication protocol in a storage device; the second communication protocol is a protocol adapted to computer equipment; the data processing chip can also read the program execution data of the second communication protocol in the storage device and send the program execution data of the second communication protocol to the computer equipment.

[0158] Figure 8 A schematic diagram of the hardware-in-the-loop test system provided in the third embodiment is shown below. Figure 8 As shown, Figure 8 The system shown in the embodiment and Figure 7 The difference in the system shown in the embodiment is that the storage module includes a cache, random access memory, and read-only memory.

[0159] The data processing chip receives transmission configuration information sent by the computer device. When the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted through random access memory, the chip stores the program execution data conforming to the second communication protocol in a cache and transfers the program execution data of the second communication protocol in the cache to the random access memory. When the chip receives a data read instruction sent by the computer device, it reads the program execution data of the second communication protocol from the random access memory and sends the program execution data of the second communication protocol to the computer device.

[0160] When the transmission configuration information indicates that the program execution data conforming to the second communication protocol is transmitted in real time, the program execution data conforming to the second communication protocol is stored in a cache; then the program execution data of the second communication protocol in the cache is read and sent to the computer device.

[0161] When the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted through read-only memory, the program execution data conforming to the second communication protocol is stored in a cache, and the program execution data conforming to the second communication protocol in the cache is transferred to random access memory, and the program execution data conforming to the second communication protocol in random access memory is transferred to read-only memory; when a data read instruction is received from a computer device, the program execution data conforming to the second communication protocol in read-only memory is read, and the program execution data conforming to the second communication protocol is sent to the computer device.

[0162] In the hardware testing system provided in this application embodiment, the hardware part uses a data processing chip (including protocol conversion function) to connect JTAG program execution data to the data processing chip via a debug port (e.g., a JTAG interface), and the data processing chip converts it into USB data. Data read / write commands are issued by the computer device to the data processing chip. USB data can be forwarded through a buffer, through random access memory (RAM), or through read-only memory (ROM). The computer device can send an SPI clock signal to the data processing chip to control the data processing chip to write to RAM and ROM via the SPI clock signal. In the software part, the computer device controls the writing to RAM and ROM via the SPI clock signal, and sends data to the computer device. The data processing chip converts the received JTAG program execution data into USB data and forwards it to the computer device so that the computer device can parse the USB data and obtain the program execution data. Real-time forwarding, first-level forwarding, and second-level forwarding are configured in the debugger. In real-time forwarding, data is forwarded through a buffer; in first-level forwarding, data is forwarded through RAM; and in second-level forwarding, data is forwarded through ROM. When the computer host has poor performance or a high load, which may affect the timeliness of data reading and storage programs, configure Level 1 forwarding. When the computer device is shut down during hardware testing, configure Level 2 forwarding.

[0163] Based on the same inventive concept, this application also provides a data storage device for implementing the data storage method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more data storage device embodiments provided below can be found in the limitations of the data storage method described above, and will not be repeated here.

[0164] In one exemplary embodiment, Figure 9 A schematic diagram of the structure of a data storage device provided in some embodiments, such as Figure 9 As shown, the data storage device 900 includes:

[0165] The protocol conversion module 901 is used to convert the program execution data output in real time by the device under test (DUT) conforming to the first communication protocol into program execution data conforming to the second communication protocol. The first communication protocol is a protocol for testing the DUT, and the second communication protocol is a protocol adapted to computer equipment. The program execution data is the execution data fed back by the stub program in the test program of the DUT. Multiple stub programs are pre-set at the key program positions in the test program of the DUT by inserting stubs.

[0166] The storage control module 902 is used to store program execution data conforming to the second communication protocol in the storage module, so that the computer device can obtain the program execution data conforming to the second communication protocol stored in the storage module.

[0167] In some embodiments, the storage module includes multiple types of storage units; the protocol conversion module 901 includes a receiving unit, a storage type determining unit, and a storage control unit. The receiving unit is used to receive transmission configuration information sent by the computer device; the transmission configuration information is used to indicate the transmission path of program running data conforming to the second communication protocol; the storage type determining unit is used to determine the target type of the storage unit for storing program running data conforming to the second communication protocol based on the transmission configuration information; the storage control unit stores the program running data conforming to the second communication protocol in the storage unit of the target type.

[0168] In some embodiments, the storage type determination unit is further configured to determine the target type of the storage unit as random access memory when the transmission configuration information indicates that program running data conforming to the second communication protocol is transmitted through random access memory.

[0169] In some embodiments, the storage type determination unit is further configured to determine the target type of the storage unit as a cache type when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted in real time.

[0170] In some embodiments, the storage type determination unit is further configured to determine that the target type of the storage unit is a read-only memory type when the transmission configuration information indicates that program running data conforming to the second communication protocol is transmitted through a read-only memory.

[0171] In some embodiments, the storage control unit is further configured to, when the transmission configuration information indicates that program running data conforming to the second communication protocol is transmitted through the random access memory in the storage module, store the program running data conforming to the second communication protocol in the cache of the storage module, and transfer the program running data conforming to the second communication protocol in the cache to the random access memory.

[0172] In some embodiments, the storage control unit is further configured to store the program execution data conforming to the second communication protocol in the cache of the storage module when the transmission configuration information indicates that the program execution data conforming to the second communication protocol is transmitted in real time.

[0173] In some embodiments, the storage control unit is further configured to, when the transmission configuration information indicates that program running data conforming to the second communication protocol is transmitted through the read-only memory in the storage module, store the program running data conforming to the second communication protocol in the cache of the storage module, transfer the program running data conforming to the second communication protocol in the cache to the random access memory in the storage module, and transfer the program running data conforming to the second communication protocol in the random access memory to the read-only memory.

[0174] In some embodiments, the receiving unit is further configured to receive a clock signal sent by the computer device; the clock signal is a waveform signal of a preset frequency; the storage control unit is further configured to transfer program running data conforming to the second communication protocol in the cache to the random access memory at the preset frequency according to the waveform signal of the preset frequency and the number of bytes written to the random access memory each time, and the data storage device 900 further includes a sending module, which is configured to send the program running data conforming to the second communication protocol in the random access memory to the computer device at the preset frequency according to the waveform signal of the preset frequency and the number of bytes read from the random access memory each time, and the number of bytes read from the random access memory each time.

[0175] In some embodiments, the receiving unit is further configured to receive a clock signal sent by the computer device; the clock signal is a waveform signal of a preset frequency; the storage control unit is further configured to transfer program execution data conforming to the second communication protocol in the random access memory to the read-only memory at the preset frequency according to the waveform signal of the preset frequency and the number of bytes written to the read-only memory each time; the data storage device 900 further includes a sending module, which is configured to send the program execution data conforming to the second communication protocol in the read-only memory to the computer device at the preset frequency according to the waveform signal of the preset frequency and the number of bytes read from the read-only memory each time.

[0176] In some embodiments, the data storage device 900 further includes a reading module and a sending module; the reading module is configured to read program execution data conforming to the second communication protocol from the target memory during the hardware-in-the-loop test, based on each received target data read request, when program execution data conforming to the second communication protocol is configured to be transmitted through a target memory in the storage module; the target memory includes random access memory or read-only memory; the sending module is configured to send the read program execution data conforming to the second communication protocol to the computer device.

[0177] In some embodiments, the reading module includes an address determination unit and a reading unit; the address determination unit is used to determine the target reading address of the program running data conforming to the second communication protocol in the target memory based on the latest running time in the program running data already acquired by the computer device carried in each received target data reading request; the reading unit is used to read the program running data conforming to the second communication protocol from the target memory according to the target reading address.

[0178] In some embodiments, the data storage device 900 further includes a retransmission module, which is configured to: upon receiving a data reception success instruction sent by the computer device, determine that the transmission of each batch of program running data conforming to the second communication protocol has been completed; upon receiving a retransmission instruction for program running data at least one runtime period sent by the computer device, determine a set read address for the program running data at the at least one runtime period; read the program running data conforming to the second communication protocol at the at least one runtime period from the target memory according to the set read address, and send the program running data conforming to the second communication protocol at the at least one runtime period to the computer device.

[0179] In some embodiments, the data storage device 900 further includes a sending module; when the program execution data conforming to the second communication protocol is configured for real-time transmission, the module sends the program execution data of the second communication protocol stored in the cache of the storage module to the computer device in real time.

[0180] In some embodiments, the data storage device 900 further includes a connection status detection module, a reading module, and a sending module; the status detection module is used to detect the connection status between the debugger and the computer device when the program execution data conforming to the second communication protocol is configured to be transmitted via a read-only memory; the reading module is used to read all the program execution data conforming to the second communication protocol stored in the read-only memory according to the predetermined data reading request sent by the computer device when the connection status is that the debugger is disconnected from the computer device during the hardware-in-the-loop test and successfully reconnected to the computer device after the hardware-in-the-loop test is completed; the sending module is used to send all the stored program execution data conforming to the second communication protocol to the computer device.

[0181] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0182] Each module in the aforementioned data storage device can be implemented entirely or partially through programs, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in the debugger, or stored as programs in the debugger's memory, so that the processor can call and execute the operations corresponding to each module.

[0183] In one exemplary embodiment, Figure 10 This is a schematic diagram of a debugger provided for some embodiments. The debugger includes a data processing chip and a storage module. The data processing chip includes a processor and a memory. The debugger may also include at least one of the following: an input / output interface, a communication interface, indicator lights, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, indicator lights, and input device are connected to the system bus via the input / output interface. The processor of the debugger provides computing and control capabilities. The memory of the debugger includes a non-volatile storage medium and / or internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the debugger is used for data exchange between the processor and external devices. The communication interface of the debugger is used for wired or wireless communication with external terminals. Wireless communication can be implemented through Wireless Fidelity (WIFI), mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a data storage method. The debugger's indicator lights are used to create a visually visible image, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The debugger's input device can be a touch layer covering the display screen, or buttons, a trackball, or a touchpad set on the debugger's housing, or an external keyboard, touchpad, or mouse, etc.

[0184] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the debugger to which the present application is applied. A specific debugger may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0185] For example, a debugger includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method of any of the above embodiments.

[0186] In one embodiment, a computer-readable storage medium is provided, wherein a computer program, when executed by a processor, implements the steps of the method provided in any of the above embodiments.

[0187] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the method provided in any of the above embodiments.

[0188] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the methods described above.

[0189] The processor, functional modules, or functional units in any embodiment of this application may include an integration of one or more of the following: a general-purpose processor, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field-programmable gate array (FPGA), a central processing unit (CPU), a graphics processing unit (GPU), an embedded neural network processing unit (NPU), a controller, a microcontroller, a microprocessor, a programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, a quantum computing-based data processing logic unit, an artificial intelligence (AI) processor, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0190] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0191] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data storage method, characterized in that, A data processing chip used in a debugger for hardware-in-the-loop testing, wherein the debugger is further configured with a storage module connected to the data processing chip; the method includes: The program execution data output in real time by the device under test (DUT) conforming to the first communication protocol is converted into program execution data conforming to the second communication protocol; the first communication protocol is a protocol for testing the DUT, and the second communication protocol is a protocol adapted to computer equipment; the program execution data is the execution data fed back by the stub program in the test program of the DUT, and multiple stub programs are pre-set at the key program positions in the test program of the DUT by inserting stubs; Receive transmission configuration information sent by the computer device; When the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted through the read-only memory in the storage module, the program execution data conforming to the second communication protocol is stored in the cache in the storage module, and the program execution data conforming to the second communication protocol in the cache is transferred to the random access memory in the storage module, and the program execution data conforming to the second communication protocol in the random access memory is transferred to the read-only memory, so that the computer device can obtain the program execution data conforming to the second communication protocol stored in the read-only memory.

2. The method according to claim 1, characterized in that, The storage module includes various types of storage units, and the method further includes at least one of the following: When the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted in real time, the target type of the storage unit is determined to be a cache type, and the program execution data conforming to the second communication protocol is stored in the cache type storage unit; When the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted through the random access memory, the target type of the storage unit is determined to be a random access memory type, and the program execution data conforming to the second communication protocol is stored in the storage unit of the random access memory type.

3. The method according to claim 1, characterized in that, The method further includes: When the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted in real time, the program execution data conforming to the second communication protocol is stored in the cache of the storage module so that the computer device can obtain the program execution data conforming to the second communication protocol stored in the cache.

4. The method according to claim 1, characterized in that, The method further includes: When the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted through the random access memory, the program execution data conforming to the second communication protocol is stored in the cache of the storage module, and the program execution data conforming to the second communication protocol in the cache is transferred to the random access memory in the storage module, so that the computer device can obtain the program execution data conforming to the second communication protocol stored in the random access memory.

5. The method according to any one of claims 1 to 4, characterized in that, The step of transferring the program execution data conforming to the second communication protocol in the cache to the random access memory in the storage module includes: Receives a clock signal sent by the computer device; the clock signal is a waveform signal of a preset frequency; Based on the waveform signal of the preset frequency and the number of bytes written to the random access memory each time, the program running data conforming to the second communication protocol in the cache is transferred to the random access memory at the preset frequency. The method further includes: sending program execution data conforming to the second communication protocol in the random access memory to the computer device at the preset frequency, based on the waveform signal of the preset frequency and the number of bytes read from the random access memory each time, according to the preset frequency.

6. The method according to any one of claims 1 to 4, characterized in that, The step of transferring the program execution data conforming to the second communication protocol from the random access memory to the read-only memory includes: Receives a clock signal sent by the computer device; the clock signal is a waveform signal of a preset frequency; Based on the waveform signal of the preset frequency and the number of bytes written to the read-only memory each time, the program running data conforming to the second communication protocol in the random access memory is transferred to the read-only memory at the preset frequency. The method further includes: sending program execution data conforming to the second communication protocol in the read-only memory to the computer device at the preset frequency according to the waveform signal of the preset frequency and the number of bytes read from the read-only memory each time.

7. The method according to any one of claims 1 to 4, characterized in that, The method further includes: When program execution data conforming to the second communication protocol is configured to be transmitted through the target memory in the storage module, during the hardware-in-the-loop test, program execution data conforming to the second communication protocol is read from the target memory according to each received target data read request; the target memory includes random access memory or read-only memory; Send the read program execution data conforming to the second communication protocol to the computer device.

8. The method according to claim 7, characterized in that, The step of reading program execution data conforming to the second communication protocol from the target memory according to each received target data read request includes: Based on the latest running time of the program running data already acquired by the computer device carried in each received target data read request, determine the target read address of the program running data conforming to the second communication protocol in the target memory; According to the target read address, program execution data conforming to the second communication protocol is read from the target memory.

9. The method according to claim 7, characterized in that, The method further includes: Upon receiving a data reception success instruction from the computer device, it is determined that each batch of program execution data conforming to the second communication protocol has been successfully transmitted. Upon receiving a retransmission instruction for program execution data for at least one runtime period sent by the computer device, determine the designated read address for the program execution data for the at least one runtime period; According to the set read address, read the program running data conforming to the second communication protocol at the at least one runtime from the target memory, and send the program running data conforming to the second communication protocol at the at least one runtime to the computer device.

10. The method according to any one of claims 1 to 4, characterized in that, The method further includes: When the program execution data conforming to the second communication protocol is configured for real-time transmission, the program execution data of the second communication protocol stored in the cache of the storage module is sent to the computer device in real time.

11. The method according to any one of claims 1 to 4, characterized in that, The method further includes: When the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted through the read-only memory, the connection status between the debugger and the computer device is detected; When the connection state is such that the debugger is disconnected from the computer device during the hardware-in-the-loop test and successfully reconnects to the computer device after the hardware-in-the-loop test is completed, all program execution data stored in the read-only memory that conforms to the second communication protocol is read according to the predetermined data read request sent by the computer device. Send all stored program execution data conforming to the second communication protocol to the computer device.

12. A hardware-in-the-loop testing system, characterized in that, The hardware-in-the-loop test system includes: a device under test, a computer device, and a debugger; the debugger includes a data processing chip and a storage module. The device under test (DUT) is used to send program execution data conforming to a first communication protocol to the data processing chip; the first communication protocol is a protocol for testing the DUT; the program execution data is the execution data fed back by the stub program in the test program of the DUT, and multiple stub programs are pre-set at the key program positions in the test program of the DUT by inserting stubs; The data processing chip is used to receive transmission configuration information sent by the computer device; convert program execution data conforming to the first communication protocol into program execution data conforming to the second communication protocol; when the transmission configuration information indicates that program execution data conforming to the second communication protocol is transmitted through the read-only memory in the storage module, the program execution data conforming to the second communication protocol is stored in the cache in the storage module, the program execution data conforming to the second communication protocol in the cache is transferred to the random access memory in the storage module, and the program execution data conforming to the second communication protocol in the random access memory is transferred to the read-only memory; the second communication protocol is a protocol adapted to the computer device; The data processing chip is also used to read program execution data conforming to the second communication protocol from the storage module, so that the computer device can obtain the program execution data conforming to the second communication protocol stored in the storage module.

13. A data storage device, characterized in that, The data storage device includes: The protocol conversion module is used to convert the program execution data output in real time by the device under test (DUT) conforming to the first communication protocol into program execution data conforming to the second communication protocol. The first communication protocol is the protocol for testing the DUT, and the second communication protocol is the protocol adapted to the computer equipment. The program execution data is the execution data fed back by the stub program in the test program of the DUT. Multiple stub programs are pre-set at the key program positions in the test program of the DUT by inserting stubs. The storage control module is configured to receive transmission configuration information sent by the computer device; when the transmission configuration information indicates that program running data conforming to the second communication protocol is transmitted through the read-only memory in the storage module, the module stores the program running data conforming to the second communication protocol in the cache of the storage module, transfers the program running data conforming to the second communication protocol in the cache to the random access memory in the storage module, and transfers the program running data conforming to the second communication protocol in the random access memory to the read-only memory, so that the computer device can obtain the program running data conforming to the second communication protocol stored in the read-only memory.

14. A debugger comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 11.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 11.

16. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 11.

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