Data processing method and device of storage device, medium and computer equipment

Abstract

The invention provides a data processing method and device of a storage device, a medium and computer equipment. The data processing method comprises the following steps: analyzing a reading request initiated by a user, and obtaining a logical addresses to be read; determining c L2P mapping tables associated with the a logical addresses according to the range of the a logical addresses, wherein c is a positive integer greater than or equal to 1; backing up an original mapping relation of the c L2P mapping tables; b latest mapping relations of a temporary information layer are updated to the c L2P mapping tables, and the original mapping relations of the c L2P mapping tables are covered; querying the updated c L2P mapping tables according to the reading request, obtaining physical addresses corresponding to the a logical addresses, and reading data; and after the reading is completed, restoring the backed-up original mapping relation to the c L2P mapping tables. Through the mapping management process of the scheme, redundancy check can be avoided, accurate locking of an updating range is realized, the check times are greatly reduced, physical limitation of bandwidth is released, and delay is greatly reduced.

Description

Technical Field

[0001] The present invention relates to a data processing method, apparatus, medium and computer device for a storage device, and belongs to the technical field of data processing methods for NandFlash memories. Background Art

[0002] Nand Flash is a non-volatile storage medium widely used in storage products such as SD, eMMC, UFS, and SSD. Its core management module is the FTL (Flash Translation Layer), and the FTL is responsible for converting the logical address of the host into a physical address and performing functions such as wear leveling and garbage collection. In the FTL algorithm, the mapping relationship between the logical address, such as 512B or 4KB, and the physical address is usually divided into two layers: one is the temporary information layer, also called temp info, and temp info stores the mapping relationship of a small number of the latest logical addresses to physical addresses; the other is the logical-to-physical address mapping table, also called the L2P table, and the L2P table stores all mapping relationships. When there is a mapping of a certain logical address in temp info, the data at the corresponding address in the L2P table is old data. The traditional logic for reading data is to first check whether the target logical address exists in temp info: if it exists, the mapping of temp info is used; if it does not exist, the L2P table is queried.

[0003] The traditional logic for reading data has certain performance bottlenecks. For example, when a user reads a logical addresses and there are b mapping relationships recorded in temp info, a×b check operations need to be performed, that is, it is necessary to traverse whether all target addresses exist in temp info. When the number b of mapping relationships in temp info is very large, the number of checks also increases sharply, resulting in a serious decline in the reading speed of the memory. These usually occur in scenarios that affect the sequential reading of a large amount of data, such as streaming video playback, data transmission and installation of large files, etc. Summary of the Invention

[0004] Aiming at the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a data processing method, apparatus, medium and computer device for a storage device. According to an embodiment of the present invention, the first solution is provided as follows: A data processing method for a storage device, comprising the following steps: Parse the read request initiated by the user to obtain a logical addresses to be read; Determine c L2P mapping tables associated therewith according to the range of the a logical addresses, where c is a positive integer greater than or equal to 1; Back up the original mapping relationships of the c L2P mapping tables; Update the b latest mapping relationships in the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships; Query the updated c L2P mapping tables according to the read request, obtain the physical addresses corresponding to the a logical addresses, and read the data; After the reading is completed, restore the backed-up original mapping relationships to the c L2P mapping tables.

[0005] Further, the a logical addresses are consecutive read logical addresses, and the determination method of the c L2P mapping tables is as follows: Calculate the number of complete L2P mapping tables covered by the starting logical address and the ending logical address of the consecutive addresses to ensure that the c value is minimized.

[0006] Further, the determination method of the c L2P mapping tables includes: Set the size of the logical address range managed by a single L2P mapping table to M; Calculate the block index of the starting logical address S: ; Calculate the block index of the ending logical address E: ; Calculate the c value: c = Start_Index - End_Index + 1.

[0007] Further, the a logical addresses are non-consecutive read logical addresses, and the determination method of the c L2P mapping tables is as follows: Traverse the distribution range of all non-consecutive logical addresses, and merge the L2P mapping tables covering these addresses to ensure that all target addresses are included.

[0008] Further, the determination method of the c L2P mapping tables includes: Set the size of the logical address range managed by a single L2P mapping table to M; Initialize the index set Index_Set = {}; Traverse each logical address addr_i, calculate the block index: , and add the index to the set Index_Set; Calculate the c value: c = │Index_Set│.

[0009] Further, the temporary information layer includes an L1 temporary layer and an L2 temporary layer. The L1 temporary layer stores extremely high-frequency mapping relationships, and the L2 temporary layer stores sub-high-frequency mapping relationships. The steps of parsing the read request initiated by the user further include: The read request preferentially queries the L1 temporary layer. When it misses, trigger the step: Update the b latest mapping relationships in the L2 temporary information layer to the c L2P mapping tables.

[0010] Further, the step of dynamically adjusting the size of the temporary information layer includes: Statistically count the I / O request frequency at a fixed period; If the current I / O request frequency is greater than or equal to the high load threshold, increase the value of b. If the current I / O request frequency is less than the low load threshold, decrease the value of b; Write the updated value of b, b_new, which is increased or decreased, into the control register and synchronize it to the temporary information management unit; When b_new > b, expand the allocation to add a new buffer area and migrate the mapping relationship. When b_new < b, shrink the capacity to release the redundant buffer area and retain the high-frequency mapping.

[0011] According to the implementation scheme of the present invention, using the data processing method of a storage device in the first scheme provided by the present invention, the second scheme is provided as: A data processing device for a storage device, including: A read and parse module, configured to parse a read request initiated by a user and obtain a logical addresses to be read; An associated mapping table determination module, configured to determine c L2P mapping tables associated with it according to the range of the a logical addresses, where c is a positive integer greater than or equal to 1; An original mapping backup module, configured to back up the original mapping relationships of the c L2P mapping tables; A mapping table update module, configured to update the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, covering their original mapping relationships; A read module, configured to query the updated c L2P mapping tables according to the read request, obtain the physical addresses corresponding to the a logical addresses and read the data; A backup and recovery module, configured to, after the reading is completed, restore the backed-up original mapping relationships to the c L2P mapping tables.

[0012] A computer device, including a memory and a processor, where the memory stores a computer program, and when the computer program is executed by the processor, the processor is caused to execute the following steps: Parse a read request initiated by a user and obtain a logical addresses to be read; Determine c L2P mapping tables associated with it according to the range of the a logical addresses, where c is a positive integer greater than or equal to 1; Back up the original mapping relationships of the c L2P mapping tables; Update the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, covering their original mapping relationships; Query the updated c L2P mapping tables according to the read request, obtain the physical addresses corresponding to the a logical addresses and read the data; After the reading is completed, restore the original mapping relationship of the backed-up c L2P mapping tables to the c L2P mapping tables.

[0013] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor is caused to perform the following steps: Parse a read request initiated by a user to obtain a logical addresses to be read; Determine c L2P mapping tables associated therewith according to the ranges of the a logical addresses, where c is a positive integer greater than or equal to 1; Back up the original mapping relationships of the c L2P mapping tables; Update the b latest mapping relationships in the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships; Query the updated c L2P mapping tables according to the read request, obtain the physical addresses corresponding to the a logical addresses and read the data; After the reading is completed, restore the original mapping relationship of the backed-up c L2P mapping tables to the c L2P mapping tables.

[0014] Compared with the prior art, the beneficial effects of the independent claim of the technical solution provided by the present application are as follows: Through the mapping management process of this solution, redundant checks can be avoided, and the b mapping relationships in the temporary information layer can be batch-merged into the associated c L2P mapping tables, and only the c L2P mapping tables related to the user request are updated instead of global updating, achieving accurate locking of the update range. The update process can be repeated cyclically, ensuring data consistency. The number of checks is reduced from a × b to c × b, releasing the physical limit of the bandwidth and greatly reducing the latency. Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0016] Among them: Figure 1 It is a flowchart of a data processing method for a storage device in an embodiment; Figure 2 It is a structural block diagram of a data processing device for a storage device in an embodiment; Figure 3 It is a structural block diagram of a computer device in an embodiment. Detailed Embodiments

[0017] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0018] Embodiment 1 The technical problem solved by this embodiment is that there are certain performance bottlenecks in the traditional logic of reading data. For example, when a user reads a logical addresses and there are b mapping relationships recorded in temp info, a×b check operations need to be performed, that is, it is necessary to traverse whether all target addresses exist in temp info. When the number b of mapping relationships in temp info is very large, the number of checks also increases sharply, resulting in a serious decline in the reading speed of the memory.

[0019] This embodiment provides a data processing method for a storage device, as Figure 1 shown, including the following steps: S101: Parse the read request initiated by the user to obtain a logical addresses to be read; S102: Determine c L2P mapping tables associated therewith according to the range of the a logical addresses, where c is a positive integer greater than or equal to 1; S103: Back up the original mapping relationships of the c L2P mapping tables; S104: Update the b latest mapping relationships in the temporary information layer to the c L2P mapping tables, covering their original mapping relationships; S105: Query the updated c L2P mapping tables according to the read request, obtain the physical addresses corresponding to the a logical addresses and read the data; S106: After the reading is completed, restore the backed-up original mapping relationships to the c L2P mapping tables.

[0020] Through the mapping management process of this solution, redundant checks can be avoided. The b mapping relationships in the temporary information layer are batch-merged into the associated c L2P mapping tables, and only the c L2P mapping tables related to the user request are updated, rather than a global update, realizing accurate locking of the update range.

[0021] Specifically, the number of physical address checks in the traditional read request is a×b times, while the number of physical address checks in this solution is c×b times. Since a≥c, then a×b≥c×b. When reading sequentially, a is much larger than c, so the performance improvement is particularly obvious. However, when reading non-sequentially, partial performance improvement can also be achieved through algorithm adjustment. Therefore, this solution can release bandwidth and reduce latency by reducing the number of physical address checks, not only greatly improving the physical addressing efficiency in various sequential read scenarios, but also being compatible with and adapting to various typical non-sequential read scenarios, comprehensively and significantly enhancing the physical addressing ability of the storage device.

[0022] Embodiment 2 This embodiment provides an operation process of a specific data processing method for a storage device. The verification scenario uses the Yangtze Memory TiPro 7000 SSD, the main control chip is IG5236, and the interface is PCle.

[0023] S201: Analyze the read request initiated by the user, and obtain a consecutive read logical addresses 0 - 1023 to be read, that is, a = 1024; S202: Set the logical address size M = 1024 managed by a single L2P mapping table; Starting block index , where is the floor symbol; Ending block index ; c = Start_Index - End_Index + 1 = 1; The output is: only need to operate the 0th L2P mapping table; S203: Load the 0th L2P mapping table from the Nand Flash, and back up the original mapping relationship to the SRAM dedicated buffer; S204: Store 16 latest mapping relationships in the temporary information layer, such as the mapping of logical addresses 2048 - 2063, and overwrite the 16 latest mapping relationships to the 0th L2P mapping table. Hardware-wise, it is updated through the main control bit operation.

[0024] S205: Directly access the 0th L2P mapping table to obtain the physical addresses corresponding to 1024 logical addresses, and continuously read data from the NandFlash. The physical addresses are: Block 10 - 13.

[0025] The query times in the traditional solution are 1024×16 = 16,384 times, while this solution only requires c×b = 1×16 = 16 times. The maximum total read latency in the traditional solution is 800 - 1000 us, while this solution is only less than 100 ns.

[0026] Embodiment 3 This embodiment provides an operation process for discontinuous reading: S301: Analyze the reading request initiated by the user, and obtain a non - continuous reading logical addresses [100, 1500, 2500] to be read, that is, a = 3 addresses.

[0027] S302: Set the logical address size M = 1024 managed by a single L2P mapping table; Initialize the index set Index_Set = {}; Traverse the addresses: ; ; ; c = │Index_Set│ = 3, that is, it is necessary to operate on the 0th, 1st, and 2nd L2P mapping tables.

[0028] S303: Load 3 L2P mapping tables from Nand Flash, and the physical addresses are: Block5 / 6 / 7; Back up the original mapping relationship to the SRAM dedicated buffer; S304: Store 16 latest mapping relationships in the temporary information layer, such as the mapping of logical addresses 2048 - 2063, and batch - overwrite the 16 latest mapping relationships to the three L2P mapping tables, and the address range is: 0~1023, 1024~2047, 2048~3071; S305: Directly access the three L2P mapping tables to obtain the physical locations of the target addresses: Address 100 → Look up table 0 → Physical address Block 10, page1; Address 1500 → Look up table 1 → Physical address Block 20, page3; Address 2500 → Look up table 2 → Physical address Block 30, page5; Read discrete data blocks from Nand Flash.

[0029] The number of queries in the traditional scheme is 3×16 = 48 times. The number of mapping queries in this scheme is c×b = 3×16 = 48 times. Although the number of queries is the same, this scheme avoids a×b traversals through merging and updates, and only directly queries the L2P table. Without additional overhead, the latency of the critical path is significantly improved, especially the CPU occupancy rate drops significantly.

[0030] Embodiment 4 This embodiment discloses an implementation method of a multi-level temporary layer mechanism. The main principle is to reduce the latency of hot data location through diversity caching and frequency-driven updates, and also has a certain control effect on the latency of non-hot data compared with the traditional solution.

[0031] Specifically, configure and initialize the multi-level temporary information layer: The L1 temporary layer is an SRAM storage area with an address range of 0x8000 to 0x8100, a capacity of 8 mapping relationships, 16 bytes per mapping relationship, totaling 128B; the L2 temporary layer is a DRAM storage area with an address range of 0x10000 to 0x11000, a capacity of 64 mapping relationships, 16 bytes per mapping relationship, totaling 1KB, and each mapping relationship maintains a 4-bit location frequency counter.

[0032] The base address of the user's read request

[500] , and the consecutive read address range is 0 to 1023; first query the L1 temporary layer, and the hardware comparator matches 8 mapping relationships in parallel. If a hit occurs, directly return the physical address. If not, trigger the L2 update: record the miss event and start the L2 to L2P mapping table merging process: Calculate the c value: address range 0 to 1023 → M = 1024 → c = 1, that is, the 0th L2P mapping table; Back up the original mapping of the 0th L2P mapping table to SRAM; Extract b mapping relationships from the L2 temporary layer, select the b = 16 mapping relationships with the highest access frequency, and overwrite the 0th L2P mapping table; Directly access the 0th L2P mapping table to obtain the physical address of address 500, such as Block 10, page1, and read data from NandFlash.

[0033] Compared with the traditional scheme of traversing mappings, this method realizes a significant reduction in the access latency of hot data through hierarchical caching and frequency-driven updates.

[0034] Embodiment Five The technical problem solved by this embodiment is that the fixed temporary information layer with a static capacity is insufficient in capacity under high load, resulting in frequent triggering of L2P updates, and the capacity is excessive under low load, wasting memory and power consumption. For example, maintaining 64 mapping pairs during idle time wastes memory.

[0035] This embodiment maximizes the load performance by retaining high-frequency mappings, and releases the mapping relationships with the lowest access frequency under low load to solve the problem of imperfect resource allocation of the static mapping layer.

[0036] Specifically, the preset parameter high load threshold is Th = 50000, with the unit of IOPS, the low load threshold is Tl = 10000, with the unit of IOPS, the step size is Δd = 8 to match the 64 - byte alignment of the cache line, the capacity range is d_min = 4, d_max = 64, and the monitored fixed period is T = 100ms, that is, the I / O request frequency is counted every T = 100ms.

[0037] Read the hardware timer to obtain the IOPS value within a fixed period. For example, in period 1, IOPS = 55,000 is a high load, and in period 2, IOPS = 8000 is a low load.

[0038] The decision logic for dynamically adjusting the b value is as follows: If IOPS ≥ Th, then b_new = min(b_current + Δb, b_max), that is, b_new > b, and the decision result is to expand the capacity; If IOPS < Tl, then b_new = max(b_current - Δb, b_min), that is, b_new < b, and the decision result is to reduce the capacity; Maintain in other cases.

[0039] Write b_new into the control register, trigger an interrupt signal, and synchronize it to the temporary information management unit to take effect the new configuration.

[0040] When expanding the capacity, allocate a new SRAM block, migrate all mapping relationships to the new block, and update the temporary layer index table; When reducing the capacity, sort the mapping relationships by access frequency, retain the high - frequency mapping relationships, such as the first 16, and release the redundant SRAM blocks.

[0041] Through this solution, during sudden high loads, the latency of the dynamic adjustment solution can be greatly improved, and during continuous low loads, the power consumption can also be effectively controlled. It solves the problem of resource mismatch in the static mapping layer and realizes the maximization of high - load performance and the optimization of low - load energy efficiency.

[0042] Embodiment Six This embodiment provides a data processing device for a storage device, as Figure 2 shown, including: A read and parse module 100, which is used to parse the read request initiated by the user and obtain a logical addresses to be read; An associated mapping table determination module 200, which is used to determine c L2P mapping tables associated with it according to the range of a logical addresses, where c is a positive integer greater than or equal to 1; An original mapping backup module 300, which is used to back up the original mapping relationships of the c L2P mapping tables; The mapping table update module 400 is used to update the b latest mapping relationships in the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships; The reading module 500 is used to query the updated c L2P mapping tables according to the reading request, obtain the physical addresses corresponding to the a logical addresses, and read the data; The backup and recovery module 600 is used to restore the backed-up original mapping relationships to the c L2P mapping tables after the reading is completed.

[0043] Figure 3 The internal structure diagram of a computer device in an embodiment is shown. The computer device may specifically be a terminal or a server. As Figure 3 shown, the computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium of the computer device stores an operating system and may also store a computer program. When the computer program is executed by the processor, the processor can implement a data processing method. The memory may also store a computer program. When the computer program is executed by the processor, the processor can execute the data processing method. Those skilled in the art can understand that Figure 3 the structure shown in is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0044] In an embodiment, a computer device is proposed, including a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the processor performs the following steps: Parse the reading request initiated by the user to obtain a logical addresses to be read; Determine the c L2P mapping tables associated with them according to the range of the a logical addresses, where c is a positive integer greater than or equal to 1; Back up the original mapping relationships of the c L2P mapping tables; Update the b latest mapping relationships in the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships; Query the updated c L2P mapping tables according to the reading request, obtain the physical addresses corresponding to the a logical addresses, and read the data; After the reading is completed, restore the backed-up original mapping relationships to the c L2P mapping tables.

[0045] In one embodiment, a computer-readable storage medium is provided, storing a computer program, which when executed by a processor, causes the processor to perform the following steps: Parse a read request initiated by a user to obtain a logical addresses to be read; Determine c L2P mapping tables associated therewith according to the ranges of the a logical addresses, where c is a positive integer greater than or equal to 1; Back up the original mapping relationships of the c L2P mapping tables; Update b latest mapping relationships in the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships; Query the updated c L2P mapping tables according to the read request to obtain physical addresses corresponding to the a logical addresses and read data; After the reading is completed, restore the backed-up original mapping relationships to the c L2P mapping tables.

[0046] Those of ordinary skill in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0047] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0048] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A data processing method for a storage device, characterized in that, It includes the following steps: Parse the read request initiated by the user to obtain a logical addresses to be read; Determine c L2P mapping tables associated with them according to the range of the a logical addresses, where c is a positive integer greater than or equal to 1; Back up the original mapping relationships of the c L2P mapping tables; Update the b latest mapping relationships in the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships; Query the updated c L2P mapping tables according to the read request, obtain the physical addresses corresponding to the a logical addresses and read the data; After the reading is completed, restore the backed-up original mapping relationships to the c L2P mapping tables.

2. The data processing method of the storage device according to claim 1, wherein: The a logical addresses are consecutive read logical addresses, and the determination method of the c L2P mapping tables is: calculate the number of complete L2P mapping tables covered according to the start logical address and the end logical address of the consecutive addresses to ensure the minimum value of c.

3. The data processing method of the storage device according to claim 2, wherein: The determination method of the c L2P mapping tables includes: Set the size of the logical address range managed by a single L2P mapping table to M; Calculate the block index of the starting logical address S: ; Calculate the block index of the end logical address E: ; Calculate the value of c: c = Start_Index - End_Index + 1.

4. The data processing method of the storage device according to claim 1, wherein: The a logical addresses are non-consecutive read logical addresses, and the determination method of the c L2P mapping tables is: traverse the distribution ranges of all non-consecutive logical addresses, and merge the L2P mapping tables covering these addresses to ensure that all target addresses are included.

5. The data processing method of the storage device according to claim 4, wherein: The determination method of the c L2P mapping tables includes: Set the size of the logical address range managed by a single L2P mapping table to M; Initialize the index set Index_Set = {}; Traverse each logical address addr_i and calculate the block index: and add the index to the set Index_Set; Calculate the value of c: c = │Index_Set│.

6. The data processing method of the storage device according to claim 4, wherein: The temporary information layer includes an L1 temporary layer and an L2 temporary layer. The L1 temporary layer stores extremely high-frequency mapping relationships, and the L2 temporary layer stores sub-high-frequency mapping relationships. The step of parsing the read request initiated by the user further includes: The read request preferentially queries the L1 temporary layer. When a miss occurs, trigger the step: update the b latest mapping relationships in the L2 temporary information layer to the c L2P mapping tables.

7. The data processing method of the storage device according to claim 4, characterized in that, The steps of dynamically adjusting the size of the temporary information layer include: Statistically analyze the I / O request frequency at a fixed period; If the current I / O request frequency is greater than or equal to the high-load threshold, increase the value of b. If the current I / O request frequency is less than the low-load threshold, decrease the value of b; Write the updated b value b_new, which is increased or decreased, into the control register and synchronize it to the temporary information management unit; When b_new > b, expand the capacity to allocate a new buffer area and migrate the mapping relationships. When b_new < b, reduce the capacity to release the redundant buffer area and retain the high-frequency mapping.

8. A data processing device for a storage device, characterized in that, It includes: A read parsing module for parsing the read request initiated by the user to obtain a logical addresses to be read; An associated mapping table determination module for determining c L2P mapping tables associated with them according to the range of the a logical addresses, where c is a positive integer greater than or equal to 1; An original mapping backup module for backing up the original mapping relationships of the c L2P mapping tables; A mapping table update module for updating the b latest mapping relationships in the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships; A reading module for querying the updated c L2P mapping tables according to the reading request, obtaining the physical addresses corresponding to the a logical addresses and reading the data; A backup recovery module for restoring the backed-up original mapping relationships to the c L2P mapping tables after the reading is completed.

9. A computer-readable storage medium, characterized in that, A computer program is stored, and when the computer program is executed by a processor, the processor is caused to execute the steps of the method according to any one of claims 1 to 7.

10. A computer device, characterized in that, It includes a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the processor is caused to execute the steps of the method according to any one of claims 1 to 7.

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