A design method for discrete memristor-driven neurons and its implementation circuit

Abstract

The present invention discloses a design method for discrete memristor-driven neurons and its implementation circuit. The method comprises determining a discrete iterative form of a voltage-controlled discrete local active memristor; designing a discrete local active memristor model based on trigonometric functions; then determining a discrete neuron model based on a two-dimensional mapping; introducing the obtained discrete local active memristor into the discrete neuron model to obtain a discrete memristor-driven neuron model; and finally constructing a nonlinear function based on trigonometric functions and substituting it into the obtained neuron model to complete the design of the discrete memristor-driven neuron. The invention also provides corresponding analog and digital circuit constructions, which have the advantages of stable operation, precise response, and excellent performance, demonstrating promising application prospects and engineering practicality.

Description

Technical Field

[0001] The present invention belongs to the field of electronic circuit design, and in particular relates to a discrete memristor-driven neuron design method and an implementation circuit thereof. Background Art

[0002] With the development of artificial intelligence and neuromorphic computing, neuron models and their hardware implementation have become a hot topic of research. Biological neurons rely on the nonlinear dynamic characteristics of ion channels and synapses to achieve efficient processing of complex information. Currently, although traditional continuous neuron models can characterize the electrical activity characteristics of neurons, they have bottlenecks when simulating discrete behaviors such as refractory periods and threshold triggering. In addition, traditional continuous neuron models are often accompanied by high computational redundancy when transplanted into digital systems. In contrast, discrete neuron models can more efficiently simulate the neuron's pulse emission process through an iterative mechanism, and have the advantages of low computational overhead, simple structure, and easy hardware implementation. Therefore, discrete neuron models have received widespread attention in neural network research.

[0003] Memristors, as a new type of nonlinear electronic component, can effectively simulate the nonlinear dynamic characteristics of biological neural systems and are suitable for describing the complex process by which neurons generate action potentials. Consequently, research on their application in neuromorphic circuits and artificial neural networks has continued to deepen in recent years. However, current research focuses primarily on incorporating memristors into continuous neuron models to enhance their nonlinear characteristics. Deep integration of memristors with discrete neuron models is still insufficient, and a discrete memristor neuron model that combines rich dynamic characteristics with low computational complexity is still lacking. Summary of the Invention

[0004] One of the objectives of the present invention is to provide a design method for a discrete memristor-driven neuron model that has both computational efficiency advantages and complex dynamic characteristics.

[0005] A second object of the present invention is to provide a circuit for realizing a discrete memristor-driven neuron.

[0006] The design method of the discrete memristor-driven neuron provided by the present invention comprises the following steps:

[0007] S1. Based on the forward difference theory, the discrete iterative form of the voltage-controlled discrete local active memristor is determined;

[0008] S2. Design a discrete local active memristor model based on trigonometric functions according to the discrete iterative form determined in step S1;

[0009] S3. Determine the discrete neuron model based on the two-dimensional mapping;

[0010] S4. Substituting the discrete local active memristor model obtained in step S2 into the discrete neuron model in step S3, a discrete memristor-driven neuron model is obtained; comprising the following steps:

[0011] Substitute the discrete local active memristor model obtained in step S2 into the discrete neuron model obtained in step S3, use the flux term in the memristor to represent the ion current recovery variable term in the model expression of the discrete neuron, and replace the flux variable of the memristor with Mapped to ion current recovery variables , thus obtaining a discrete memristor-driven neuron model;

[0012] S5. Construct a nonlinear function based on the trigonometric function and substitute it into the discrete memristor-driven neuron model obtained in step S4 to complete the design of the discrete memristor-driven neuron.

[0013] The step S1 specifically includes the following steps:

[0014] Based on the forward difference theory, the following formula is used as the discretization iterative operation form of the voltage-controlled discrete local active memristor: Where, for N Input voltage at the moment; for N Output current at the moment; for N The internal state variables of the memristor at the moment; is the memetic derivative function; is a nonlinear modulation function; is the scale factor.

[0015] The step S2 specifically includes the following steps:

[0016] Selected memetic derivative function for , select the nonlinear modulation function for ;in, a is the nonlinear modulation function Amplitude parameter of ;

[0017] Therefore, the discrete local active memristor model is determined as: .

[0018] The step S3 specifically includes the following steps:

[0019] Based on the two-dimensional mapping, the discrete neuron model is expressed using the following formula: In the formula The neuronal membrane potential n Iteration value;I is the external excitation current; is the first variable of ion current recovery n Iteration value; is the first parameter to be set; q is the second parameter set; The third parameter to be set.

[0020] The step S4 specifically includes the following steps:

[0021] The new discrete memristor-driven neuron model is expressed as follows: In the formula To have N Nonlinear function of type characteristics; k is the memristive coupling strength.

[0022] The step S5 specifically includes the following steps:

[0023] The nonlinear curve function constructed based on the sine function is: ,in g is the set nonlinear intensity parameter, and ;

[0024] Substitute the nonlinear curve function into the discrete memristor-driven neuron model obtained in step S4 to obtain , complete the design of discrete memristor-driven neuron model.

[0025] The present invention also provides a discrete memristor-driven neuron implementation circuit, including an analog implementation circuit and a digital implementation circuit;

[0026] Based on the sample-and-hold circuit, operational amplifier and operation function editor, the analog circuit of discrete memristor-driven neuron model is realized;

[0027] Based on the control chip, a digital implementation circuit of the discrete memristor-driven neuron model is realized.

[0028] The analog implementation circuit includes a first step wave function generator, a second step wave function generator, a third step wave function generator, a first sample and hold, a second sample and hold, a third sample and hold, a fourth sample and hold, a NOT gate, a first function editor, a second function editor, a third function editor, a multiplier, a first proportional gain device, a second proportional gain device, a first operational amplifier, a second operational amplifier, a third operational amplifier, a fourth operational amplifier, and first to fourteenth resistors;

[0029] The negative electrode of the first step wave function generator is grounded, and the first step wave function generator is used to generate a first initial step wave signal , and the first initial step wave signal Output to the first input terminal of the first sample holder, the first input terminal of the third sample holder and the input terminal of the NOT gate; the NOT gate is used to convert the first initial step wave signal In reverse, the output end of the NOT gate is simultaneously connected to the first input end of the second sample holder and the first input end of the fourth sample holder; the output end of the first sample holder is connected to the second input end of the second sample holder, and the output end of the third sample holder is connected to the second input end of the fourth sample holder; the signal output from the output end of the second sample holder is divided into three paths, the first path is connected to the input end of the first function editor, the second path is connected to the first input end of the multiplier, and the third path is connected to the input inverting end of the third operational amplifier through the eighth resistor connected in series; the first function editor is used to convert the input signal into a sinusoidal signal output; the output end of the first function editor is connected to the input inverting end of the first operational amplifier through the first resistor connected in series; the input non-inverting end of the first operational amplifier is grounded; the The input inverting terminal is also connected to the output terminal of the first operational amplifier through a fifth resistor connected in series; the output terminal of the first operational amplifier is connected to the input inverting terminal of the second operational amplifier through a sixth resistor connected in series; the input non-inverting terminal of the second operational amplifier is grounded; the input inverting terminal of the second operational amplifier is also connected to the output terminal of the second operational amplifier through a seventh resistor; the output terminal of the second operational amplifier is directly connected to the second input terminal of the first sample and hold; the second input terminal of the multiplier is connected to the output terminal of the second function editor, and the second mathematical function editor is used to convert the input signal into a cosine signal output; the output terminal of the multiplier is connected to the input inverting terminal of the first operational amplifier through a second resistor; the negative pole of the second step wave function generator is grounded, and the second step wave function generator is used to generate a second initial step wave signal , and the second initial step wave signal The inverting input terminal of the first operational amplifier is connected via a third resistor connected in series; the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the first operational amplifier via a fourth resistor; the output terminal of the fourth operational amplifier is also connected to the input terminal of the second function editor via a first proportional gain device; the output terminal of the fourth sample and hold is connected to the inverting input terminal of the third operational amplifier via a ninth resistor; the output terminal of the fourth sample and hold is also connected to the inverting input terminal of the third operational amplifier via a second proportional gain device, a third function editor and a tenth resistor connected in series in sequence; the third function editor is used to convert the input signal into a sinusoidal signal output; the negative pole of the third step wave function generator is grounded, and the third step wave function generator is used to generate a third initial step wave signal , and the third initial step wave signal The inverting input terminal of the third operational amplifier is connected via a twelfth resistor connected in series; the non-inverting input terminal of the third operational amplifier is grounded, and the inverting input terminal of the third operational amplifier is also connected to the output terminal of the third operational amplifier via an eleventh resistor; the output terminal of the third operational amplifier is connected to the inverting input terminal of the fourth operational amplifier via a thirteenth resistor connected in series; the inverting input terminal of the fourth operational amplifier is also connected to the output terminal of the fourth operational amplifier via a fourteenth resistor; and the output terminal of the fourth operational amplifier is directly connected to the second input terminal of the third sample and hold.

[0030] The digital implementation circuit is specifically a digital circuit composed of a control chip of model TMS320F28335; the iterative operation of the discrete memristor-driven neuron model is realized by the control chip, thereby realizing the discrete memristor-driven neuron model with a digital circuit.

[0031] The discrete memristor-driven neuron design method and implementation circuit provided by this invention combine the nonlinear characteristics of memristors with discrete neuron models, effectively reducing the computational complexity of the system while significantly enhancing the dynamic characteristics of the neuron model. This method not only completes the modeling and design of the novel discrete memristor-driven neuron but also enables the construction of corresponding analog and digital circuits. The method boasts stable operation, precise response, and excellent performance, demonstrating promising application prospects and engineering practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the method flow of the design method of the present invention.

[0033] Figure 2 The composite nonlinear function in the design method of the present invention , under different parameters g The characteristic curve diagram below.

[0034] Figure 3 The discrete memristor-driven neuron model in the design method of the present invention is Global dynamics characteristic diagram of the changes within the interval.

[0035] Figure 4 The discrete memristor-driven neuron model in the design method of the present invention has different parameters. g Different discharge modes are presented under different conditions. Figure 4 (a) Time series diagram under multi-cycle discharge mode; Figure 4 (b) Phase trajectory diagram under multi-cycle discharge mode; Figure 4 (c) Time Time series diagram under chaotic discharge mode; Figure 4 (d) Time Phase trajectory diagram under chaotic discharge mode; Figure 4 (e) is Time Time series diagram of chaotic discharge mode; Figure 4 (f) is Time Phase trajectory diagram under chaotic discharge mode.

[0036] Figure 5 This is a schematic diagram of an analog circuit for implementing the circuit of the present invention.

[0037] Figure 6 This is a simulation experiment result diagram of the analog type circuit of the present invention. Figure 6 (a) Time series diagram in multi-cycle discharge mode; Figure 6 (b) Phase trajectory diagram under multi-cycle discharge mode; Figure 6 (c) hour, Time series diagram under chaotic discharge mode; Figure 6 (d) hour, Phase trajectory diagram under chaotic discharge mode; Figure 6 (e) hour, Time series diagram under chaotic discharge mode; Figure 6 (f) is hour, Phase trajectory diagram under chaotic discharge mode.

[0038] Figure 7 This is a diagram of the digital circuit configuration for implementing the circuit of the present invention.

[0039] Figure 8 This is a hardware experiment result diagram of the digital implementation circuit of the present invention, wherein Figure 8 (a) Time series diagram in multi-cycle discharge mode; Figure 8 (b) Phase trajectory diagram under multi-cycle discharge mode; Figure 8 (c) hour, Time series diagram under chaotic discharge mode; Figure 8 (d) hour, Phase trajectory diagram under chaotic discharge mode, Figure 8 (e) is hour, Time series diagram under chaotic discharge mode; Figure 8 (f) is hour, Phase trajectory diagram under chaotic discharge mode. DETAILED DESCRIPTION

[0040] like Figure 1 The figure shows a flow chart of the design method of the present invention: The design method of the discrete memristor-driven neuron disclosed in the present invention comprises the following steps:

[0041] S1. Based on the forward difference theory, determine the discrete iterative form of the voltage-controlled discrete local active memristor. The specific steps include:

[0042] The local active memristor introduced in this invention is a universal memristor with local negative differential resistance. The local active characteristic is the root cause of system complexity. Based on the forward difference theory, the following formula is used as the discretization iterative calculation form of the voltage-controlled discrete local active memristor: Where, for N Input voltage at the moment; for N Output current at the moment; for N The internal state variables of the memristor at the moment; is the memetic derivative function; is a nonlinear modulation function; is the scale factor.

[0043] S2. Based on the discrete iteration form determined in step S1, design a discrete local active memristor model based on trigonometric functions, specifically comprising the following steps:

[0044] Selected memetic derivative function for , select the nonlinear modulation function for ;in, a is the nonlinear modulation function Amplitude parameter of ;

[0045] Therefore, the discrete local active memristor model is determined as .

[0046] S3. Determine a discrete neuron model based on the two-dimensional mapping, including the following steps:

[0047] Traditional discrete neuron models are mostly based on the Integrate-and-Fire (IF) model, which widely introduces slow variables to regulate the dynamic behavior of neuronal membrane potential. Based on two-dimensional mapping, the discrete neuron model is expressed using the following formula: In the formula The neuronal membrane potential n Iteration value; I is the external excitation current; is the first variable of ion current recovery n Iteration value; is the first parameter of the setting, which is a positive parameter, and The value must be less than the set positive threshold (the purpose is to ensure Much less than 1); q is the second parameter set; is the third parameter set; 、 q and Used to regulate different firing states of discrete neuron models.

[0048] In this model, the ionic current recovery variable They are all linear terms, which makes it difficult to characterize the nonlinear recovery mechanism that actually exists in the neural discharge process, limiting the applicability of the model in the simulation of complex neural dynamics.

[0049] S4. Substituting the discrete local active memristor model obtained in step S2 into the discrete neuron model in step S3, a discrete memristor-driven neuron model is obtained, comprising the following steps:

[0050] The core of this invention lies in the introduction of discrete local active memristors into a neuron model based on two-dimensional mapping. By replacing the ionic current recovery variable in the neuron model with the magnetic flux state variable in the memristor, a nonlinear regulation mechanism coupling neuron membrane potential and magnetic flux is implemented, constructing a new discrete memristor-driven neuron model. This design enables the neuron model to have stronger nonlinear expression capabilities and exhibit diverse dynamic behaviors.

[0051] Substitute the expression of the discrete local active memristor obtained in step S2 into the discrete neuron model in step S3, use the flux term in the memristor to represent the ion current recovery variable term in the model expression of the discrete neuron, and replace the flux variable of the memristor with Mapped to ion current recovery variables , thus obtaining a discrete memristor-driven neuron model;

[0052] In specific implementation, the following formula is used as the discrete memristor-driven neuron model: In the formula To have N Nonlinear curve function of type characteristics; k is the memristive coupling strength.

[0053] S5. Construct a nonlinear function based on trigonometric functions and substitute it into the discrete memristor-driven neuron model obtained in step S4 to complete the design of the discrete memristor-driven neuron, which specifically includes the following steps:

[0054] The nonlinear curve function constructed based on the sine function is: ,in g is the set nonlinear intensity parameter, and ; Set at the same time ; When the parameter g The value is greater than 1 and presents a controllable parameter range N Type characteristics; Figure 2 The parameters are shown g Take 3 different sets of values ​​( ), the sine function-based N The characteristic curve of the type When the interval changes, the three nonlinear functions show strange symmetry;

[0055] Substitute the nonlinear curve function into the discrete memristor-driven neuron model obtained in step S4 to obtain , completing the design of discrete memristor-driven neurons.

[0056] For the obtained discrete memristor-driven neuron model, set the parameters And the initial state is Under these conditions, the bifurcation diagram based on the membrane potential iteration sequence and the Lyapunov exponent spectrum (LEs) of the quantitative analysis are constructed to characterize the system under The global dynamic characteristics of the changes within the controllable parameter range; specifically Figure 3 shown.

[0057] Among them, the bifurcation diagram reflects the evolution of the system state by extracting the periodic characteristics of the iterative sequence, and the maximum Lyapunov exponent The sign change of Characterizing chaos, The corresponding period, indicating quasi-periodicity), provides a rigorous mathematical criterion for the dynamic evolution of the system. Figure 3 The bifurcation diagram and Lyapunov index spectrum show high consistency in the characterization of dynamic characteristics. g Gradually increases, the system experiences a quasi-periodic state Multi-cycle state The chaotic state changes, accompanied by period-doubling bifurcations and the generation of multiple period windows.

[0058] In the initial range Approaching zero, the system is in a quasi-periodic state;

[0059] As g increases, There are multiple narrow period windows in the nearby system. Less than 0;

[0060] In a wider area, Sustained positive values ​​reveal a prevailing chaotic state.

[0061] In order to observe the discharge mode under different parameters, the parameters are set respectively. g For three different sets of values, the and Time series and about Phase trajectory as Figure 4 As shown. When , the discrete memristor-driven neuron model is in multi-cycle discharge mode ( , ), the time-iterative sequence of the membrane potential and ion current recovery variables is as follows Figure 4 (a) shows the corresponding phase diagram. Figure 4 (b) shown; when When the neuron model is in Type chaotic discharge mode ( , ), whose time series and phase diagram are as follows Figure 4 (c) with Figure 4 (d) shown; when When the neuron model is in different Type chaotic discharge mode ( , ), its time iteration sequence and phase diagram are shown in Figure 4 (e) with Figure 4 (f).

[0062] The discrete memristor-driven neuron model provides a solid theoretical foundation for the hardware implementation of neuromorphic systems. The realization of its physical model relies on analog and digital circuits to complete the engineering transformation of the technical prototype. Based on the dynamic characteristics of this model, the present invention constructs a dual verification platform consisting of analog simulation circuits and digital hardware circuits. By replicating the model's dynamic behavior at the circuit level, the correctness of its theoretical description is verified. Furthermore, the feasibility of the model's engineering application in neuromorphic systems is further demonstrated through the implementation of hardware circuits.

[0063] The implementation circuit of the discrete memristor-driven neuron disclosed in the present invention includes an analog implementation circuit and a digital implementation circuit;

[0064] Based on the sample-and-hold circuit, operational amplifier and operation function editor, the analog circuit of discrete memristor-driven neuron model is realized;

[0065] Based on the control chip, a digital implementation circuit of the discrete memristor-driven neuron model is realized.

[0066] During specific implementation, the present invention uses a simulation experimental circuit based on the PSIM platform to systematically verify the feasibility of the analog circuit implementation solution.

[0067] The analog implementation circuit of the present invention is as follows: Figure 5 As shown, it includes a first step wave function generator, a second step wave function generator, a third step wave function generator, a first sample and hold ( ), the second sample and hold ( ), the third sample and hold ( ), the fourth sample holder ( ), NOT gate (D), first function editor ( ), the second function editor ( ), the third function editor ( ), Multiplier ( M ), the first proportional gain ( ), the second proportional gain ( ), the first operational amplifier ( ), the second operational amplifier ( ), the third operational amplifier ( ), the fourth operational amplifier ( ) and the first to fourteenth resistors ( );

[0068] The negative electrode of the first step wave function generator is grounded, and the first step wave function generator is used to generate a first initial step wave signal , and the first initial step wave signal Output to the first input terminal of the first sample holder, the first input terminal of the third sample holder and the input terminal of the NOT gate; the NOT gate is used to convert the first initial step wave signal In reverse, the output end of the NOT gate is simultaneously connected to the first input end of the second sample holder and the first input end of the fourth sample holder; the output end of the first sample holder is connected to the second input end of the second sample holder, and the output end of the third sample holder is connected to the second input end of the fourth sample holder; the signal output from the output end of the second sample holder is divided into three paths, the first path is connected to the input end of the first function editor, the second path is connected to the first input end of the multiplier, and the third path is connected to the input inverting end of the third operational amplifier through the eighth resistor connected in series; the first mathematical function editor is used to convert the input signal into a sinusoidal signal output; the output end of the first function editor is connected to the input inverting end of the first operational amplifier through the first resistor connected in series; the input non-inverting end of the first operational amplifier is grounded; the first operational amplifier The input inverting terminal is also connected to the output terminal of the first operational amplifier through a fifth resistor connected in series; the output terminal of the first operational amplifier is connected to the input inverting terminal of the second operational amplifier through a sixth resistor connected in series; the input non-inverting terminal of the second operational amplifier is grounded; the input inverting terminal of the second operational amplifier is also connected to the output terminal of the second operational amplifier through a seventh resistor; the output terminal of the second operational amplifier is directly connected to the second input terminal of the first sample and hold; the second input terminal of the multiplier is connected to the output terminal of the second function editor, and the second mathematical function editor is used to convert the input signal into a cosine signal output; the output terminal of the multiplier is connected to the input inverting terminal of the first operational amplifier through a second resistor; the negative pole of the second step wave function generator is grounded, and the second step wave function generator is used to generate a second initial step wave signal , and the second initial step wave signal The inverting input terminal of the first operational amplifier is connected via a third resistor connected in series; the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the first operational amplifier via a fourth resistor; the output terminal of the fourth operational amplifier is also connected to the input terminal of the second function editor via a first proportional gain device; the output terminal of the fourth sample and hold is connected to the inverting input terminal of the third operational amplifier via a ninth resistor; the output terminal of the fourth sample and hold is also connected to the inverting input terminal of the third operational amplifier via a second proportional gain device, a third function editor and a tenth resistor connected in series in sequence; the third function editor is used to generate a sine signal; the negative pole of the third step wave function generator is grounded, and the third step wave function generator is used to generate a third initial step wave signal , and the third initial step wave signal The inverting input terminal of the third operational amplifier is connected via a twelfth resistor connected in series; the non-inverting input terminal of the third operational amplifier is grounded, and the inverting input terminal of the third operational amplifier is also connected to the output terminal of the third operational amplifier via an eleventh resistor; the output terminal of the third operational amplifier is connected to the inverting input terminal of the fourth operational amplifier via a thirteenth resistor connected in series; the inverting input terminal of the fourth operational amplifier is also connected to the output terminal of the fourth operational amplifier via a fourteenth resistor; and the output terminal of the fourth operational amplifier is directly connected to the second input terminal of the third sample and hold.

[0069] Among them, the operational amplifier is used to realize the addition, subtraction, ratio and reverse operation of the signal; the voltage difference between the sample and hold is used to realize the differential calculation in the model iteration equation; the mathematical function editor is responsible for realizing the nonlinear function in the model and The above circuit units work together to form the analog circuit structure of discrete memristor-driven neurons, and its circuit state equation can be expressed as: in and To restore the voltage form of the variables for neuronal membrane potential and ionic current, the multiplier gain is set to ;The specific resistance parameters are: , , ; and The ratio is used to adjust the parameters in the model g ; Proportional gain controller and All set to ; Step wave function generator The peak-to-peak voltage is set to 3 V, the frequency is 10 kHz, and the duty cycle is 50%; and They are set to -0.1 V and 0.01 V respectively to match the initial voltage conditions, and the step duration is 0.1 ms.

[0070] During the PSIM simulation process, the simulation parameters are set as follows: the time step is , the total simulation time is 2.1 s, and the data sampling time is 2.0 s; by adjusting resistance value, can flexibly realize different parameters g The switching of the resistance value can verify the diverse dynamic characteristics of the model in the simulation circuit. Configured as , and When the captured and Time series and Phase trajectory such as Figure 6 As shown, Figure 6 PSIM circuit experimental simulation results and Figure 4 The numerical simulation results are basically consistent with those in .

[0071] The digital implementation circuit described in the present invention is specifically a digital circuit composed of a control chip with the model TMS320F28335; the iterative operation of the discrete memristor-driven neuron model is realized by the control chip, thereby realizing the discrete memristor-driven neuron model with a digital circuit.

[0072] DSP has the advantages of high integration, strong reliability and low operating power consumption. Therefore, the present invention uses a DSP-based digital hardware platform to verify the above simulation experimental results; the digital hardware implementation not only verifies the correctness of the discrete memristor-driven neuron model, but also provides a feasible path for its application in the engineering field.

[0073] Figure 7 The corresponding digital circuit implementation is demonstrated. The hardware includes a computer, an emulator (XDS100-V2), a DSP development board (TMS320F28335), a digital-to-analog converter (DAC 8552), and an oscilloscope. Firmware is compiled and debugged using the C language in the DSP integrated development environment CCS11.0, generating machine code that can run on the DSP. Figure 7 In this paper, only the DSP chip model TMS320F28335 can realize the digital implementation circuit, while the computer and simulator are used to program the DSP chip, and the digital-to-analog converter and oscilloscope are used to display the output of the DSP chip for experimental verification.

[0074] Connect the DAC module output signal to the dual channels of the oscilloscope for synchronous output observation. Oscilloscope channel A displays the membrane potential related voltage signal , channel B shows the ion current recovery variable voltage signal , and then construct the XY oscilloscope observation mode. Figure 8 The results of discrete memristor-driven neuron model under different parameter conditions are shown. and Time series and Phase trajectory, the experimental waveform obtained is Figure 4 The numerical simulation results shown are highly consistent.

[0075] The comprehensive simulation results based on the PSIM platform and the digital hardware verification results based on the DSP platform fully demonstrated the effectiveness of the discrete memristor-driven neuron model in practical applications, verified the rationality of the design scheme, and confirmed the engineering feasibility of the circuit implementation through the consistency between the experimental and simulation results.

Claims

1. A design method for discrete memristor-driven neurons, characterized in that The steps include: S1. Based on the forward difference theory, the discrete iterative form of the voltage-controlled discrete local active memristor is determined; S2. Design a discrete local active memristor model based on trigonometric functions according to the discrete iterative form determined in step S1; S3. Determine the discrete neuron model based on the two-dimensional mapping; S4. Substituting the discrete local active memristor model obtained in step S2 into the discrete neuron model in step S3, a discrete memristor-driven neuron model is obtained; comprising the following steps: Substituting the discrete local active memristor model obtained in step S2 into the discrete neuron model obtained in step S3, using the flux term in the memristor to represent the ion current recovery variable term in the model expression of the discrete neuron, mapping the flux variable of the memristor to the ion current recovery variable, thereby obtaining a discrete memristor-driven neuron model; The new discrete memristor-driven neuron model is expressed as follows: In the formula The neuronal membrane potential n Iteration value; To have N Nonlinear function of type characteristics; k is the memristive coupling strength; is the first variable of ion current recovery n Iteration value; a is the nonlinear modulation function Amplitude parameter of ; is the scale factor; for N The internal state variables of the memristor at the moment; S5. Construct a nonlinear function based on the trigonometric function and substitute it into the discrete memristor-driven neuron model obtained in step S4 to complete the design of the discrete memristor-driven neuron.

2. The design method of discrete memristor-driven neurons according to claim 1, characterized in that The step S1 specifically includes the following steps: Based on the forward difference theory, the following formula is used as the discretization iterative operation form of the voltage-controlled discrete local active memristor: Where, for N Input voltage at the moment; for N Output current at the moment; for N The internal state variables of the memristor at the moment; is the memetic derivative function; is a nonlinear modulation function; is the scale factor.

3. The design method of discrete memristor-driven neurons according to claim 2, characterized in that The step S2 specifically includes the following steps: Selected memetic derivative function for , select the nonlinear modulation function for ;in, a is the nonlinear modulation function Amplitude parameter of ; Therefore, the discrete local active memristor model is determined as .

4. The design method of discrete memristor-driven neurons according to claim 3, characterized in that The step S3 specifically includes the following steps: Based on the two-dimensional mapping, the discrete neuron model is expressed using the following formula: In the formula The neuronal membrane potential n Iteration value; I is the external excitation current; is the first variable of ion current recovery n Iteration value; is the first parameter to be set; q is the second parameter set; The third parameter to be set.

5. The design method of discrete memristor-driven neurons according to claim 1, characterized in that The step S5 specifically includes the following steps: The nonlinear curve function constructed based on the sine function is: ,in g is the set nonlinear intensity parameter, and ; Substitute the nonlinear curve function into the discrete memristor-driven neuron model obtained in step S4 to obtain , complete the design of discrete memristor-driven neuron model.

6. A discrete memristor-driven neuron implementation circuit obtained by using the discrete memristor-driven neuron design method according to any one of claims 1 to 5, comprising an analog implementation circuit and a digital implementation circuit; Based on the sample-and-hold circuit, operational amplifier and operation function editor, the analog circuit of discrete memristor-driven neuron model is realized; Based on the control chip, a digital implementation circuit of the discrete memristor-driven neuron model is realized.

7. The implementation circuit according to claim 6, characterized in that The analog implementation circuit includes a first step wave function generator, a second step wave function generator, a third step wave function generator, a first sample and hold, a second sample and hold, a third sample and hold, a fourth sample and hold, a NOT gate, a first function editor, a second function editor, a third function editor, a multiplier, a first proportional gain device, a second proportional gain device, a first operational amplifier, a second operational amplifier, a third operational amplifier, a fourth operational amplifier, and first to fourteenth resistors; The negative electrode of the first step wave function generator is grounded, and the first step wave function generator is used to generate a first initial step wave signal , and the first initial step wave signal Output to the first input terminal of the first sample holder, the first input terminal of the third sample holder and the input terminal of the NOT gate; the NOT gate is used to convert the first initial step wave signal In reverse, the output end of the NOT gate is simultaneously connected to the first input end of the second sample holder and the first input end of the fourth sample holder; the output end of the first sample holder is connected to the second input end of the second sample holder, and the output end of the third sample holder is connected to the second input end of the fourth sample holder; the signal output from the output end of the second sample holder is divided into three paths, the first path is connected to the input end of the first function editor, the second path is connected to the first input end of the multiplier, and the third path is connected to the input inverting end of the third operational amplifier through the eighth resistor connected in series; the first function editor is used to convert the input signal into a sinusoidal signal output; the output end of the first function editor is connected to the input inverting end of the first operational amplifier through the first resistor connected in series; the input non-inverting end of the first operational amplifier is grounded; the The input inverting terminal is also connected to the output terminal of the first operational amplifier through a fifth resistor connected in series; the output terminal of the first operational amplifier is connected to the input inverting terminal of the second operational amplifier through a sixth resistor connected in series; the input non-inverting terminal of the second operational amplifier is grounded; the input inverting terminal of the second operational amplifier is also connected to the output terminal of the second operational amplifier through a seventh resistor; the output terminal of the second operational amplifier is directly connected to the second input terminal of the first sample and hold; the second input terminal of the multiplier is connected to the output terminal of the second function editor, and the second mathematical function editor is used to convert the input signal into a cosine signal output; the output terminal of the multiplier is connected to the input inverting terminal of the first operational amplifier through a second resistor; the negative pole of the second step wave function generator is grounded, and the second step wave function generator is used to generate a second initial step wave signal , and the second initial step wave signal The inverting input terminal of the first operational amplifier is connected via a third resistor connected in series; the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the first operational amplifier via a fourth resistor; the output terminal of the fourth operational amplifier is also connected to the input terminal of the second function editor via a first proportional gain device; the output terminal of the fourth sample and hold is connected to the inverting input terminal of the third operational amplifier via a ninth resistor; the output terminal of the fourth sample and hold is also connected to the inverting input terminal of the third operational amplifier via a second proportional gain device, a third function editor and a tenth resistor connected in series in sequence; the third function editor is used to convert the input signal into a sinusoidal signal output; the negative pole of the third step wave function generator is grounded, and the third step wave function generator is used to generate a third initial step wave signal , and the third initial step wave signal The inverting input terminal of the third operational amplifier is connected via a twelfth resistor connected in series; the non-inverting input terminal of the third operational amplifier is grounded, and the inverting input terminal of the third operational amplifier is also connected to the output terminal of the third operational amplifier via an eleventh resistor; the output terminal of the third operational amplifier is connected to the inverting input terminal of the fourth operational amplifier via a thirteenth resistor connected in series; the inverting input terminal of the fourth operational amplifier is also connected to the output terminal of the fourth operational amplifier via a fourteenth resistor; and the output terminal of the fourth operational amplifier is directly connected to the second input terminal of the third sample and hold.

8. The implementation circuit according to claim 6, characterized in that The digital implementation circuit is specifically a digital circuit composed of a control chip of model TMS320F28335; the iterative operation of the discrete memristor-driven neuron model is realized by the control chip, thereby realizing the discrete memristor-driven neuron model with a digital circuit.

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