Chaotic feature-based chip defect detection method, electronic equipment and medium

Abstract

The invention provides a method for detecting chip defects based on chaotic features, electronic equipment and a medium, and the method comprises the steps: obtaining the physical quantity data of a chip in a working state, determining the embedding dimension and the embedding delay of the physical quantity data, reconstructing the reconstruction phase space of the physical quantity data according to the embedding dimension and the embedding delay, and obtaining the chip defects based on the reconstructed phase space. And according to the reconstructed phase space, determining a chaotic characteristic value of the physical quantity data, and inputting the physical quantity data and the chaotic characteristic value into a pre-constructed HKLS-SVM model for detection to obtain a detection result. Therefore, the weak signal change generated by the chip tiny defects can be accurately and quickly captured based on the chaotic features, the detection precision of the chip defects is improved, the model corresponding to the chaotic algorithm is low in data dependence, the training process and the calculation process are simple, the chip detection efficiency is improved, and the chip detection cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip detection, and particularly to a method, an electronic device and a medium for detecting chip defects based on chaotic characteristics. Background Art

[0002] In the chip manufacturing industry, with the continuous progress of semiconductor technology, the integration of chips is getting higher and higher, and the feature size is continuously shrinking. Developing from the early micron-level process to the current nanometer-level, the number of transistors integrated per unit area has increased exponentially. This enables chips to achieve more powerful functions in a smaller volume, but at the same time, it also poses extremely high requirements on the quality and reliability of chips. Even extremely tiny defects, such as nanoscale impurities, atomic-level lattice defects, or extremely fine circuit short circuits and open circuits, may seriously affect the performance, stability, and service life of chips.

[0003] In the complex process of chip manufacturing, from wafer preparation, lithography, etching to packaging and other links, it is possible to introduce tiny defects. For example, in the lithography process, due to uneven coating of photoresist, slight deviation of exposure dose, or defects in the mask plate, it may lead to precision errors in the chip pattern and form tiny defects; in the etching process, inconsistent etching rate or improper control of etching time may also cause damage or deformation of the chip structure and generate tiny defects. Moreover, with the continuous innovation of chip manufacturing processes, new processes and materials are emerging continuously, which further increases the possibility of generating tiny defects and the difficulty of detection.

[0004] Traditional chip detection technologies, such as optical detection and electron beam detection, gradually expose their limitations when facing increasingly tiny defects. Among them, optical detection is limited by the diffraction limit of light. For nanoscale tiny defects, the resolution is insufficient, it is difficult to accurately identify, and the reliability of the detection results is relatively low; although electron beam detection has high resolution, the detection speed is slow, the cost is high, and it may cause a certain degree of damage to the chip. In addition, when these traditional detection technologies detect complex structure chips or multi-layer chips, due to signal interference and occlusion, the reliability of the detection results is relatively low.

[0005] Therefore, how to improve the detection efficiency of chips and the reliability of detection results is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0006] The present invention provides a method, an electronic device and a medium for detecting chip defects based on chaotic characteristics, so as to solve the defects of low detection efficiency and low reliability of detection results of chips in the prior art.

[0007] On the one hand, the present invention provides a method for detecting chip defects based on chaotic characteristics, which includes: Obtain the physical quantity data of the chip in the working state; Determine the embedding dimension and embedding delay of the physical quantity data; Reconstruct the reconstructed phase space of the physical quantity data according to the embedding dimension and the embedding delay; Determine the chaotic eigenvalue of the physical quantity data according to the reconstructed phase space; Input the physical quantity data and the chaotic eigenvalue into a pre-constructed HKLS-SVM model for detection to obtain a detection result.

[0008] According to a method for detecting chip defects based on chaotic characteristics provided by the present invention, the calculation process of the embedding delay of the physical quantity data includes: Construct an autocorrelation function based on the time series length of the physical quantity data, the initial value of the time series of the physical quantity data, the mean value of the time series of the physical quantity data, and the embedding delay; Assign values to the embedding delay at a preset step size until the value of the autocorrelation function drops to a first preset threshold, and take the current assignment as the embedding delay.

[0009] According to a method for detecting chip defects based on chaotic characteristics provided by the present invention, the calculation process of the embedding dimension of the physical quantity data includes: For each trajectory point in the original phase space of the physical quantity data, find at least one neighboring trajectory point in the m-dimensional space; Add the trajectory point and the corresponding at least one neighboring trajectory point to the m+1 dimension, and calculate the rate of change of the distance between the trajectory point and each neighboring trajectory point; among them, the neighboring points with a rate of change of distance greater than a second preset threshold are false neighboring points; Assign a value to m such that when the proportion of the false neighboring points approaches 0, take the current assignment of m as the embedding dimension.

[0010] According to a method for detecting chip defects based on chaotic characteristics provided by the present invention, it further includes: If the detection result indicates that the chip has a defect, obtain the time difference between the abnormal physical quantity data detected by multiple sensors on the chip; Determine the defect position of the chip according to the time difference and the attribute data of the chip.

[0011] According to a method for detecting chip defects based on chaotic characteristics provided by the present invention, the attribute data of the chip includes the size of the chip, the material of the chip, and the circuit layout of the chip; Determine the defect position of the chip according to the time difference and the attribute data of the chip, including: Determine the position of each sensor according to the size of the chip; Determine the transmission speed of the abnormal physical quantity data according to the material of the chip and the circuit layout of the chip; Determine the defective position of the chip according to the time difference, the position of each sensor, and the transmission speed.

[0012] A method for detecting chip defects based on chaotic characteristics provided by the present invention further includes: Control the light source generator to irradiate the defective position of the chip; and / or Generate description information of the defective position of the chip and output the description information.

[0013] A method for detecting chip defects based on chaotic characteristics provided by the present invention, obtaining physical quantity data of the chip in the working state, includes: Determine the data acquisition frequency according to the characteristic information of the chip and the detection accuracy requirement information; Obtain the physical quantity data of the chip in the working state according to the data acquisition frequency.

[0014] A method for detecting chip defects based on chaotic characteristics provided by the present invention, determining the data acquisition frequency according to the characteristic information of the chip and the detection accuracy requirement information, includes: Determine the initial signal bandwidth of the data to be acquired according to the characteristic information of the chip; Determine the accuracy bandwidth margin corresponding to the detection accuracy requirement information according to the preset correlation relationship between the accuracy requirement and the bandwidth margin; Determine the final signal bandwidth of the data to be acquired according to the initial signal bandwidth, the accuracy bandwidth margin, and the preset anti-interference bandwidth margin; Determine the data acquisition frequency according to the final signal bandwidth.

[0015] On the other hand, the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the method for detecting chip defects based on chaotic characteristics as described above.

[0016] On the other hand, the present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the method for detecting chip defects based on chaotic characteristics as described above.

[0017] On the other hand, the present invention also provides a computer program product, including a computer program, which when executed by a processor, implements the method for detecting chip defects based on chaotic characteristics as described in any one of the above.

[0018] The method for detecting chip defects based on chaotic characteristics provided by the present invention can obtain the physical quantity data of the chip in the working state, determine the embedding dimension and embedding delay of the physical quantity data, reconstruct the reconstructed phase space of the physical quantity data according to the embedding dimension and the embedding delay, determine the chaotic characteristic value of the physical quantity data according to the reconstructed phase space, and input the physical quantity data and the chaotic characteristic value into a pre-constructed HKLS-SVM model for detection to obtain a detection result. In this way, it is possible to accurately and quickly capture the weak signal changes caused by tiny chip defects based on chaotic characteristics, improve the detection accuracy of chip defects, and the model corresponding to the chaotic algorithm has a low dependence on data, and the training process and calculation process are simple, which improves the efficiency of chip detection and reduces the cost of chip detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 is one of the flowcharts of the method for detecting chip defects based on chaotic characteristics provided by the embodiments of the present invention; Figure 2 is the flowchart of the method for determining the sampling frequency provided by the embodiments of the present invention; Figure 3 is the second flowchart of the method for detecting chip defects based on chaotic characteristics provided by the embodiments of the present invention; Figure 4 is the structural diagram of the electronic device provided by the embodiments of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention in conjunction with the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present invention fall within the scope of protection of the present invention.

[0022] Fundamentals of Chaos Theory: Chaos is a seemingly random complex behavior exhibited in deterministic systems, which is extremely sensitive to initial conditions. Tiny initial differences can lead to huge changes in the system state over time. In chaotic systems, common characteristic parameters include the maximum Lyapunov exponent, correlation dimension, etc. A maximum Lyapunov exponent greater than zero indicates that the system has chaotic characteristics, and the larger the value, the higher the sensitivity of the system to initial conditions; the correlation dimension reflects the fractal characteristics of the system and is used to describe the complexity of the system attractor. These chaotic characteristic parameters can be used to analyze the dynamic behavior and tiny changes of the system. Among them, the correlation dimension is a non-integer, and if the correlation dimension is less than the embedding dimension, it indicates chaotic characteristics.

[0023] Based on this foundation of chaos theory, research on physical quantity data such as the voltage, current, and temperature of the chip reveals that the physical quantity data of the chip also has chaotic characteristics. Specifically, after collecting the physical quantity data of some chips known to have faults and defects, the embedding dimension and embedding delay of the physical quantity data of the chip can be analyzed, and based on the embedding dimension and embedding delay, the reconstructed phase space of the physical quantity data can be reconstructed. Then, based on the reconstructed phase space, the chaotic characteristic values of the physical quantity data can be determined, and based on the chaotic characteristic values of the physical quantity data, it can be determined whether the physical quantity data of the chip has chaotic characteristics. Among them, the chaotic characteristic values of the physical quantity data can include the maximum Lyapunov exponent, correlation dimension, etc. Through repeated experiments and calculations, it can be obtained that the maximum Lyapunov exponent is greater than 0, the correlation dimension is a non-integer, and the correlation dimension is less than the embedding dimension. Therefore, it can be determined that when the chip has defects, the physical quantity data of the chip has chaotic characteristics.

[0024] Based on the above research findings, the present invention provides the following technical solutions: Figure 1 It is one of the flow schematic diagrams of the method for detecting chip defects based on chaotic characteristics provided by the embodiments of the present invention.

[0025] As Figure 1 shown, for the method for detecting chip defects based on chaotic characteristics provided by the embodiments of the present invention, the execution subject can be a processor in an electronic device. This method mainly includes the following steps: 101. Obtain the physical quantity data of the chip in the working state; In a specific implementation process, a high-precision sensor can be used to collect various physical quantity data of the chip in the working state (including the running state and the test state), such as current, voltage, temperature, etc. at a set data acquisition frequency. Among them, the data acquisition frequency can be determined according to the characteristic information of the chip and the information on the detection accuracy requirements. The specific determination process can refer to Figure 2 , where Figure 2It is a flowchart of a method for determining a sampling frequency provided by an embodiment of the present invention. As Figure 2 shown, the method may include the following steps: 201. Determine the initial signal bandwidth of the data to be acquired according to the characteristic information of the chip; In a specific implementation process, the characteristic information of the chip may include the operating frequency of the chip, and the operating frequency of the chip reflects the basic change speed of the internal signal of the chip. Generally speaking, the higher the operating frequency, the faster the signal changes, and the wider the signal bandwidth of the data to be acquired may be. For example, the operating frequency of a microprocessor chip is 2 GHz, which means that its internal signal may change at a rate of 2 GHz, so the signal bandwidth should at least cover this frequency range. And the rise time and fall time of the signal reflect the change speed of the signal from low level to high level or from high level to low level. The shorter the rise time and fall time , the more high-frequency components the signal contains, and the wider the required signal bandwidth.

[0026] Therefore, the initial signal bandwidth of the data to be acquired can be estimated according to the rise time or fall time of the signal. Among them, the empirical formula for estimating the initial signal bandwidth of the data to be acquired can be as follows: , where is the rise time or fall time .

[0027] 202. Determine the precision bandwidth margin corresponding to the detection precision requirement information according to the preset correlation between the precision requirement and the bandwidth margin; In a specific implementation process, the detection precision requirement determines the degree of signal details that need to be captured, and has an important impact on the estimation of the signal bandwidth. For example, the detection precision requirement may be that the voltage change is less than 1 mV or the time change is less than 1 ns, then a wider signal bandwidth is required to capture these subtle changes. The corresponding bandwidth margin can be set according to different detection precision requirements to form the correlation between the precision requirement and the bandwidth margin. This correlation between the precision requirement and the bandwidth margin can be a table or other forms of existence, and this embodiment does not make specific limitations. In this way, when the detection precision requirement information is obtained, the precision bandwidth margin corresponding to the detection precision requirement information can be obtained according to this correlation between the precision requirement and the bandwidth margin.

[0028] 203. Determine the final signal bandwidth of the data to be acquired according to the initial signal bandwidth, the precision bandwidth margin, and the preset anti-interference bandwidth margin; In a specific implementation process, noise and interference will affect the quality of the acquired data. To reduce the influence of noise and interference, the acquisition frequency can be appropriately increased to increase the redundancy and anti-interference ability of the data. Specifically, through experiments or referring to the experience of similar applications, a suitable noise margin can be determined as the anti-interference bandwidth margin, such as a margin of 20% to 50%. In this way, the final signal bandwidth of the data to be acquired can be determined according to the initial signal bandwidth, the precision bandwidth margin, and the preset anti-interference bandwidth margin. For example, the sum of the initial signal bandwidth, the precision bandwidth margin, and the preset anti-interference bandwidth margin is used as the final signal bandwidth of the data to be acquired.

[0029] 204. Determine the data acquisition frequency according to the final signal bandwidth.

[0030] In a specific implementation process, if a certain signal is acquired, the generally required data acquisition frequency is more than twice the bandwidth of the signal. Therefore, the data acquisition frequency determined in this embodiment is at least twice the final signal bandwidth.

[0031] It should be noted that although the influence of noise and interference has been considered in the process of acquiring the physical quantity data of the acquisition chip, and the relevant anti-interference bandwidth margin is added when setting the data sampling frequency. However, during the acquisition process, it may still be affected by various noises, such as the electronic noise of the detection device itself, environmental electromagnetic interference, etc., which will affect the accuracy of the chaos analysis. Therefore, the wavelet threshold denoising method and the Gaussian low-pass filtering method can be used to process the original data, and finally the physical quantity data of the chip can be obtained. Among them, by comparing the effects of different filtering methods, a Gaussian low-pass filter that can effectively remove noise while retaining the data characteristics to the greatest extent is selected to smooth the data, providing a reliable data basis for the subsequent chaos analysis.

[0032] 102. Determine the embedding dimension and embedding delay of the physical quantity data; In a specific implementation process, an autocorrelation function can be constructed based on the time series length of the physical quantity data, the initial value of the time series of the physical quantity data, the mean value of the time series of the physical quantity data, and the embedding delay, and the embedding delay is assigned according to a preset step size until the value of the autocorrelation function drops to a first preset threshold, and the current assignment is used as the embedding delay. The first preset threshold can be 0.

[0033] Specifically, the autocorrelation function can be the following calculation formula (1): (1) Wherein, represents the value of the autocorrelation function, Represents the time series length of the physical quantity data, Represents the initial value of the time series of the physical quantity data, Represents the mean value of the time series of the physical quantity data, Represents the embedding delay.

[0034] In a specific implementation process, when the embedding dimension is insufficient, the adjacent trajectory points of a certain trajectory point in the phase space are "false trajectory points", which overlap due to projection into a low-dimensional space. As the embedding dimension increases, the proportion of false trajectory points will decrease. Therefore, the embedding dimension can be obtained based on this principle.

[0035] Specifically, for each trajectory point in the original phase space of the physical quantity data, find at least one neighboring trajectory point in the m-dimensional space; add the trajectory point and the corresponding at least one neighboring trajectory point to the m + 1 dimension, and calculate the rate of change of the distance between the trajectory point and each neighboring trajectory point; among them, the neighboring points with a rate of change of distance greater than the second preset threshold are false neighboring points; assign a value to m such that when the proportion of the false neighboring points approaches 0, the current assignment of m is used as the embedding dimension, where approaching 0 means the value of m can make the proportion of the false neighboring points as close to 0 as possible.

[0036] 103. Reconstruct the reconstructed phase space of the physical quantity data according to the embedding dimension and the embedding delay; In a specific implementation process, the reconstructed phase space can be obtained according to the obtained embedding dimension and embedding delay. Among them, the reconstructed phase space can be represented by the calculation formula (2): (2) Wherein, Represents all the trajectory points of the reconstructed phase space.

[0037] 104. Determine the chaotic eigenvalue of the physical quantity data according to the reconstructed phase space; In a specific implementation process, the chaotic eigenvalue of the physical quantity data can be determined according to the reconstructed phase space. Among them, the specific process can refer to the relevant technologies of existing chaotic algorithms and will not be elaborated here.

[0038] 105. Input the physical quantity data and the chaotic eigenvalue into a pre-constructed HKLS-SVM model for detection to obtain a detection result.

[0039] In a specific implementation process, the principle of Support Vector Machine (SVM): SVM is a classification algorithm based on statistical learning theory. Its core idea is to find an optimal classification hyperplane in the feature space to maximize the margin between different classes of data. Least Squares Support Vector Machine (LS-SVM) is an improved form of SVM. It simplifies the calculation process and improves the classification efficiency by converting inequality constraints into equality constraints. In practical applications, the performance of SVM depends to a large extent on the choice of kernel function. Different kernel functions are suitable for different problems. For example, the Gaussian kernel function is good at dealing with local features, while the sigmoid kernel function has an advantage in capturing global features. Therefore, a Hybrid Kernel Least Squares Support Vector Machine (HKLS-SVM) model can be constructed based on the Gaussian kernel function and the sigmoid kernel function, so as to combine the advantages of the Gaussian kernel function and the sigmoid kernel function, and use the Particle Swarm Optimization (PSO) algorithm to optimize the model parameters to improve the classification performance of the model. When training the model, the maximum Lyapunov exponent, correlation dimension, and the average values of the physical quantity data of the chip (such as average current, average voltage, etc.) are selected as the input feature vectors. The signals of normal chips and chips with minor defects are respectively labeled as "-1" and "1" to train the model so that the model can accurately distinguish normal signals and minor defect signals.

[0040] In this way, after obtaining the chaotic characteristic values of the physical quantity data of the chip, the chaotic characteristic values of the physical quantity data and the physical quantity data of the chip can be input into the pre-constructed HKLS-SVM model for detection to obtain the detection result. Among them, if the detection result is "1", it is judged that a minor defect is detected in the chip. If the detection result is "-1", it is judged that no minor defect is detected in the chip.

[0041] In a specific implementation process, the detection of the chip based on the chaotic algorithm in this embodiment has the following effects: First, by utilizing the sensitive characteristics of chaotic features to minor changes, it can more accurately capture the weak signal changes caused by minor defects in the chip, and can extract more subtle features from complex chip signals, avoiding misjudgment and missed judgment caused by insufficient feature extraction, thereby greatly improving the detection accuracy of minor defects in the chip.

[0042] II. Reducing the Dependence on Massive Annotated Data. The chaos algorithm can discover the internal laws of the chip's operating state from a small amount of data. Even when the data is limited, it can effectively detect tiny defects. At the same time, for new chip models and defect types, the chaos algorithm can quickly adapt to data changes without the need to re-collect a large amount of data and train the model for a long time, improving the adaptability and detection efficiency of the detection system and meeting the requirements of rapid chip production and product replacement.

[0043] III. Improving Detection Efficiency and Real-time Performance: During the chip production process, detection efficiency is crucial. The detection processes of existing technologies are complex and involve large amounts of calculations, making it difficult to meet the requirements of real-time detection. The present invention utilizes the advantage of the chaos algorithm in quickly processing data to optimize the detection process. By directly analyzing chip data in the chaos domain, it reduces the complex intermediate conversion and calculation steps, speeds up the detection, realizes real-time monitoring and rapid response to tiny chip defects, discovers problems in a timely manner and processes them, thereby improving the overall efficiency of chip production.

[0044] IV. Reducing Detection Costs: For existing chip tiny defect detection technologies, whether it is obtaining a large amount of annotated data or running complex CNN models, it requires a large amount of human, material, and computing resources, resulting in high detection costs. The present invention adopts the chaos algorithm, reduces the dependence on massive annotated data, and reduces the costs of data collection and annotation. At the same time, the chaos algorithm is relatively simple, has a low computational complexity, has low requirements for computing resources, and can run on ordinary hardware devices, reducing hardware costs and energy consumption, thereby achieving the purpose of reducing the detection costs of chip tiny defects.

[0045] Figure 3 It is the second schematic flowchart of the method for detecting chip defects based on chaos features provided by an embodiment of the present invention. As Figure 3 shown, the method for detecting chip defects based on chaos features provided by an embodiment of the present invention mainly includes the following steps: 301. Obtain the physical quantity data of the chip in the working state; 302. Determine the embedding dimension and embedding delay of the physical quantity data; 303. According to the initial signal bandwidth, the precision bandwidth margin, and the preset anti-interference bandwidth margin, determine the final signal bandwidth of the data to be obtained; 304. According to the reconstructed phase space, determine the chaos eigenvalue of the physical quantity data; 305. Input the physical quantity data and the chaos eigenvalue into a pre-constructed HKLS-SVM model for detection to obtain a detection result; Steps 301 to 305 above can refer to the above relevant embodiments and will not be elaborated here.

[0046] 306. If the detection result indicates that the chip has a defect, obtain the time difference between the abnormal physical quantity data detected by multiple sensors on the chip. In a specific implementation process, if the obtained detection result indicates that the chip has a defect, in order to provide accurate information for subsequent repair or processing, the time difference between the abnormal physical quantity data detected by multiple sensors on the chip can be obtained, so that the defect location of the chip can be located according to the obtained time difference subsequently.

[0047] 307. Determine the defect location of the chip according to the time difference and the attribute data of the chip.

[0048] In a specific implementation process, the attribute data of the chip may include the size of the chip, the material of the chip, and the circuit layout of the chip. The calculation formulas for the defect location of different chips are different according to their attribute data. In this embodiment, the position of each sensor can be determined according to the size of the chip, and then the transmission speed of the abnormal physical quantity data can be determined according to the material of the chip and the circuit layout of the chip. Then, according to the time difference, the position of each sensor, and the transmission speed, the defect location of the chip can be determined.

[0049] Specifically, taking a rectangular chip as an example, the size of the chip is length L and width W. There are 4 sensors, denoted as sensor 1 to sensor 4, which are placed at the four corners of the chip respectively. Then, according to the length and width of the chip, the position of each sensor can be obtained, and the coordinates corresponding to the position of each sensor are sensor 1(0, 0), sensor 2(L, 0), sensor 3(L, W), and sensor 4(0, W).

[0050] In a specific implementation process, different materials and different layouts of the chip have different effects on the data transmission speed. Therefore, experiments can be carried out for different materials and different layout methods to obtain the corresponding data transmission speeds, and the corresponding relationship of material-layout-speed can be constructed. In this way, the transmission speed of the abnormal physical quantity data can be determined according to the material of the chip and the circuit layout of the chip by using this corresponding relationship. Wherein, the transmission speed of the abnormal physical quantity data is denoted as v.

[0051] In a specific implementation process, the defect location of the chip can be further determined according to the time difference, the position of each sensor, and the transmission speed.

[0052] Specifically, based on the obtained time difference, the distance difference of the abnormal physical quantity data reaching each sensor can be calculated. The specific calculation formula can refer to the following formula (3): (3) Wherein, represents the distance difference between the abnormal physical quantity data reaching sensor 2 and the abnormal physical quantity data reaching sensor 1, represents the time difference between the abnormal physical quantity data arriving at sensor 2 and the abnormal physical quantity data arriving at sensor 1; represents the distance difference between the abnormal physical quantity data reaching sensor 3 and the abnormal physical quantity data reaching sensor 1, represents the time difference between the abnormal physical quantity data arriving at sensor 2 and the abnormal physical quantity data arriving at sensor 1; represents the distance difference between the abnormal physical quantity data reaching sensor 4 and the abnormal physical quantity data reaching sensor 1, It represents the time difference between when the abnormal physical quantity data reaches the sensor 4 and when the abnormal physical quantity data reaches the sensor 1.

[0053] Assume that the coordinates of the defect position of the chip are (x, y), and the distance between the defect position of the chip and sensor 1 is , the measurement values ​​of sensors 2 to 4 can be used to construct the following calculation formulas (4) to (6): Among them, the calculation formula (4) corresponding to sensor 2 is as follows: (4) Among them, the calculation formula (5) corresponding to sensor 3 is as follows: (5) Among them, the calculation formula (6) corresponding to sensor 4 is as follows: (6) Combining equations (4) to (6), we can obtain Calculation formula (7): (7) Will Substituting into equations (4) and (6), we can obtain the coordinates of the defect position of the chip as equation (8): (8) In a specific implementation process, in order to facilitate relevant personnel to quickly find the defective position of the chip, the light source generator can be controlled to adjust the irradiation angle of the light so as to irradiate the defective position of the chip; and / or, the description information of the defective position of the chip is generated and output. For example, the relevant information of the electrical components in the area where the defective position of the chip is located can be determined according to the layout of the chip, so that the defective position of the chip can be quickly found according to the relevant information of the electrical components.

[0054] The method for detecting chip defects based on chaotic characteristics in this embodiment can utilize the unique dynamic characteristics of the chaotic algorithm and combine with the chip structure characteristics to achieve more accurate defect localization. By means of chaotic analysis, the chaotic characteristic change region caused by defects is determined, providing a more accurate basis for defect localization. Moreover, the chaotic algorithm can also work better in coordination with other detection technologies, organically combining chaotic characteristics with microscopic detection technologies, rule-based detection technologies, etc., to form a more comprehensive and efficient detection system, improving the comprehensive detection ability for tiny defects in complex chips.

[0055] Based on the same general inventive concept, the present invention also protects an electronic device. The electronic device provided by the present invention will be described below, and the electronic device described below can be correspondingly referred to the method for detecting chip defects based on chaotic characteristics described above.

[0056] Figure 4 FIG. is a schematic structural diagram of the electronic device provided by the embodiments of the present invention. The electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communication bus 440. Among them, the processor 410, the communications interface 420, and the memory 430 complete mutual communication through the communication bus 440. The processor 410 can call the logic instructions in the memory 430 to execute the method for detecting chip defects based on chaotic characteristics.

[0057] In addition, when the logic instructions in the above-mentioned memory 430 are implemented in the form of software functional units and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that makes contributions to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0058] On the other hand, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it is configured to execute the method for detecting chip defects based on chaotic characteristics provided by the above-mentioned various methods.

[0059] It should be noted that the relevant data that may be involved in the embodiments of this application are all processed in strict accordance with the requirements of laws and regulations, following the principles of legality, legitimacy, and necessity, for reasonable purposes based on business scenarios, and are personal information actively provided by users during the use of products / services, or generated due to the use of products / services, as well as obtained with user authorization.

[0060] The relevant data processed by this application may vary depending on the specific product / service scenario, and it is necessary to be subject to the specific scenario of the user's use of the product / service. It may involve the user's account information, device information, driving information, vehicle information, or other relevant information. This application will treat the user's personal information and its processing with a high degree of due diligence.

[0061] This application attaches great importance to the security of relevant data and has taken security protection measures that meet industry standards and are reasonable and feasible to protect the relevant data, preventing the relevant data from being accessed without authorization, publicly disclosed, used, modified, damaged, or lost.

[0062] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0063] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for detecting chip defects based on chaotic characteristics, characterized in that, Including: Obtain the physical quantity data of the chip in the working state; Determine the embedding dimension and embedding delay of the physical quantity data; According to the embedding dimension and the embedding delay, reconstruct the reconstructed phase space of the physical quantity data; According to the reconstructed phase space, determine the chaotic eigenvalue of the physical quantity data; Input the physical quantity data and the chaotic eigenvalue into a pre-constructed HKLS-SVM model for detection to obtain a detection result.

2. The method for detecting chip defects based on chaotic characteristics according to claim 1, wherein The calculation process of the embedding delay of the physical quantity data includes: Based on the time series length of the physical quantity data, the initial value of the time series of the physical quantity data, the mean value of the time series of the physical quantity data, and the embedding delay, construct an autocorrelation function; Assign values to the embedding delay in accordance with a preset step size until the value of the autocorrelation function drops to a first preset threshold, and use the current assignment as the embedding delay.

3. The method for detecting chip defects based on chaotic characteristics according to claim 1, wherein The calculation process of the embedding dimension of the physical quantity data includes: For each trajectory point in the original phase space of the physical quantity data, find at least one neighboring trajectory point in the m-dimensional space; Add the trajectory point and the corresponding at least one neighboring trajectory point to the m+1 dimension, and calculate the rate of change of the distance between the trajectory point and each neighboring trajectory point; among them, the neighboring points with a rate of change of distance greater than a second preset threshold are false neighboring points; Assign a value to m such that when the proportion of the false neighboring points approaches 0, use the current assignment of m as the embedding dimension.

4. The method for detecting chip defects based on chaotic characteristics according to claim 1, wherein It also includes: If the detection result indicates that the chip has a defect, obtain the time difference between the abnormal physical quantity data detected by multiple sensors on the chip; According to the time difference and the attribute data of the chip, determine the defect location of the chip.

5. The method for detecting chip defects based on chaotic characteristics according to claim 4, characterized in that The attribute data of the chip includes the size of the chip, the material of the chip, and the circuit layout of the chip; Determining the defect location of the chip according to the time difference and the attribute data of the chip includes: According to the size of the chip, determine the position of each sensor; According to the material of the chip and the circuit layout of the chip, determine the transmission speed of the abnormal physical quantity data; According to the time difference, the position of each sensor, and the transmission speed, determine the defect location of the chip.

6. The method for detecting chip defects based on chaotic characteristics according to claim 5, wherein It also includes: Control the light source generator to irradiate the defect location of the chip; And / or Generate description information of the defect location of the chip and output the description information.

7. The method for detecting chip defects based on chaotic characteristics according to any one of claims 1 to 6, characterized in that, Obtaining the physical quantity data of the chip in the working state includes: According to the characteristic information of the chip and the detection accuracy requirement information, determine the data acquisition frequency; According to the data acquisition frequency, obtain the physical quantity data of the chip in the working state.

8. The method for detecting chip defects based on chaotic characteristics according to claim 7, wherein Determining the data acquisition frequency according to the characteristic information of the chip and the detection accuracy requirement information includes: According to the characteristic information of the chip, determine the initial signal bandwidth of the data to be obtained; According to the preset correlation relationship between the accuracy requirement and the bandwidth margin, determine the accuracy bandwidth margin corresponding to the detection accuracy requirement information; According to the initial signal bandwidth, the accuracy bandwidth margin, and the preset anti-interference bandwidth margin, determine the final signal bandwidth of the data to be obtained; Determine the data acquisition frequency according to the final signal bandwidth.

9. An electronic device, characterized in that, Comprising: A memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the program, the method for detecting chip defects based on chaotic characteristics as described in any one of claims 1 to 8 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the method for detecting chip defects based on chaotic characteristics as described in any one of claims 1 to 8 is implemented.

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