Method for detecting chip defects based on chaotic characteristics, electronic device, and medium

Abstract

The application provides a method for detecting chip defects based on chaotic characteristics, an electronic device and a medium. The method comprises the following steps: acquiring physical quantity data of a chip in a working state; determining an embedding dimension and an embedding delay of the physical quantity data; reconstructing a reconstructed phase space of the physical quantity data according to the embedding dimension and the embedding delay; determining a chaotic characteristic value of the physical quantity data according to the reconstructed phase space; inputting the physical quantity data and the chaotic characteristic value into a pre-constructed HKLS-SVM model for detection to obtain a detection result. In this way, the weak signal change caused by the tiny defect of the chip can be accurately and quickly captured based on the chaotic characteristics, the detection accuracy of the chip defect is improved, the model corresponding to the chaotic algorithm has low data dependence, the training process and the calculation process are simple, the chip detection efficiency is improved, and the chip detection cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip detection, and in particular to a method for detecting chip defects based on chaotic characteristics, an electronic device and a medium. BACKGROUND

[0002] In the chip manufacturing industry, with the continuous progress of semiconductor technology, the integration of chips is becoming higher and higher, and the feature size is continuously shrinking. From the early micron process to the current nanometer process, the number of transistors integrated on a unit area has increased exponentially. This enables chips to achieve more powerful functions in a smaller volume, but at the same time puts extremely high requirements on the quality and reliability of chips. Even extremely small defects, such as nanoscale impurities, atomic lattice defects, or extremely fine line short circuits, can seriously affect the performance, stability and service life of the chip.

[0003] In the complex process of chip manufacturing, from silicon wafer preparation, photolithography, etching to packaging, etc., there is a possibility of introducing small defects. For example, in the photolithography process, due to uneven coating of photoresist, small deviations in exposure dose or defects in the mask, it may cause precision errors in the chip pattern, forming small defects; in the etching process, the inconsistency of etching rate or improper control of etching time may also cause damage or deformation of the chip structure, resulting in small defects. Moreover, with the continuous innovation of chip manufacturing processes, new processes and materials are constantly emerging, which further increases the possibility of small defects and the difficulty of detection.

[0004] Traditional chip detection technologies, such as optical detection and electron beam detection, gradually reveal their limitations when faced with increasingly small defects. Among them, optical detection is limited by the diffraction limit of light, and for nanoscale small defects, the resolution is insufficient, making it difficult to accurately identify, and the reliability of the detection result is low; electron beam detection has high resolution, but the detection speed is slow, the cost is high, and it may cause some damage to the chip. In addition, these traditional detection technologies have low reliability of detection results when detecting complex structure chips or multi-layer chips due to signal interference and obstruction.

[0005] Therefore, how to improve the detection efficiency of chips and the reliability of detection results is a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0006] The present application provides a method for detecting chip defects based on chaotic characteristics, an electronic device and a medium, to solve the defects of low detection efficiency and low reliability of detection results in the prior art.

[0007] In one aspect, the present application provides a method for detecting chip defects based on chaotic characteristics, comprising:

[0008] acquire physical quantity data of the chip in a working state;

[0009] determine an embedding dimension and an embedding delay of the physical quantity data;

[0010] reconstruct a reconstructed phase space of the physical quantity data according to the embedding dimension and the embedding delay;

[0011] determine a chaotic characteristic value of the physical quantity data according to the reconstructed phase space;

[0012] input the physical quantity data and the chaotic characteristic value into a pre-constructed HKLS-SVM model for detection to obtain a detection result.

[0013] According to the method for detecting chip defects based on chaotic characteristics provided by the application, the calculation process of the embedding delay of the physical quantity data comprises:

[0014] construct an autocorrelation function based on the time series length of the physical quantity data, the initial value of the time series of the physical quantity data, the mean value of the time series of the physical quantity data and the embedding delay;

[0015] value the embedding delay according to a preset step size, and when the value of the autocorrelation function falls to a first preset threshold value, take the current value as the embedding delay.

[0016] According to the method for detecting chip defects based on chaotic characteristics provided by the application, the calculation process of the embedding dimension of the physical quantity data comprises:

[0017] for each trajectory point in the original phase space of the physical quantity data, find at least one adjacent trajectory point in an m-dimensional space;

[0018] increase the trajectory point and the corresponding at least one adjacent trajectory point to an m+1-dimensional space, and calculate the distance change rate between the trajectory point and each adjacent trajectory point; wherein the adjacent point with a distance change rate greater than a second preset threshold value is a false adjacent point;

[0019] value m so that when the proportion of the false adjacent points tends to 0, take the current value of m as the embedding dimension.

[0020] According to the method for detecting chip defects based on chaotic characteristics provided by the application, the method further comprises:

[0021] if the detection result indicates that the chip has defects, acquire the time difference of the abnormal physical quantity data detected by multiple sensors on the chip;

[0022] determine the defect position of the chip according to the time difference and the attribute data of the chip.

[0023] A method for detecting chip defects based on chaotic characteristics is provided, wherein attribute data of the chip includes size of the chip, material of the chip and circuit layout of the chip.

[0024] According to the time difference and the attribute data of the chip, a defect position of the chip is determined, including:

[0025] According to the size of the chip, a position of each sensor is determined;

[0026] According to the material of the chip and the circuit layout of the chip, a transmission speed of the abnormal physical quantity data is determined;

[0027] According to the time difference, the position of each sensor and the transmission speed, the defect position of the chip is determined.

[0028] The method for detecting chip defects based on chaotic characteristics further includes:

[0029] controlling a light source generator to irradiate the defect position of the chip; and / or

[0030] generating description information of the defect position of the chip and outputting the description information.

[0031] The method for detecting chip defects based on chaotic characteristics further includes:

[0032] According to the characteristic information of the chip and detection precision requirement information, a data acquisition frequency is determined;

[0033] According to the data acquisition frequency, the physical quantity data of the chip in a working state is acquired.

[0034] According to the characteristic information of the chip and detection precision requirement information, a data acquisition frequency is determined, including:

[0035] According to the characteristic information of the chip, an initial signal bandwidth of data to be acquired is determined;

[0036] According to a preset correlation between precision requirement and bandwidth margin, a precision bandwidth margin corresponding to the detection precision requirement information is determined;

[0037] According to the initial signal bandwidth, the precision bandwidth margin and a preset anti-interference bandwidth margin, a final signal bandwidth of the data to be acquired is determined;

[0038] According to the final signal bandwidth, the data acquisition frequency is determined.

[0039] In another aspect, the present application also provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method for detecting chip defects based on chaotic characteristics according to any one of the above aspects when executing the program.

[0040] In another aspect, the present application also provides a non-transitory computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method for detecting chip defects based on chaotic characteristics according to any one of the above aspects.

[0041] In another aspect, the present application also provides a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the method for detecting chip defects based on chaotic characteristics according to any one of the above aspects.

[0042] The method for detecting chip defects based on chaotic characteristics provided by the present application can obtain physical quantity data of a chip in a working state, determine an embedding dimension and an embedding delay of the physical quantity data, reconstruct a reconstructed phase space of the physical quantity data according to the embedding dimension and the embedding delay, determine a chaotic characteristic value of the physical quantity data according to the reconstructed phase space, input the physical quantity data and the chaotic characteristic value into a pre-constructed HKLS-SVM model for detection, and obtain a detection result. In this way, the weak signal change caused by a small chip defect can be accurately and quickly captured based on chaotic characteristics, the detection accuracy of the chip defect is improved, the model corresponding to the chaotic algorithm has a relatively low dependence on data, the training process and the calculation process are simple, the efficiency of chip detection is improved, and the cost of chip detection is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0044] Figure 1 is one of the flowcharts of the method for detecting chip defects based on chaotic characteristics provided by the embodiments of the present application;

[0045] Figure 2 is a flowchart of the method for determining a sampling frequency provided by the embodiments of the present application;

[0046] Figure 3 is another flowchart of the method for detecting chip defects based on chaotic characteristics provided by the embodiments of the present application;

[0047] Figure 4 Figure 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0049] Chaotic theory basis: chaos is a kind of complex behavior that appears in a deterministic system, which is extremely sensitive to initial conditions, and small initial differences will lead to huge changes in system state over time. In a chaotic system, commonly used characteristic parameters include maximum Lyapunov exponent, correlation dimension, etc. The maximum Lyapunov exponent greater than zero indicates that the system has chaotic characteristics, and the larger the value, the higher the sensitivity of the system to initial conditions; the correlation dimension reflects the fractal characteristics of the system, which is used to describe the complexity of the system attractor. These chaotic characteristic parameters can be used to analyze the dynamic behavior and small changes of the system. Among them, the correlation dimension is a non-integer, and the correlation dimension is less than the embedding dimension, which indicates that it has chaotic characteristics.

[0050] Based on the chaotic theory basis, it is found that the physical quantity data of the chip also has chaotic characteristics by studying the voltage, current, temperature and other physical quantity data of the chip. Specifically, after collecting the physical quantity data of some chips known to have fault defects, the physical quantity data of the chip is analyzed to obtain the embedding dimension and embedding delay of the physical quantity data of the chip, and according to the embedding dimension and embedding delay, the reconstructed phase space of the physical quantity data is reconstructed, then according to the reconstructed phase space, the chaotic characteristic value of the physical quantity data is determined, and according to the chaotic characteristic value of the physical quantity data, it is determined whether the physical quantity data of the chip has chaotic characteristics. The chaotic characteristic value of the physical quantity data can include maximum Lyapunov exponent, correlation dimension, etc. Through repeated experiments and calculations, it can be found that the maximum Lyapunov exponent is greater than 0, the correlation dimension is a non-integer, and the correlation dimension is less than the embedding dimension, so it can be determined that the chip has defects, and the physical quantity data of the chip has chaotic characteristics.

[0051] Based on the above research findings, the present application provides the following technical solutions:

[0052] Figure 1 Figure 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application.

[0053] As Figure 1 shown, the method for detecting chip defects based on chaotic characteristics provided by the embodiment of the application can be executed by a processor in an electronic device, and the method mainly includes the following steps:

[0054] 101, acquiring physical quantity data of the chip in a working state;

[0055] In a specific implementation process, a high-precision sensor can be used to collect a plurality of physical quantity data of the chip in a working state (including a running state and a testing state) at a set data collection frequency, such as current, voltage, temperature, and the like. The data collection frequency can be determined according to characteristic information of the chip and detection precision requirement information, and a specific determination process can be referred to Figure 2 , wherein Figure 2 is a flowchart of the method for determining a sampling frequency provided by the embodiment of the application, as shown in Figure 2 , the method can include the following steps:

[0056] 201, determining an initial signal bandwidth of data to be acquired according to the characteristic information of the chip;

[0057] In a specific implementation process, the characteristic information of the chip can include a working frequency of the chip, and the working frequency of the chip reflects a basic change speed of internal signals of the chip. Generally, the higher the working frequency, the faster the signal changes, and the wider the signal bandwidth of data to be acquired can be. For example, the working frequency of a microprocessor chip is 2 GHz, which means that the internal signals can change at a rate of 2 GHz, and the signal bandwidth needs to cover at least this frequency range. The rise time and the fall time reflect the change speed of the signal from a low level to a high level or from a high level to a low level. The shorter the rise time and the fall time , the more high-frequency components the signal contains, and the wider the required signal bandwidth.

[0058] Therefore, the initial signal bandwidth of data to be acquired can be estimated according to the rise time or the fall time . An empirical formula for estimating the initial signal bandwidth of data to be acquired can be as follows: , wherein is the rise time or the fall time .

[0059] 202, determining an accuracy bandwidth margin corresponding to the detection precision requirement information according to a preset correlation between an accuracy requirement and a bandwidth margin;

[0060] In a specific implementation process, the detection accuracy requirement determines the degree of signal details to be captured, and has an important influence on the estimation of signal bandwidth. For example, the detection accuracy requirement can be that the voltage change is less than 1 mV or the time change is less than 1 ns, and then a wider signal bandwidth is required to capture these subtle changes. According to different detection accuracy requirements, a corresponding bandwidth margin can be set to form an association between the accuracy requirement and the bandwidth margin, which can be a table or other forms, and the embodiment does not make specific limitations. In this way, after obtaining the detection accuracy requirement information, the accuracy bandwidth margin corresponding to the detection accuracy requirement information can be obtained according to the association between the accuracy requirement and the bandwidth margin.

[0061] 203. Determine the final signal bandwidth of the data to be acquired according to the initial signal bandwidth, the accuracy bandwidth margin, and a preset anti-interference bandwidth margin;

[0062] In a specific implementation process, noise and interference can affect the quality of the collected data. In order to reduce the influence of noise and interference, the collection frequency can be appropriately increased to increase the redundancy and anti-interference ability of the data. Specifically, a suitable noise margin can be determined as an anti-interference bandwidth margin through experiments or by referring to the experience of similar applications, such as a margin of 20% to 50%. In this way, the final signal bandwidth of the data to be acquired can be determined according to the initial signal bandwidth, the accuracy bandwidth margin, and the preset anti-interference bandwidth margin. For example, the sum of the initial signal bandwidth, the accuracy bandwidth margin, and the preset anti-interference bandwidth margin is taken as the final signal bandwidth of the data to be acquired.

[0063] 204. Determine the data collection frequency according to the final signal bandwidth.

[0064] In a specific implementation process, if a certain signal is acquired, the data collection frequency required is usually more than 2 times the bandwidth of the signal. Therefore, the data collection frequency determined in the embodiment is at least 2 times the final signal bandwidth.

[0065] It should be noted that although the above process of collecting physical quantity data of the chip has considered the influence of noise and interference, and the relevant anti-interference bandwidth margin is added when setting the data sampling frequency. However, during the collection process, the chip may still be disturbed by various noises, such as electronic noise of the detection device itself and environmental electromagnetic interference, which can affect the accuracy of the chaos analysis. Therefore, the wavelet threshold denoising method and the Gaussian low-pass filtering method can be used to process the original data, and finally the physical quantity data of the chip is obtained. Among them, by comparing the effects of different filtering methods, the Gaussian low-pass filter which can effectively remove noise while preserving the characteristics of the data to the greatest extent is selected to smooth the data, and provides a reliable data basis for subsequent chaos analysis.

[0066] 102、determining the embedding dimension and embedding delay of the physical quantity data;

[0067] In one specific implementation process, the autocorrelation function can be constructed based on the time series length of the physical quantity data, the time series initial value of the physical quantity data, the time series mean of the physical quantity data, and the embedding delay, and the embedding delay is assigned according to a preset step size, until the value of the autocorrelation function falls to a first preset threshold, and the current assignment is taken as the embedding delay. The first preset threshold can be 0.

[0068] Specifically, the autocorrelation function can be the following calculation formula (1):

[0069] (1)

[0070] wherein, the value of the autocorrelation function, the time series length of the physical quantity data, the time series initial value of the physical quantity data, the time series mean of the physical quantity data, the embedding delay.

[0071] In one specific implementation process, when the embedding dimension is insufficient, the neighboring trajectory points of a certain trajectory point in the phase space are "false trajectory points", which overlap due to projection into a low-dimensional space, and with the increase of the embedding dimension, the proportion of false trajectory points will decrease, so the embedding dimension can be obtained based on this principle.

[0072] Specifically, for each trajectory point in the original phase space of the physical quantity data, at least one neighboring trajectory point is found in the m-dimensional space; the trajectory point and the corresponding at least one neighboring trajectory point are increased to m+1 dimensions, and the distance change rate between the trajectory point and each neighboring trajectory point is calculated; wherein the neighboring point with a distance change rate greater than a second preset threshold is a false neighboring point; m is assigned such that when the proportion of false neighboring points approaches 0, the current assignment of m is taken as the embedding dimension. Here, approaching 0 means that the value of m can make the proportion of false neighboring points as close to 0 as possible.

[0073] 103、reconstructing a reconstructed phase space of the physical quantity data according to the embedding dimension and the embedding delay;

[0074] In one specific implementation process, the reconstructed phase space can be obtained according to the obtained embedding dimension and embedding delay. The reconstructed phase space can be represented by calculation formula (2):

[0075] (2)

[0076] wherein, representing all trajectory points of the reconstructed phase space.

[0077] 104. determining the chaotic characteristic value of the physical quantity data according to the reconstructed phase space;

[0078] In one specific implementation process, the chaotic characteristic value of the physical quantity data can be determined according to the reconstructed phase space. The specific process can refer to the related technology of existing chaos algorithm, which will not be repeated here.

[0079] 105. inputting the physical quantity data and the chaotic characteristic value into a pre-constructed HKLS-SVM model for detection to obtain a detection result.

[0080] In one specific implementation process, the support vector machine (SVM) principle: SVM is a classification algorithm based on statistical learning theory, and its core idea is to find an optimal classification hyperplane in the feature space to maximize the separation between different classes. Least squares support vector machine (LS-SVM) is an improved form of SVM, which simplifies the calculation process and improves the classification efficiency by converting inequality constraints into equality constraints. In practical applications, the performance of SVM depends largely on the selection of kernel functions, and different kernel functions are suitable for different problems. For example, the Gaussian kernel function is good at processing local features, while the sigmoid kernel function has an advantage in capturing global features, so a hybrid kernel least squares support vector machine (Hybrid Kernel Least Squares Support Vector Machine, HKLS-SVM, HKLS-SVM) model can be constructed based on the Gaussian kernel function and the sigmoid kernel function, so as to combine the advantages of the Gaussian kernel function and the sigmoid kernel function, and use the particle swarm optimization (PSO) algorithm to optimize the model parameters to improve the classification performance of the model. When training the model, select the maximum Lyapunov exponent, the correlation dimension, and the average value of the physical quantity data of the chip (such as the average current, the average voltage, etc.) as the input feature vector, and mark the signals of normal chips and chips containing micro defects as "-1" and "1" respectively, so as to train the model, so that the model can accurately distinguish between normal signals and micro defect signals.

[0081] In this way, after obtaining the chaotic characteristic value of the physical quantity data of the chip, the chaotic characteristic value of the physical quantity data and the physical quantity data of the chip can be input into the pre-constructed HKLS-SVM model for detection to obtain a detection result. If the detection result is "1", it is judged that the chip has a micro defect. If the detection result is "-1", it is judged that the chip does not have a micro defect.

[0082] In a specific implementation process, the detection of the chip based on the chaotic algorithm in the embodiment has the following effects:

[0083] I. The sensitive characteristics of chaotic features to micro changes can more accurately capture the weak signal changes caused by micro defects of the chip, and can excavate more subtle features from complex chip signals, avoiding misjudgment and missed judgment caused by insufficient feature extraction, thereby greatly improving the detection accuracy of micro defects of the chip.

[0084] II. Reduce the dependence on large-scale labeled data. The chaotic algorithm can discover the internal law of the chip running state from a small amount of data, and can effectively detect micro defects even in the case of limited data. At the same time, for new chip models and defect types, the chaotic algorithm can quickly adapt to data changes without the need to collect a large amount of data and train the model for a long time, improving the adaptability and detection efficiency of the detection system, and meeting the needs of rapid production and updating of chips.

[0085] III. Improve detection efficiency and real-time performance: In the chip production process, detection efficiency is crucial. The detection process of the prior art is complex and has a large amount of calculation, which is difficult to meet the needs of real-time detection. The present application utilizes the advantage of the chaotic algorithm in quickly processing data to optimize the detection process. By directly analyzing the chip data from the chaotic domain, the intermediate complex conversion and calculation steps are reduced, the detection speed is accelerated, real-time monitoring and rapid response to micro defects of the chip are realized, problems are discovered and processed in time, and the overall efficiency of chip production is improved.

[0086] IV. Reduce detection cost: Existing chip micro defect detection technologies, whether obtaining a large amount of labeled data or running a complex CNN model, require a large amount of manpower, material resources and computing resources, resulting in high detection cost. The present application uses the chaotic algorithm to reduce the dependence on large-scale labeled data and reduce the cost of data collection and labeling. At the same time, the chaotic algorithm is relatively simple and has a low computational complexity, and the requirement for computing resources is not high, which can be run on ordinary hardware devices, reducing hardware cost and energy consumption, thereby achieving the purpose of reducing the cost of chip micro defect detection.

[0087] Figure 3 is a flowchart of the method for detecting chip defects based on chaotic characteristics provided by the embodiment of the present application. As Figure 3As shown, the method for detecting chip defects based on chaotic characteristics provided by the embodiment of the present application mainly comprises the following steps:

[0088] 301. Obtain physical quantity data of the chip in a working state;

[0089] 302. Determine the embedding dimension and embedding delay of the physical quantity data;

[0090] 303. Determine the final signal bandwidth of the data to be obtained according to the initial signal bandwidth, the precision bandwidth margin, and a preset anti-interference bandwidth margin;

[0091] 304. Determine the chaotic characteristic value of the physical quantity data according to the reconstructed phase space;

[0092] 305. Input the physical quantity data and the chaotic characteristic value into a pre-constructed HKLS-SVM model for detection to obtain a detection result;

[0093] The above steps 301 to 305 can refer to the related embodiments described above, and will not be repeated here.

[0094] 306. If the detection result indicates that the chip has defects, obtain the time difference of abnormal physical quantity data detected by multiple sensors on the chip;

[0095] In a specific implementation process, if the obtained detection result indicates that the chip has defects, in order to provide accurate information for subsequent repair or processing, the time difference of abnormal physical quantity data detected by multiple sensors on the chip can be obtained, so that the defect position of the chip can be located according to the obtained time difference.

[0096] 307. Determine the defect position of the chip according to the time difference and attribute data of the chip.

[0097] In a specific implementation process, the attribute data of the chip can include the size of the chip, the material of the chip, and the circuit layout of the chip. The attribute data of different chips is different for the calculation of the defect position of the chip. In this embodiment, the position of each sensor can be determined according to the size of the chip, and then the transmission speed of the abnormal physical quantity data can be determined according to the material of the chip and the circuit layout of the chip, and finally the defect position of the chip can be determined according to the time difference, the position of each sensor, and the transmission speed.

[0098] Specifically, take a rectangular chip as an example. The chip's dimensions are length L and width W. There are four sensors, denoted as sensor 1 to sensor 4, placed at the four corners of the chip. The position of each sensor can be determined based on the length and width of the chip. The corresponding coordinates of each sensor's position are sensor 1 (0, 0), sensor 2 (L, 0), sensor 3 (L, W), and sensor 4 (0, W).

[0099] In a specific implementation, different chip materials and layouts have different effects on data transmission speed. Therefore, experiments can be conducted on different materials and layouts to obtain corresponding data transmission speeds and establish a material-layout-speed correspondence. This correspondence can then be used to determine the transmission speed of the abnormal physical quantity data based on the chip material and circuit layout. The transmission speed of the abnormal physical quantity data is denoted as v.

[0100] In a specific implementation process, the defect position of the chip can be further determined according to the time difference, the position of each sensor and the transmission speed.

[0101] Specifically, the distance difference between the abnormal physical quantity data and each sensor can be calculated based on the obtained time difference. For details, please refer to the following calculation formula (3):

[0102] (3)

[0103] in, represents the distance difference between the abnormal physical quantity data reaching sensor 2 and the abnormal physical quantity data reaching sensor 1, Indicates the time difference between the abnormal physical quantity data arriving at sensor 2 and the abnormal physical quantity data arriving at sensor 1; represents the distance difference between the abnormal physical quantity data reaching sensor 3 and the abnormal physical quantity data reaching sensor 1, Indicates the time difference between the abnormal physical quantity data arriving at sensor 2 and the abnormal physical quantity data arriving at sensor 1; represents the distance difference between the abnormal physical quantity data reaching sensor 4 and the abnormal physical quantity data reaching sensor 1, It represents the time difference between the abnormal physical quantity data reaching sensor 4 and the abnormal physical quantity data reaching sensor 1.

[0104] Assume that the coordinates of the chip defect position are (x, y) and the distance between the chip defect position and sensor 1 is , the measurement values ​​of sensors 2 to 4 can be used to construct the following calculation formulas (4) to (6):

[0105] Among them, the calculation formula (4) corresponding to sensor 2 is as follows:

[0106] (4)

[0107] Among them, the calculation formula (5) corresponding to sensor 3 is as follows:

[0108] (5)

[0109] Among them, the calculation formula (6) corresponding to sensor 4 is as follows:

[0110] (6)

[0111] Combining equations (4) to (6), we can obtain Calculation formula (7):

[0112] (7)

[0113] Will Substituting into equations (4) and (6), we can obtain the coordinates of the chip defect position equation (8) as follows:

[0114] (8)

[0115] In a specific implementation, to facilitate rapid identification of the chip defect location, a light source generator may be controlled to adjust the light irradiation angle so as to illuminate the chip defect location; and / or descriptive information of the chip defect location may be generated and output. For example, information related to electrical components in the area where the chip defect location is located may be determined based on the chip layout. In this way, the chip defect location can be quickly located based on the information related to the electrical components.

[0116] The method for detecting chip defects based on chaotic features in this embodiment leverages the unique dynamic characteristics of the chaos algorithm, combined with the structural characteristics of the chip, to achieve more accurate defect location. Chaotic analysis identifies the region of chaotic feature changes caused by the defect, providing a more accurate basis for defect location. Furthermore, the chaos algorithm can be better coordinated with other detection technologies, organically combining chaotic features with microscopic detection techniques and rule-based detection technologies to form a more comprehensive and efficient detection system, improving the comprehensive detection capabilities for minor defects in complex chips.

[0117] Based on the same general inventive concept, the present invention also protects an electronic device. The electronic device provided by the present invention is described below. The electronic device described below and the method for detecting chip defects based on chaotic characteristics described above can refer to each other.

[0118] Figure 4is a structural schematic diagram of an electronic device provided by an embodiment of the present application. The electronic device can include a processor 410, a communications interface 420, a memory 430, and a communications bus 440, wherein the processor 410, the communications interface 420, and the memory 430 complete communications with each other through the communications bus 440. The processor 410 can invoke a logical instruction in the memory 430 to execute a method of detecting chip defects based on chaotic characteristics.

[0119] In addition, the logical instruction in the memory 430 described above can be implemented in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0120] In yet another aspect, the present application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the method of detecting chip defects based on chaotic characteristics provided by the above-mentioned methods.

[0121] It should be noted that the related data involved in each embodiment of the present application are strictly in accordance with the requirements of laws and regulations, and follow the principles of legality, legitimacy, and necessity, and are based on the legitimate purpose of the business scene, and process the personal information of the user actively provided or generated in the process of using the product / service, and the personal information authorized by the user.

[0122] The related data processed by the present application will be different due to the specific product / service scene, and the specific scene of the user using the product / service should be used as the standard, which may involve the user's account information, device information, driving information, vehicle information, or other related information. The present application will treat the personal information of the user with a high degree of diligence and obligation.

[0123] The present application attaches great importance to the security of relevant data, and has taken reasonable and feasible security protection measures in line with industry standards to protect relevant data from unauthorized access, public disclosure, use, modification, damage or loss.

[0124] The device embodiments described above are only schematic, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e. may be located in one place, or may be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the present embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0125] Through the description of the above embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software and the necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of software products, and the computer software products can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0126] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for detecting chip defects based on chaotic characteristics, characterized in that: include: Acquiring physical quantity data of a chip in a working state and attribute data of the chip; wherein the attribute data of the chip includes the size of the chip, the material of the chip, and the circuit layout of the chip; and the physical quantity data includes current, voltage, and temperature; determining an embedding dimension and an embedding delay of the physical quantity data; reconstructing a reconstructed phase space of the physical quantity data according to the embedding dimension and the embedding delay; determining a chaotic eigenvalue of the physical quantity data according to the reconstructed phase space; Inputting the physical quantity data and the chaotic characteristic value into a pre-built HKLS-SVM model for detection to obtain a detection result; If the detection result indicates that the chip is defective, obtaining the time difference between the detection of abnormal physical quantity data by multiple sensors on the chip; Determining the position of each sensor according to the size of the chip; determining a transmission speed of the abnormal physical quantity data according to a material of the chip and a circuit layout of the chip; A defective position of the chip is determined according to the time difference, the position of each sensor, and the transmission speed.

2. The method for detecting chip defects based on chaotic characteristics according to claim 1, characterized in that: The calculation process of the embedding delay of the physical quantity data includes: constructing an autocorrelation function based on the time series length of the physical quantity data, the time series initial value of the physical quantity data, the time series mean value of the physical quantity data, and the embedding delay; The embedding delay is assigned a value according to a preset step size until the value of the autocorrelation function drops to a first preset threshold, and the current assigned value is used as the embedding delay.

3. The method for detecting chip defects based on chaotic characteristics according to claim 1, characterized in that: The calculation process of the embedding dimension of the physical quantity data includes: For each trajectory point in the original phase space of the physical quantity data, finding at least one adjacent trajectory point in the m-dimensional space; Adding the trajectory point and the corresponding at least one neighboring trajectory point to m+1 dimensions, and calculating a distance change rate between the trajectory point and each neighboring trajectory point; wherein a neighboring point with a distance change rate greater than a second preset threshold is a false neighboring point; Assign a value to m so that the proportion of the false neighboring points approaches 0, and use the current value of m as the embedding dimension.

4. The method for detecting chip defects based on chaotic characteristics according to claim 1, characterized in that: Also includes: controlling a light source generator to illuminate a defective position of the chip; and / or Generate description information of the defect location of the chip and output the description information.

5. The method for detecting chip defects based on chaotic features according to any one of claims 1 to 4, characterized in that: Obtain physical quantity data of the chip in working state, including: Determining a data acquisition frequency based on the characteristic information of the chip and the detection accuracy requirement information; According to the data acquisition frequency, physical quantity data of the chip in the working state is obtained.

6. The method for detecting chip defects based on chaotic characteristics according to claim 5, characterized in that: Determine the data acquisition frequency based on the chip's characteristic information and detection accuracy requirements, including: Determining an initial signal bandwidth for data to be acquired based on characteristic information of the chip; Determining the accuracy bandwidth margin corresponding to the detection accuracy requirement information according to the preset correlation relationship between the accuracy requirement and the bandwidth margin; Determining a final signal bandwidth of the data to be acquired according to the initial signal bandwidth, the precision bandwidth margin, and a preset anti-interference bandwidth margin; The data acquisition frequency is determined according to the final signal bandwidth.

7. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for detecting chip defects based on chaotic features as claimed in any one of claims 1 to 6 is implemented.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for detecting chip defects based on chaotic features as described in any one of claims 1 to 6 is implemented.

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