Display device

Abstract

A display device includes: a pixel unit including a first pixel row connected to a first emission line and a second pixel row connected to a second emission line; an emission driver including a first emission stage connected to the first emission line and a second emission stage connected to the second emission line; and a scan driver including first and second scan stages connected to the first and second pixel rows, respectively, in which one first emission stage is connected to the first emission start line and one second emission stage is connected to the second emission start line, except for one first emission stage connected to the first emission start line, and one second emission stage connected to the second emission start line. Each first emission stage is connected to a first emission line of a previous first emission stage, and each second emission stage is connected to a second emission line of a previous second emission stage except for one second emission stage connected to a second emission start line.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2024-0004254, filed on January 10, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] With the advancement of information technology, the importance of display devices that serve as an interface between users and information has become more prominent. Accordingly, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting displays (OLEDs) is increasing.

[0004] When a display device displays a moving image, it is desirable to display it at a high frequency to ensure smooth movement. However, since there is no movement when a still image is displayed, the still image can be displayed at a lower frequency. In addition, displaying at a lower frequency is beneficial for reducing power consumption.

[0005] However, a problem occurs when the display frequency of the device is switched from a high frequency to a low frequency because flicker may become visible due to a change in brightness. Summary of the Invention

[0006] Embodiments of the present disclosure provide a display device that prevents visible flicker by separating emission stages for odd-numbered pixel rows and even-numbered pixel rows.

[0007] According to an embodiment of the present disclosure, a display device includes: a pixel unit including a first pixel row connected to a first emission line and a second pixel row connected to a second emission line, wherein the second pixel row alternates with the first pixel row; an emission driver including a first emission stage connected to the first emission line and a second emission stage connected to the second emission line; and a scan driver including a first scan stage connected to the first pixel row and a second scan stage connected to the second pixel row, wherein one first emission stage of the first emission stages is connected to a first emission start line, one second emission stage of the second emission stages is connected to a second emission start line, and each of the first emission stages except the one first emission stage connected to the first emission start line is connected to the first emission line of the previous first emission stage, and each of the second emission stages except the one second emission stage connected to the second emission start line is connected to the second emission line of the previous second emission stage.

[0008] After the emission driver applies an emission control signal having a conductive level to one of the first emission line and the second emission line, the emission driver applies the emission control signal having the conductive level to the other of the first emission line and the second emission line, except for the emission line to which the emission control signal having the conductive level is applied.

[0009] The first emission stage is connected to the first emission clock line, the second emission stage is connected to the second emission clock line, and the pulses of the first emission clock signal applied to the first emission clock line and the pulses of the second emission clock signal applied to the second emission clock line do not overlap with each other.

[0010] One first scan stage in the first scan stage is connected to the first scan start line, one second scan stage in the second scan stage is connected to the second scan start line, and each of the first scan stages, except for the one first scan stage connected to the first scan start line, is connected to the first scan line of the previous first scan stage, and each of the second scan stages, except for the one second scan stage connected to the second scan start line, is connected to the second scan line of the previous second scan stage.

[0011] The first scan stage is connected to the first scan clock line, the second scan stage is connected to the second scan clock line, and the pulses of the first scan clock signal applied to the first scan clock line and the pulses of the second scan clock signal applied to the second scan clock line do not overlap with each other.

[0012] The first emission clock signal and the first scan clock signal have the same waveform.

[0013] The second emission clock signal and the second scan clock signal have the same waveform.

[0014] According to an embodiment of the present disclosure, a display device includes: a pixel unit including a first pixel row and a second pixel row alternating with the first pixel row; an emission driver including a first emission stage connected to a first emission line and a second emission stage connected to a second emission line, the first emission line being connected to pixels located in a first pixel column among the first pixel rows and pixels located in a second pixel column among the second pixel rows, the second emission line being connected to pixels located in a first pixel column among the second pixel rows and pixels located in a second pixel column among the first pixel rows; and a scan driver connected to the pixel unit, wherein one first emission stage in the first emission stage is connected to a first emission start line, one second emission stage in the second emission stage is connected to a second emission start line, and each of the first emission stages, except for the one first emission stage connected to the first emission start line, is connected to the first emission line of the previous first emission stage, and each of the second emission stages, except for the one second emission stage connected to the second emission start line, is connected to the second emission line of the previous second emission stage.

[0015] After the emission driver applies an emission control signal having a conductive level to one of the first emission line and the second emission line, the emission driver applies the emission control signal having the conductive level to the other of the first emission line and the second emission line, except for the emission line to which the emission control signal having the conductive level is applied.

[0016] The first emission stage is connected to the first emission clock line, the second emission stage is connected to the second emission clock line, and the pulses of the first emission clock signal applied to the first emission clock line and the pulses of the second emission clock signal applied to the second emission clock line do not overlap with each other.

[0017] The scan driver includes a first scan stage connected to the first scan line and a second scan stage connected to the second scan line. The first scan line is connected to the pixels located in the first pixel column among the first pixel rows and the pixels located in the second pixel column among the second pixel rows. The second scan line is connected to the pixels located in the first pixel column among the second pixel rows and the pixels located in the second pixel column among the first pixel rows.

[0018] One of the first scan stages in the first scan stage is connected to the first scan start line, one of the second scan stages in the second scan stage is connected to the second scan start line. Except for the one first scan stage connected to the first scan start line, each of the first scan stages is connected to the first scan line of the previous first scan stage. Except for the one second scan stage connected to the second scan start line, each of the second scan stages is connected to the second scan line of the previous second scan stage.

[0019] The first scan stage is connected to the first scan clock line, the second scan stage is connected to the second scan clock line, and the pulses of the first scan clock signal applied to the first scan clock line and the pulses of the second scan clock signal applied to the second scan clock line do not overlap with each other.

[0020] The first emission clock signal and the first scan clock signal have the same waveform.

[0021] The second emission clock signal and the second scan clock signal have the same waveform.

[0022] According to the present disclosure, by separating the emission stages for odd-numbered pixel rows and even-numbered pixel rows, the visibility of flicker can be prevented, and the power consumption required for high-frequency driving can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0024] Figure 1 FIG. is a diagram showing a display device according to an embodiment of the present disclosure;

[0025] Figure 2 FIG. is a diagram showing a pixel according to an embodiment of the present disclosure;

[0026] Figure 3 FIG. is a diagram showing a method of driving a pixel according to an embodiment of the present disclosure;

[0027] Figure 4 and Figure 5 and Figure 6 and Figure 7 FIG. is a diagram showing a transmission driver, a pixel unit, and a scan driver according to a first embodiment of the present disclosure; and

[0028] Figure 8 and Figure 9 FIG. is a diagram showing a transmission driver, a pixel unit, and a scan driver according to a second embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in various forms and is not limited to the embodiments described below.

[0030] In the drawings, parts irrelevant to the present disclosure may be omitted for clarity, and the same reference numerals may be given to similar parts throughout the specification.

[0031] In addition, terms such as "unit" and "module" used below or functional blocks shown in the drawings may be implemented as a software configuration, a hardware configuration, or a combination of both.

[0032] Figure 1 FIG. is a diagram showing a display device according to an embodiment of the present disclosure.

[0033] Referring to Figure 1 , a display device 10 according to an embodiment of the present disclosure may include a timing controller 11, a data driver 12, a scan driver 13, a transmission driver 14, and a pixel unit 15.

[0034] The timing controller 11 may receive grayscale and control signals for each image frame from a processor. The timing controller 11 may provide control signals suitable for each specification to the data driver 12, the scan driver 13, the transmission driver 14, and other components to display an image corresponding to the image frame.

[0035] The timing controller 11 may render grayscale corresponding to the specification of the pixel unit 15. For example, the processor may provide red grayscale, green grayscale, and blue grayscale for each unit point.

[0036] The data driver 12 can generate data voltages to be supplied to the data lines DL1, DL2, DL3, ……, DLj, ……, and DLn using the provided grayscale and control signals. The data voltages supplied to the data lines DL1, DL2, DL3, ……, DLj, ……, and DLn can be supplied to the pixels PXij selected by the scan signal. j is an integer greater than 0, and n is an integer greater than j.

[0037] The scan driver 13 can receive a scan clock signal, a scan start signal, etc. from the timing controller 11, and generate scan signals to be supplied to the scan lines SL1, SL2, SL3, ……, SLi, SLp, ……, and SLm. i is an integer greater than 0, p is an integer greater than i, and m is an integer greater than p.

[0038] The scan driver 13 can supply the scan signals to the scan lines SL1 to SLm. For example, the scan driver 13 can sequentially supply scan signals having an on-pulse level. The scan driver 13 can include scan stages configured as shift registers. For example, the scan driver 13 can generate scan signals by sequentially transmitting a scan start signal in the form of an on-pulse to the next scan stage under the control of the scan clock signal.

[0039] The emission driver 14 can receive an emission clock signal, an emission control signal, etc. from the timing controller 11, and generate emission signals. The emission driver 14 can supply the emission signals to the emission lines EL1, EL2, EL3, ……, ELq, ……, and ELo. For example, the emission driver 14 can sequentially supply emission signals having an off-pulse level. The emission driver 14 can include emission stages configured as shift registers. For example, the emission driver 14 can generate emission signals by sequentially transmitting the emission control signal to the next emission stage under the control of the emission clock signal. q is an integer greater than 0, and o is an integer greater than q.

[0040] The pixel unit 15 can include a plurality of pixels. Each of the pixels can be connected to at least two of the scan lines SL1 to SLm and at least one of the emission lines EL1 to ELo. Additionally, each of the pixels can be connected to at least one of the data lines DL1 to DLn. For example, the pixel PXij can be connected to the i-th scan line SLi, the p-th scan line SLp, the q-th emission line ELq, and the j-th data line DLj. A pixel row can be a group of pixels connected to the same scan line and the same emission line. For example, the i-th pixel row can be the pixels connected to the i-th scan line SLi, the p-th scan line SLp, and the q-th emission line ELq. The i-th pixel row includes the pixel PXij. The pixels constituting the i-th pixel row can be connected to different data lines.

[0041] Figure 2 FIG. is a diagram showing a pixel according to an embodiment of the present disclosure.

[0042] Referring Figure 2 , the pixel PXij includes transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst, and a light emitting diode LD.

[0043] Hereinafter, a circuit composed of P-type transistors will be described as an example. However, those skilled in the art can design a circuit using N-type transistors by adjusting the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art can design a circuit using a combination of P-type transistors and N-type transistors. A P-type transistor refers to a transistor in which the current increases as the voltage difference between the gate electrode and the source electrode increases in the negative direction. An N-type transistor refers to a transistor in which the current increases as the voltage difference between the gate electrode and the source electrode increases in the positive direction. The transistor can be constructed in various forms such as a thin film transistor (TFT), a field effect transistor (FET), and a bipolar junction transistor (BJT).

[0044] The transistor T1 may have a gate electrode connected to a node N1 (hereinafter, also referred to as the first node), a first electrode connected to a node N2, and a second electrode connected to a node N3. The transistor T1 may be a driving transistor.

[0045] The transistor T2 may have a gate electrode connected to the p-th scan line SLp, a first electrode connected to the j-th data line DLj, and a second electrode connected to the node N2. The transistor T2 may be a scan transistor.

[0046] The transistor T3 may have a gate electrode connected to the p-th scan line SLp, a first electrode connected to the node N1, and a second electrode connected to the node N3. The transistor T3 may be a diode-connected transistor. In an embodiment, the transistor T3 may be constructed such that two sub-transistors are connected in series and controlled by a single signal. For example, the transistor T3 may be constructed such that a first sub-transistor T3-1 and a second sub-transistor T3-2 are connected in series and controlled by a signal applied from the p-th scan line SLp.

[0047] The transistor T4 may have a gate electrode connected to the i-th scan line SLi, a first electrode connected to the node N1, and a second electrode connected to the initialization line INTL. In another embodiment, the gate electrode of the transistor T4 may be connected to another scan line. The fourth transistor T4 may be a gate initialization transistor.

[0048] In an embodiment, the transistor T4 may be configured such that two sub-transistors are connected in series and controlled by a single signal. For example, the transistor T4 may be configured such that the first sub-transistor T4-1 and the second sub-transistor T4-2 are connected in series and controlled by a signal applied from the i-th scan line SLi.

[0049] The transistor T5 may have a gate electrode connected to the q-th emission line ELq, a first electrode connected to the first display power line ELVDDL, and a second electrode connected to the node N2. The transistor T5 may be a first emission transistor. In another embodiment, the gate electrode of the transistor T5 may be connected to another emission line.

[0050] The transistor T6 may have a gate electrode connected to the q-th emission line ELq, a first electrode connected to the node N3, and a second electrode connected to the anode of the light-emitting diode LD. The transistor T6 may be a second emission transistor. In another embodiment, the gate electrode of the transistor T6 may be connected to another emission line.

[0051] The transistor T7 may have a gate electrode connected to the p-th scan line SLp, a first electrode connected to the initialization line INTL, and a second electrode connected to the anode of the light-emitting diode LD. The transistor T7 may be an anode initialization transistor. In another embodiment, the gate electrode of the transistor T7 may be connected to another scan line.

[0052] The first electrode of the storage capacitor Cst may be connected to the first display power line ELVDDL, and the second electrode may be connected to the node N1.

[0053] The anode of the light-emitting diode LD may be connected to the second electrode of the transistor T6, and the cathode of the light-emitting diode LD may be connected to the second display power line ELVSSL. The light-emitting diode LD may be composed of an organic light-emitting diode, an inorganic light-emitting diode, or a quantum dot / well light-emitting diode, etc.

[0054] The first display power line ELVDDL may be supplied with a first power voltage (hereinafter, also referred to as the first display power voltage), the second display power line ELVSSL may be supplied with a second power voltage (hereinafter, also referred to as the second display power voltage), and the initialization line INTL may be supplied with an initialization voltage.

[0055] For example, during the display period of the display device 10, the first power voltage may be greater than the second power voltage. For example, the initialization voltage may be equal to or greater than the second power voltage. For example, the initialization voltage may correspond to the minimum data voltage that can be provided. For example, the amplitude of the initialization voltage may be less than the amplitude of the data voltage that can be provided.

[0056] Figure 3FIG. is a diagram illustrating a method of driving a pixel according to an embodiment of the present disclosure.

[0057] Referring Figure 3 , based on the pixel PXij described above with reference to Figure 2 the driving method is described. In addition, each pixel in the i-th pixel row is driven using the same method as shown in Figure 3 .

[0058] First, the conduction level (logic low level) of the i-th scan signal can be applied to the i-th scan line SLi. At this time, since the cut-off level (logic high level) of the scan signal is applied to the p-th scan line SLp, the transistor T2 is cut off, and the data voltage for another pixel is prevented from entering the pixel PXij.

[0059] At this time, since the transistor T4 is turned on, the first node N1 is connected to the initialization line INTL, and the voltage of the first node N1 is initialized. Since the cut-off level of the emission signal is applied to the q-th emission line ELq, the transistors T5 and T6 are cut off, and unnecessary light emission of the light-emitting diode LD due to the initialization voltage application process is prevented.

[0060] Next, the data voltage for the pixel PXij is applied to the j-th data line DLj, and the conduction level of the scan signal is applied to the p-th scan line SLp. Accordingly, the transistors T2, T1, and T3 are turned on, and the j-th data line DLj and the first node N1 are electrically connected to each other. Therefore, the compensation voltage obtained by subtracting the threshold voltage of the transistor T1 from the data voltage is applied to the second electrode (e.g., the first node N1) of the storage capacitor Cst. The storage capacitor Cst holds a voltage corresponding to the difference between the first display power voltage and the compensation voltage. This period can be referred to as a threshold voltage compensation period.

[0061] At this time, since the transistor T7 is turned on, the anode of the light-emitting diode LD and the initialization line INTL are connected to each other. The light-emitting diode LD is initialized to have a charge amount corresponding to the voltage difference between the initialization voltage and the second display power voltage.

[0062] Thereafter, when the conduction level of the emission signal is applied to the q-th emission line ELq, the transistors T5 and T6 can be turned on. Therefore, a drive current path is formed through the first display power line ELVDDL, the transistor T5, the transistor T1, the transistor T6, the light-emitting diode LD, and the second display power line ELVSSL.

[0063] Adjust the amount of drive current flowing between the first and second electrodes of transistor T1 according to the voltage held in storage capacitor Cst. Light-emitting diode LD emits light having a brightness corresponding to the amount of drive current. Light-emitting diode LD continues to emit light until the cut-off level of the emission signal is applied to the q-th emission line ELq.

[0064] Figures 4 to 7 FIG. is a diagram showing an emission driver, a pixel unit, and a scan driver according to a first embodiment of the present disclosure.

[0065] Referring to Figure 4 , the connection relationship between the emission driver 14a and the pixel unit 15a according to the first embodiment is shown. For ease of description, Figure 4 Four emission stages EST11 to EST14 are shown.

[0066] The emission driver 14a may include first emission stages EST11, EST13,... connected to the first emission lines EL1, EL3,... and second emission stages EST12, EST14,... connected to the second emission lines EL2, EL4,....

[0067] The pixel unit 15a may include a first pixel row connected to the first emission lines EL1, EL3,... and a second pixel row alternating with the first pixel row and connected to the second emission lines EL2, EL4,....

[0068] The first emission lines EL1, EL3,... may be connected to the first pixel row. For example, the first pixel row may be the odd-numbered pixel rows. For example, the first emission lines EL1, EL3,... may be odd-numbered emission lines. For example, the first emission stages EST11, EST13,... may be odd-numbered emission stages.

[0069] The second emission lines EL2, EL4,... may be connected to the second pixel row. For example, the second pixel row may be the even-numbered pixel rows. For example, the second emission lines EL2, EL4,... may be even-numbered emission lines. For example, the second emission stages EST12, EST14,... may be even-numbered emission stages.

[0070] Each of the emission stages EST11 to EST14 may include a first input terminal 101, a second input terminal 102, and an output terminal 103.

[0071] One of the first emission stages EST11, EST13, …, the first input terminal 101 of the first emission stage EST11 can be connected to the first emission control line ELML1 (or also referred to as the first emission start line). One of the second emission stages EST12, EST14, …, the first input terminal 101 of the second emission stage EST12 can be connected to the second emission control line ELML2 (or also referred to as the second emission start line). The output terminal 103 of the first emission stage EST11 can be connected to the first emission line EL1, and the output terminal 103 of the second emission stage EST12 can be connected to the second emission line EL2.

[0072] Except for the first emission stage EST11, each of the first emission stages EST13, … can be connected to the first emission line of the previous first emission stage. Except for the second emission stage EST12, each of the second emission stages EST14, … can be connected to the second emission line of the previous second emission stage.

[0073] For example, the first input terminal 101 of the first emission stage EST13 can be connected to the first emission line EL1 of the first emission stage EST11. For example, the first input terminal 101 of the first emission stage EST13 can be connected to the output terminal 103 of the first emission stage EST11. The first input terminal 101 of the second emission stage EST14 can be connected to the second emission line EL2 of the second emission stage EST12. For example, the first input terminal 101 of the second emission stage EST14 can be connected to the output terminal 103 of the second emission stage EST12.

[0074] The second input terminals 102 of the first emission stages EST11, EST13, … can be connected to the first emission clock line ECKL1. The second input terminals 102 of the second emission stages EST12, EST14, … can be connected to the second emission clock line ECKL2. The pulses of the first emission clock signal ECK1 applied to the first emission clock line ECKL1 and the pulses of the second emission clock signal ECK2 applied to the second emission clock line ECKL2 do not overlap with each other in time (refer to Figure 7 ).

[0075] The emission stages EST11 to EST14 can be connected to the first emission power line VDDL and the second emission power line VSSL. The voltage level of the emission signal can be set based on the voltage of the first emission power line VDDL or the second emission power line VSSL.

[0076] In an embodiment, after the transmission driver 14a applies the conduction level of the transmission control signal to one of the first transmission lines EL1, EL3, …… and the second transmission lines EL2, EL4, ……, the transmission driver 14a can then apply the conduction level of the transmission control signal to the transmission lines other than the transmission line to which the conduction level of the transmission control signal is currently applied.

[0077] For example, after the transmission driver 14a applies the conduction level of the transmission control signal to the first transmission lines EL1, EL3, ……, the transmission driver 14a can apply the conduction level of the transmission control signal to the second transmission lines EL2, EL4, ……. Additionally, after the transmission driver 14a applies the conduction level of the transmission control signal to the second transmission lines EL2, EL4, ……, the transmission driver 14a can apply the conduction level of the transmission control signal to the first transmission lines EL1, EL3, …….

[0078] Refer to Figure 4 and Figure 5 , a method for driving the first transmission stage EST11 and the second transmission stage EST12 is described.

[0079] Figure 5 The first transmission control signal ELM1 applied to the first transmission control line ELML1 and the second transmission control signal ELM2 applied to the second transmission control line ELML2 during one frame period FR are shown.

[0080] During one frame period FR, the first transmission control signal ELM1 defines a non - transmission period corresponding to the cut - off level (high level) and a transmission period corresponding to the conduction level (low level). For example, consecutive non - transmission periods and transmission periods can form a transmission cycle. The first transmission control signal ELM1 can have two transmission cycles during one frame period FR. Similarly, the second transmission control signal ELM2 can also have two transmission cycles during one frame period FR.

[0081] The pulses of the cut - off level (high level) of the first transmission control signal ELM1 supplied to the first input terminal 101 of the first transmission stage EST11 may not overlap with the pulses of the cut - off level (high level) of the second transmission control signal ELM2 supplied to the first input terminal 101 of the second transmission stage EST12.

[0082] Referring to the first period P1, the first emission control signal ELM1 may have a cut-off level (high level), and the second emission control signal ELM2 may have a conduction level (low level). Accordingly, the first pixel rows connected to the first emission stages EST11, EST13, … may not emit light, and the second pixel rows connected to the second emission stages EST12, EST14, … may emit light. When the brightness is set to 100% for the case where all the pixels included in the display device emit light and the brightness is set to 0% for the case where all the pixels included in the display device do not emit light, since only the second pixel rows emit light during the first period P1, the display device may have a brightness of 50% during this period.

[0083] Referring to the second period P2, the first emission control signal ELM1 and the second emission control signal ELM2 may have a conduction level. Accordingly, the first pixel rows connected to the first emission stages EST11, EST13, … may emit light, and the second pixel rows connected to the second emission stages EST12, EST14, … may emit light. Since the first pixel rows and the second pixel rows emit light during the second period P2, the display device may have a brightness of 100%.

[0084] Referring to the third period P3, the first emission control signal ELM1 may have a conduction level, and the second emission control signal ELM2 may have a cut-off level. Accordingly, the first pixel rows connected to the first emission stages EST11, EST13, … may emit light, and the second pixel rows connected to the second emission stages EST12, EST14, … may not emit light. During the third period P3, since only the first pixel rows emit light, the display device may have a brightness of 50%.

[0085] Based on the first emission control signal ELM1 and the second emission control signal ELM2, the first pixel rows and the second pixel rows can be independently controlled. Accordingly, the brightness of the display device does not change abruptly from 100% to 0%. Instead, the brightness changes gradually (such as from 100% to 50% and from 50% to 100%), thereby preventing the visibility of flicker due to differences in the brightness waveform.

[0086] In addition, a first pixel row controlled by a first emission control signal ELM1 and a second pixel row controlled by a second emission control signal ELM2 are arranged adjacent to each other. When, at alternating times, the first pixel row reaches its maximum brightness and the second pixel row reaches its maximum brightness, what the user can recognize is that during one frame period FR, an emission control signal having four emission cycles is applied to the pixel row. Accordingly, the emission control signal having four emission cycles can be achieved by a combination of the first emission control signal ELM1 and the second emission control signal ELM2 each having two emission cycles. This reduces the power consumed for high-frequency driving.

[0087] However, the present disclosure is not limited to Figure 5 the waveforms shown therein, and the cut-off level of the pulse of the first emission control signal ELM1 may overlap with the cut-off level of the pulse of the second emission control signal ELM2. In addition, the width of the cut-off level of the pulse of the first emission control signal ELM1 may be different from the width of the cut-off level of the pulse of the second emission control signal ELM2. In other words, the width of the cut-off level of the pulse of the first emission control signal ELM1 and the width of the cut-off level of the pulse of the second emission control signal ELM2 can be set to control the period during which the brightness of the display device changes from 50% to 0% or from 0% to 50%.

[0088] Referring to Figure 6 , a connection relationship between the scan driver 13a and the pixel unit 15a according to the first embodiment is shown. For ease of description, Figure 6 four scan levels ST1 to ST4 are shown.

[0089] The scan driver 13a may include a first scan level ST1, ST3,... connected to the first scan lines SL1, SL3,... and a second scan level ST2, ST4,... connected to the second scan lines SL2, SL4,....

[0090] The pixel unit 15a may include a first pixel row connected to the first scan lines SL1, SL3,... and a second pixel row alternating with the first pixel row and connected to the second scan lines SL2, SL4,.... For example, one of the first pixel rows (including, for example, pixels PX11 to PX13) may be connected to both the first scan line SL1 and SL3. As another example, one of the first pixel rows (including, for example, pixels PX31 to PX33) may be connected to both the first scan line SL3 and SL5. For example, one of the second pixel rows (including, for example, pixels PX21 to PX23) may be connected to both the second scan line SL2 and SL4. As another example, one of the second pixel rows (including, for example, pixels PX41 to PX43) may be connected to both the second scan line SL4 and SL6.

[0091] The first scan lines SL1, SL3, … can be connected to the first pixel row. For example, the first pixel row can be the pixel row with an odd number. For example, the first scan lines SL1, SL3, … can be the scan lines with an odd number. For example, the first scan stages ST1, ST3, … can be the scan stages with an odd number.

[0092] The second scan lines SL2, SL4, … can be connected to the second pixel row. For example, the second pixel row can be the pixel row with an even number. For example, the second scan lines SL2, SL4, … can be the scan lines with an even number. For example, the second scan stages ST2, ST4, … can be the scan stages with an even number.

[0093] Each of the scan stages ST1 to ST4 can include a first input terminal 1001, a second input terminal 1002, and an output terminal 1003.

[0094] The first input terminal 1001 of a first scan stage ST1 among the first scan stages ST1, ST3, … can be connected to the first scan start line FLML1. The first input terminal 1001 of a second scan stage ST2 among the second scan stages ST2, ST4, … can be connected to the second scan start line FLML2. The output terminal 1003 of the first scan stage ST1 can be connected to the first scan line SL1, and the output terminal 1003 of the second scan stage ST2 can be connected to the second scan line SL2.

[0095] Except for the first scan stage ST1, each of the first scan stages ST3, … can be connected to the first scan line of the previous first scan stage. Except for the second scan stage ST2, each of the second scan stages ST4, … can be connected to the second scan line of the previous second scan stage. For example, the first input terminal 1001 of the first scan stage ST3 can be connected to the first scan line SL1 of the first scan stage ST1. In other words, the first input terminal 1001 of the first scan stage ST3 can be connected to the output terminal 1003 of the first scan stage ST1. Additionally, the first input terminal 1001 of the second scan stage ST4 can be connected to the second scan line SL2 of the second scan stage ST2. In other words, the first input terminal 1001 of the second scan stage ST4 can be connected to the output terminal 1003 of the second scan stage ST2.

[0096] The second input terminals 1002 of the first scan stages ST1, ST3, … can be connected to the first scan clock line CKL1. The second input terminals 1002 of the second scan stages ST2, ST4, … can be connected to the second scan clock line CKL2. Pulses of the first scan clock signal CK1 applied to the first scan clock line CKL1 and pulses of the second scan clock signal CK2 applied to the second scan clock line CKL2 do not overlap with each other in time (refer to Figure 7 ).

[0097] Each of the scan stages ST1 to ST4 can be connected to the first scan power line VHPL and the second scan power line VLPL. Here, the voltage of the first scan power line VHPL can be set to a cut-off level (gate cut-off voltage, logic high level). In addition, the voltage of the second scan power line VLPL can be set to a conduction level (gate conduction voltage, logic low level).

[0098] The pixel unit 15a can be connected to the emission driver 14a. For example, the first pixel row (including, for example, pixels PX11, PX12, PX13, …) can be connected to the first emission line EL1, and the second pixel row (including, for example, pixels PX21, PX22, PX23, …) can be connected to the second emission line EL2. For example, the first pixel row (including, for example, pixels PX31, PX32, PX33, …) can be connected to the first emission line EL3, and the second pixel row (including, for example, pixels PX41, PX42, PX43, …) can be connected to the second emission line EL4. Since the emission driver 14a is similar to the Figure 4 emission driver 14a, its detailed description is omitted.

[0099] Refer to Figure 4 , Figure 6 and Figure 7 for a method of driving the scan driver 13a, the emission driver 14a, and the pixel unit 15a.

[0100] Figure 7 Shows signals applied to the scan driver 13a and the emission driver 14a during one frame period.

[0101] The first emission control signal ELM1 can be supplied to the first input terminal 101 of the first emission stage EST11. The first emission clock signal ECK1 can be supplied to the second input terminals 102 of the first emission stages EST11, EST13, …

[0102] The second emission control signal ELM2 can be supplied to the first input terminal 101 of the second emission stage EST12. The second emission clock signal ECK2 can be supplied to the second input terminal 102 of the second emission stages EST12, EST14,....

[0103] The pulses of the first emission clock signal ECK1 and the pulses of the second emission clock signal ECK2 do not overlap with each other in time. In an embodiment, the emission operations of the pixels connected to the first emission lines EL1, EL3,... and the emission operations of the pixels connected to the second emission lines EL2, EL4,... can be alternately performed.

[0104] The first scan start signal FLM1 can be supplied to the first input terminal 1001 of the first scan stage ST1. The first scan clock signal CK1 can be supplied to the second input terminal 1002 of the first scan stages ST1, ST3,....

[0105] The second scan start signal FLM2 can be supplied to the first input terminal 1001 of the second scan stage ST2. The second scan clock signal CK2 can be supplied to the second input terminal 1002 of the second scan stages ST2, ST4,....

[0106] The pulses of the first scan clock signal CK1 and the pulses of the second scan clock signal CK2 do not overlap with each other in time. In an embodiment, the scan operations of the pixels connected to the first scan lines SL1, SL3,... and the scan operations of the pixels connected to the second scan lines SL2, SL4,... can be alternately performed.

[0107] The first scan clock signal CK1 and the first emission clock signal ECK1 can have the same pulse waveform. Accordingly, the scan operation and the emission operation of the first pixel row can be synchronized.

[0108] The second scan clock signal CK2 and the second emission clock signal ECK2 can have the same pulse waveform. Accordingly, the scan operation and the emission operation of the second pixel row can be synchronized.

[0109] In an embodiment, the scan operation and the emission operation can be synchronously performed on the odd-numbered pixel rows, and the scan operation and the emission operation can be synchronously performed on the even-numbered pixel rows.

[0110] In another example, the pixel unit 15a may be divided into two or more regions, and the scanning operation and the emission operation may be sequentially performed on each region. For example, when the upper half of the pixel unit 15a is designated as the first region and the lower half of the pixel unit 15a is designated as the second region, the scanning operation and the emission operation may be first performed on the odd-numbered pixel rows of the first region, followed by the even-numbered pixel rows of the first region. Thereafter, the scanning operation and the emission operation may be performed on the odd-numbered pixel rows of the second region, followed by the even-numbered pixel rows of the second region.

[0111] However, as long as the scanning operation and the emission operation of each in the synchronous pixel rows are synchronized, the present disclosure is not limited to Figure 7 the waveform shown in, and may be changed according to the internal structure of each of the emission stage and the scanning stage.

[0112] Figure 8 and Figure 9 FIG. is a diagram illustrating an emission driver, a pixel unit, and a scanning driver according to a second embodiment of the present disclosure.

[0113] Referring to Figure 8 , a connection relationship between the emission driver 14b and the pixel unit 15b according to the second embodiment is shown. For ease of description, Figure 8 four emission stages EST11 to EST14 are shown. Additionally, since Figure 8 the emission driver 14b and the pixel unit 15b of are similar to Figure 4 the emission driver 14a and the pixel unit 15a of, repeated descriptions are omitted.

[0114] The emission driver 14b may include first emission stages EST11, EST13,... connected to the first emission lines EL1, EL3,... and second emission stages EST12, EST14,... connected to the second emission lines EL2, EL4,....

[0115] For example, the first emission stages EST11, EST13,... may be odd-numbered emission stages. The second emission stages EST12, EST14,... may be even-numbered emission stages.

[0116] The first emission lines EL1, EL3,... may be connected to the pixels located in the first pixel column among the first pixel rows of the pixel unit 15b and the pixels located in the second pixel column among the second pixel rows of the pixel unit 15b. The second emission lines EL2, EL4,... may be connected to the pixels located in the first pixel column among the second pixel rows of the pixel unit 15b and the pixels located in the second pixel column among the first pixel rows of the pixel unit 15b.

[0117] In an embodiment, the first pixel row may be an odd-numbered pixel row, the second pixel row may be an even-numbered pixel row, the first pixel column may be an odd-numbered pixel column, and the second pixel column may be an even-numbered pixel column. For example, the first emission line EL1 may be connected to the first pixel PX11 and the third pixel PX13 of the first pixel row and the second pixel PX22 of the second pixel row. The second emission line EL2 may be connected to the first pixel PX21 and the third pixel PX23 of the second pixel row and the second pixel PX32 of the first pixel row.

[0118] Referring to Figure 7 and Figure 8 , the first emission control signal ELM1 may be supplied to the first input terminal 101 of the first emission stage EST11. The first emission clock signal ECK1 may be supplied to the second input terminal 102 of the first emission stages EST11, EST13,.... The second emission control signal ELM2 may be supplied to the first input terminal 101 of the second emission stage EST12. The second emission clock signal ECK2 may be supplied to the second input terminal 102 of the second emission stages EST12, EST14,....

[0119] In an embodiment, the emission operations of the pixels connected to the first emission lines EL1, EL3,... and the emission operations of the pixels connected to the second emission lines EL2, EL4,... may be alternately performed.

[0120] Referring to Figure 9 , the connection relationship between the scan driver 13b and the pixel unit 15b according to the second embodiment is shown. For ease of description, Figure 9 four scan stages ST1 to ST4 are shown. Additionally, since Figure 9 the scan driver 13b and the pixel unit 15b of Figure 6 are similar to the scan driver 13a and the pixel unit 15a of

[0121] the description thereof is omitted.

[0122] The scan driver 13b may include a first scan stage ST1, ST3,... connected to the first scan lines SL1, SL3,... and a second scan stage ST2, ST4,... connected to the second scan lines SL2, SL4,....

[0123] In an embodiment, the first pixel row may be an odd-numbered pixel row, the second pixel row may be an even-numbered pixel row, the first pixel column may be an odd-numbered pixel column, and the second pixel column may be an even-numbered pixel column.

[0124] For example, the first scan line SL1 may be connected to the first pixel PX11 and the third pixel PX13 of the first pixel row and the second pixel PX22 of the second pixel row. The second scan line SL2 may be connected to the first pixel PX21 and the third pixel PX23 of the second pixel row and the second pixel PX32 of the first pixel row.

[0125] Referring to Figure 7 and Figure 9 , the first scan start signal FLM1 may be supplied to the first input terminal 1001 of the first scan stage ST1. The first scan clock signal CK1 may be supplied to the second input terminals 1002 of the first scan stage ST1, ST3,.... The second scan start signal FLM2 may be supplied to the first input terminal 1001 of the second scan stage ST2. The second scan clock signal CK2 may be supplied to the second input terminals 1002 of the second scan stage ST2, ST4,....

[0126] In an embodiment, the scanning operations of the pixels connected to the first scan lines SL1, SL3,... and the scanning operations of the pixels connected to the second scan lines SL2, SL4,... may be alternately performed.

[0127] The scope of the present disclosure is not limited to what is described in the detailed description of the specification, but should be defined by the claims. The meaning and scope of the claims, including all changes and modifications obtained from equivalent concepts, should be considered within the scope of the present disclosure.

Claims

1. A display device, comprising: A pixel unit, including a first pixel row connected to a first emission line and a second pixel row connected to a second emission line, wherein the second pixel row alternates with the first pixel row; An emission driver, including a first emission stage connected to the first emission line and a second emission stage connected to the second emission line; and A scan driver, including a first scan stage connected to the first pixel row and a second scan stage connected to the second pixel row, wherein one first emission stage in the first emission stage is connected to a first emission start line, and one second emission stage in the second emission stage is connected to a second emission start line, except for the one first emission stage connected to the first emission start line, each of the first emission stages is connected to the first emission line of the previous first emission stage, and except for the one second emission stage connected to the second emission start line, each of the second emission stages is connected to the second emission line of the previous second emission stage.

2. The display device according to claim 1, wherein, After the emission driver applies an emission control signal having a conductive level to one of the first emission line and the second emission line, except for the emission line to which the emission control signal having the conductive level is applied, the emission driver applies the emission control signal having the conductive level to the other emission line among the first emission line and the second emission line.

3. The display device according to claim 1 or 2, wherein, The first emission stage is connected to a first emission clock line, The second emission stage is connected to a second emission clock line, and Pulses of a first emission clock signal applied to the first emission clock line and pulses of a second emission clock signal applied to the second emission clock line do not overlap with each other.

4. The display device according to claim 3, wherein, One first scan stage in the first scan stage is connected to a first scan start line, and one second scan stage in the second scan stage is connected to a second scan start line, except for the one first scan stage connected to the first scan start line, each of the first scan stages is connected to the first scan line of the previous first scan stage, and except for the one second scan stage connected to the second scan start line, each of the second scan stages is connected to the second scan line of the previous second scan stage.

5. The display device according to claim 4, wherein, The first scan stage is connected to a first scan clock line, The second scan stage is connected to a second scan clock line, and Pulses of a first scan clock signal applied to the first scan clock line and pulses of a second scan clock signal applied to the second scan clock line do not overlap with each other.

6. A display device, comprising: A pixel unit, including a first pixel row and a second pixel row alternating with the first pixel row; A transmission driver, comprising a first transmission stage connected to a first transmission line and a second transmission stage connected to a second transmission line, where the first transmission line is connected to pixels located in a first pixel column among the first pixel rows and pixels located in a second pixel column among the second pixel rows, and the second transmission line is connected to pixels located in the first pixel column among the second pixel rows and pixels located in the second pixel column among the first pixel rows; and a scan driver, connected to the pixel unit, wherein, one first transmission stage among the first transmission stages is connected to a first transmission start line, and one second transmission stage among the second transmission stages is connected to a second transmission start line, except for the one first transmission stage connected to the first transmission start line, each of the first transmission stages is connected to the first transmission line of the previous first transmission stage, and except for the one second transmission stage connected to the second transmission start line, each of the second transmission stages is connected to the second transmission line of the previous second transmission stage.

7. The display device according to claim 6, wherein, After the transmission driver applies a transmission control signal having a conductive level to one of the first transmission line and the second transmission line, the transmission driver applies the transmission control signal having the conductive level to the other of the first transmission line and the second transmission line except for the transmission line to which the transmission control signal having the conductive level is applied.

8. The display device according to claim 6 or 7, wherein, The first transmission stage is connected to a first transmission clock line, the second transmission stage is connected to a second transmission clock line, and pulses of a first transmission clock signal applied to the first transmission clock line and pulses of a second transmission clock signal applied to the second transmission clock line do not overlap with each other.

9. The display device according to claim 8, wherein, The scan driver includes a first scan stage connected to a first scan line and a second scan stage connected to a second scan line, where the first scan line is connected to the pixels located in the first pixel column among the first pixel rows and the pixels located in the second pixel column among the second pixel rows, and the second scan line is connected to the pixels located in the first pixel column among the second pixel rows and the pixels located in the second pixel column among the first pixel rows.

10. The display device according to claim 9, wherein, One first scan stage among the first scan stages is connected to a first scan start line, and one second scan stage among the second scan stages is connected to a second scan start line, except for the one first scan stage connected to the first scan start line, each of the first scan stages is connected to the first scan line of the previous first scan stage, and except for the one second scan stage connected to the second scan start line, each of the second scan stages is connected to the second scan line of the previous second scan stage.

Images