Pixel driving circuit, driving method thereof and array substrate

Abstract

The invention provides a pixel driving circuit and a driving method thereof, and an array substrate, and relates to the technical field of display, and the pixel driving circuit comprises a driving sub-circuit, a reset sub-circuit, a data writing and reading sub-circuit, and a light-emitting control sub-circuit. A pixel driving circuit is set to have a first reset stage and a second reset stage, in the first reset stage, a driving sub-circuit is configured to be switched on after being switched off for a preset time period, and a light-emitting device is made to display a black-state picture. Before data is written into each frame of display picture, in a first reset stage, a driving sub-circuit is closed for a preset time period, and an electric signal between a pixel driving circuit and a light-emitting device is cut off, so that a signal in the previous frame of display picture is eliminated as far as possible; in addition, after the driving sub-circuit is switched on again, the light-emitting device displays a black-state picture, the white picture of partial residual area in the previous frame of display picture is further counteracted, and the residual image is eliminated.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a pixel driving circuit, a driving method thereof, and an array substrate. Background Art

[0002] With the rapid development of OLED (Organic Light-Emitting Diode) display technology, people have higher and higher requirements for the characteristics of OLED display products. Based on the superiority of OLED display products, the diversity of their display refreshing, and the successive development of multi-frequency display products, OLED display technology is also continuously updated and iterated.

[0003] However, when an OLED display product switches images, the brightness information of the previous frame of the picture may be retained on the new picture, and this image sticking phenomenon can be easily captured by the human eye, which is called the afterimage phenomenon of OLED display. Summary of the Invention

[0004] The embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, an embodiment of the present application provides a pixel driving circuit, including: a driving sub-circuit, a reset sub-circuit, a data writing and reading sub-circuit, and a light emitting control sub-circuit;

[0006] The reset sub-circuit is electrically connected to a first node, a second node, a fourth node, a first input signal line, a second input signal line, a third input signal line, a third gate control signal line, and a fourth gate control signal line respectively; the driving sub-circuit is electrically connected to the first node, the second node, a third node, and a first power supply signal line respectively; the data writing and reading sub-circuit is electrically connected to the first node, the second node, the third node, the reset sub-circuit, a data signal line, a first gate control signal line, and a second gate control signal line respectively; the light emitting control sub-circuit is electrically connected to the first power supply signal line, the first node, the third node, the fourth node, and a light emitting control signal line respectively; the fourth node is electrically connected to a light emitting device;

[0007] Wherein, the pixel driving circuit includes a first reset stage and a second reset stage. In the first reset stage, the driving sub-circuit is configured to be turned on after being turned off for a preset time period, and to make the light emitting device display a black state picture.

[0008] In the pixel driving circuit provided by some embodiments of the present application, in the first reset stage,

[0009] the reset sub-circuit is configured to reset the second node;

[0010] The reset sub - circuit and the data writing and reading sub - circuit are configured to act together and turn off the driving sub - circuit within the preset time period;

[0011] The reset sub - circuit and the light - emitting control sub - circuit are configured to act together to turn on the driving sub - circuit and conduct the path between the driving sub - circuit and the light - emitting device, so that the light - emitting device displays a black - state picture.

[0012] In the pixel driving circuit provided by some embodiments of the present application, in the second reset stage,

[0013] The reset sub - circuit and the data writing and reading sub - circuit are configured to act together to turn off the driving sub - circuit again;

[0014] The reset sub - circuit is further configured to reset the first node, the second node, and the third node.

[0015] In the pixel driving circuit provided by some embodiments of the present application, the driving sub - circuit includes a second transistor and a storage capacitor, the data writing and reading sub - circuit includes a first transistor and a third transistor, the reset sub - circuit includes a fourth transistor, a seventh transistor, and an eighth transistor, and the light - emitting control sub - circuit includes a fifth transistor and a sixth transistor;

[0016] The gate of the third transistor is electrically connected to the first gate control signal line, the source of the third transistor is electrically connected to the second node, and the drain of the third transistor is electrically connected to the third node; the gate of the fourth transistor is electrically connected to the fourth gate control signal line, the source of the fourth transistor is electrically connected to the first input signal line, and the drain of the fourth transistor is electrically connected to the second node; the gates of the fifth transistor and the sixth transistor are both electrically connected to the light - emitting control signal line, the source of the fifth transistor is electrically connected to the first power supply signal line, the drain of the fifth transistor is electrically connected to the first node, the source of the sixth transistor is electrically connected to the third node, the drain of the sixth transistor is electrically connected to the fourth node; the source of the seventh transistor is electrically connected to the second input signal line, the drain of the seventh transistor is electrically connected to the fourth node; the gate of the eighth transistor is electrically connected to the third gate control signal line, the source of the eighth transistor is electrically connected to the third input signal line, and the drain of the eighth transistor is electrically connected to the first node.

[0017] In the pixel driving circuit provided by some embodiments of the present application, the first reset stage includes a first time period, a second time period, and a third time period set in sequence;

[0018] In the first time period, the fourth gate control signal input by the fourth gate control signal line is configured to control the fourth transistor to turn on, and transmit the signal input by the first input signal line to the second node through the fourth transistor, completing the reset of the second node; the second node is electrically connected to the gate of the second transistor.

[0019] In the pixel driving circuit provided by some embodiments of the present application, in the second time period, the first gate control signal input by the first gate control signal line is configured to control the third transistor to turn on, and connect the second node and the third node together;

[0020] The third gate control signal input by the third gate control signal line is configured to control the eighth transistor to turn on, and write the signal input by the third input signal line to the first node; the voltage of the second node is configured to be pulled up during this process, and control the second transistor to turn off.

[0021] In the pixel driving circuit provided by some embodiments of the present application, in the third time period, the third gate control signal input by the third gate control signal line is configured to control the seventh transistor and the eighth transistor to turn on, and write the signal input by the third input signal line to the first node, and write the signal input by the second input signal line to the fourth node; the threshold voltage of the second transistor is approximately equal to the gate-source voltage of the second transistor;

[0022] The emission control signal input by the emission control signal line is configured to control the fifth transistor and the sixth transistor to turn on, and the path between the first power supply signal line, the second transistor and the light-emitting device is configured to be turned on, so that the light-emitting device displays a black-state picture.

[0023] In the pixel driving circuit provided by some embodiments of the present application, the voltage of the first power supply signal transmitted in the first power supply signal line is the same as the voltage of the signal transmitted in the third input signal line.

[0024] In the pixel driving circuit provided by some embodiments of the present application, the third gate control signal input by the third gate control signal line is configured to control the eighth transistor to turn off after the second time period and before the third time period.

[0025] In the pixel driving circuit provided by some embodiments of the present application, the third gate control signal is configured to control the conduction time of the eighth transistor in the third time period to be longer than the conduction time of the eighth transistor in the second time period.

[0026] In the pixel driving circuit provided in some embodiments of the present application, the second reset stage includes a fourth time period and a fifth time period;

[0027] In the fourth time period, the first gate control signal input by the first gate control signal line is configured to control the third transistor to conduct, and connect the second node and the third node together; the third gate control signal input by the third gate control signal line is configured to control the eighth transistor to conduct, and write the signal input by the third input signal line into the first node to reset the first node; the voltage of the second node is configured to be pulled up during this process and control the second transistor to turn off;

[0028] In the fifth time period, the first gate control signal input by the first gate control signal line is configured to control the third transistor to conduct, and connect the second node and the third node together; the fourth gate control signal input by the fourth gate control signal line is configured to control the fourth transistor to conduct, and transmit the signal input by the first input signal line through the fourth transistor to the second node and the third node, completing the reset of the second node and the third node.

[0029] In the pixel driving circuit provided in some embodiments of the present application, the fourth gate control signal is configured to have a shorter reset time for the second node in the first reset stage than in the second reset stage.

[0030] In the pixel driving circuit provided in some embodiments of the present application, in one frame of display screen, the light emission control signal input by the light emission control signal line includes a plurality of pulse signals of a first level and a plurality of pulse signals of a second level, the pulse signals of the first level and the pulse signals of the second level are arranged at intervals, and the first level is greater than the second level;

[0031] Wherein, starting from the second reset stage, the pulse width of the first pulse signal of the first level is greater than the pulse widths of the subsequent pulse signals of the first level.

[0032] In the pixel driving circuit provided in some embodiments of the present application, the gate of the first transistor is electrically connected to the second gate control signal line, the source of the first transistor is electrically connected to the data signal line, and the drain of the first transistor is electrically connected to the first node;

[0033] The gate of the second transistor is electrically connected to the second node, the source of the second transistor is electrically connected to the first node, and the drain of the second transistor is electrically connected to the third node;

[0034] The gate of the seventh transistor is electrically connected to the third gate control signal line, the source of the seventh transistor is electrically connected to the second input signal line, and the drain of the seventh transistor is electrically connected to the fourth node; the first electrode of the storage capacitor is electrically connected to the first power supply signal line, and the second electrode of the storage capacitor is electrically connected to the second node.

[0035] In a second aspect, an embodiment of the present application provides a driving method for a pixel driving circuit, which is applied to drive the pixel driving circuit described in any one of the first aspect. The method includes:

[0036] In the first time period of the first reset stage, the second node of the pixel driving circuit is reset;

[0037] In the second time period, the driving sub-circuit of the pixel driving circuit is turned off within the preset time period;

[0038] In the third time period, the driving sub-circuit is turned on and the path between the driving sub-circuit and the light-emitting device is turned on, so that the light-emitting device displays a black-state picture.

[0039] In the driving method provided by some embodiments of the present application, in the first time period of the first reset stage, the step of resetting the second node of the pixel driving circuit includes:

[0040] A low-level fourth gate control signal is input to the fourth gate control signal line, a high-level light-emitting control signal is input to the light-emitting control signal line, a high-level first gate control signal is input to the first gate control signal line, a high-level second gate control signal is input to the second gate control signal line, and a high-level third gate control signal is input to the third gate control signal line.

[0041] In the driving method provided by some embodiments of the present application, in the second time period, the step of turning off the driving sub-circuit of the pixel driving circuit within the preset time period includes:

[0042] A low-level first gate control signal is input to the first gate control signal line, a low-level third gate control signal is input to the third gate control signal line, a high-level light-emitting control signal is input to the light-emitting control signal line, a high-level second gate control signal is input to the second gate control signal line, and a high-level fourth gate control signal is input to the fourth gate control signal line.

[0043] In the driving method provided in some embodiments of the present application, in the third time period, the step of turning on the driving sub-circuit and conducting the path between the driving sub-circuit and the light-emitting device so that the light-emitting device displays a black-state picture includes:

[0044] Input a low-level light-emitting control signal to the light-emitting control signal line, input a low-level third gate control signal to the third gate control signal line, input a high-level first gate control signal to the first gate control signal line, input a high-level second gate control signal to the second gate control signal line, and input a high-level fourth gate control signal to the fourth gate control signal line.

[0045] In a third aspect, an embodiment of the present application provides an array substrate, including the pixel driving circuit as described in any one of the first aspects.

[0046] The above description is only an overview of the technical solutions of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the description. And in order to make the above and other purposes, features and advantages of the present application more obvious and understandable, the specific embodiments of the present application are specifically exemplified below. Description of the Drawings

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to these drawings.

[0048] Figure 1 It is an explanatory diagram of a black and white checkerboard picture test in a related technology provided by an embodiment of the present application;

[0049] Figure 2 It is a pixel driving circuit diagram provided by an embodiment of the present application;

[0050] Figure 3 For Figure 2 A part of the timing diagram corresponding to the pixel driving circuit shown;

[0051] Figure 4 For Figure 2 The timing diagram of a frame of display picture corresponding to the pixel driving circuit shown;

[0052] Figures 5 to 11 For Figure 2 The pixel driving circuit shown is under the control of the timing signal in Figure 3 The state explanatory diagram of different stages;

[0053] Figure 12Comparison of the brightness change trends of the display panel prepared from the array substrate of the present application and the display panel in the related art after the black and white checkerboard pattern test;

[0054] Figure 13 Score curve of the afterimage score of the display panel prepared from the array substrate of the present application and the display panel in the related art after the black and white checkerboard pattern test. Detailed implementation manners

[0055] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0056] Unless otherwise required by the context, in the whole specification and claims, the term "comprising" is interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples", etc., are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the described specific features, structures, materials or characteristics can be included in any one or more embodiments or examples in any appropriate manner.

[0057] In the embodiments of the present application, the same items or similar items with basically the same functions and roles are partially named with words such as "first" and "second" only to clearly describe the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features.

[0058] The features such as "parallel", "perpendicular" and "same" used in the embodiments of the present application include the strict sense of "parallel", "perpendicular", "same" and other features, as well as the cases with certain errors such as "substantially parallel", "substantially perpendicular" and "substantially the same". Considering the measurement and errors related to the measurement of a specific quantity (for example, the limitations of the measurement system), it means within the acceptable deviation range for a specific value determined by those of ordinary skill in the art. For example, "substantially" can mean within one or more standard deviations, or within 10% or 5% of the value. "At least one" means one or more, and "a plurality" means at least two.

[0059] The "same layer" in the embodiments of the present application refers to the relationship between multiple film layers formed by the same material after the same step (e.g., a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. The polygons in this specification are not strictly defined, and can be approximate triangles, parallelograms, trapezoids, pentagons or hexagons, etc., and there may be some small deformations caused by tolerances.

[0060] In this specification, "electrically connected" and "coupled" include the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0061] With the continuous development of display technology, organic light-emitting diode display devices (OLED) have become the research hotspot and technology development direction of major manufacturers due to their advantages such as wide color gamut, high contrast, thin and light design, self-luminescence, and wide viewing angle. At present, organic light-emitting diode display devices (OLED) have been widely used in various electronic products, ranging from small electronic products such as smart bracelets, smart watches, smart phones, tablet computers, etc. to large electronic products such as laptops, desktop computers, and televisions. Therefore, the market demand for active matrix organic light-emitting diode display devices is also growing.

[0062] However, OLED technology still faces a power consumption bottleneck. When OLED display terminals are actually used, when the display screen switches, the brightness information of the previous screen may be retained on the new screen. This image sticking phenomenon is easily captured by the human eye and is called the afterimage phenomenon of OLED display. In the display screen, there is a difference in the gate voltage of the transistors in the black and white areas, which leads to the hysteresis effect of the transistors and causes the offset of the transistor threshold voltage, which is one of the main reasons for the afterimage. Usually, the display performance of the display panel can be tested to the extreme by displaying a black and white chessboard screen to judge the possibility of afterimage. Figure 1As shown, 1. First, the display panel shows a reference image (e.g., a gray image at W31 gray level) and tests its baseline brightness. 2. Second, the display panel then shows a black-and-white checkerboard image and maintains it for a period of time (e.g., 3 minutes). 3. Finally, the reference image is restored. If there is an afterimage problem, the residual image of the previous black-and-white checkerboard image will be reflected on the subsequently displayed gray image. By comparing the brightness changes of the gray image before and after showing the black-and-white checkerboard image, the afterimage level of the display panel can be evaluated. Figure 1 W31, W0, and W255 shown in it can be understood as L31, L0, and L255 gray levels in sequence.

[0063] For example, the brightness of this image can be tested when the reference image is restored for display for 30 seconds (T30), or for another example, the brightness of this image can be tested when the reference image is restored for display for 300 seconds (T300). Among them, when testing the brightness after restoring the display of the reference image, the brightness of the black and white areas can be tested separately, and compared with the brightness of the original reference image as a percentage, and the afterimage score is calculated. The higher the afterimage score, the less significant the afterimage phenomenon and the better the display effect.

[0064] For example, the brightness percentage in the black area can be calculated using the following formula:

[0065] B% = (Lum T30 - Lum base ) / Lum base , formula (1);

[0066] Among them, Lum T30 is the brightness value of the black checkerboard area measured when the reference image is restored for display for 30 seconds, Lum base is the brightness value of the reference image. It can be understood that Lum T60 is the brightness value of the black checkerboard area measured when the reference image is restored for display for 60 seconds, and the representation method of the brightness value at other times can be deduced by analogy.

[0067] The brightness percentage in the white area can be calculated using the following formula:

[0068] W% = (Lum T30 - Lum base ) / Lum base , formula (2);

[0069] Among them, Lum T30 is the brightness value of the white checkerboard area measured when the reference image is restored for display for 30 seconds, Lum base is the brightness value of the reference image. It can be understood that Lum T60To restore the brightness value of the white checkerboard area measured when the reference image is displayed for 60 seconds, the brightness values at other times are expressed in the same way.

[0070] Afterimage score = a*(W%-B%), where a is a coefficient; formula (3).

[0071] The embodiment of the present application provides a pixel driving circuit and a driving method thereof, and an array substrate. The pixel driving circuit is provided with a first reset stage and a second reset stage. In the first reset stage, the driving subcircuit is configured to be turned on after being turned off for a preset time period, and the light-emitting device displays a black state picture. In this way, before each frame of the display picture is written, in the first reset stage of the pixel driving circuit, the driving subcircuit turns off the preset time period, cuts off the electrical signal between the pixel driving circuit and the light-emitting device, so that the signal in the previous frame of the display picture is eliminated as much as possible; in addition, after the driving subcircuit is turned on again, the light-emitting device displays a black state picture, further offsets the white picture of the residual part of the area in the previous frame of the display picture, and further eliminates the residual image; and then through the second reset stage set by the pixel driving circuit, the pixel driving circuit and the light-emitting device connected thereto are reset by electrical signals, so as to eliminate the residual information of the previous picture as thoroughly as possible, solve the residual image problem, and improve the display effect.

[0072] The pixel driving circuit and driving method thereof, and the array substrate provided in the embodiments of the present application will be introduced and described in detail below in conjunction with the accompanying drawings.

[0073] The embodiment of the present application provides a pixel driving circuit, such as Figure 2 As shown, it includes: a driving subcircuit 2, a reset subcircuit 1, a data writing and reading subcircuit 3 and a light emitting control subcircuit 4;

[0074] The reset sub-circuit 1 is electrically connected to the first node N1, the second node N2, the fourth node N4, the first input signal line VINIT, the second input signal line VAR, the third input signal line Vobs, the third gate control signal line SC3 and the fourth gate control signal line SC4 respectively;

[0075] The driving sub-circuit 2 is electrically connected to the first node N1, the second node N2, the third node N3 and the first power signal line VDD respectively;

[0076] The data writing and reading sub-circuit 3 is electrically connected to the first node N1, the second node N2, the third node N3, the reset sub-circuit 1, the data signal line Data, the first gate control signal line SC1 and the second gate control signal line SC2 respectively;

[0077] The light-emitting control sub-circuit 4 is electrically connected to the first power supply signal line VDD, the first node N1, the third node N3, the fourth node N4, and the light-emitting control signal line EM respectively; the fourth node N4 is electrically connected to a light-emitting device (such as an OLED).

[0078] Among them, as shown in Figure 2 and Figure 3 , the pixel driving circuit includes a first reset stage H1 and a second reset stage H2. In the first reset stage H1, the driving sub-circuit 2 is configured to be turned on after being turned off for a preset time period, and the light-emitting device (such as an OLED) is made to display a black-state picture.

[0079] Here, the specific circuit structures included in the above driving sub-circuit 2, reset sub-circuit 1, data writing and reading sub-circuit 3, and light-emitting control sub-circuit 4 are not limited. As long as the corresponding functions are satisfied, they are within the scope of protection of the pixel driving circuit provided by the embodiments of the present application.

[0080] It should be noted that the above first node N1, second node N2, third node N3, and fourth node N4 are not actual circuit structures, but concepts defined for the convenience of describing the circuit structure.

[0081] In an exemplary embodiment, the above light-emitting device may be a light-emitting diode (LED), an organic light-emitting diode (OLED), a Micro LED (Micro light Emitting Diode), or a Mini LED (Mini light Emitting Diode).

[0082] Among them, when the light-emitting device is an organic light-emitting diode (OLED), the display device provided with the above pixel driving circuit may be a silicon-based display device or a glass-based display device. The silicon-based display device means that the driving circuit of the display device is arranged on a silicon-based substrate and the driving circuit is prepared by MOS process. The glass-based display device means that the driving circuit of the display device is arranged on a glass-based substrate and the driving circuit is prepared by TFT process.

[0083] Exemplarily, the reset sub - circuit 1 is used to reset the voltages of the first node N1, the second node N2, and the fourth node N4. The driving sub - circuit 2 is used to conduct the path between the first node N1 and the third node N3 and provide a driving current to the light - emitting device. The data writing and reading sub - circuit 3 is used to write a data signal Data to the first node N1 and read the threshold voltage Vth of the driving transistor in the driving sub - circuit 2. The light - emitting control sub - circuit 4 is used to conduct the path between the first power supply signal line VDD and the driving sub - circuit 2 and conduct the path between the driving sub - circuit 2 and the anode of the light - emitting device.

[0084] The above - mentioned driving sub - circuit 2, reset sub - circuit 1, data writing and reading sub - circuit 3, and light - emitting control sub - circuit 4 each include at least one transistor.

[0085] Here, the types of transistors in the above - mentioned driving sub - circuit 2, reset sub - circuit 1, data writing and reading sub - circuit 3, and light - emitting control sub - circuit 4 are not limited.

[0086] Each transistor in this application can be independently selected from N - type transistors or P - type transistors.

[0087] Among them, this specification takes each transistor as a P - type transistor as an example for illustration. For an N - type transistor, the working level state is a high - level state, and the non - working level state is a low - level state; for a P - type transistor, the working level state is a low - level state, and the non - working level state is a high - level state. The working level state refers to the level state that can make the source and drain of the transistor conduct, and the non - working level state refers to the level state that can make the source and drain of the transistor disconnect.

[0088] It should be noted that the pixel driving circuit includes a first reset stage H1 and a second reset stage H2. In the two reset stages, the electrical states presented by the pixel driving circuit are not completely the same; that is to say, the driving processes of the pixel driving circuit in the two reset stages are not completely the same, and the first reset stage H1 and the second reset stage H2 are not a conventional repetition of the reset stage.

[0089] Furthermore, in the first reset stage H1, in order to improve the afterimage problem of the OLED display product, the driving sub - circuit 2 in the pixel driving circuit is turned off for a period of time. After the driving sub - circuit 2 is turned off, the path for providing a driving current to the light - emitting device in the pixel driving circuit is turned off. Even if there are electrical signals of the previous frame of the display image remaining in the pixel driving circuit, they cannot be transmitted to the light - emitting device, so as to eliminate as much as possible the signals in the previous frame of the display image; in addition, the driving sub - circuit 2 continues to conduct and transmit the electrical signal of the black - state display image to the light - emitting device, so that the light - emitting device displays a black - state image; the black - state image can cover and offset the white image in some areas remaining in the previous frame of the display image, further eliminating the afterimage.

[0090] Furthermore, after the first reset stage H1, the pixel driving circuit further goes through a second reset stage H2 to reset the signals in the pixel driving circuit again, eliminating the residual information of the previous display frame (including eliminating the residual information of the previous display frame and the black screen signal displayed during the first reset stage H1).

[0091] An embodiment of the present application provides a pixel driving circuit. By setting a first reset stage and a second reset stage, in the first reset stage, the driving sub-circuit is configured to turn on after being turned off for a preset period of time, and the light-emitting device is made to display a black screen. In this way, before each display frame is written, in the first reset stage of the pixel driving circuit, the driving sub-circuit is turned off for a preset period of time, cutting off the electrical signal between the pixel driving circuit and the light-emitting device, so as to eliminate the signal in the previous display frame as much as possible. In addition, after the driving sub-circuit is turned on again, the light-emitting device displays a black screen, further canceling the white screen in some areas remaining in the previous display frame, further eliminating the ghost image. Then, through the second reset stage set in the pixel driving circuit, the electrical signals of the pixel driving circuit and the light-emitting device connected thereto are reset, thereby eliminating the residual information of the previous screen as thoroughly as possible, solving the ghost image problem, and improving the display effect.

[0092] The processes of the first reset stage H1 and the second reset stage H2 of the pixel driving circuit will be specifically described below.

[0093] Among them, as Figure 2 shown, in the first reset stage H1, first, the reset sub-circuit 1 is configured to reset the second node N2. Since the second node N2 is electrically connected to the gate of the driving transistor (the second transistor T2) in the driving sub-circuit 2, it can be understood that at this time, the reset sub-circuit 1 resets the driving sub-circuit 2. Secondly, the reset sub-circuit 1 and the data writing and reading sub-circuit 3 are configured to cooperate to turn off the driving sub-circuit 2 within a preset period of time. Finally, the reset sub-circuit 1 and the light-emitting control sub-circuit 4 are configured to cooperate to turn on the driving sub-circuit 2 and conduct the path between the driving sub-circuit 2 and the light-emitting device (such as an OLED), so that the light-emitting device displays a black screen.

[0094] In the pixel driving circuit provided in some embodiments of the present application, in the second reset stage H2, first, the reset sub-circuit 1 and the data writing and reading sub-circuit 3 are configured to cooperate to turn off the driving sub-circuit 2 again. Secondly, the reset sub-circuit 1 is further configured to reset the first node N1, the second node N2, and the third node N3.

[0095] Next, a specific circuit structure of a pixel driving circuit provided by an embodiment of the present application will be introduced, so as to specifically illustrate the first reset stage H1 and the second reset stage H2 in combination with the specific circuit structure and driving timing later.

[0096] In the pixel driving circuit provided by some embodiments of the present application, as Figure 2 shown, the driving sub-circuit 2 includes a second transistor T2 (driving transistor) and a storage capacitor Cst, the data writing and reading sub-circuit 3 includes a first transistor T1 and a third transistor T3, the reset sub-circuit 1 includes a fourth transistor T4, a seventh transistor T7 and an eighth transistor T8, and the light emission control sub-circuit 4 includes a fifth transistor T5 and a sixth transistor T6;

[0097] Among them, as Figure 2 shown, the gate of the third transistor T3 is electrically connected to the first gate control signal line SC1, the source of the third transistor T3 is electrically connected to the second node N2, and the drain of the third transistor T3 is electrically connected to the third node N3; the gate of the fourth transistor T4 is electrically connected to the fourth gate control signal line SC4, the source of the fourth transistor T4 is electrically connected to the first input signal line VINIT, and the drain of the fourth transistor T4 is electrically connected to the second node N2; the gates of the fifth transistor T5 and the sixth transistor T6 are both electrically connected to the light emission control signal line EM, the source of the fifth transistor T5 is electrically connected to the first power supply signal line VDD, the drain of the fifth transistor T5 is electrically connected to the first node N1, the source of the sixth transistor T6 is electrically connected to the third node N3, and the drain of the sixth transistor T6 is electrically connected to the fourth node N4; the gate of the seventh transistor T7 is electrically connected to the third gate control signal line SC3, the source of the seventh transistor T7 is electrically connected to the second input signal line VAR, and the drain of the seventh transistor T7 is electrically connected to the fourth node N4; the gate of the eighth transistor T8 is electrically connected to the third gate control signal line SC3, the source of the eighth transistor T8 is electrically connected to the third input signal line Vobs, and the drain of the eighth transistor T8 is electrically connected to the first node N1.

[0098] In an exemplary embodiment, the first transistor T1, the third transistor T3, the second transistor T2 (driving transistor), the fourth transistor T4, the seventh transistor T7 and the eighth transistor T8, and the fifth transistor T5 and the sixth transistor T6 are all P-type transistors.

[0099] Figure 3 The timing provided in [reference] takes the above transistors as all P-type transistors as an example. Of course, when the above transistors are all N-type transistors, the corresponding timing is opposite to the timing provided in Figure 3 the [reference].

[0100] In the pixel driving circuit provided by some embodiments of the present application, asFigure 3 As shown, the first reset stage H1 includes a first time period t1, a second time period t2, and a third time period t3 arranged in sequence;

[0101] In the first time period t1, in combination with Figure 3 and Figure 5 As shown, the fourth gate control signal input by the fourth gate control signal line SC4 is configured to control the fourth transistor T4 to conduct, and transmit the signal input by the first input signal line VINIT to the second node N2 through the fourth transistor T4, completing the reset (which can also be called initialization) of the second node N2; the second node N2 is electrically connected to the gate of the second transistor T2 (driving transistor). It can be understood that resetting the second node N2 is to reset the gate of the second transistor T2.

[0102] In the pixel driving circuit provided by some embodiments of the present application, in the second time period t2, in combination with Figure 3 and Figure 6 As shown, the first gate control signal input by the first gate control signal line SC1 is configured to control the third transistor T3 to conduct, and connect the second node N2 and the third node N3 together; the third gate control signal input by the third gate control signal line SC3 is configured to control the eighth transistor T8 to conduct, and write the signal input by the third input signal line Vobs to the first node N1; the voltage of the second node N2 is configured to be pulled up during this process, and control the second transistor T2 to turn off.

[0103] It should be noted that when the eighth transistor T8 conducts, the voltage of the first node N1 is Vobs. Since the second node N2 and the third node N3 are connected together, the voltages of the second node N2 and the third node N3 are both Vobs + Vth, where Vth is the threshold voltage of the second transistor T2. Since the voltage at the gate position of the second transistor T2 is Vobs + Vth, which is in a high voltage state, the second transistor T2 turns off during the second time period t2, eliminating the brightness of the display screen of the previous frame.

[0104] In the pixel driving circuit provided by some embodiments of the present application, in the third time period t3, in combination with Figure 3 and Figure 7As shown, the third gate control signal input by the third gate control signal line SC3 is configured to control the seventh transistor T7 and the eighth transistor T8 to conduct, and write the signal input by the third input signal line Vobs to the first node N1, and write the signal input by the second input signal line VAR to the fourth node N4; at this time, the threshold voltage Vth of the second transistor T2 is approximately equal to the gate-source voltage Vgs of the second transistor T2; the light emission control signal input by the light emission control signal line EM is configured to control the fifth transistor T5 and the sixth transistor T6 to conduct, and the path between the first power supply signal line VSS, the second transistor T2, and the light emitting device (such as an OLED) is configured to conduct, so that the light emitting device displays a black state image.

[0105] It should be noted that the voltage of the first power supply signal transmitted in the first power supply signal line VDD is the same as the voltage of the signal transmitted in the third input signal line Vobs, that is, Vdd = Vobs.

[0106] As Figure 7 shown, in the third time period t3 when the fifth transistor T5 and the eighth transistor T8 are both conducting, the voltage of the first power supply signal transmitted in the first power supply signal line VDD is set to be the same as the voltage of the signal transmitted in the third input signal line Vobs, and only in the third time period t3 can the Vobs signal be written at the position of the first node N1; when the sixth transistor T6 and the seventh transistor T7 are both conducting, the fourth node N4 and the third node N3 are connected together, and then the third node N3 is also written with the signal input by the second input signal line VAR; in this way, the gate-source voltage Vgs of the second transistor T2 (driving transistor) = Vg - Vs = Vobs + Vth - Vobs = Vth; the gate-source voltage Vgs is the voltage during the black screen light emission process. At this time, the current flowing through the second transistor T2 (driving transistor) is very small, and the source-drain voltage Vds of the second transistor T2 (driving transistor) = Vd - Vs = Var - Vdd = Var - Vobs, which is also approximately equal to the voltage in the black screen working state. In this stage, the pixel driving circuit controls the light emitting device to display a black screen.

[0107] In addition, it should be noted that the voltage Vinit of the signal input by the first input signal line VINIT is less than the voltage Vdd of the signal transmitted in the first power supply signal line VDD, and the voltage Var of the signal input by the second input signal line VAR is less than the voltage Vinit of the signal input by the first input signal line VINIT; that is, Var < Vinit < Vdd = Vobs. In addition, the voltage of the signal input by the data signal line Data is greater than the voltage Vinit of the signal input by the first input signal line VINIT, that is, Var < Vinit < Vdata.

[0108] In the pixel driving circuit provided in some embodiments of the present application, asFigure 3 As shown, the third gate control signal input by the third gate control signal line SC3 is configured to control the eighth transistor T8 to turn off after the second time period t2 and before the third time period t3. That is to say, during the second time period, with the assistance of the eighth transistor T8, the gate voltage of the second transistor T2 is raised, so that the second transistor T2 turns off to completely eliminate the brightness of the display screen of the previous frame and improve the ghosting problem; while during the third time period t3, the second transistor T2 is turned on. In order to avoid the interference of the pixel driving circuit state in the second time period t2 on the pixel driving circuit state in the third time period t3, the third gate control signal input by the third gate control signal line SC3 is configured to control the eighth transistor T8 to turn off after the second time period t2 and before the third time period t3.

[0109] In the pixel driving circuit provided in some embodiments of the present application, as Figure 3 shown in the timing of the marked third time period t3 and the second time period t2, the third gate control signal SC3 is configured to control the conduction time of the eighth transistor T8 in the third time period t3 to be greater than the conduction time of the eighth transistor T8 in the second time period t2.

[0110] As Figure 3 shown in the timing, when the third gate control signal SC3 is configured to control the conduction time of the eighth transistor T8 in the third time period t3 to be greater than the conduction time of the eighth transistor T8 in the second time period t2, the light emission control signal input by the light emission control signal line EM controls the conduction time of the fifth transistor T5 and the sixth transistor T6 in the third time period t3 to be greater than the conduction time of the eighth transistor T8 in the third time period t3. In this way, in the first reset stage H1, the time period during which the pixel driving circuit controls the light emitting device to display a black state screen is greater than the time when the second transistor T2 (driving transistor) in the pixel driving circuit is turned off to eliminate the signal of the previous frame.

[0111] In the embodiments of the present application, by setting the conduction time of the eighth transistor T8 in the third time period t3 to be greater than the conduction time of the eighth transistor T8 in the second time period t2, the time for the pixel driving circuit to control the light emitting device to display a black state screen can be extended, so that the black screen can offset the residual brightness of the previous frame as much as possible, and the ghosting can be eliminated as thoroughly as possible, so as to write a new signal subsequently and avoid the ghosting phenomenon when displaying a new screen, and the ghosting problem is improved to the greatest extent.

[0112] In the pixel driving circuit provided in some embodiments of the present application, as Figure 3 shown, the second reset stage H2 includes a fourth time period t4 and a fifth time period t5;

[0113] In the fourth time period t4, in combination with Figure 3 and Figure 8 As shown, the first gate control signal input by the first gate control signal line SC1 is configured to control the third transistor T3 to turn on, and connect the second node N2 and the third node N3 together; the third gate control signal input by the third gate control signal line SC3 is configured to control the eighth transistor T8 to turn on, and write the signal input by the third input signal line Vobs to the first node N1 to reset the first node N1; the voltage of the second node N2 is configured to be pulled up during this process and control the second transistor T2 to turn off;

[0114] Among them, the driving process of the fourth time period t4 is the same as that of the second time period t2 in the previous text. Refer to the description in the previous text here and will not be elaborated here.

[0115] It should be noted that when the eighth transistor T8 is turned on during the fourth time period t4, the signal input by the third input signal line Vobs can be written to the first node N1 to complete the reset of the first node.

[0116] In the fifth time period t5, in combination with Figure 3 and Figure 9 As shown, the first gate control signal input by the first gate control signal line SC1 is configured to control the third transistor T3 to turn on, and connect the second node N2 and the third node N3 together; the fourth gate control signal input by the fourth gate control signal line SC4 is configured to control the fourth transistor T4 to turn on, and transmit the signal input by the first input signal line VINIT to the second node N2 and the third node N3 through the fourth transistor T4 to complete the reset of the second node N2 and the third node N3.

[0117] So far, the pixel driving circuit has completed the driving processes of the first reset stage H1 and the second reset stage H2. Under the superposition effect of the two reset stages, the pixel driving circuit can completely eliminate the signal remaining from the previous frame on the display panel, thereby avoiding the situation where the signal of the previous frame remains in the display picture when writing the signal of the new frame of the display picture, and thus maximizing the improvement of the ghosting problem that appears in the display picture.

[0118] In the pixel driving circuit provided in some embodiments of the present application, as Figure 3 shown, the fourth gate control signal SC4 is configured such that the reset time S1 of the second node N2 in the first reset stage H1 is less than the reset time S2 of the second node N2 in the second reset stage H2. The second node N2 is electrically connected to the gate of the second transistor T2 (driving transistor). It can be understood that resetting the second node N2 is to reset the gate of the second transistor T2 (driving transistor).

[0119] In this application, the fourth gate control signal SC4 is mainly used to control the fourth transistor T4 to turn on, so as to reset the gate voltage of the second transistor T2 (driving transistor). During the first reset phase H1, after resetting the gate voltage of the second transistor T2 (driving transistor) in the first time period t1, it is mainly used to pave the way for raising the voltage of the second node N2 subsequently, so as to turn off the second transistor T2 to eliminate the electrical signal of the previous frame of the picture. Since no new display data is written subsequently, and there are still the second time period t2 and the third time period t3 subsequently, in order to reduce the driving time and improve the refresh rate, the reset time of the gate voltage of the second transistor T2 (driving transistor) can be appropriately shortened on the premise of ensuring the reset effect of the first reset phase H1.

[0120] During the second reset phase H2, the fourth gate control signal SC4 controls the fourth transistor T4 to conduct, so as to reset the gate voltage of the second transistor T2 (driving transistor) and then prepare to start writing new data to display a new picture. Therefore, during the second reset phase H2, it is necessary to reset the gate voltage of the second transistor T2 (driving transistor) for a longer time to ensure a better reset effect.

[0121] In the pixel driving circuit provided by some embodiments of this application, as Figure 4 shown, in a frame of display picture, the light emission control signals input by the light emission control signal line EM include a plurality of pulse signals of a first level (for example Figure 4 the high-level signal in the EM signal) and a plurality of pulse signals of a second level (for example Figure 4 the low-level signal in the EM signal), the pulse signals of the first level and the pulse signals of the second level are arranged at intervals, and the first level is greater than the second level; wherein, starting from the second reset phase H2, the pulse width W1 of the first pulse signal of the first level (for example Figure 4 the high-level signal in the EM signal) is greater than the pulse width W2 of the subsequent pulse signals of the first level.

[0122] It should be noted that starting from the second reset phase H2, when the pulse width W1 of the first pulse signal of the first level (for example Figure 4 the high-level signal in the EM signal) in the EM signal is greater than the pulse width W2 of the subsequent pulse signals of the first level, the conduction time of the fourth transistor T4 controlled by the fourth gate control signal SC4 can be increased, so as to increase the reset time of the gate voltage of the second transistor T2 (driving transistor), thereby ensuring a better reset effect and further improving the problem of afterimage, and preparing for the signal of writing a new display picture.

[0123] Exemplarily, in the related art, the time for resetting the gate voltage of the second transistor T2 (driving transistor) is usually 5H, where H is the charging time of one row of pixel units; while in the embodiments of the present application, the pulse width W1 of the first pulse signal of the first level of the EM signal can be extended (for example, Figure 4 the high-level signal in the EM signal), and its pulse width can be extended to 90H. Furthermore, on this basis, the time for resetting the gate voltage of the second transistor T2 (driving transistor) is extended (for example, from 5H in the related art to 15H).

[0124] Exemplarily, as Figure 3 shown, the fourth gate control signal SC4 is configured such that the reset time S1 of the second node N2 in the first reset stage H1 is less than the reset time S2 of the second node N2 in the second reset stage H2, and the reset time S2 of the fourth gate control signal SC4 for the second node N2 in the second reset stage H2 can be approximately 15H.

[0125] Exemplarily, the time of the first reset stage H1 can be approximately 26H.

[0126] Exemplarily, the width of the first pulse signal of the first level of the EM signal is 90H, and the widths of the subsequent pulse signals of the first level are 68H.

[0127] In the related art, the EM signal is an equal pulse width signal, and the widths of the pulse signals of each first level are all 80H.

[0128] In the embodiments of the present application, by setting and extending the first pulse signal of the first level of the EM signal, and setting the pulse width W1 of the first pulse signal of the first level (for example, Figure 4 the high-level signal in the EM signal) to be greater than the pulse width W2 of the subsequent pulse signals of each first level, the pulse signals of multiple first levels of the EM signal (high-level pulse signals) are of unequal width, rather than setting equal-width high-level signals as in the related art. In this way, when the reset time is extended, the time of the pulse signal of the second level of the EM signal in one frame of the display screen can be maintained as unchanged as possible (the pulse signal of the second level of the EM signal is the stage when the light-emitting device is turned on and emits light), thereby ensuring the effective light-emitting time of the light-emitting device and the display effect of the display panel prepared by the array substrate.

[0129] In the pixel driving circuit provided in some embodiments of the present application, as Figure 2 shown, the gate of the first transistor T1 is electrically connected to the second gate control signal line SC2, the source of the first transistor T1 is electrically connected to the data signal line Data, and the drain of the first transistor T1 is electrically connected to the first node N1;

[0130] The gate of the second transistor T2 is electrically connected to the second node N2, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the third node N3; the gate of the seventh transistor T7 is electrically connected to the third gate control signal line SC3, the source of the seventh transistor T7 is electrically connected to the second input signal line VAR, and the drain of the seventh transistor T7 is electrically connected to the fourth node N4; the first electrode of the storage capacitor Cst is electrically connected to the first power supply signal line VDD, and the second electrode of the storage capacitor Cst is electrically connected to the second node N2.

[0131] The following combines Figure 2 and Figure 3 The shown timing sequence, taking each transistor in the pixel driving circuit as a P-type transistor as an example, specifically explains and introduces the driving processes of the third stage H3 and the fourth stage H4 of the pixel driving circuit. The driving processes of the first reset stage H1 and the second reset stage H2 of the pixel driving circuit can refer to the previous introduction and will not be repeated here.

[0132] In the third stage H3, also known as the data writing and reading stage, combining Figure 3 and Figure 10 as shown, the first gate control signal line SC1 inputs a low-level first gate control signal, the second gate control signal line SC2 inputs a low-level second gate control signal, the first transistor T1 and the third transistor T3 are turned on, and the signal transmitted by the data signal line Data is written to the first node N1 through the first transistor T1. At this time, since the third transistor T3 is turned on, the second node N2 and the third node N3 are connected together. At this time, the voltage of the first node N1 is Vdata, and the voltages of the second node N2 and the third node N3, V N2 = Vdata + Vth.

[0133] In the fourth stage H4, also known as the compensation and light-emitting stage, combining Figure 3 and Figure 11 as shown, the light-emitting control signal line EM inputs a low-level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the voltage of the first node N1 becomes V N1 = Vdd. During the light-emitting process, the current I is proportional to (Vgs - Vth) 2 According to the previous text,

[0134] Vgs - Vth = Vg - Vs - Vth = V N2 - V N1 - Vth = Vdata + Vth - Vdd - Vth = Vdata - Vdd;

[0135] It can be seen from this that during the light-emitting process, the current I is proportional to (Vdata - Vdd) 2It is proportional to the threshold voltage Vth of the driving transistor.

[0136] An embodiment of the present application provides a driving method of a pixel driving circuit, which is applied to drive the pixel driving circuit as described above, and the driving method includes:

[0137] S1, in a first time period t1 of a first reset phase, resetting the second node of the pixel driving circuit;

[0138] Since the second node N2 is electrically connected to the gate of the driving transistor (the second transistor T2 ) in the driving sub-circuit 2 , it can be understood that at this time, the reset sub-circuit 1 resets the driving sub-circuit 2 .

[0139] S2, in a second time period t2, turning off the driving sub-circuit of the pixel driving circuit within a preset time period;

[0140] Under the cooperation of the reset sub-circuit 1 and the data writing and reading sub-circuit 3 , the driving sub-circuit 2 is turned off within a preset time period.

[0141] The preset time period here may be equal to the time consumed by the second time period t2; for example, Figure 3 As shown, the reset time S1 for the second node N2 in the first reset phase H1 may be shorter than the reset time S2 for the second node N2 in the second reset phase H2.

[0142] S3. In a third time period t3, the driving sub-circuit is turned on and the path between the driving sub-circuit and the light-emitting device is turned on, so that the light-emitting device displays a black state image.

[0143] In the third time period t3, the reset subcircuit 1 and the light control subcircuit 4 are configured to work together to turn on the drive subcircuit 2 and conduct the path between the drive subcircuit 2 and the light emitting device (eg, OLED), so that the light emitting device displays a black state picture.

[0144] The embodiment of the present application provides a driving method of a pixel driving circuit, wherein the pixel driving circuit is set in the first reset stage, and the driving subcircuit is turned on after being turned off for a preset period of time, and the light-emitting device displays a black state image. In this way, before each frame of the display image is written, in the first reset stage of the pixel driving circuit, the driving subcircuit is turned off for a preset period of time, and the electrical signal between the pixel driving circuit and the light-emitting device is cut off, so that the signal in the previous frame of the display image is eliminated as much as possible; in addition, after the driving subcircuit is turned on again, the light-emitting device displays a black state image, further offsetting the white image remaining in some areas of the previous frame of the display image, further eliminating the afterimage, solving the afterimage problem, and improving the display effect.

[0145] In the driving method provided by some embodiments of the present application, in S1, in the first time period of the first reset stage, the step of resetting the second node of the pixel driving circuit includes:

[0146] S11. Input a low-level fourth gate control signal to the fourth gate control signal line SC4, input a high-level light emission control signal to the light emission control signal line EM, input a high-level first gate control signal to the first gate control signal line SC1, input a high-level second gate control signal to the second gate control signal line SC2, and input a high-level third gate control signal to the third gate control signal line SC3.

[0147] Combined with Figure 3 and Figure 5 As shown, the fourth gate control signal input to the fourth gate control signal line SC4 controls the fourth transistor T4 to conduct, and transmits the signal input by the first input signal line VINIT to the second node N2 through the fourth transistor T4, completing the reset (which can also be called initialization) of the second node N2; the second node N2 is electrically connected to the gate of the second transistor T2 (driving transistor). It can be understood that resetting the second node N2 is to reset the gate of the second transistor T2.

[0148] In the driving method provided by some embodiments of the present application, in S2, in the second time period, the step of turning off the driving sub-circuit of the pixel driving circuit within a preset time period includes:

[0149] S21. Input a low-level first gate control signal to the first gate control signal line SC1, input a low-level third gate control signal to the third gate control signal line SC3, input a high-level light emission control signal to the light emission control signal line EM, input a high-level second gate control signal to the second gate control signal line SC2, and input a high-level fourth gate control signal to the fourth gate control signal line SC4.

[0150] Combined with Figure 3 and Figure 6 As shown, the first gate control signal input to the first gate control signal line SC1 controls the third transistor T3 to conduct, and connects the second node N2 and the third node N3 together; the third gate control signal input to the third gate control signal line SC3 controls the eighth transistor T8 to conduct, and writes the signal input by the third input signal line Vobs to the first node N1; the voltage of the second node N2 is pulled up during this process, and controls the second transistor T2 to turn off.

[0151] It should be noted that when the eighth transistor T8 is turned on, the voltage of the first node N1 is Vobs. Since the second node N2 and the third node N3 are connected together, the voltages of the second node N2 and the third node N3 are both Vobs + Vth, where Vth is the threshold voltage of the second transistor T2. Since the voltage at the gate position of the second transistor T2 is Vobs + Vth, which is in a high voltage state, the second transistor T2 is turned off in the second time period t2 to erase the brightness of the display screen of the previous frame.

[0152] In the driving method provided in some embodiments of the present application, in the third time period, the step of turning on the driving sub - circuit and conducting the path between the driving sub - circuit and the light - emitting device to make the light - emitting device display a black - state picture includes:

[0153] S31: Input a low - level light - emitting control signal to the light - emitting control signal line EM, input a low - level third gate control signal to the third gate control signal line SC3, input a high - level first gate control signal to the first gate control signal line SC1, input a high - level second gate control signal to the second gate control signal line SC2, and input a high - level fourth gate control signal to the fourth gate control signal line SC4.

[0154] Combined Figure 3 with Figure 7 As shown, the third gate control signal input to the third gate control signal line SC3 controls the seventh transistor T7 and the eighth transistor T8 to turn on, and writes the signal input by the third input signal line Vobs to the first node N1, and writes the signal input by the second input signal line VAR to the fourth node N4; at this time, the threshold voltage Vth of the second transistor T2 is approximately equal to the gate - source voltage Vgs of the second transistor T2; the light - emitting control signal input to the light - emitting control signal line EM controls the fifth transistor T5 and the sixth transistor T6 to turn on, and the path between the first power signal line VSS, the second transistor T2 and the light - emitting device (such as OLED) is conducted, so that the light - emitting device displays a black - state picture.

[0155] It should be noted that the voltage of the first power signal transmitted in the first power signal line VDD is the same as the signal voltage transmitted in the third input signal line Vobs, that is, Vdd = Vobs.

[0156] As Figure 7As shown, during the third time period t3 when the fifth transistor T5 and the eighth transistor T8 are simultaneously turned on, the voltage of the first power signal transmitted in the first power signal line VDD is set to be the same as the voltage of the signal transmitted in the third input signal line Vobs, so that the Vobs signal can be written at the position of the first node N1 during the third time period t3; when the sixth transistor T6 and the seventh transistor T7 are simultaneously turned on, the fourth node N4 and the third node N3 are connected together, and then the third node N3 is also written with the signal input by the second input signal line VAR; in this way, the gate-source voltage Vgs of the second transistor T2 (driving transistor) is Vgs = Vg - Vs = Vobs + Vth - Vobs = Vth; the gate-source voltage Vgs is the voltage during the black screen light-emitting process. At this time, the current flowing through the second transistor T2 (driving transistor) is very small, and the source-drain voltage Vds of the second transistor T2 (driving transistor) is Vds = Vd - Vs = Var - Vdd = Var - Vobs, which is also approximately equal to the voltage in the black screen working state. In this stage, the pixel driving circuit controls the light-emitting device to display a black screen.

[0157] An embodiment of the present application provides an array substrate, including the pixel driving circuit as described above.

[0158] The above array substrate has the same advantages as the pixel driving circuit described above.

[0159] An embodiment of the present application provides a display panel, and the display panel includes the driving substrate as described in any one of the above.

[0160] The above display panel has the same advantages as the array substrate described above.

[0161] Figure 12The brightness change trend curve of the display panel driven by the driving method provided in the embodiments of the present application during the black and white checkerboard screen test is provided. Among them, the curve marked B before is the curve of the brightness change with time measured in the area where the black checker is located when the display panel driven by the pixel driving circuit in the related art restores the display of the reference screen during the black and white checkerboard screen test; the curve marked W before is the curve of the brightness change with time measured in the area where the white checker is located when the display panel driven by the pixel driving circuit in the related art restores the display of the reference screen during the black and white checkerboard screen test; the curve marked B after is the curve of the brightness B% change with time measured in the area where the black checker is located when the display panel driven by the pixel driving circuit in the present application restores the display of the reference screen during the black and white checkerboard screen test; the curve marked W after is the curve of the brightness W% change with time measured in the area where the white checker is located when the display panel driven by the pixel driving circuit in the present application restores the display of the reference screen during the black and white checkerboard screen test; it can be seen that the brightness difference between the black and white areas of the display panel driven by the pixel driving circuit in the present application becomes significantly smaller when restoring the display of the reference screen during the black and white checkerboard screen test. Among them, B% and W% are calculated by the formulas (1) and (2) described above respectively.

[0162] In addition, Figure 13 The afterimage score data of the display panel driven by the driving method provided in the embodiments of the present application during the black and white checkerboard screen test is provided. Among them, the afterimage score is calculated according to the formula (3) described above. The mark before is the afterimage score of the display panel driven by the pixel driving circuit in the related art, and the mark after is the afterimage score of the display panel driven by the pixel driving circuit in the present application. It can be seen from Figure 13 that after the improvement of the driving method of the present application, the afterimage score of the display panel is greatly improved, indicating that the improvement effect of the afterimage problem is very significant.

[0163] As mentioned above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A pixel driving circuit, wherein, Comprising: A driving sub - circuit, a reset sub - circuit, a data writing and reading sub - circuit, and a light - emitting control sub - circuit; The reset sub - circuit is electrically connected to the first node, the second node, the fourth node, the first input signal line, the second input signal line, the third input signal line, the third gate control signal line, and the fourth gate control signal line respectively; the driving sub - circuit is electrically connected to the first node, the second node, the third node, and the first power supply signal line respectively; the data writing and reading sub - circuit is electrically connected to the first node, the second node, the third node, the reset sub - circuit, the data signal line, the first gate control signal line, and the second gate control signal line respectively; the light - emitting control sub - circuit is electrically connected to the first power supply signal line, the first node, the third node, the fourth node, and the light - emitting control signal line respectively; the fourth node is electrically connected to the light - emitting device; Wherein, the pixel driving circuit includes a first reset stage and a second reset stage. In the first reset stage, the driving sub - circuit is configured to be turned on after being turned off for a preset time period, and to make the light - emitting device display a black - state picture.

2. The pixel driving circuit according to claim 1, wherein In the first reset stage, The reset sub - circuit is configured to reset the second node; The reset sub - circuit and the data writing and reading sub - circuit are configured to act together to turn off the driving sub - circuit within the preset time period; The reset sub - circuit and the light - emitting control sub - circuit are configured to act together to turn on the driving sub - circuit and conduct the path between the driving sub - circuit and the light - emitting device, so that the light - emitting device displays a black - state picture.

3. The pixel driving circuit according to claim 2, wherein, In the second reset stage, The reset sub - circuit and the data writing and reading sub - circuit are configured to act together to turn off the driving sub - circuit again; The reset sub - circuit is further configured to reset the first node, the second node, and the third node.

4. The pixel driving circuit according to claim 3, wherein, The driving sub - circuit includes a second transistor and a storage capacitor, the data writing and reading sub - circuit includes a first transistor and a third transistor, the reset sub - circuit includes a fourth transistor, a seventh transistor, and an eighth transistor, and the light - emitting control sub - circuit includes a fifth transistor and a sixth transistor; The gate of the third transistor is electrically connected to the first gate control signal line, the source of the third transistor is electrically connected to the second node, and the drain of the third transistor is electrically connected to the third node; the gate of the fourth transistor is electrically connected to the fourth gate control signal line, the source of the fourth transistor is electrically connected to the first input signal line, and the drain of the fourth transistor is electrically connected to the second node; the gates of the fifth transistor and the sixth transistor are both electrically connected to the light emission control signal line, the source of the fifth transistor is electrically connected to the first power supply signal line, the drain of the fifth transistor is electrically connected to the first node, the source of the sixth transistor is electrically connected to the third node, and the drain of the sixth transistor is electrically connected to the fourth node; the gate of the seventh transistor is electrically connected to the third gate control signal line, the source of the seventh transistor is electrically connected to the second input signal line, and the drain of the seventh transistor is electrically connected to the fourth node; the gate of the eighth transistor is electrically connected to the third gate control signal line, the source of the eighth transistor is electrically connected to the third input signal line, and the drain of the eighth transistor is electrically connected to the first node.

5. The pixel driving circuit according to claim 4, wherein, The first reset stage includes a first time period, a second time period, and a third time period set in sequence; In the first time period, the fourth gate control signal input to the fourth gate control signal line is configured to control the fourth transistor to conduct, and transmit the signal input to the first input signal line through the fourth transistor to the second node, completing the reset of the second node; the second node is electrically connected to the gate of the second transistor.

6. The pixel driving circuit according to claim 5, wherein, In the second time period, the first gate control signal input to the first gate control signal line is configured to control the third transistor to conduct, and connect the second node and the third node together; The third gate control signal input to the third gate control signal line is configured to control the eighth transistor to conduct, and write the signal input to the third input signal line into the first node; The voltage of the second node is configured to be pulled up during this process, and control the second transistor to turn off.

7. The pixel driving circuit according to claim 6, wherein, In the third time period, the third gate control signal input to the third gate control signal line is configured to control the seventh transistor and the eighth transistor to conduct, and write the signal input to the third input signal line into the first node, and write the signal input to the second input signal line into the fourth node; the threshold voltage of the second transistor is approximately equal to the gate-source voltage of the second transistor; The light emission control signal input to the light emission control signal line is configured to control the fifth transistor and the sixth transistor to conduct, and the path between the first power supply signal line, the second transistor, and the light emitting device is configured to conduct, so that the light emitting device displays a black state picture.

8. The pixel driving circuit according to claim 7, wherein The voltage of the first power supply signal transmitted in the first power supply signal line is the same as the voltage of the signal transmitted in the third input signal line.

9. The pixel driving circuit according to claim 7, wherein, The third gate control signal input by the third gate control signal line is configured to control the eighth transistor to turn off after the second time period and before the third time period.

10. The pixel driving circuit according to claim 9, wherein, The third gate control signal is configured to control the conduction time of the eighth transistor in the third time period to be greater than the conduction time of the eighth transistor in the second time period.

11. The pixel driving circuit according to claim 7, wherein, The second reset stage includes a fourth time period and a fifth time period; In the fourth time period, the first gate control signal input by the first gate control signal line is configured to control the third transistor to conduct and connect the second node and the third node together; the third gate control signal input by the third gate control signal line is configured to control the eighth transistor to conduct and write the signal input by the third input signal line to the first node to reset the first node; the voltage of the second node is configured to be pulled up during this process and control the second transistor to turn off; In the fifth time period, the first gate control signal input by the first gate control signal line is configured to control the third transistor to conduct and connect the second node and the third node together; the fourth gate control signal input by the fourth gate control signal line is configured to control the fourth transistor to conduct and transmit the signal input by the first input signal line through the fourth transistor to the second node and the third node to complete the reset of the second node and the third node.

12. The pixel driving circuit according to claim 11, wherein, The fourth gate control signal is configured to have a shorter reset time for the second node in the first reset stage than in the second reset stage.

13. The pixel driving circuit according to claim 12, wherein, In a frame display screen, the light emission control signal input by the light emission control signal line includes a plurality of pulse signals of a first level and a plurality of pulse signals of a second level, the pulse signals of the first level and the pulse signals of the second level are arranged at intervals, and the first level is greater than the second level; Among them, starting from the second reset stage, the pulse width of the first pulse signal of the first level is greater than the pulse widths of the subsequent pulse signals of the first level.

14. The pixel driving circuit according to any one of claims 4 to 13, wherein, The gate of the first transistor is electrically connected to the second gate control signal line, the source of the first transistor is electrically connected to the data signal line, and the drain of the first transistor is electrically connected to the first node; The gate of the second transistor is electrically connected to the second node, the source of the second transistor is electrically connected to the first node, and the drain of the second transistor is electrically connected to the third node; The first electrode of the storage capacitor is electrically connected to the first power supply signal line, and the second electrode of the storage capacitor is electrically connected to the second node.

15. A driving method for a pixel driving circuit, wherein, Applied to drive the pixel driving circuit according to any one of claims 4 to 14, the method includes: In the first time period of the first reset stage, reset the second node of the pixel driving circuit; In the second time period, turn off the driving sub-circuit of the pixel driving circuit within the preset time period; In the third time period, turn on the driving sub-circuit and conduct the path between the driving sub-circuit and the light-emitting device, so that the light-emitting device displays a black-state picture.

16. The driving method according to claim 15, wherein, In the first time period of the first reset stage, the step of resetting the second node of the pixel driving circuit includes: Input a low-level fourth gate control signal to the fourth gate control signal line, input a high-level light-emitting control signal to the light-emitting control signal line, input a high-level first gate control signal to the first gate control signal line, input a high-level second gate control signal to the second gate control signal line, and input a high-level third gate control signal to the third gate control signal line.

17. The driving method according to claim 15, wherein, In the second time period, the step of turning off the driving sub-circuit of the pixel driving circuit within the preset time period includes: Input a low-level first gate control signal to the first gate control signal line, input a low-level third gate control signal to the third gate control signal line, input a high-level light-emitting control signal to the light-emitting control signal line, input a high-level second gate control signal to the second gate control signal line, and input a high-level fourth gate control signal to the fourth gate control signal line.

18. The driving method according to claim 15, wherein In the third time period, the step of turning on the driving sub-circuit and conducting the path between the driving sub-circuit and the light-emitting device, so that the light-emitting device displays a black-state picture includes: Input a low-level light-emitting control signal to the light-emitting control signal line, input a low-level third gate control signal to the third gate control signal line, input a high-level first gate control signal to the first gate control signal line, input a high-level second gate control signal to the second gate control signal line, and input a high-level fourth gate control signal to the fourth gate control signal line.

19. An array substrate, wherein, Including the pixel driving circuit according to any one of claims 1 to 14.

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