Display module and display device

Abstract

The invention discloses a display module and a display device. The display module comprises a display substrate and an integrated circuit, the display substrate comprises a display area and a peripheral area surrounding the display area, and the peripheral area comprises a binding area located on one side of the display area; the display area comprises a plurality of pixel units and is set to display a picture; the integrated circuit is in binding connection with the display substrate in the binding area and is arranged to provide a first control signal for the plurality of pixel units so as to control the brightness of a picture; wherein the display area comprises a normal brightness area and a first brightness area, and the first brightness area is located on the side, away from the integrated circuit, of the normal brightness area; the first control signals received by the plurality of pixel units in the first brightness area are smaller than the first control signals received by the plurality of pixel units in the normal brightness area, so that the picture brightness of the first brightness area is smaller than the picture brightness of the normal brightness area.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of display technologies, and particularly relates to a display module and a display device. Background Art

[0002] An organic light-emitting diode (OLED) is an active light-emitting display device, which has the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, etc. With the continuous development of display technologies, a display device using an OLED as a light-emitting element and controlled by thin film transistors (TFTs) has become the mainstream product in the current display field.

[0003] However, pixels located at the edge of an OLED display device have a problem of flickering. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0005] Embodiments of the present disclosure provide a display module and a display device to solve the problem that pixels located at the edge of an OLED display device flicker.

[0006] In a first aspect, embodiments of the present disclosure provide a display module, including: a display substrate and an integrated circuit. The display substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a bonding area located on one side of the display area. The display area includes a plurality of pixel units configured to display a picture. The integrated circuit is bonded to the display substrate in the bonding area and configured to provide a first control signal to the plurality of pixel units to control the brightness of the picture. Among them, the display area includes a normal brightness area and a first brightness area. The first brightness area is located on the side of the normal brightness area away from the integrated circuit. The plurality of pixel units located in the first brightness area receive a smaller first control signal than the plurality of pixel units located in the normal brightness area, so that the picture brightness of the first brightness area is less than the picture brightness of the normal brightness area.

[0007] In an exemplary embodiment, the plurality of pixel units include a plurality of pixel unit rows arranged along a first direction. The bonding area is located on one side of the display area along a second direction. The first direction and the second direction intersect. The first brightness area includes at least one of the pixel unit rows.

[0008] In an exemplary embodiment, the ratio of the picture brightness value of the first brightness area to the picture brightness value of the normal brightness area is greater than or equal to 0.2 and less than or equal to 0.75.

[0009] In an exemplary embodiment, the display area further includes at least one brightness transition area located between the normal brightness area and the first brightness area. The picture brightness of the brightness transition area is greater than the picture brightness of the first brightness area and less than the picture brightness of the normal brightness area.

[0010] In an exemplary embodiment, the display area includes two or more of the brightness transition areas. In the direction away from the normal brightness area, the picture brightness values of the two or more brightness transition areas gradually decrease.

[0011] In an exemplary embodiment, the brightness transition area includes a second brightness area; the first brightness area includes one row of pixel units; the second brightness area includes one row of pixel units.

[0012] In an exemplary embodiment, the pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel; the first control signals received by the multiple pixel units in the first brightness area are less than the first control signals received by the multiple pixel units in the normal brightness area, including: the first control signal received by the red sub-pixel in the first brightness area is less than the first control signal received by the red sub-pixel in the normal brightness area; the first control signal received by the green sub-pixel in the first brightness area is less than the first control signal received by the green sub-pixel in the normal brightness area; the first control signal received by the blue sub-pixel in the first brightness area is less than the first control signal received by the blue sub-pixel in the normal brightness area.

[0013] In an exemplary embodiment, the first control signal is a voltage signal, or the first control signal is a current signal.

[0014] In an exemplary embodiment, the first control signal is a data voltage.

[0015] In a second aspect, an embodiment of the present disclosure provides a display device including the display module as described above.

[0016] The display substrate provided by the embodiments of the present disclosure divides the display area into a normal brightness area and a first brightness area, and the first brightness area is located on the side of the normal brightness area away from the integrated circuit. By setting the picture brightness of the first brightness area to be less than that of the normal brightness area, the requirement for current of the pixel units located at the edge away from the integrated circuit is reduced. Even in the case where the leakage current of individual pixel units is large, there will be no flashing phenomenon, improving the display effect. It solves the problem that the pixels at the edge of the OLED display device flicker.

[0017] Other advantages of the present disclosure can be realized and obtained through the solutions described in the specification and the drawings.

[0018] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0019] The drawings are used to provide an understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation to the technical solutions of the present disclosure.

[0020] Figure 1 It is a schematic structural diagram of a display device;

[0021] Figure 2 It is a schematic plan view of a display substrate;

[0022] Figure 3 It is a schematic equivalent circuit diagram of a pixel driving circuit;

[0023] Figure 4 It is a schematic structural diagram of a display module in an exemplary embodiment;

[0024] Figure 5 It is a sub-pixel distribution diagram of a display substrate in an exemplary embodiment;

[0025] Figure 6 It is a cross-sectional view of a display substrate in an exemplary embodiment in the display area. Detailed Embodiments

[0026] The present disclosure describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be apparent to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope encompassed by the embodiments described in the present disclosure. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be used in combination with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0027] The present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements already disclosed in the present disclosure can also be combined with any conventional features or elements to form unique inventive solutions defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present disclosure can be implemented alone or in any suitable combination. Therefore, the embodiments are not subject to other limitations except those made in accordance with the appended claims and their equivalents. In addition, various modifications and changes can be made within the scope of the appended claims.

[0028] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the specific order of steps described. As will be understood by those of ordinary skill in the art, other step orders are possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can vary and still remain within the spirit and scope of the embodiments of the present disclosure.

[0029] In the drawings, sometimes for clarity, the sizes of one or more constituent elements, the thickness of layers, or regions are exaggerated. Therefore, one aspect of the present disclosure is not necessarily limited to such dimensions, and the shapes and sizes of one or more components in the drawings do not reflect the true scale. In addition, the drawings schematically show ideal examples, and one aspect of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

[0030] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit the quantity. "Plurality" in the present disclosure means two or more quantities.

[0031] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the components is appropriately changed according to the direction of the described components. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the situation.

[0032] In this specification, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the communication inside two components. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the situation.

[0033] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transmit electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0034] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and therefore, it also includes a state where the angle is more than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and therefore, it also includes a state where the angle is more than 85° and less than 95°.

[0035] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 It is a schematic structural diagram of a display device. As Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting element connected to the circuit unit. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line, the data signal line, and the light-emitting signal line. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light-emitting driver to the light-emitting driver. The data driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3,..., and Dn. For example, the data driver may sample the gray value using a clock signal and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, where n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3,..., and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal, where m may be a natural number. The light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3,..., and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light-emitting driver may sequentially provide emission signals having cut-off level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be configured in the form of a shift register and may generate emission signals in such a way that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal, where o may be a natural number.

[0037] Figure 2 is a schematic plan view of a display substrate. As Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix. The plurality of pixel units P arranged along the first direction X may be referred to as pixel unit rows, and the plurality of pixel units P arranged along the second direction Y may be referred to as pixel unit columns. The first direction X and the second direction Y intersect with each other. For example, the first direction X and the second direction Y may be perpendicular to each other. At least one pixel unit P may include a first sub-pixel P1 that emits light of a first color, a second sub-pixel P2 that emits light of a second color, and a third sub-pixel P3 that emits light of a third color. Each sub-pixel may include a circuit unit and a light-emitting element. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to a scanning signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting element. The light-emitting elements in each sub-pixel are respectively connected to the pixel driving circuit of the corresponding sub-pixel, and the light-emitting elements are configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0038] In an exemplary embodiment, Figure 2 The first pixel row X1 to the sixth pixel row X6, and the first pixel column Y1 to the fourth pixel column Y4 are schematically shown, and the number and arrangement of the pixel units on the display substrate can be set as needed.

[0039] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or triangular formation, etc., and the present disclosure does not limit this here.

[0040] In an exemplary embodiment, the pixel unit may include four sub-pixels. For example, the four sub-pixels may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel (W) that emits white light. Another example is that the four sub-pixels may include a red sub-pixel, a blue sub-pixel, and two green sub-pixels. In an exemplary embodiment, the four sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, square, or diamond-shaped formation, etc., and the present disclosure does not limit this here.

[0041] Figure 3 It is an equivalent circuit schematic diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As Figure 3As shown, the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7) and one storage capacitor C, and the pixel driving circuit is respectively connected to six signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a light emitting signal line E, an initial signal line INIT, and a first power supply line VDD).

[0042] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. Among them, the first node N1 is respectively connected to a first pole of the third transistor T3, a second pole of the fourth transistor T4, and a second pole of the fifth transistor T5, the second node N2 is respectively connected to a second pole of the first transistor, a first pole of the second transistor T2, a gate electrode of the third transistor T3, and a second end of the storage capacitor C, and the third node N3 is respectively connected to a second pole of the second transistor T2, a second pole of the third transistor T3, and a first pole of the sixth transistor T6.

[0043] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power supply line VDD, and a second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the gate electrode of the third transistor T3.

[0044] A gate electrode of the first transistor T1 is connected to the second scan signal line S2, a first pole of the first transistor T1 is connected to the initial signal line INIT, and a second pole of the first transistor is connected to the second node N2. When a conductive level scan signal is applied to the second scan signal line S2, the first transistor T1 transfers an initial voltage to the gate electrode of the third transistor T3 to initialize the charge amount of the gate electrode of the third transistor T3.

[0045] A gate electrode of the second transistor T2 is connected to the first scan signal line S1, a first pole of the second transistor T2 is connected to the second node N2, and a second pole of the second transistor T2 is connected to the third node N3. When a conductive level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the gate electrode of the third transistor T3 to the second pole.

[0046] A gate electrode of the third transistor T3 is connected to the second node N2, that is, the gate electrode of the third transistor T3 is connected to the second end of the storage capacitor C, a first pole of the third transistor T3 is connected to the first node N1, and a second pole of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines the amount of a driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its gate electrode and the first pole.

[0047] The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1. The first pole of the fourth transistor T4 is connected to the data signal line D, and the second pole of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, a scan transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D into the pixel driving circuit.

[0048] The gate electrode of the fifth transistor T5 is connected to the light-emitting signal line E. The first pole of the fifth transistor T5 is connected to the first power supply line VDD, and the second pole of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line E. The first pole of the sixth transistor T6 is connected to the third node N3, and the second pole of the sixth transistor T6 is connected to the first electrode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting element EL to emit light by forming a drive current path between the first power supply line VDD and the second power supply line VSS.

[0049] The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2. The first pole of the seventh transistor T7 is connected to the initial signal line INIT, and the second pole of the seventh transistor T7 is connected to the first electrode of the light-emitting element EL. When a conduction-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transfers an initial voltage to the first electrode of the light-emitting element EL to initialize the electric charge accumulated in the first electrode of the light-emitting element EL or to release the electric charge accumulated in the first electrode of the light-emitting element EL.

[0050] In an exemplary embodiment, the light-emitting element EL can be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or can be a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. In this embodiment, the first electrode can be an anode, and the second electrode can be a cathode. The present disclosure does not limit this.

[0051] In an exemplary embodiment, the second electrode of the light-emitting element EL is connected to the second power supply line VSS, and the signal of the second power supply line VSS is a continuously provided low-level signal, and the signal of the first power supply line VDD is a continuously provided high-level signal.

[0052] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0053] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may employ low-temperature polycrystalline silicon thin-film transistors, or may employ oxide thin-film transistors, or may employ low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polycrystalline silicon thin-film transistor uses low-temperature poly-silicon (LTPS for short), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). The low-temperature polycrystalline silicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature polycrystalline silicon thin-film transistor and the oxide thin-film transistor on a display substrate to form a low-temperature polycrystalline oxide (LTPO for short) display substrate can utilize the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve the display quality.

[0054] Taking the example that all 7 transistors are P-type transistors, the working process of the pixel driving circuit may include:

[0055] In the first stage A1, called the reset stage, the signal of the second scan signal line S2 is a low-level signal, and the signals of the first scan signal line S1 and the light-emitting signal line E are high-level signals. The low-level signal of the second scan signal line S2 turns on the first transistor T1 and the seventh transistor T7. The conduction of the first transistor T1 provides the initial voltage of the initial signal line INIT to the second node N2, initializes the storage capacitor C, and clears the original data voltage in the storage capacitor. The conduction of the seventh transistor T7 provides the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializes (resets) the first electrode of the OLED, and clears the pre-stored voltage inside it, completing the initialization. The high-level signals of the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The OLED does not emit light in this stage.

[0056] The second stage A2, called the data writing stage or the threshold compensation stage, has the signal of the first scan signal line S1 as a low-level signal, the signals of the second scan signal line S2 and the light-emitting signal line E as high-level signals, and the data signal line D outputs a data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scan signal line S1 being a low-level signal turns on the second transistor T2 and the fourth transistor T4. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the second end (the second node N2) of the storage capacitor C is Vd - |Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The signal of the second scan signal line S2 being a high-level signal turns off the first transistor T1 and the seventh transistor T7. The signal of the light-emitting signal line E being a high-level signal turns off the fifth transistor T5 and the sixth transistor T6.

[0057] The third stage A3, called the light-emitting stage, has the signal of the light-emitting signal line E as a low-level signal, and the signals of the first scan signal line S1 and the second scan signal line S2 as high-level signals. The signal of the light-emitting signal line E being a low-level signal turns on the fifth transistor T5 and the sixth transistor T6. Since the voltage Vd - |Vth| is written at the second end of the storage capacitor C in the previous stage, the third transistor T3 remains in the on state in this stage. The power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the OLED to emit light.

[0058] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first pole. Since the voltage of the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0059] I = K * (Vgs - Vth) 2 = K * [(Vdd - Vd + |Vth|) - Vth] 2 = K * (Vdd - Vd) 2

[0060] Wherein, I is the driving current flowing through the third transistor T3, which is also the driving current for driving the OLED. K is a constant, Vgs is the voltage difference between the gate electrode and the first pole of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0061] The OLED display technology is applied to mobile terminals in various scenarios, such as mobile phones, tablet computers, wearable products, and in-vehicle displays. Users have higher and higher requirements for characteristics such as the brightness, contrast ratio, viewing angle display effect, power consumption, and screen-to-body ratio of display products. The OLED display device includes a display substrate and an integrated circuit. The integrated circuit can control multiple pixel units on the display substrate to emit light, so that the picture displayed on the display substrate presents a certain brightness level. However, the inventors of this application have found through research that during the display process of the display substrate, there are abnormalities in some individual pixel units in several pixel unit rows on the side far from the integrated circuit, causing the entire picture to have a "marquee" - like flicker on the edge far from the integrated circuit, which affects the user experience. Further research has found that due to the relatively large leakage current in the display units with display abnormalities, under the action of the same current, the light - emitting efficiency of these pixel units is different from that of other normal pixel units, making the human eye observe the flicker. It is very difficult to correct the display abnormalities of individual pixel units on the display substrate by adjusting the parameters of the entire display picture, increasing the processing difficulty.

[0062] Embodiments of the present disclosure provide a display module, including a display substrate and an integrated circuit. The display substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a bonding area located on one side of the display area.

[0063] The display area includes multiple pixel units configured to display a picture. The integrated circuit is bonded and connected to the display substrate in the bonding area and is configured to provide a first control signal to the multiple pixel units to control the brightness of the picture. Wherein,

[0064] The display area includes a normal brightness area and a first brightness area. The first brightness area is located on the side of the normal brightness area far from the integrated circuit. The first control signal received by the multiple pixel units located in the first brightness area is less than the first control signal received by the multiple pixel units located in the normal brightness area, so that the picture brightness of the first brightness area is less than the picture brightness of the normal brightness area.

[0065] The display module provided by the embodiment of the present disclosure divides the display area into a normal brightness area and a first brightness area, and the first brightness area is located on the side of the normal brightness area away from the integrated circuit. By setting the picture brightness of the first brightness area to be less than that of the normal brightness area, the requirement for current of the pixel units located at the edge away from the integrated circuit is reduced. Even in the case where the leakage current of individual pixel units is large, there will be no flickering phenomenon, and the display effect is improved.

[0066] Figure 4 It is a schematic structural diagram of a display module in an exemplary embodiment. As Figure 4 shown, the display module includes a display substrate 1 and an integrated circuit 2. The display substrate 1 includes a display area 100 and a peripheral area surrounding the display area 100. The display area 100 at least includes a plurality of pixel units P arranged regularly. The plurality of pixel units P include a pixel unit rows and b pixel unit columns. The first pixel unit row X1 is located on the side of the a-th pixel unit row Xa away from the integrated circuit 2. Both a and b are positive integers. The plurality of pixel units P are configured to display dynamic pictures or still images, and the display area 100 can be referred to as an active area (AA). The peripheral area includes: a first peripheral area 200 located on one side of the display area 100 along the second direction Y, and a second peripheral area 300 located outside the display area 100 and away from one side of the first peripheral area 200. The first peripheral area 200 and the second peripheral area 300 are connected to surround the display area 100. The first peripheral area 200 can also be referred to as a bonding area. The integrated circuit 2 is bonded and connected to the display substrate 1 in the bonding area. The integrated circuit 2 can be a driving integrated circuit (DIC). The integrated circuit 2 can be connected to each pixel unit through a plurality of signal transmission lines K to transmit a first control signal to each pixel unit P, so that the display picture presents a certain gray-scale brightness. The signal transmission lines K can extend along the second direction Y and be connected to each pixel unit column. The display area 100 includes a normal brightness area Q0 and a first brightness area Q1. The first brightness area Q1 is located on the side of the normal brightness area Q0 away from the integrated circuit 2. The first control signal received by the plurality of pixel units P located in the first brightness area Q1 is less than the first control signal received by the plurality of pixel units located in the normal brightness area Q0, so that the picture brightness of the first brightness area Q1 is less than that of the normal brightness area Q0. Since the pixel units with abnormal display generally are located in several pixel unit rows of the display area 100 away from the integrated circuit 2. For example, they may be located in the first pixel unit row X1 and the second pixel unit row X2. The areas where these pixel units P with abnormal display are located can be divided into the first brightness area Q1. By setting the picture brightness of the first brightness area Q1 to be less than that of the remaining normal brightness area Q0 on the display area 100, the requirement for current of the pixel units P in the first brightness area Q1 can be reduced, thereby reducing the picture flicker caused by the leakage current in these pixel units and improving the display effect.

[0067] In an exemplary embodiment, a pixel unit P may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. A signal transmission line K may include a plurality of signal transmission sub-lines (not shown in the figure). Each signal transmission sub-line may be connected to sub-pixels of the same color within the same pixel unit column to achieve control of sub-pixels of different colors.

[0068] Figure 5 It is a sub-pixel distribution diagram of a display substrate in an exemplary embodiment. As Figure 5 shown, the display substrate may include a plurality of red sub-pixels R, a plurality of green sub-pixels G, and a plurality of blue sub-pixels B arranged in an array. Among the plurality of green sub-pixels G, in the first direction X, the plurality of red sub-pixels R and the plurality of blue sub-pixels B are arranged alternately. In the second direction Y, the plurality of red sub-pixels R and the plurality of blue sub-pixels B are arranged alternately. The red sub-pixel R and the blue sub-pixel B may be quadrilateral, such as a rhombus. The plurality of green sub-pixels G may be strip-shaped and may include a plurality of first green sub-pixels G1 and a plurality of second green sub-pixels G2. The extending direction of the plurality of first green sub-pixels G1 may intersect the extending direction of the plurality of second green sub-pixels G2. For example, the extending directions of the first green sub-pixel G1 and the second green sub-pixel G2 may be respectively parallel to two adjacent sides of the rhombus of the blue sub-pixel B. In the first direction X, the plurality of first green sub-pixels G1 and the plurality of second green sub-pixels G2 are arranged alternately. In the second direction Y, the plurality of first green sub-pixels G1 and the plurality of second green sub-pixels G2 are arranged alternately. Figure 5 The dashed box in shows a pixel unit P, which includes a red sub-pixel R, a blue sub-pixel B, a first green sub-pixel G1, and a second green sub-pixel G2. Adjacent pixel units P may share a red sub-pixel R and a blue sub-pixel B. In other embodiments, a pixel unit P may include different numbers of sub-pixels and sub-pixels with other color combinations.

[0069] In an exemplary embodiment, with continued reference to Figure 4 , the first brightness region Q1 includes at least one pixel unit row. Figure 4 Taking the first brightness region Q1 including the first pixel unit row X1 as an example for illustration in, in other embodiments, the first brightness region Q1 may include some pixel units in a pixel unit row and does not necessarily include a complete pixel unit row. The shape, range, and the pixel units included in the first brightness region Q1 may be set as needed.

[0070] In an exemplary embodiment, the ratio between the picture brightness value of the first brightness area Q1 and the picture brightness value of the normal brightness area Q0 may be greater than or equal to 0.2 and less than or equal to 0.75. For example, the ratio between the picture brightness value of the first brightness area Q1 and the picture brightness value of the normal brightness area Q0 may be approximately 0.25. Taking specific gray-scale values as an example, when the gray-scale value of the normal brightness area Q0 is 255, the gray-scale value of the first brightness area Q1 may be approximately 64.

[0071] In an exemplary embodiment, the display area 100 further includes at least one brightness transition area. The at least one brightness transition area is located between the normal brightness area Q0 and the first brightness area Q1. The picture brightness of the brightness transition area is greater than the picture brightness of the first brightness area Q1 and less than the picture brightness of the normal brightness area Q0, so that the picture brightness of the display area 100 gradually decreases along the direction from the normal brightness area Q0 to the first brightness area Q1.

[0072] In an exemplary embodiment, the ratio between the picture brightness value of the brightness transition area and the picture brightness value of the normal brightness area Q0 may be greater than or equal to 0.3 and less than or equal to 1. For example, the ratio between the picture brightness value of the brightness transition area and the picture brightness value of the normal brightness area Q0 may be approximately 0.5. Taking specific gray-scale values as an example, when the gray-scale value of the normal brightness area Q0 is 255, the gray-scale value of the brightness transition area may be approximately 128.

[0073] In an exemplary embodiment, as shown in Figure 4 shown, Figure 4 FIG. illustrates the case where only one brightness transition area is provided. The brightness transition area includes a second brightness area Q2, and the case where the second brightness area Q2 includes a second pixel unit row X2 is taken as an example for illustration. In other embodiments, the display area 100 may include more than two brightness transition areas, and the picture brightness of the plurality of brightness transition areas may gradually increase along the direction away from the normal brightness area Q0 to achieve a smooth transition of the picture brightness. The brightness transition area may include some pixel units in a pixel unit row, and does not necessarily include a complete pixel unit row. The shape, range, and the pixel unit situation included in the brightness transition area can be set as needed.

[0074] In an exemplary embodiment, the ratio between the picture brightness value of the first brightness area Q1 and the picture brightness value of the second brightness area Q2 may be approximately 0.5, and the ratio between the picture brightness value of the second brightness area Q2 and the picture brightness value of the normal brightness area Q0 may be approximately 0.5. Taking specific gray-scale values as an example, when the gray-scale value of the normal brightness area Q0 is 255, the gray-scale value of the second brightness area Q2 may be approximately 128, and the gray-scale value of the first brightness area Q1 may be approximately 64.

[0075] In an exemplary embodiment, the display area 100 may include multiple brightness transition zones, and the gray-scale values of each brightness transition zone can be set as needed. Table 1 below records the gray-scale value settings of different brightness zones when seven brightness transition zones are set between the first brightness zone Q1 and the normal brightness zone Q0. These seven brightness transition zones are the second brightness zone Q2 to the eighth brightness zone Q8 respectively. The gray-scale value R represents the gray-scale value of red in different brightness zones, the gray-scale value G represents the gray-scale value of green in different brightness zones, and the gray-scale value B represents the gray-scale value of blue in different brightness zones.

[0076] Table 1

[0077]

[0078] As shown in Table 1, the picture gray-scale values of the seventh brightness zone Q7 and the eighth brightness zone Q8 are set to be the same as those of the normal brightness zone. The number of brightness transition zones and the gray-scale values within the brightness transition zones can be set as needed.

[0079] In an exemplary embodiment, the first control signal can be a voltage signal, or the first control signal can be a current signal.

[0080] In an exemplary embodiment, when the first control signal is a voltage signal, the first control signal can be a data voltage. The integrated circuit 2 can output the corresponding data voltage to each sub-pixel after Gamma correction of the digital gray-scale value, so that the picture presents the brightness corresponding to the gray-scale. By modifying the Gamma Look-Up Table (LUT) of the integrated circuit 2, different degrees of correction can be performed on the sub-pixels in the first brightness zone Q1 and the normal brightness zone Q0, so that the picture brightness of the first brightness zone Q1 is less than the picture brightness of the normal brightness zone Q0.

[0081] Figure 6 It is a cross-sectional view of the display substrate in the display area in an exemplary embodiment, showing the structure of three sub-pixels of the display substrate. As Figure 6 shown, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 12 provided on the substrate 10, a light-emitting device 13 provided on the side of the driving circuit layer 12 away from the substrate 10, and a packaging layer 14 provided on the side of the light-emitting device 13 away from the substrate 10. In some possible implementation manners, the display substrate may include other film layers, such as spacer posts, touch layers, etc., and may also include an upper glass on the side of the packaging layer 14 away from the substrate 10. The present disclosure does not make limitations here.

[0082] In some exemplary embodiments, the substrate 10 can be a flexible substrate or a rigid substrate. The flexible substrate can include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0083] In some exemplary embodiments, the driving circuit layer 12 of each sub-pixel can include a plurality of transistors and storage capacitors constituting the pixel driving circuit, Figure 6 which is schematically illustrated by taking one driving transistor and one storage capacitor included in each sub-pixel as an example. In some possible implementation manners, the driving circuit layer 12 of each sub-pixel can include: a first insulating layer 21 disposed on the substrate; an active layer disposed on the first insulating layer 21; a second insulating layer 22 covering the active layer; a gate electrode and a first capacitor electrode disposed on the second insulating layer 202; a third insulating layer 23 covering the gate electrode and the first capacitor electrode; a second capacitor electrode disposed on the third insulating layer 23; a fourth insulating layer 24 covering the second capacitor electrode. Through holes are formed in the second insulating layer 22, the third insulating layer 23, and the fourth insulating layer 24, and the through holes expose the active layer; a source electrode and a drain electrode are disposed on the fourth insulating layer 24, and the source electrode and the drain electrode are respectively connected to the active layer through the through holes; a planarization layer 25 covering the foregoing structure, and a through hole is formed in the planarization layer 25, and the through hole exposes the drain electrode. The active layer, the gate electrode, the source electrode, and the drain electrode form a driving transistor 231, and the first capacitor electrode and the second capacitor electrode form a storage capacitor 232. In an exemplary embodiment, the foregoing insulating layer can be formed of an organic material or an inorganic material, and a single insulating layer can be a single-layer structure or a multi-layer composite structure, and the present disclosure does not limit this.

[0084] In some exemplary embodiments, the light-emitting device 13 can include an anode 31, a pixel definition layer 32, a light-emitting functional layer 33, and a cathode 34. The anode 31 is disposed on the planarization layer 25 and is connected to the drain electrode of the driving transistor 231 through a through hole formed in the planarization layer 25; the pixel definition layer 32 is disposed on the anode 31 and the planarization layer 25, and a pixel opening is provided on the pixel definition layer 32, and the pixel opening exposes the anode 31; the light-emitting functional layer 33 is at least partially disposed in the pixel opening, and the light-emitting functional layer 33 is connected to the anode 31; the cathode 34 is disposed on the light-emitting functional layer 33, and the cathode 34 is connected to the light-emitting functional layer 33; the light-emitting functional layer 33 emits corresponding color light under the drive of the anode 31 and the cathode 34.

[0085] In an exemplary embodiment, the material of the anode 31 may be a transparent conductive material, which may be formed by a single material or a stack of multiple materials. For example, it may be a three-layer composite structure of ITO / Ag / ITO, and the present disclosure is not limited thereto.

[0086] In some exemplary embodiments, the encapsulation layer 14 may include a stacked first encapsulation layer 41, second encapsulation layer 42, and third encapsulation layer 43. The first encapsulation layer 41 and the third encapsulation layer 43 may be made of inorganic materials, which can prevent the penetration of moisture, oxygen, etc. The second encapsulation layer 42 may be made of an organic material, which can improve the flatness of the encapsulation layer 14. The second encapsulation layer 42 is disposed between the first encapsulation layer 41 and the third encapsulation layer 43, which can ensure that external water vapor cannot enter the light-emitting device 13. In an exemplary embodiment, the encapsulation layer 14 may cover the display area AA.

[0087] In some exemplary embodiments, the light-emitting functional layer of the light-emitting device may include a light-emitting layer (EML, Emitting Layer), and one or more of a hole injection layer (HIL, Hole Injection Layer), hole transport layer (HTL, Hole Transport Layer), hole blocking layer (HBL, Hole Block Layer), electron blocking layer (EBL, Electron Block Layer), electron injection layer (EIL, Electron Injection Layer), and electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the anode and the cathode, light is emitted according to the required gray scale by utilizing the light-emitting characteristics of the organic material.

[0088] The embodiments of the present disclosure further provide a display device, including the display module described in any of the above embodiments. The display device may be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function, and the embodiments of the present disclosure are not limited thereto.

[0089] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A display module, comprising: A display substrate and an integrated circuit, the display substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a bonding area located on one side of the display area; The display area includes a plurality of pixel units configured to display an image; the integrated circuit is bonded to the display substrate in the bonding area and is configured to provide a first control signal to the plurality of pixel units to control the brightness of the image; wherein, The display area includes a normal brightness area and a first brightness area, the first brightness area being located on the side of the normal brightness area away from the integrated circuit; the first control signal received by the plurality of pixel units located in the first brightness area is less than the first control signal received by the plurality of pixel units located in the normal brightness area, such that the image brightness of the first brightness area is less than the image brightness of the normal brightness area.

2. The display module according to claim 1, wherein The plurality of pixel units includes a plurality of pixel unit rows arranged in a first direction; the bonding area is located on one side of the display area in a second direction; the first direction and the second direction intersect; The first brightness area includes at least one of the pixel unit rows.

3. The display module according to claim 1, wherein The ratio between the image brightness value of the first brightness area and the image brightness value of the normal brightness area is greater than or equal to 0.2 and less than or equal to 0.

75.

4. The display module according to claim 2, wherein, The display area further includes at least one brightness transition area located between the normal brightness area and the first brightness area, the image brightness of the brightness transition area being greater than the image brightness of the first brightness area and less than the image brightness of the normal brightness area.

5. The display module according to claim 4, wherein The display area includes two or more of the brightness transition areas, and in the direction away from the normal brightness area, the image brightness values of the two or more brightness transition areas gradually decrease.

6. The display module according to claim 4, wherein The brightness transition area includes a second brightness area; The first brightness area includes one of the pixel unit rows; the second brightness area includes one of the pixel unit rows.

7. The display module according to claim 1, wherein The pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel; the first control signal received by the plurality of pixel units located in the first brightness area being less than the first control signal received by the plurality of pixel units located in the normal brightness area includes: The first control signal received by the red sub-pixels located in the first brightness area is less than the first control signal received by the red sub-pixels located in the normal brightness area; the first control signal received by the green sub-pixels located in the first brightness area is less than the first control signal received by the green sub-pixels located in the normal brightness area; the first control signal received by the blue sub-pixels located in the first brightness area is less than the first control signal received by the blue sub-pixels located in the normal brightness area.

8. The display module according to claim 7, wherein The first control signal is a voltage signal, or the first control signal is a current signal.

9. The display module according to claim 8, wherein The first control signal is a data voltage.

10. A display device, comprising a display module according to any one of claims 1 to 9.

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