Display panel and display device

Abstract

The invention provides a display panel and a display device, the display panel divides a second data line to a (2a * n + 1) th data line in (2a * n + 2) data lines into n data line groups, and the ith data line in each data line group is electrically connected with the (i + a) th data line in the data line group so as to share one data channel, the first type of sub-pixels in the yth column of sub-pixels is electrically connected with the yth data line, and the second type of sub-pixels in the yth column of sub-pixels is electrically connected with the (y + 1) th data line, so that each column of sub-pixels is controlled by two data lines, and in the display period of one frame of picture, the number of the sub-pixels in each column of sub-pixels is increased. Part of sub-pixels in each column of sub-pixels can receive data voltage of positive polarity through one data line, and the other part of sub-pixels can receive data voltage of negative polarity through the other data line, so that the polarity of each sub-pixel is opposite to that of the adjacent sub-pixels, and the problem of vertical stripes can be eliminated.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] A display panel with a DRD (Dual Rate Driving) architecture can reduce the number of COFs (Chip On Flex). Specifically, in a display panel with a DRD architecture, one data line controls two columns of sub-pixels, so that the number of COFs can be halved. However, the display panel with this architecture usually uses the column inversion driving method to achieve data inversion, which is prone to vertical stripes and affects the image quality. Summary of the Invention

[0003] In view of this, the main purpose of this application is to provide a display panel and a display device, aiming to solve the problem that the existing display panel with a DRD architecture is prone to vertical stripes.

[0004] To achieve the above object, a first aspect of the present application provides a display panel, the display panel includes 2m scan lines, 2a×n + 2 data lines, and a plurality of sub-pixels. The 2m scan lines are arranged in the column direction; the 2a×n + 2 data lines are arranged in the row direction; wherein, 2 ≤ a, 1 ≤ n, the second data line to the 2a×n + 1st data line among the 2a×n + 2 data lines are divided into n data line groups, each data line group includes 2a data lines arranged in sequence, the i-th data line in each data line group is electrically connected to the i + a-th data line in the same data line group, wherein, 1 ≤ i ≤ a; the plurality of sub-pixels are arranged in an m-row, 2a×n + 1-column array; wherein, the sub-pixels in the x-th row are located between the 2x - 1st scan line and the 2x-th scan line among the 2m scan lines, the sub-pixels in the x-th row include n sub-pixel groups, each sub-pixel group includes 2a sub-pixels arranged in sequence in the row direction, the first a sub-pixels in each sub-pixel group in the x-th row of sub-pixels are electrically connected to the 2x - 1st scan line among the 2m scan lines, and the last a sub-pixels in each sub-pixel group in the x-th row of sub-pixels are electrically connected to the 2x-th scan line among the 2m scan lines; the sub-pixels in the y-th column are located between the y-th data line and the y + 1st data line among the 2a×n + 2 data lines, the first type of sub-pixels in the y-th column of sub-pixels are electrically connected to the y-th data line among the 2a×n + 2 data lines, and the second type of sub-pixels in the y-th column of sub-pixels are electrically connected to the y + 1st data line among the 2a×n + 2 data lines; wherein, 1 ≤ x ≤ m, 1 ≤ y ≤ 2a×n + 1, the first type of sub-pixels are the sub-pixels located in the odd rows, the second type of sub-pixels are the sub-pixels located in the even rows, or, the first type of sub-pixels are the sub-pixels located in the even rows, and the second type of sub-pixels are the sub-pixels located in the odd rows; wherein, during the display period of one frame of the picture, the polarity of the data voltage transmitted by each data line among the 2a×n + 2 data lines remains the corresponding polarity, and the polarities of the data voltages transmitted by any two adjacent data lines among the 2a×n + 2 data lines are opposite, so that the polarity of any sub-pixel among the plurality of sub-pixels is opposite to the polarity of the adjacent sub-pixels.

[0005] The display panel provided by the present application divides the 2nd to the (2a×n + 1)th data lines among the 2a×n + 2 data lines into n data line groups. The i-th data line in each data line group is electrically connected to the (i + a)-th data line in the same data line group to share a data channel. The first type of sub-pixels in the y-th column of sub-pixels is electrically connected to the y-th data line among the 2a×n + 2 data lines, and the second type of sub-pixels in the y-th column of sub-pixels is electrically connected to the (y + 1)-th data line among the 2a×n + 2 data lines, so that each column of sub-pixels is controlled by two data lines. Thus, during the display period of one frame of the picture, some sub-pixels in each column of sub-pixels can receive a positive-polarity data voltage through one data line, and some other sub-pixels can receive a negative-polarity data voltage through the other data line, making the polarity of each sub-pixel opposite to that of the adjacent sub-pixels, thereby realizing dot inversion driving, which can eliminate the vertical stripe problem of the existing DRD architecture display panel and improve the display effect.

[0006] In some embodiments, the polarity of the data voltage transmitted by each of the 2a×n + 2 data lines during the display period of the current frame of the picture is opposite to the polarity of the data voltage transmitted by the same data line during the display period of the previous frame of the picture.

[0007] In some embodiments, a = 6, the first type of sub-pixels are the sub-pixels located in the even rows, and the second type of sub-pixels are the sub-pixels located in the odd rows; among the sub-pixels in the same odd row, the sub-pixels located in the (1 + 2a×j)-th column to the sub-pixels located in the 2a×(j + 1)-th column belong to the same sub-pixel group, and among the sub-pixels in the same even row, the sub-pixels located in the (2 + 2a×j)-th column to the sub-pixels located in the 2a×(j + 1)+1-th column belong to the same sub-pixel group; where 0 ≤ j ≤ n.

[0008] In some embodiments, a = 6, the first type of sub-pixels are the sub-pixels located in the odd rows, and the second type of sub-pixels are the sub-pixels located in the even rows; among the sub-pixels in the same odd row, the sub-pixels located in the (2 + 2a×j)-th column to the sub-pixels located in the 2a×(j + 1)+1-th column belong to the same sub-pixel group, and among the sub-pixels in the same even row, the sub-pixels located in the (1 + 2a×j)-th column to the sub-pixels located in the 2a×(j + 1)-th column belong to the same sub-pixel group; where 0 ≤ j ≤ n.

[0009] In some embodiments, all the sub-pixels in the same column of sub-pixels have the same color.

[0010] In some embodiments, the sub-pixels in each row are arranged in a cyclic order of first color sub-pixels, second color sub-pixels, and third color sub-pixels in the row direction.

[0011] In some embodiments, in each data line group, the i-th data line includes opposite first and second ends and a cross-connection point located between the first end and the second end. The first end of the i-th data line is electrically connected to the source driver circuit for receiving the data voltage output by the source driver circuit. The (i + a)-th data line is electrically connected to the cross-connection point on the i-th data line through a jumper wire, where the jumper wire extends along the row direction.

[0012] In some embodiments, in each data line group, the i-th data line includes a common segment between the first end and the cross-connection point and a branch segment between the cross-connection point and the second end, and the cross-sectional area of the (i + a)-th data line is greater than the cross-sectional area of the branch segment of the i-th data line.

[0013] In some embodiments, in each data line group, the difference between the sum of the impedance value of the (i + a)-th data line and the impedance value of the jumper wire electrically connected to the (i + a)-th data line and the impedance value of the branch segment of the i-th data line is less than or equal to a preset impedance threshold.

[0014] A second aspect of the present application further provides a display device, which includes a gate driver circuit, a source driver circuit, and the display panel described in the first aspect above. The gate driver circuit is electrically connected to 2m scan lines in the display panel and is configured to output corresponding scan signals to the 2m scan lines. The source driver circuit is electrically connected to 2a × n + 2 data lines in the display panel and is configured to output corresponding data voltages to the 2a × n + 2 data lines.

[0015] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. Description of the Drawings

[0016] Figure 1 It is a schematic diagram of an exemplary display panel;

[0017] Figure 2 It is a schematic diagram of a display panel provided by an embodiment of the present application;

[0018] Figure 3 For Figure 2 It is a conversion schematic diagram of the image data when the shown display panel is displaying;

[0019] Figure 4 It is a schematic diagram of another display panel provided by an embodiment of the present application.

[0020] The description of the reference numerals is as follows:

[0021] Display device 1

[0022] Display panels 100, 100'

[0023] Source driver circuit 200

[0024] Gate driver circuit 300

[0025] Timing controller 400

[0026] Scan lines G, G1 - G8

[0027] Data lines S, S1 - S26

[0028] Sub - pixel P

[0029] Data channels H1 - H14

[0030] First end 11

[0031] Second end 12

[0032] Cross - connection point 13

[0033] Common segment 101

[0034] Branch segment 102

[0035] Cross - connecting wire 20

[0036] The following specific embodiments will further illustrate the present application in conjunction with the above - mentioned drawings. Specific embodiments

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0038] In addition, the terms "first", "second", etc. in the description of the present invention are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non - exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0039] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0040] See also Figure 1 , Figure 1 1 is a schematic diagram of an exemplary display panel. In the related art, the display panel 100 ′ of the DRD architecture usually uses a column inversion driving method to achieve data inversion, which is prone to vertical stripes and affects the image quality.

[0041] Specifically, the display panel 100' of the DRD architecture may include a plurality of scan lines G, a plurality of data lines S, and a plurality of sub-pixels P, wherein the plurality of scan lines G extend in the row direction and are arranged at intervals in the column direction. For the convenience of distinction, the first scan line is identified as G1, the second scan line is identified as G2, and the identification of other scan lines is similar. The plurality of data lines S extend in the column direction and are arranged at intervals in the row direction. For the convenience of distinction, the first data line is identified as S1, the second data line is identified as S2, and the identification of other data lines is similar.

[0042] The plurality of sub-pixels P are arranged in a multi-row and multi-column array. The plurality of sub-pixels P may include red sub-pixels, green sub-pixels, and blue sub-pixels. The number of the plurality of scan lines G is twice the number of rows of the plurality of sub-pixels P. Each row of sub-pixels P is located between two corresponding scan lines G and is scanned by the two corresponding scan lines G. Figure 1 As shown, the first scan line G1 is used to scan the sub-pixels P located in odd columns in the first row of sub-pixels P, the second scan line G2 is used to scan the sub-pixels P located in even columns in the first row of sub-pixels P, and so on. The number of the plurality of data lines S is half the number of columns of the plurality of sub-pixels P, and the data lines S in each row are located between two corresponding columns of sub-pixels P, and are used to output data voltages to the two corresponding columns of sub-pixels P. In this way, two adjacent columns of sub-pixels in the display panel 100' share one data channel of the COF, and the number of COFs can be halved. For example Figure 1 As shown, the first data line S1 is located between the first column of sub-pixels P and the second column of sub-pixels P, and is used to output corresponding data voltages to the first column of sub-pixels P and the second column of sub-pixels P, that is, the first column of sub-pixels P and the second column of sub-pixels P share a data channel.

[0043] In the related art, a column inversion driving method is usually used to drive the display panel 100' of the DRD architecture. The column inversion method refers to inverting the polarity of the data voltage every specified number of sub-pixel columns. Figure 1As shown, for the column inversion driving method, during the display period of displaying the same frame of the screen, the polarities of the data voltages on each data line are always of the same polarity (positive polarity or negative polarity). Among them, the symbol of the positive polarity is "+", and the symbol of the negative polarity is "-". As Figure 1 shown, the polarities of the data voltages on the multiple data lines S are alternately positive and negative. For example, the polarity of the data voltage output by the first data line S1 is positive polarity, the polarity of the data voltage output by the second data line S2 is negative polarity, and so on for the data voltages output by other data lines. Therefore, when displaying the same frame of the screen, the sub-pixel columns arranged in the row direction are filled with data voltages with a cycle of "positive, positive, negative, negative". Thus, when displaying the same frame of the screen, when the common voltage VCOM of the display panel 100' shifts, vertical stripes are likely to appear. For example, when the common voltage VCOM shifts in the positive direction, the brightness of the sub-pixel columns with positive polarity will be darker, and the brightness of the sub-pixel columns with negative polarity will be brighter. In this way, when the user observes the Figure 1 display panel 100' as shown, vertical stripes of bright and dark intervals will be seen.

[0044] In view of this, please refer to Figure 2 , Figure 2 which is a schematic diagram of a display panel provided by an embodiment of the present application. The present application provides a display panel 100, and the display panel 100 includes 2m scan lines G, 2a×n + 2 data lines S, and multiple sub-pixels P.

[0045] Among them, the 2m scan lines G extend in the row direction and are arranged at intervals in the column direction.

[0046] The 2a×n + 2 data lines S extend in the column direction and are arranged at intervals in the row direction. Among them, 2≤a, 1≤n, and the second data line to the 2a×n + 1th data line among the 2a×n + 2 data lines S are divided into n data line groups. Each data line group includes 2a data lines S arranged in sequence. The i-th data line in each data line group is electrically connected to the (i + a)-th data line in the same data line group, where 1≤i≤a.

[0047] The multiple sub-pixels P are arranged in an array of m rows and 2a×n + 1 columns. Among them, the sub-pixels P in the x-th row are located between the (2x - 1)-th scanning line and the 2x-th scanning line among the 2m scanning lines G. The sub-pixels P in the x-th row include n sub-pixel groups, and each sub-pixel group includes 2a sub-pixels P arranged in sequence along the row direction. The first a sub-pixels P in each sub-pixel group in the x-th row of sub-pixels P are electrically connected to the (2x - 1)-th scanning line among the 2m scanning lines G, and the last a sub-pixels P in each sub-pixel group in the x-th row of sub-pixels P are electrically connected to the 2x-th scanning line among the 2m scanning lines G. The sub-pixels P in the y-th column are located between the y-th data line and the (y + 1)-th data line among the 2a×n + 2 data lines S. The first type of sub-pixels P in the y-th column of sub-pixels P are electrically connected to the y-th data line among the 2a×n + 2 data lines S, and the second type of sub-pixels P in the y-th column of sub-pixels P are electrically connected to the (y + 1)-th data line among the 2a×n + 2 data lines S. Among them, 1 ≤ x ≤ m, 1 ≤ y ≤ 2a×n + 1. The first type of sub-pixels P are the sub-pixels P located in odd rows, and the second type of sub-pixels P are the sub-pixels P located in even rows, or the first type of sub-pixels P are the sub-pixels P located in even rows, and the second type of sub-pixels P are the sub-pixels P located in odd rows.

[0048] Among them, during the display period of one frame of the picture, the polarity of the data voltage transmitted by each of the 2a×n + 2 data lines S remains the corresponding polarity, and the polarities of the data voltages transmitted by any two adjacent data lines S among the 2a×n + 2 data lines S are opposite, so that the polarity of any sub-pixel P among the multiple sub-pixels P is opposite to the polarity of the adjacent sub-pixel P.

[0049] Among them, the fact that the polarity of the data voltage transmitted by each data line S remains the corresponding polarity means that the polarity of the data voltage transmitted by each data line S remains unchanged during the display period of one frame of the picture. For example Figure 2 as shown, the polarity of the data voltage transmitted by the first data line S1 remains negative during the display period of one frame of the picture, and the polarity of the data voltage transmitted by the second data line S2 remains positive during the display period of one frame of the picture.

[0050] It is not difficult to understand that since the polarity of the data voltage transmitted by each data line S remains unchanged during the display period of one frame of the picture and does not need to be switched, therefore, the power consumption of the source driver circuit 200 for outputting the data voltage is relatively low, the temperature of the source driver circuit 200 will drop relatively, and the cost of the heat dissipation sticker can be saved.

[0051] The display panel 100 provided by the present application divides the 2nd to the (2a×n + 1)th data lines S among the 2a×n + 2 data lines S into n data line groups, electrically connects the i-th data line in each data line group to the (i + a)-th data line in the same data line group to share a data channel, and sets the first type of sub-pixels P in the y-th column of sub-pixels P to be electrically connected to the y-th data line among the 2a×n + 2 data lines S, and the second type of sub-pixels P in the y-th column of sub-pixels P to be electrically connected to the (y + 1)-th data line among the 2a×n + 2 data lines S, so as to enable each column of sub-pixels P to be controlled by two data lines S. Thus, during the display period of one frame of the picture, a part of the sub-pixels P in each column of sub-pixels P can receive a positive-polarity data voltage through one data line S, and another part of the sub-pixels P can receive a negative-polarity data voltage through the other data line S, such that the polarity of each sub-pixel P is opposite to the polarity of the adjacent sub-pixel P, thereby realizing dot inversion driving, which can eliminate the vertical stripe problem of the existing DRD architecture display panel 100', and can improve the display effect.

[0052] Exemplarily, as Figure 2 shown, taking a = 6, n = 2, m = 4 as an example, where the first type of sub-pixels P are the sub-pixels P located in the even rows, and the second type of sub-pixels P are the sub-pixels P located in the odd rows, the display panel 100 will be introduced.

[0053] Among them, in the sub-pixels P of the same odd row, the sub-pixels P located in the (1 + 2a×j)-th column to the sub-pixels P located in the 2a×(j + 1)-th column belong to the same sub-pixel group, and in the sub-pixels P of the same even row, the sub-pixels P located in the (2 + 2a×j)-th column to the sub-pixels P located in the 2a×(j + 1)+1-th column belong to the same sub-pixel group. Wherein, 0 ≤ j ≤ n.

[0054] Specifically, as Figure 2As shown in the figure, the 2nd data line S2 to the 25th data line S25 are divided into two data line groups. Specifically, the 2nd data line S2 to the 13th data line S13 form the 1st data line group, and the 14th data line S14 to the 25th data line S25 form the 2nd data line group. The 1st data line S1 is separately connected to the 1st data channel H1. In the 1st data line group, the 2nd data line S2 is electrically connected to the 8th data line S8 and shares the 2nd data channel H2. The 3rd data line S3 is electrically connected to the 9th data line S9 and shares the 3rd data channel H3. The 4th data line S4 is electrically connected to the 10th data line S10 and shares the 4th data channel H4. The 5th data line S2 is electrically connected to the 11th data line S11 and shares the 5th data channel H5. The 6th data line S6 is electrically connected to the 12th data line S12 and shares the 6th data channel H6. The 7th data line S7 is electrically connected to the 13th data line S13 and shares the 7th data channel H7. In the 2nd data line group, the 14th data line S14 is electrically connected to the 20th data line S20 and shares the 8th data channel H8. The 15th data line S15 is electrically connected to the 21st data line S21 and shares the 9th data channel H9. The 16th data line S16 is electrically connected to the 22nd data line S22 and shares the 10th data channel H10. The 17th data line S17 is electrically connected to the 23rd data line S23 and shares the 11th data channel H11. The 18th data line S18 is electrically connected to the 24th data line S24 and shares the 12th data channel H12. The 19th data line S19 is electrically connected to the 25th data line S25 and shares the 13th data channel H13. The 26th data line S26 is separately connected to the 14th data channel H14. Thus, the display panel 100 can control 25 columns of sub-pixels for display through 14 data channels.

[0055] Among them, in the 1st column of sub-pixels P, the sub-pixels P located in odd rows are electrically connected to the 2nd data line S2, and the sub-pixels P located in even rows are electrically connected to the 1st data line S1. In the 2nd column of sub-pixels P, the sub-pixels P located in odd rows are electrically connected to the 3rd data line S3, and the sub-pixels P located in even rows are electrically connected to the 2nd data line S2. In the 3rd column of sub-pixels P, the sub-pixels P located in odd rows are electrically connected to the 4th data line S4, and the sub-pixels P located in even rows are electrically connected to the 3rd data line S3. The connection methods of the sub-pixels P in other columns are deduced by analogy and will not be elaborated here.

[0056] Among them, in the sub-pixels P of the first row, the sub-pixels P located in columns 1 to 12 belong to the same sub-pixel group. Among them, the sub-pixels P located in columns 1 to 6 are electrically connected to the first scan line G1, and the sub-pixels P located in columns 7 to 12 are electrically connected to the second scan line G2. The sub-pixels P located in columns 13 to 24 belong to the same sub-pixel group. Among them, the sub-pixels P located in columns 13 to 18 are electrically connected to the first scan line G1, and the sub-pixels P located in columns 19 to 24 are electrically connected to the second scan line G2. The sub-pixel P located in column 25 is electrically connected to the first scan line G1.

[0057] In the sub-pixels P of the second row, the sub-pixel P located in column 1 is electrically connected to the first scan line G1. The sub-pixels P located in columns 2 to 13 belong to the same sub-pixel group. Among them, the sub-pixels P located in columns 2 to 7 are electrically connected to the third scan line G3, and the sub-pixels P located in columns 8 to 13 are electrically connected to the fourth scan line G4. The sub-pixels P located in columns 14 to 25 belong to the same sub-pixel group. Among them, the sub-pixels P located in columns 14 to 19 are electrically connected to the third scan line G3, and the sub-pixels P located in columns 20 to 25 are electrically connected to the fourth scan line G4.

[0058] The connection relationship between the sub-pixels P of other odd rows and the corresponding scan lines G is similar to that of the sub-pixels P of the first row, and the connection relationship between the sub-pixels P of other even rows and the corresponding scan lines G is similar to that of the sub-pixels P of the second row, which will not be elaborated here.

[0059] During the display period of one frame of the picture, the polarities of the data voltages output by the 26 data lines S cycle according to the period of "negative, positive, negative, positive". Specifically, as Figure 2 shown, the polarity of the data voltage output by the first data line S1 is negative. The sub-pixels P located in even rows in the first column of sub-pixels P receive the data voltage output by the first data line S1, and the polarities are also all negative. The polarity of the data voltage output by the second data line S2 is positive. The sub-pixels P located in odd rows in the first column and the seventh column of sub-pixels P, and the sub-pixels P located in even rows in the second column and the eighth column of sub-pixels P receive the data voltage output by the second data line S2, and the polarities are also all positive, and so on. Thus, the polarity of any sub-pixel P is opposite to that of the adjacent sub-pixel P.

[0060] Among them, the display panel 100 is applied to the display device 1, and the display device 1 further includes a source driver circuit 200, a gate driver circuit 300, and a timing controller (TCON) 400.

[0061] Among them, the timing controller 400 is electrically connected to both the source driver circuit 200 and the gate driver circuit 300. The timing controller 400 is configured to receive image data and control signals, perform preprocessing such as format conversion and data sorting on the image data to obtain an image signal, and output the image signal to the source driver circuit 200. The timing controller 400 is further configured to generate a scan control signal and a clock signal, and output the scan control signal and the clock signal to the gate driver circuit 300.

[0062] Specifically, the timing controller 400 is configured to receive image data, perform format conversion on the image data, and sort the image data according to the connection relationship between multiple sub-pixels P in the display panel 100 and 2m scan lines and 2a×n + 2 data lines to obtain an image signal.

[0063] Exemplarily, please refer to Figure 3 , Figure 3 For Figure 2 the conversion schematic diagram of the image data when the display panel shown is displaying. Figure 3 The image data above the arrow in [] is the image data received by the timing controller 400, and the image data below the arrow is the image data obtained after the timing controller 400 sorts the data. Among them, Figure 3 in [], D k，l is used to represent the image data of the sub-pixel P located in the k-th row and the l-th column. As Figure 3 shown, the timing controller 400 is configured to split a received row of image data into two rows. Specifically, for the first row of received image data, the timing controller 400 is configured to cyclically split the first row of image data D 1，1 ~image data D 1，24 into groups of six data and distribute them to the first and second rows of the 2nd data channel H2 to the 13th data channel H13, and distribute the first row of image data D 1，25 to the first row of the 14th data channel H14.

[0064] For the second row of received image data, the timing controller 400 is configured to distribute the second row of image data D 2，1 to the third row of the 1st data channel H1, and distribute the second row of image data D 2，2 ~image data D 2，25Split the data in groups of six and cycle them to the third and fourth rows of the second data channel H2 to the thirteenth data channel H13. Since when the first scan line G1, the second scan line G2, and the fourth scan line G4 are scanned, the first data line S1 does not need to transmit data voltage, and when the second scan line G2 to the fourth scan line G4 are scanned, the twenty-sixth data line S26 does not need to transmit data voltage. Therefore, dummy data (DUMMY, DY) needs to be inserted into the first, second, and fourth rows of the first data channel H1, and dummy data needs to be inserted into the second, third, and fourth rows of the fourteenth data channel H14.

[0065] The source driver circuit 200 outputs corresponding data voltages to the first data channel H1 to the fourteenth data channel H14 based on the image signal output by the timing controller 400. Among them, the source driver circuit 200 may include multiple COFs, and each COF may include multiple data channels.

[0066] The gate driver circuit 300 outputs corresponding scan signals to the 2m scan lines G based on the scan control signal and the clock signal output by the timing controller 400.

[0067] In some embodiments, the polarity of the data voltage transmitted by each data line S in the 2a×n + 2 data lines S during the display period of the current frame image is opposite to the polarity of the data voltage transmitted by this data line S during the display period of the previous frame image. That is to say, if the polarity of the data voltage transmitted by a certain data line S during the display period of the previous frame image is positive polarity, then the polarity of the data voltage transmitted by it during the display period of the current frame image is negative polarity. If the polarity of the data voltage transmitted by a certain data line S during the display period of the previous frame image is negative polarity, then the polarity of the data voltage transmitted by it during the display period of the current frame image is positive polarity. In this way, the polarity inversion of each sub-pixel P can be achieved.

[0068] In some embodiments, all the sub-pixels P in the same column of sub-pixels P have the same color.

[0069] In some embodiments, the sub-pixels P in each row are arranged in a cyclic order of the first color sub-pixel P, the second color sub-pixel P, and the third color sub-pixel P in the row direction. Among them, the first color, the second color, and the third color are all different. Exemplarily, the first color, the second color, and the third color are red, green, and blue respectively.

[0070] In some embodiments, in each data line group, the i-th data line includes opposite first end 11, second end 12, and a crossover point 13 located between the first end 11 and the second end 12. Wherein, the first end 11 of the i-th data line is electrically connected to the source driver circuit 200 for receiving the data voltage output by the source driver circuit 200. The (i + a)-th data line is electrically connected to the crossover point 13 on the i-th data line through a jumper wire 20. Wherein, the jumper wire 20 extends in the row direction.

[0071] In some embodiments, in each data line group, the difference between the sum of the impedance value of the (i + a)-th data line and the impedance value of the jumper wire 20 electrically connected to the (i + a)-th data line and the impedance value of the branch segment 102 of the i-th data line is less than or equal to a preset impedance threshold. Preferably, the preset impedance threshold is set to 0, that is, the sum of the impedance value of the (i + a)-th data line and the impedance value of the jumper wire 20 electrically connected to the (i + a)-th data line is equal to the impedance value of the branch segment 102 of the i-th data line.

[0072] It should be noted that since there is impedance in the data trace, a voltage drop will occur during the transmission of the data voltage in the data line S and the jumper wire 20. Moreover, the greater the impedance value of the data trace, the greater the voltage drop. Then, the closer the sum of the impedance value of the (i + a)-th data line and the impedance value of the jumper wire 20 electrically connected to the (i + a)-th data line is set to the impedance value of the branch segment 102 of the i-th data line, the closer the voltage drop generated when the data voltage is transmitted to the second end of the (i + a)-th data line is to the voltage drop generated when the data voltage is transmitted to the second end of the i-th data line. Thus, the higher the uniformity of the display screen of the display panel 100.

[0073] In some embodiments, in each data line group, the i-th data line includes a common segment 101 between the first end 11 and the crossover point 13 and a branch segment 102 between the crossover point 13 and the second end 12. The cross-sectional area of the (i + a)-th data line is greater than the cross-sectional area of the branch segment 102 of the i-th data line. Preferably, the cross-sectional area of the jumper wire 20 electrically connected to the i-th data line is also greater than the cross-sectional area of the branch segment 102 of the i-th data line.

[0074] Since the i+ath data line is electrically connected to the jumper point 13 on the i-th data line through a jumper line 20, the sum of the length of the i+ath data line and the length of the jumper line 20 must be longer than the length of the i-th data line. Therefore, by setting the cross-sectional area of ​​the i+ath data line to be larger than the cross-sectional area of ​​the branch segment 102 of the i-th data line, and / or setting the cross-sectional area of ​​the jumper line 20 electrically connected to the i-th data line to be larger than the cross-sectional area of ​​the branch segment 102 of the i-th data line, the difference between the sum of the impedance value of the i+ath data line and the impedance value of the jumper line 20 electrically connected to the i+ath data line and the impedance value of the branch segment 102 of the i-th data line can be reduced, thereby improving the uniformity of the display screen of the display panel 100.

[0075] See also Figure 4 , Figure 4 A schematic diagram of another display panel provided in an embodiment of the present application. Figure 4 The display panel 100 is shown with Figure 2 The structure of the display panel 100 shown in FIG. 1 is similar, except that: Figure 4 In the display panel 100 shown, the first type of sub-pixels P are sub-pixels P located in odd rows, and the second type of sub-pixels P are sub-pixels P located in even rows. In the sub-pixels P in the same odd row, the sub-pixels P located in the 2+2a×j column to the sub-pixel P located in the 2a×(j+1)+1 column belong to the same sub-pixel group, and in the sub-pixels P in the same even row, the sub-pixels P located in the 1+2a×j column to the sub-pixel P located in the 2a×(j+1) column belong to the same sub-pixel group. Wherein, 0≤j≤n.

[0076] Specifically, Figure 4 As shown, in the first column of sub-pixels P, the sub-pixels P located in odd rows are electrically connected to the first data line S1, and the sub-pixels P located in even rows are electrically connected to the second data line S2. In the second column of sub-pixels P, the sub-pixels P located in odd rows are electrically connected to the second data line S2, and the sub-pixels P located in even rows are electrically connected to the third data line S3. In the third column of sub-pixels P, the sub-pixels P located in odd rows are electrically connected to the third data line S3, and the sub-pixels P located in even rows are electrically connected to the fourth data line S4. The connection methods of the sub-pixels P in other columns are similar and will not be described in detail.

[0077] Among them, in the sub-pixels P of the first row, the sub-pixel located in the first column is electrically connected to the first scan line G1, and the sub-pixels P located in the second to thirteenth columns belong to the same sub-pixel group. Among them, the sub-pixels P located in the second to seventh columns are electrically connected to the first scan line G1, and the sub-pixels P located in the eighth to thirteenth columns are electrically connected to the second scan line G2. The sub-pixels P located in the fourteenth to twenty-fifth columns belong to the same sub-pixel group. Among them, the sub-pixels P located in the fourteenth to nineteenth columns are electrically connected to the first scan line G1, and the sub-pixels P located in the twentieth to twenty-fifth columns are electrically connected to the second scan line G2.

[0078] In the sub-pixels P of the second row, the sub-pixels P located in the first to twelfth columns belong to the same sub-pixel group. Among them, the sub-pixels P located in the first to sixth columns are electrically connected to the third scan line G3, and the sub-pixels P located in the seventh to twelfth columns are electrically connected to the fourth scan line G4. The sub-pixels P located in the thirteenth to twenty-fourth columns belong to the same sub-pixel group. Among them, the sub-pixels P located in the thirteenth to eighteenth columns are electrically connected to the third scan line G3, and the sub-pixels P located in the nineteenth to twenty-fourth columns are electrically connected to the fourth scan line G4. The sub-pixel P located in the twenty-fifth column is electrically connected to the third scan line G3.

[0079] The connection relationship between the sub-pixels P of other odd rows and the corresponding scan lines G is similar to that of the sub-pixels P of the first row, and the connection relationship between the sub-pixels P of other even rows and the corresponding scan lines G is similar to that of the sub-pixels P of the second row, which will not be elaborated here.

[0080] During the display period of one frame of the picture, the polarities of the data voltages output by the 26 data lines S cycle according to the period of "positive, negative, positive, negative". Specifically, as Figure 4 shown, the polarity of the data voltage output by the first data line S1 is positive, and the sub-pixels P located in the odd rows in the first column of the sub-pixels P receive the data voltage output by the first data line S1, and the polarities are also all positive. The polarity of the data voltage output by the second data line S2 is negative, and the sub-pixels P located in the even rows in the first and seventh columns of the sub-pixels P, and the sub-pixels P located in the odd rows in the second and eighth columns of the sub-pixels P receive the data voltage output by the second data line S2, and the polarities are also all negative, and so on. Thus, the polarity of any sub-pixel P is opposite to the polarity of the adjacent sub-pixel P.

[0081] It should be noted that Figure 2 、 Figure 4 are only exemplary and should not be regarded as a limitation to this application. In other embodiments, a, n, and m can also be other positive integer values.

[0082] Please refer to again Figure 2, the present application further provides a display device 1, and the display device 1 includes a gate driving circuit 300, a source driving circuit 200, and the display panel 100 described in any of the above embodiments.

[0083] Among them, the gate driving circuit 300 is electrically connected to 2m scan lines G in the display panel 100, and the gate driving circuit 300 is configured to output corresponding scan signals to the 2m scan lines G. The source driving circuit 200 is electrically connected to 2a×n + 2 data lines S in the display panel 100, and the source driving circuit 200 is configured to output corresponding data voltages to the 2a×n + 2 data lines S.

[0084] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principle and spirit of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A display panel, characterized in that, The display panel includes: 2m scan lines arranged in the column direction; 2a×n + 2 data lines arranged in the row direction; wherein, 2 ≤ a, 1 ≤ n, the second to the (2a×n + 1)-th data lines among the 2a×n + 2 data lines are divided into n data line groups, each data line group includes 2a data lines arranged in sequence, and the i-th data line in each data line group is electrically connected to the (i + a)-th data line in the same data line group, where 1 ≤ i ≤ a; and Multiple sub-pixels arranged in an m-row and (2a×n + 1)-column array; wherein, the sub-pixels in the x-th row are located between the (2x - 1)-th and the 2x-th scan lines among the 2m scan lines, the sub-pixels in the x-th row include n sub-pixel groups, each sub-pixel group includes 2a sub-pixels arranged in sequence in the row direction, the first a sub-pixels in each sub-pixel group in the x-th row sub-pixels are electrically connected to the (2x - 1)-th scan line among the 2m scan lines, and the last a sub-pixels in each sub-pixel group in the x-th row sub-pixels are electrically connected to the 2x-th scan line among the 2m scan lines; the sub-pixels in the y-th column are located between the y-th and the (y + 1)-th data lines among the 2a×n + 2 data lines, the first type of sub-pixels in the y-th column sub-pixels are electrically connected to the y-th data line among the 2a×n + 2 data lines, and the second type of sub-pixels in the y-th column sub-pixels are electrically connected to the (y + 1)-th data line among the 2a×n + 2 data lines; where 1 ≤ x ≤ m, 1 ≤ y ≤ 2a×n + 1, the first type of sub-pixels are the sub-pixels located in the even rows, the second type of sub-pixels are the sub-pixels located in the odd rows, or the first type of sub-pixels are the sub-pixels located in the odd rows, and the second type of sub-pixels are the sub-pixels located in the even rows; Wherein, in the display period of one frame of the picture, the polarities of the data voltages transmitted by each of the 2a×n + 2 data lines are maintained as the corresponding polarities, and the polarities of the data voltages transmitted by any two adjacent data lines among the 2a×n + 2 data lines are opposite, so that the polarity of any sub-pixel among the multiple sub-pixels is opposite to the polarity of the adjacent sub-pixels.

2. The display panel according to claim 1, wherein, The polarity of the data voltage transmitted by each of the 2a×n + 2 data lines in the display period of the current frame of the picture is opposite to the polarity of the data voltage transmitted by this data line in the display period of the previous frame of the picture.

3. The display panel according to claim 1, characterized in that, a = 6, the first type of sub-pixels are the sub-pixels located in the even rows, and the second type of sub-pixels are the sub-pixels located in the odd rows; among the sub-pixels in the same odd row, the sub-pixels located in the (1 + 2a×j)-th column to the sub-pixels located in the 2a×(j + 1)-th column belong to the same sub-pixel group, and among the sub-pixels in the same even row, the sub-pixels located in the (2 + 2a×j)-th column to the sub-pixels located in the 2a×(j + 1)+1-th column belong to the same sub-pixel group; where 0 ≤ j ≤ n.

4. The display panel according to claim 1, wherein a = 6, the first type of sub-pixels are the sub-pixels located in the odd rows, and the second type of sub-pixels are the sub-pixels located in the even rows; among the sub-pixels in the same odd row, the sub-pixels located in the (2 + 2a×j)-th column to the sub-pixels located in the (2a×(j + 1)+1)-th column belong to the same sub-pixel group, and among the sub-pixels in the same even row, the sub-pixels located in the (1 + 2a×j)-th column to the sub-pixels located in the 2a×(j + 1)-th column belong to the same sub-pixel group; where 0 ≤ j ≤ n.

5. The display panel according to claim 1, characterized in that All sub-pixels in the same column of sub-pixels have the same color.

6. The display panel according to claim 5, characterized in that The sub-pixels in each row are arranged in a cyclic order of first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels in the row direction.

7. The display panel according to claim 1, characterized in that, In each data line group, the i-th data line includes an opposite first end, a second end, and a cross connection point located between the first end and the second end. Among them, the first end of the i-th data line is electrically connected to the source driver circuit for receiving the data voltage output by the source driver circuit; the (i + a)-th data line is electrically connected to the cross connection point on the i-th data line through a jumper wire; where the jumper wire extends along the row direction.

8. The display panel according to claim 7, characterized in that, In each data line group, the i-th data line includes a common segment between the first end and the cross connection point and a branch segment between the cross connection point and the second end, and the cross-sectional area of the (i + a)-th data line is larger than the cross-sectional area of the branch segment of the i-th data line.

9. The display panel according to claim 7, characterized in that, In each data line group, the difference between the sum of the impedance value of the (i + a)-th data line and the impedance value of the jumper wire electrically connected to the (i + a)-th data line and the impedance value of the branch segment of the i-th data line is less than or equal to a preset impedance threshold.

10. A display device, characterized in that, The display device includes: A gate driver circuit; A source driver circuit; and A display panel according to any one of claims 1 to 9; where the gate driver circuit is electrically connected to all 2m scan lines in the display panel, and the gate driver circuit is used to output corresponding scan signals to the 2m scan lines; the source driver circuit is electrically connected to all 2a×n + 2 data lines in the display panel, and the source driver circuit is used to output corresponding data voltages to the 2a×n + 2 data lines.

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