Efficient write operation detection for memory devices

Abstract

The invention relates to efficient write operation detection for a memory device. The described techniques provide a memory system to set flags according to a state of an access operation. The memory system can receive a command to write data and can adjust a value of a mode register based on whether a write operation is valid. In some examples, the memory system can set the mode register value after successfully receiving, decoding, or completing the write command. In some other examples, if the memory system experiences a failure when receiving, decoding, or executing the write command, the memory system may avoid setting the mode register value. A host device can poll the mode register to identify validity of the write operation, and can perform one or more corrective actions when the write operation is invalid.

Description

[0001] Cross-reference

[0002] This patent application claims the benefit of U.S. Patent Application No. 18 / 979,319, filed on December 12, 2024, and U.S. Patent Application No. 63 / 619,160, filed on January 9, 2024, both titled "VALID WRITE OPERATION DETECTION FOR MEMORY DEVICES" by Uribe et al., each of which is assigned to its assignee and the entire contents of each of which are hereby incorporated by reference in their entirety. Technical Field

[0003] The following relates to one or more systems of a memory, including detection of a valid write operation of a memory device. Background Art

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored by the memory cell. To store information, the memory device can write (e.g., program, set, assign) a state to the memory cell. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. Summary of the Invention

[0005] A device is described. The device can include processing circuitry associated with one or more memory devices. The processing circuitry can be configured to cause the device to: receive a write command indicating data is to be written to one or more memory cells of a memory system; initiate a write operation to write the data to the one or more memory cells at least in part based on the write command; and adjust a value of a mode register from a first value to a second value at least in part based on initiating the write operation, where the value of the mode register indicates the validity of the write operation.

[0006] Describe an apparatus. The apparatus may include processing circuitry associated with one or more memory devices. The processing circuitry may be configured to cause the apparatus to: transmit from a host system a write command indicating data to be written to one or more memory cells of a memory system; poll a mode register of the memory system at least in part based on the write command, wherein a value of the mode register indicates the validity of a write operation at the memory system; and determine whether to issue a command to the memory system to perform a retransmission of the write command or a subsequent access command at least in part based on the value of the mode register.

[0007] Describe an apparatus. The apparatus may include processing circuitry associated with one or more memory devices. The processing circuitry may be configured to cause the apparatus to: receive a write command indicating data to be written to one or more memory cells of a memory system; initiate a write operation to write the data to the one or more memory cells at least in part based on the write command; and bias a pin from a first value to a second value at least in part based on initiating the write operation, wherein a value of the pin indicates the validity of the write operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. shows an example of a system supporting detection of a valid write operation of a memory device in accordance with an example disclosed herein.

[0009] Figure 2 FIG. shows an example of an architecture supporting detection of a valid write operation of a memory device in accordance with an example disclosed herein.

[0010] Figure 3 FIG. shows an example of a process flow supporting detection of a valid write operation of a memory device in accordance with an example disclosed herein.

[0011] Figure 4 FIG. shows a block diagram of a memory system supporting detection of a valid write operation of a memory device in accordance with an example disclosed herein.

[0012] Figure 5 FIG. shows a block diagram of a host system supporting detection of a valid write operation of a memory device in accordance with an example disclosed herein.

[0013] Figures 6 to 8 FIG. shows a flow diagram illustrating one or more methods supporting detection of a valid write operation of a memory device in accordance with an example disclosed herein. DETAILED DESCRIPTION

[0014] A memory system is operable to perform various operations (e.g., applications) associated with storing and accessing data in one or more memory cells of the memory system. For example, the memory system may receive one or more access commands (e.g., from a host system) to direct the memory system to store data in one or more memory cells (e.g., a write command), obtain data stored in one or more memory cells (e.g., a read command), or both. In some instances, the memory system may experience one or more failures when receiving or executing a command, such as failing to exit a mode in which a command is received (e.g., a self-refresh mode), failing to decode a command (the command contains invalid information (e.g., due to a package fault) or the hardware of the memory system is not operating correctly), or any combination thereof and other instances. Such failures can cause the memory system to be unable to receive, decode, or execute a command, and data associated with the command may be lost (e.g., if the write command is not successful). Additionally, some error correction code (ECC) schemes are unable to detect such failures, such as host inline ECC and link ECC schemes, which can identify whether stored data contains one or more errors (e.g., a command execution failure is not detected). For example, if the memory system fails to execute a write command indicating new data and the old data remains stored in one or more memory cells (e.g., not overwritten by the new data), then the ECC scheme may detect whether there are errors in the old data and not detect a failure during command execution. In some cases, the memory system may support functional safety applications (e.g., automotive functional safety), which may be associated with one or more time to failure (FIT) constraints and other constraints or related parameters. However, failures during receiving or executing access commands and the failure to detect such failures can cause the memory system to be unable to meet the FIT constraints, thereby limiting the performance of the memory system and other challenges.

[0015] To indicate the validity of an operation associated with an access command, a memory system may set a flag according to the status of the operation. For example, the memory system may receive a command to write data and may adjust a value in, for example, a mode register or another location based on whether a write operation (e.g., triggered by the write command) is valid. The memory system may adjust a value such as a mode register value from a first value (e.g., binary value '0', which may be a default value) to a second value (e.g., binary value '1') to indicate that the write operation is valid (e.g., the write operation has been received, decoded, determined to be or otherwise accurately executed, and other validity indications). In some instances, the memory system may set the mode register value after successfully receiving and decoding the write command (e.g., but before completing the execution of the write operation) or may set the mode register value after successfully completing the write operation. If the memory system experiences a failure during the reception, decoding, or execution of the write command, then the memory system may avoid setting the mode register value. Additionally or alternatively, the memory system may use one or more different methods (e.g., via a pin (e.g., a decoded status flag (DSF) pin, an alert pin, or some other type of pin), sending a message indication, or including the status of the write operation or one or more other methods) to signal, for example, the status of the write operation to the host device.

[0016] The host device may poll the mode register (or a pin or another location) to identify the validity of the write operation. For example, if the host device identifies that the mode register value is set to the second value (e.g., indicating that the write operation is valid), then the host device may reset the value of the mode register (e.g., to the default value) and may issue one or more subsequent access commands. Alternatively, if the host device identifies that the mode register value is set to the first value (e.g., the write operation is invalid), then the host device may determine to perform one or more corrective actions. For example, the host device may issue a retransmission of the write command to the memory system, may pause an application associated with the write command, may deactivate an address space associated with the write command, or any combination thereof. Such techniques may improve the detection of command execution failures, which may support the memory system in meeting FIT rate constraints and mitigate data loss.

[0017] In addition to being applied to the memory systems described herein, techniques for detecting effective write operations for memory devices can generally also be implemented to improve the performance of various electronic devices and systems, including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and gaming. Some electronic device applications, including high-performance applications such as AI, AR, VR, and gaming, can be associated with relatively high processing requirements to meet user expectations. Thus, improving the processing capabilities of electronic devices by reducing response time, improving power consumption, reducing complexity, increasing data throughput or access speed, reducing communication time, or increasing memory capacity or density, and other performance metrics can improve the user experience or attractiveness. Implementing the techniques described herein can improve the performance of electronic devices by reducing the failure rate of write commands due to in-flight failures, which can reduce or mitigate the latency associated with recovering lost or incorrect stored data and other benefits.

[0018] In addition to being applied to the memory systems described herein, techniques for detecting effective write operations for memory devices can generally also be implemented to support edge computing applications. Edge computing is a distributed computing paradigm that brings computing and data storage closer to the data source than traditional cloud services. As the use of edge computing to provide computing, storage, and networking services geographically closer to end users increases, many devices and systems can benefit from improved processing, performance, and storage at the edge device. For example, increasing the memory density, capacity, and processing capabilities of edge devices can reduce the device's dependence on remote computing or devices, which would otherwise increase the latency of operations performed at the device. Implementing the techniques described herein can support edge computing technologies and other benefits by reducing the failure rate of write commands due to in-flight failures at the edge device.

[0019] The features of the present disclosure are illustrated and described in the context of systems and architectures. The features of the present disclosure are further illustrated and described in the context of process flows and flowcharts.

[0020] Figure 1 An example of a system 100 that supports detecting effective write operations for a memory device in accordance with an example disclosed herein is described. System 100 can include portions of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, a smartphone, a wearable device, an Internet-connected device, a vehicle controller, a system-on-chip (SoC), or other fixed or portable electronic systems, and other examples. System 100 includes a host system 105, a memory system 110, and one or more channels 115 (e.g., for supporting communication coupling) that couple the host system 105 to the memory system 110. System 100 can include any number of one or more memory systems 110 coupled to the host system 105.

[0021] The host system 105 may include one or more components (such as circuitry, processing circuitry, one or more processing components) that execute processes using a memory, any one or more of which may be referred to as or included in the processor 125. The processor 125 may include at least one of one or more processing elements that may be co-located or distributed, including a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a controller, discrete gate or transistor logic, one or more discrete hardware components, or combinations thereof. The processor 125 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a system-on-chip (SoC) or components thereof, and other instances.

[0022] The host system 105 may also include at least one of one or more components (such as circuitry, logic, instructions) that implement the functionality of an external memory controller (such as a host system memory controller), which may be referred to as or included in the host system controller 120. For example, the host system controller 120 may issue commands or other signaling for operating the memory system 110, such as write commands, read commands, configuration signaling, or other operation signaling. In some instances, the host system controller 120 or the associated functionality described herein may be implemented by or be part of the processor 125. For example, the host system controller 120 may be hardware, instructions (such as software, firmware), or some combination thereof implemented by the processor 125 or other components of the host system 105. In various instances, the host system 105 or the host system controller 120 may be referred to as the host.

[0023] The memory system 110 provides physical memory locations (such as addresses) that may be used or referenced by the system 100. The memory system 110 may include a memory system controller 140 and one or more memory devices 145 (such as memory packages, memory dies, memory chips) operable to store data. The memory system 110 may be configured to operate with different types of host systems 105 and may respond to commands from the host system 105 (such as, from the host system controller 120). For example, the memory system 110 (such as the memory system controller 140) may receive a write command indicating that the memory system 110 stores data received from the host system 105, or a read command indicating that the memory system 110 provides data stored in the memory device 145 to the host system 105, or a refresh command indicating that the memory system 110 refreshes data stored in the memory device 145, and other types of commands and operations.

[0024] The memory system controller 140 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory system 110. The memory system controller 140 may include hardware or instructions to support the memory system 110 in performing various operations, and may be operable to receive, transfer, or respond to commands, data, or control information related to the operation of the memory system 110. The memory system controller 140 may be operable to communicate with one or more of the host system controller 120, one or more memory devices 145, or the processor 125. In some instances, the memory system controller 140 may cooperate with the host system controller 120, the local controller 150 of the memory device 145, or any combination thereof to control the operation of the memory system 110. Although an example of the memory system controller 140 is illustrated as a separate component of the memory system 110, in some instances, aspects of the functionality of the memory system 110 may be implemented by at least one of the processor 125, the host system controller 120, one or more local controllers 150, or any combination thereof.

[0025] Each memory device 145 may include a local controller 150 and one or more memory arrays 155. The memory array 155 may be a collection of memory cells (e.g., two-dimensional array, three-dimensional array), where each memory cell may be operable to store data (e.g., as one or more stored bits). Each memory array 155 may include memory cells of various architectures, such as random access memory (RAM) cells, dynamic RAM (DRAM) cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, ferroelectric RAM (FeRAM) cells, magnetic RAM (MRAM) cells, resistive RAM (RRAM) cells, phase change memory (PCM) cells, chalcogenide memory cells, NOR memory cells, and NAND memory cells, or any combination thereof.

[0026] The local controller 150 may include at least one of one or more components (such as circuitry, logic, instructions) operable to control the operation of the memory device 145. In some instances, the local controller 150 may be operable to communicate with the memory system controller 140 (e.g., receive or transmit data or commands or both). In some instances, the memory system 110 may not include the memory system controller 140, and the local controller 150 or the host system controller 120 may perform the functions of the memory system controller 140 described herein. In some instances, the local controller 150 or the memory system controller 140 or both may include a decoding component operable to access the addresses of the memory cells of the memory array 155, a sensing component for sensing the states of the memory cells of the memory array 155, a writing component for writing the states to the memory cells of the memory array 155, or various other components operable to support the described operations of the memory system 110.

[0027] The host system 105 (such as the host system controller 120) and the memory system 110 (such as the memory system controller 140) may use one or more channels 115 to convey information (such as data, commands, control information, configuration information). Each channel 115 may be an instance of a transmission medium for carrying information, and each channel 115 may include one or more signal paths (such as transmission media, electrical conductors, conductive paths) between terminals (such as nodes, pins, contacts) associated with components of the system 100. The terminals may be instances of conductive input or output points of the devices of the system 100, and the terminals may operate as part of the channel 115. To support communication over the channel 115, the host system 105 (such as the host system controller 120) and the memory system 110 (such as the memory system controller 140) may include a receiver (such as a latch) for receiving signals, a transmitter (such as a driver) for transmitting signals, a decoder for decoding or demodulating received signals, or an encoder for encoding or modulating signals to be transmitted, as well as other components to support signaling over the channel 115, which may be included in the respective interface portions of the respective systems.

[0028] Channel 115 is dedicated to conveying one or more types of information, and channel 115 can include unidirectional channels, bidirectional channels, or both. For example, channel 115 can include one or more command / address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some instances, channel 115 can be configured to supply power from one system to another system (e.g., from host system 105 to memory system 110, according to a regulated voltage). In some instances, at least a subset of channel 115 can be configured according to a protocol (e.g., a logic protocol, a communication protocol, an operation protocol, an industry standard), and the protocol can support the configuration operations of host system 105 and memory system 110 and the interaction between host system 105 and memory system 110.

[0029] A command / address channel (e.g., a CA channel) can operate to convey commands between host system 105 and memory system 110, including control information associated with the commands (e.g., address information, configuration information). The commands carried by the command / address channel can include a write command having an address of data to be written to memory system 110 or a read command having an address of data to be read from memory system 110.

[0030] A data channel (e.g., a DQ channel) can operate to convey (e.g., bidirectionally) information (e.g., data, control information) between host system 105 and memory system 110. For example, the data channel can convey information written from host system 105 to memory system 110 or information read from memory system 110 to host system 105. In some instances, channel 115 can include one or more error detection code (EDC) channels. The EDC channel can operate to convey error detection signals, such as a checksum or a parity bit, which can accompany the information transmitted through the data channel.

[0031] In some instances of the system 100, the memory system 110 may experience one or more failures when receiving or executing a command (e.g., a write command) from the host system 105. For example, the memory system 110 fails to exit the mode of receiving a command (e.g., fails to exit the self-refresh mode), fails to decode the command (the command may contain invalid information (e.g., due to a package fault), and the hardware of the memory system 110 may not operate properly), or any combination thereof, and other instances. Such failures may cause the memory system 110 to fail to receive, decode, or execute the command, and the data associated with the command may be lost (e.g., if the write command is unsuccessful). Some ECC schemes cannot detect such failures, such as host inline ECC and link ECC schemes, which can identify whether the stored data contains one or more errors. In some cases, the memory system 110 may support functional safety applications (e.g., automotive functional safety), which may be associated with one or more FIT rate constraints. However, failures during receiving or executing access commands and the failure to detect such failures may cause the memory system 110 to fail to meet the FIT rate constraints, thereby limiting the performance of the memory system 110.

[0032] In some cases, the memory system 110 may set a flag to indicate the validity of an access operation. That is, the memory system controller 140 may be operable to adjust the value of the flag according to the validity (or status) of an access operation (e.g., a write operation). For example, the memory system controller 140 may adjust the value of the mode register 160 from a first value (e.g., a binary value '0', which may be the default value) to a second value (e.g., a binary value '1') to indicate that the write operation is valid. In such instances, the memory system controller 140 may set the value of the mode register 160 after successfully receiving and decoding the write command or may set the value of the mode register 160 after successfully completing the write operation. As another example, if the memory system 110 experiences a failure when receiving, decoding, or executing a write command, then the memory system controller 140 may avoid setting the value of the mode register 160.

[0033] Additionally or alternatively, in some instances, the memory system 110 may signal the status of a write operation (e.g., to the host system 105) via pin 165, which may be an instance of a DSF pin or an alert pin or some other type of pin. The host system 105 may poll the mode register 160, pin 165, or both to identify the validity of the write operation. In some instances, the value of the mode register 160 may be loaded into pin 165. The host system 105 may be coupled to or otherwise access the mode register 160, pin 165, or both. If the host system 105 identifies the write operation as valid based on the mode register 160 and / or pin 165, then the host system 105 may reset the value of the mode register 160 (e.g., to a default value) and may issue one or more subsequent access commands to the memory system 110 (e.g., as part of normal operation). Alternatively, if the host system 105 identifies the write operation as invalid, then the host system 105 may determine to perform one or more corrective actions. For example, the host system 105 may issue a retransmission of the write command to the memory system 110, may pause an application associated with the write command, may deactivate an address space associated with the write command, or any combination thereof. Such techniques may improve the detection of command execution failures, which may support the memory system 110 in meeting FIT rate constraints and mitigating data loss.

[0034] Figure 2 An example of an architecture 200 (e.g., a memory architecture) that supports detection of valid write operations for a memory device in accordance with examples disclosed herein is illustrated. Architecture 200 may be implemented in the memory system 110 or one or more of its components (e.g., the memory device 145). Aspects of architecture 200 may be referred to as or implemented in a semiconductor component, such as a memory die.

[0035] The architecture 200 includes memory cells 205 that are programmable to store information. In some instances, the memory cells 205 may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some instances, the memory cells 205 (e.g., multi-level memory cells) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). The memory cells 205 may be arranged in an array, such as a memory array 155.

[0036] In an instance of architecture 200, a memory cell 205 may include a storage component (e.g., capacitor 230) and a select component 235 (e.g., a cell select component, a transistor). Capacitor 230 may be a dielectric capacitor or a ferroelectric capacitor. A node of capacitor 230 may be coupled to a voltage source 240, which may be a cell plate reference voltage (e.g., Vpl) or may be a ground voltage (e.g., Vss). The charge stored by memory cell 205 (e.g., by capacitor 230) may represent a programming state. Other memory architectures that support the techniques described herein may implement different types or arrangements of storage components and associated circuitry (e.g., with or without select components).

[0037] Architecture 200 may include access lines in various arrangements, such as word lines 210 and digit lines 215. The access lines may be conductive lines that are coupled to memory cells 205 and may be used to perform access operations on memory cells 205. Word lines 210 may be referred to as row lines, and digit lines 215 may be referred to as column lines or bit lines, among other terms. Memory cells 205 may be located at intersections of the access lines, and the intersections may be referred to as the addresses of memory cells 205.

[0038] In some architectures, word lines 210 may be coupled to the gates of select components 235 of memory cells 205 and may be operable to control select components 235 (e.g., switch, modulate the conductivity of select components 235). Digit lines 215 may be operable to couple memory cells 205 to sense components 245. In some architectures, memory cells 205 (e.g., capacitor 230) may be coupled to digit lines 215 during portions of access operations. For example, word lines 210 and select components 235 of memory cells 205 may be operable to couple or isolate capacitor 230 of memory cells 205 from digit lines 215.

[0039] By activating (e.g., applying a voltage to) an access line such as word line 210 or digit line 215, operations such as read and write may be performed on memory cell 205. Access to memory cell 205 may be controlled by a row decoder 220 or a column decoder 225 or a combination thereof. For example, row decoder 220 may receive a row address (e.g., from a local memory controller 260) and activate word lines 210 based on the received row address, and column decoder 225 may receive a column address and activate digit lines 215 based on the received column address. Selecting or deselecting memory cell 205 may include using word lines 210 to activate or deactivate select components 235. For example, when select component 235 is deactivated, capacitor 230 may be isolated from digit line 215, and when select component 235 is activated, capacitor 230 may be coupled to digit line 215.

[0040] The sensing component 245 is operable to detect a state (e.g., charge) stored by the capacitor 230 of the memory cell 205 and determine the logic state of the memory cell 205 based on the stored state. The sensing component 245 may include one or more sense amplifiers to amplify or otherwise convert a signal resulting from accessing the memory cell 205. The sensing component 245 may compare the signal detected from the memory cell 205 with a reference 250 (e.g., a reference voltage). The detected logic state of the memory cell 205 may be provided as an output of the sensing component 245 (e.g., via the input / output 255), and may indicate the detected logic state to another component of the memory system 110 of the implementation architecture 200.

[0041] The local memory controller 260 may control access to the memory cells 205 through various components (e.g., the row decoder 220, the column decoder 225, the sensing component 245), and may be an instance of or otherwise included in the local controller 150 or the memory system controller 140 or both. In some instances, one or more of the row decoder 220, the column decoder 225, and the sensing component 245 may be collocated with or included in the local memory controller 260. The local memory controller 260 is operable to receive commands or data from one or more different controllers (e.g., the host system controller 120, the memory system controller 140), translate the commands or data into information usable by the architecture 200, initiate or control one or more operations of the architecture 200, and convey data from the architecture 200 to the host (e.g., the host system 105) based on the execution of one or more operations.

[0042] The local memory controller 260 is operable to perform one or more access operations on one or more memory cells 205 of the architecture 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, among others. In some instances, the access operations may be performed or otherwise coordinated by the local memory controller 260 in response to one or more access commands (e.g., from the host system 105). The local memory controller 260 is operable to perform other access operations not listed herein or other operations related to the operations of the architecture 200 that are not directly related to accessing the memory cells 205.

[0043] To support access operations, the local memory controller 260 may identify a target memory cell 205 on which an access operation is to be performed, which may be associated with identifying a target word line 210 and a target digit line 215 (e.g., the address of the target memory cell 205) coupled to the target memory cell 205. The local memory controller 260 may control the activation of the target word line 210 and the target digit line 215 to access the target memory cell 205. During a write operation, the local memory controller 260 may control the application of a signal (e.g., a write pulse, a write voltage) to the target digit line 215 to store a particular state (e.g., charge in the capacitor 230) of the memory cell 205. The signal that forms part of the write operation may comprise one or more voltage levels applied to the target memory cell 205 (e.g., via the target digit line 215) over one or more respective durations. During a read operation, the target memory cell 205 may transfer a signal (e.g., charge, voltage) to the sense component 245 based on the activation of the target word line 210 and the target digit line. The local memory controller 260 may activate the sense component 245 (e.g., initiate a sense amplifier that latches the sense component 245), which may comprise comparing the signal transferred from the memory cell 205 with a reference (e.g., reference 250). Based on the comparison, the sense component 245 may determine the logical state stored on the memory cell 205.

[0044] In some instances of the architecture 200, the memory system may experience one or more faults when receiving or executing a command (e.g., a write command indicating data to be written to one or more memory cells 205). Such faults may cause the memory system to be unable to receive, decode, or execute the command, and the data associated with the command may be lost (e.g., if the write command is unsuccessful). Additionally, some ECC schemes are unable to detect such faults, such as host inline ECC and link ECC schemes, which may identify whether stored data contains one or more errors. In some cases, the memory system may support functional safety applications (e.g., automotive functional safety), which may be associated with one or more FIT rate constraints. However, faults during the receipt or execution of access commands and the failure to detect such faults may cause the memory system to fail to meet the FIT rate constraints, lose data, or both, thereby limiting the performance of the memory system.

[0045] In some cases, a memory system may set a flag to indicate the validity of an access operation. That is, a memory system controller may operate to adjust the value of the flag based on the validity (or status) of an access operation (e.g., a write operation). For example, a controller (e.g., memory system controller 140 or local memory controller 260) may adjust the value of a mode register from a first value (e.g., binary '0') to a second value (e.g., binary '1') to indicate that a write operation is valid. In such an instance, the controller may set the mode register value after successfully receiving and decoding a write command or may set the mode register value after successfully completing a write operation. As another example, if the memory system experiences a failure during receipt, decoding, or execution of a write command, then the controller may avoid setting the mode register value. In some instances, the memory system may signal the status of a write operation via a pin, which may be an instance of a DSF pin or an alert pin.

[0046] A host system may poll the mode register (or pin) to identify the validity of a write operation. For example, if the host system identifies that the mode register value is set to the second value (e.g., indicating that the write operation is valid), then the host system may reset the value of the mode register (e.g., to a default value) and may issue one or more subsequent access commands to the memory system 110 (e.g., as part of normal operation). Alternatively, if the host system identifies that the mode register value is the first value (e.g., indicating that the write operation is invalid), then the host system may determine to perform one or more corrective actions. For example, the host system may issue a retransmission of the write command to the memory system, may pause an application associated with the write command, may deactivate an address space associated with the write command, or any combination thereof. Such techniques may improve the detection of command execution failures, which may support the memory system in meeting FIT rate constraints and mitigating data loss.

[0047] Figure 3 An example of a process flow 300 that supports detection of a valid write operation of a memory device in accordance with examples disclosed herein is shown. The process flow 300 may implement one or more aspects of the system 100 and the architecture 200 or may be implemented by one or more aspects of the system 100 and the architecture 200. For example, the process flow 300 may depict an instance of signaling between a memory system 305 and a host system 310, which may be an instance of a corresponding aspect described for reference Figure 1 described. The process flow 300 may support the memory system 305 indicating the status of a write operation to write data to one or more memory cells of the memory system 305, which may be an instance of the memory cells 205 described for reference Figure 2 described. Alternative instances may be implemented, where some processes are performed in a different order than described or not performed. In some cases, the process may include additional features not mentioned below, or additional processes may be added.

[0048] At 315, the memory system 305 may receive a write command from the host system 310. In some cases, the write command may indicate data to be written to one or more memory cells of the memory system 305.

[0049] At 320, in some instances, the memory system 305 may attempt to decode the write command based on receiving the write command (e.g., as part of initiating a write operation or to support initiating a write operation). For example, the memory system 305 may identify data to be written and an address space corresponding to one or more memory cells based on decoding the write command, which may support the memory system 305 in initiating a write operation associated with the write command. In some other instances, the memory system 305 may not successfully decode the write command (e.g., a command execution failure), which may prevent the memory system 305 from successfully executing the write command (e.g., rendering the write operation invalid).

[0050] At 325, in some instances, the memory system 305 may initiate a write operation to write data to one or more memory cells based on receiving and decoding the write command. In some cases, the memory system 305 may successfully initiate the write operation (e.g., the write operation is valid). In some other cases, the memory system 305 may experience a failure in receiving or decoding the command, which may cause the memory system 305 to not successfully initiate the write operation (e.g., the write operation is invalid). For example, the command may be associated with a packet failure (e.g., the command indicates corrupted or incorrect data), the input buffer of the memory system 305 may be full or otherwise malfunction, the memory system 305 may be operating in a mode (e.g., self-refresh mode) in which the memory system 305 is unable to receive and / or execute commands, and the memory system 305 fails to exit the mode of receiving commands, the hardware of the memory system 305 fails to operate correctly, or any combination thereof.

[0051] At 330, in some instances, the memory system 305 may complete the write operation (e.g., based on successfully decoding the write command and initiating the write operation). For example, the memory system 305 may successfully write data to one or more memory cells (e.g., verify the write operation). In some other instances, the memory system 305 may not successfully complete the write operation (e.g., a command execution failure) and may not be able to write data to one or more memory cells (e.g., render the write operation invalid). If the memory system 305 does not successfully complete the write operation, the data to be written may be lost (e.g., old data may still be stored in one or more memory cells).

[0052] At 335, the memory system 305 may adjust the value of a mode register according to the status of a write operation. For example, if the memory system 305 successfully executes and completes the write operation at 330, then the memory system 305 may adjust the mode register from a first value (e.g., a binary value '0', which may be a default value) to a second value (e.g., a binary value '1'), where the second value may indicate that the write operation is valid. In some cases, the memory system 305 may adjust the mode register value at various stages of the write operation. As a first example, the memory system 305 may adjust the value of the mode register to the second value based on successfully decoding a write command and initiating the write operation (e.g., at operations 320 and 325) (e.g., after successfully decoding the write command and initiating the write operation, when successfully decoding the write command and initiating the write operation, or in response to successfully decoding the write command and initiating the write operation). As a second example, the memory system 305 may adjust the value of the mode register to the second value based on successfully completing the write operation (e.g., at operation 330). The stage of the memory access operation that triggers the memory system 305 to adjust the mode register value (e.g., the decode and initiate operation or the complete operation) may be based on the target robustness of the fault detection scheme, the location of the fault detection circuitry, or both. Additionally or alternatively, the memory system 305 may operate to switch the trigger for adjusting the mode register value (e.g., dynamically) between various stages of the write operation.

[0053] In some instances, if the memory system 305 fails to successfully execute a write operation, then the memory system 305 may avoid adjusting the value of the mode register. For example, if the memory system 305 fails to decode and initiate or fails to complete the write operation (e.g., based on the trigger for setting the mode register value), then the memory system 305 may avoid adjusting the value of the mode register (e.g., the value of the mode register may remain at the default value). The default value of the mode register may indicate that the write operation is invalid (e.g., not completed).

[0054] At 340, the memory system 305 may transmit a validity signal indicating the validity of a write operation to the host system 310. In some cases, to transmit the validity signal, the memory system 305 may load the value of a mode register into a pin configured to indicate the validity of a write operation (e.g., bias the pin according to the mode register value). For example, if the memory system 305 identifies that a write operation is valid, the memory system 305 may set the mode register from a first value to a second value and may bias the pin from a first voltage to a second voltage (e.g., the second voltage indicates that the write operation is valid). Additionally or alternatively, the memory system 305 may bias the pin to the second voltage after identifying that the write operation is valid (e.g., without adjusting the value of the mode register). In some instances, the pin may be an example of a DSF pin (e.g., a direct media interface (DMI) I / O pin that is used as DSF+ during a read operation to output a status or flag failure before the start of a data burst) or an alert pin (e.g., a double data rate 4 (DDR4) and / or low power DDR6 (LPDDR6) alert pin that is output to indicate a failure state) or some other type of pin coupled to the memory system 305 and the host system 310.

[0055] By adjusting the value of the mode register, biasing the pin, or both, according to the validity (or status) of a write command, the memory system 305 may improve fault detection in command execution, which may support the memory system 305 in meeting one or more FIT rate constraints (e.g., units representing failure rates and how many failures occur per 10 9 hours). For example, the memory system 305 may operate to perform a functional safety application (e.g., an automotive functional safety application), which may be associated with a FIT rate constraint, such as undetected <0.4 FIT (e.g., for a stand-alone DRAM device in automotive safety integrity level (ASIL) D). In some instances, one or more ECC schemes implemented by the memory system 305 (e.g., host inline ECC and link ECC) may not be suitable for detecting faults during command execution (e.g., faults during decoding, starting, or completing a command). For example, such ECC schemes may be configured to detect whether the values stored into the memory array are correct (e.g., detect data corruption). In such instances, if the memory system 305 fails to execute a write command, the memory system 305 cannot overwrite the old data with the new data indicated in the write command. However, if the old data does not contain an error (e.g., is not corrupted), the ECC scheme does not detect an error in the data and the host system 310 may still not know about the command execution fault. Thus, the memory system 305 may improve command execution fault detection by indicating the validity of an access operation via the value of the mode register and / or the pin, which may support the memory system 305 in meeting the FIT rate constraints of one or more applications (e.g., automotive functional safety applications).

[0056] At 345, the host system 310 may poll the mode register based on a transmitted write command. In some cases, the host system 310 may identify the value of the mode register based on polling the mode register, which may indicate the validity of a write operation at the memory system 305. In some instances, the host system 310 may determine whether to issue a command to the memory system 305 to perform a retransmission of the write command or to perform a subsequent access command based on the value of the mode register. For example, if the host system 310 identifies that the write command has been successfully executed (e.g., based on the mode register being set to a second value) and the host system 310 does not have a subsequent access command queued for transmission to the memory system 305, then the host system 310 may avoid issuing another command to the memory system 305. Additionally or alternatively, the host system 310 may poll the pin and may identify the validity of the write operation based on the value of the pin (e.g., a DSF pin or an alert pin) according to a validity signal received from the memory system 305 (e.g., at 340).

[0057] At 350, in some instances, the host system 310 may transmit a command to reset the value of the mode register to the memory system 305. For example, the host system 310 may determine the value of the mode register (which may be referred to as a first value, a second value, a'set' mode register value, a binary value '1', or the like) based on polling the mode register and may indicate that the write operation is valid. In such instances, the host system 310 may transmit a command to reset the value of the mode register back to a default value (e.g., from a'set' value to an 'unset' value) based on determining that the value of the mode register indicates that the write operation is valid. Such techniques may support the memory system 305 indicating the validity of subsequent access operations.

[0058] At 355, in some instances, the host system 310 may transmit one or more commands to the memory system 305 based on the value of the mode register, a validity signal indicated via a pin, or both. As a first example, the host system 310 may determine to transmit a subsequent access command to the memory system 305 based on the value of the mode register indicating that the write operation is valid. In such instances, the subsequent access command may be an instance of a read command indicating that data is to be read from one or more memory cells, or may be an instance of a second write command indicating that a second data is to be written to one or more memory cells (or one or more second memory cells of the memory system 305). In some cases, if the subsequent access command is a second write command, then the memory system 305 may indicate the validity of the second write operation associated with the second write command via the mode register value (or the pin) according to operations 320 to 340. For example, the memory system 305 may avoid adjusting the value of the mode register from a first value to a second value based on a failure to decode or complete (e.g., according to a trigger of the set mode register value) the second write command, where the first value may indicate that the second write operation is invalid.

[0059] As a second example, the host system 310 may determine a retransmission of a write command to the memory system 305 based on the value of the mode register indicating that the write operation is invalid. In some cases, the memory system 305 may receive the retransmission of the write command, may restart the write operation (e.g., attempt to execute the write command again), and may adjust the mode register value based on the validity of the write operation (e.g., avoid adjusting the mode register value if the write operation is still unsuccessful, or adjust the mode register value to a second value if the write operation is successful). In some examples, the host system 310 may transmit an erase command to erase data from one or more memory cells (e.g., clear the data) before issuing a retransmission of the write command. In some examples, the host system 310 may continue to retransmit the write command until the write operation at the memory system 305 is successful (e.g., the host system 310 identifies the mode register value as the second value).

[0060] As a third example, the host system 310 may determine to deactivate an address space associated with one or more memory cells based on the write operation being invalid. For example, the host system 310 may identify that write operations at the address space are more likely to be unsuccessful (e.g., the address space is associated with a threshold number of command execution failures, the number of command execution failures is greater than one or more other address spaces of the memory system, or both), and may transmit a command to the memory system 305 indicating deactivation of the address space. In some examples, if the host system 310 determines to issue a retransmission of the write command, the retransmission of the write command may indicate writing data to one or more second memory cells of the memory system that are different from (e.g., associated with a different address space than) one or more first memory cells.

[0061] As a fourth example, the host system 310 may pause the execution of an application associated with a write command based on the mode register value indicating that the write operation is invalid. For example, the host system 310 may transmit a command to the memory system 305 indicating that the memory system 305 is to pause (e.g., temporarily terminate) the application associated with the write command, which may support the host system 310 in performing one or more corrective actions, such as retransmitting the write command, deactivating the address space associated with the write command, or both, and other examples.

[0062] Such techniques may improve the detection of command execution failures, which may support the memory system 305 in meeting FIT rate constraints and mitigating data loss, and other examples.

[0063] Figure 4 FIG. 400 is a block diagram of a memory system 420 that supports effective write operation detection of a memory device in accordance with examples disclosed herein. The memory system 420 may be a reference Figures 1 to 3Examples of aspects of the described memory system. Memory system 420 or its various components can be examples of components for performing various aspects of effective write operation detection of a memory device as described herein. For example, memory system 420 can include a command receiving component 425, a command initiating component 430, a mode register adjustment component 435, a pin biasing component 440, a command decoding component 445, a command execution component 450, a signal transmission component 455, or any combination thereof. Components (e.g., one or more processors, one or more memories) of each of these components or sub-components can communicate with each other directly or indirectly (e.g., via one or more buses).

[0064] The command receiving component 425 can be configured to or otherwise support a component for receiving a write command indicating that data is to be written to one or more memory cells of the memory system. The command initiating component 430 can be configured to or otherwise support a component for initiating a write operation to write data to one or more memory cells at least in part based on the write command. The mode register adjustment component 435 can be configured to or otherwise support a component for adjusting the value of a mode register from a first value to a second value at least in part based on initiating the write operation, where the value of the mode register indicates the effectiveness of the write operation.

[0065] In some instances, the command decoding component 445 can be configured to or otherwise support a component for decoding the write command at least in part based on receiving the write command. In some instances, the mode register adjustment component 435 can be configured to or otherwise support a component for adjusting the value of the mode register to a second value at least in part based on decoding the write command and initiating the write operation, where the second value indicates that the write operation is valid.

[0066] In some instances, the command execution component 450 can be configured to or otherwise support a component for completing the write operation at least in part based on initiating the write operation. In some instances, the mode register adjustment component 435 can be configured to or otherwise support a component for adjusting the value of the mode register to a second value at least in part based on completing the write operation, where the second value indicates that the write operation is valid.

[0067] In some instances, the command receiving component 425 can be configured to or otherwise support a component for receiving a second write command indicating that second data is to be written to one or more second memory cells of the memory system after adjusting the mode register back to the first value. In some instances, the mode register adjustment component 435 can be configured to or otherwise support a component for avoiding adjusting the value of the mode register from the first value to the second value at least in part based on a failure to decode the second write command, where the first value indicates that the write operation is invalid.

[0068] In some instances, the command receiving component 425 may be configured to or otherwise support components for receiving a retransmission of a second write command indicating that second data is written to one or more second memory cells of the memory system, at least in part based on avoiding adjusting a value of a mode register.

[0069] In some instances, the signal transmission component 455 may be configured to or otherwise support components for transmitting, via a pin and at least in part based on adjusting a value of a mode register to a second value, a signal indicating the validity of a write operation to a host device.

[0070] In some instances, the pin includes a decoded status flag or an alert pin.

[0071] In some instances, the first value includes a first binary value of a mode register and the second value includes a second binary value of the mode register.

[0072] In some instances, the command receiving component 425 may be configured to or otherwise support components for receiving a write command indicating that data is written to one or more memory cells of the memory system. In some instances, the command initiation component 430 may be configured to or otherwise support components for initiating a write operation to write data to one or more memory cells, at least in part based on the write command. The pin biasing component 440 may be configured to or otherwise support components for biasing a pin from a first value to a second value, at least in part based on initiating the write operation, where the value of the pin indicates the validity of the write operation.

[0073] In some instances, the command decoding component 445 may be configured to or otherwise support components for decoding a write command, at least in part based on receiving the write command. In some instances, the pin biasing component 440 may be configured to or otherwise support components for biasing the pin to a second value, at least in part based on decoding and initiating the write operation, where the second value indicates that the write operation is valid.

[0074] In some instances, the pin includes a decoded status flag or an alert pin.

[0075] In some instances, the described functionality of the memory system 420 or its various components may be supported by at least a portion of at least one processor or may refer to at least a portion of at least one processor, where the at least one processor may include one or more processing elements (such as a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some instances, the described functionality of the memory system 420 or its various components may be implemented, at least in part, by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) executable by the at least one processor.

[0076] Figure 5 FIG. 500 is a block diagram of a host system 520 that supports detection of a valid write operation of a memory device in accordance with an example disclosed herein. The host system 520 may be an example of aspects of the host system described in reference Figures 1 to 3 The host system 520 or its various components may be examples of components for performing various aspects of detecting a valid write operation of a memory device as described herein. For example, the host system 520 may include a command transmission component 525, a mode register polling component 530, a command management component 535, a mode register adjustment component 540, a signal receiving component 545, an application management component 550, an address space management component 555, or any combination thereof. Components of each of these components or sub-components (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0077] The command transmission component 525 may be configured to or otherwise support a component for transmitting from the host system a write command indicating writing of data to one or more memory cells of the memory system. The mode register polling component 530 may be configured to or otherwise support a component for polling a mode register of the memory system at least in part based on the write command, where the value of the mode register indicates the validity of a write operation at the memory system. The command management component 535 may be configured to or otherwise support a component for determining whether to issue a command to the memory system to perform a retransmission of the write command or a subsequent access command at least in part based on the value of the mode register.

[0078] In some examples, the mode register polling component 530 may be configured to or otherwise support a component for determining that the value of the mode register includes a first value indicating that a write operation is valid at least in part based on polling the mode register. In some examples, the mode register adjustment component 540 may be configured to or otherwise support a component for resetting the value of the mode register from the first value to a second value at least in part based on determining that the value of the mode register includes the first value.

[0079] In some examples, to support determining whether to issue a command to the memory system, the command management component 535 may be configured to or otherwise support a component for determining to transmit a subsequent access command to the memory system at least in part based on the value of the mode register indicating that a write operation is valid, where the subsequent access command includes a read command indicating reading of data from one or more memory cells or a second write command indicating writing of second data to one or more memory cells.

[0080] In some instances, to support determining whether to issue a command to a memory system, the command management component 535 may be configured to or otherwise support components for determining a retransmission of a write command to the memory system based at least in part on a value of a mode register that includes a second value indicating that a write operation is invalid.

[0081] In some instances, the command transmission component 525 may be configured to or otherwise support components for transmitting an erase command to erase data from one or more memory cells based at least in part on a write operation being invalid. In some instances, the command transmission component 525 may be configured to or otherwise support components for transmitting a retransmission of a write command based at least in part on the erase command.

[0082] In some instances, the application management component 550 may be configured to or otherwise support components for pausing the execution of an application associated with a write command based at least in part on a write operation being invalid.

[0083] In some instances, the address space management component 555 may be configured to or otherwise support components for deactivating an address space associated with one or more memory cells based at least in part on a write operation being invalid, wherein a retransmission of a write command indicates data is written to one or more second memory cells of a memory system different from the one or more memory cells based at least in part on the deactivated address space.

[0084] In some instances, the signal receiving component 545 may be configured to or otherwise support components for receiving via a pin a signal indicating the validity of a write operation, wherein determining whether to issue a command is based at least in part on the received signal.

[0085] In some instances, the pin includes a decoded status flag or an alert pin.

[0086] In some instances, the described functionality of the host system 520 or its various components may be supported by at least a portion of at least one processor or may refer to at least a portion of at least one processor, wherein the at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some instances, the described functionality of the host system 520 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) executable by the at least one processor.

[0087] Figure 6FIG. 600 is a flow chart showing a method for detecting an effective write operation of a memory device in support of an example disclosed herein. Operations of method 600 may be implemented by the memory system or components thereof described herein. For example, operations of method 600 may be performed by the memory system referenced Figures 1 to 4 as described. In some examples, the memory system may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0088] At 605, the method may include receiving a write command indicating that data is to be written to one or more memory cells of the memory system. In some examples, aspects of operation 605 may be performed by the command receiving component 425 referenced Figure 4 as described.

[0089] At 610, the method may include initiating a write operation to write the data to the one or more memory cells based at least in part on the write command. In some examples, aspects of operation 610 may be performed by the command initiation component 430 referenced Figure 4 as described.

[0090] At 615, the method may include adjusting a value of a mode register from a first value to a second value based at least in part on initiating the write operation, where the value of the mode register indicates the effectiveness of the write operation. In some examples, aspects of operation 615 may be performed by the mode register adjustment component 435 referenced Figure 4 as described.

[0091] In some examples, a device described herein may perform one or several methods such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing the following aspects of the present disclosure:

[0092] Aspect 1: A method, device, or non-transitory computer-readable medium includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a write command indicating that data is to be written to one or more memory cells of a memory system; initiating a write operation to write the data to the one or more memory cells based at least in part on the write command; and adjusting a value of a mode register from a first value to a second value based at least in part on initiating the write operation, where the value of the mode register indicates the effectiveness of the write operation.

[0093] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to Aspect 1, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: decoding the write command at least in part based on receiving the write command, wherein adjusting the value of the mode register comprises adjusting the value of the mode register to the second value at least in part based on decoding the write command and initiating the write operation, wherein the second value indicates that the write operation is valid.

[0094] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 2, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: completing the write operation at least in part based on initiating the write operation, wherein adjusting the value of the mode register comprises adjusting the value of the mode register to the second value at least in part based on completing the write operation, wherein the second value indicates that the write operation is valid.

[0095] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 3, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: after adjusting the mode register back to the first value, receiving a second write command indicating that second data is written to one or more second memory cells of the memory system; and avoiding adjusting the value of the mode register from the first value to the second value at least in part based on a failure to decode the second write command, wherein the first value indicates that the write operation is invalid.

[0096] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to Aspect 4, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a retransmission of the second write command indicating that the second data is written to the one or more second memory cells of the memory system at least in part based on avoiding adjusting the value of the mode register.

[0097] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 5, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: transmitting a signal indicating the validity of the write operation to a host device via a pin and at least in part based on adjusting the value of the mode register to the second value.

[0098] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to Aspect 6, wherein the pin comprises a decoded status flag or an alert pin.

[0099] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 7, wherein the first value comprises a first binary value of the mode register and the second value comprises a second binary value of the mode register.

[0100] Figure 7 FIG. 700 is a flow diagram illustrating a method for detecting an effective write operation of a memory device in support of an example disclosed herein. The operations of method 700 may be implemented by a host system or components thereof described herein. For example, the operations of method 700 may be performed by the host system referenced Figures 1 to 3 and described in FIGS. 5. In some instances, the host system may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0101] At 705, the method may include transmitting, from the host system, a write command indicating data to be written to one or more memory cells of the memory system. In some instances, aspects of operation 705 may be performed by the command transmission component 525 referenced Figure 5 and described in FIGS.

[0102] At 710, the method may include polling a mode register of the memory system at least in part based on the write command, wherein the value of the mode register indicates the effectiveness of a write operation at the memory system. In some instances, aspects of operation 710 may be performed by the mode register polling component 530 referenced Figure 5 and described in FIGS.

[0103] At 715, the method may include determining, at least in part based on the value of the mode register, whether to issue a command to the memory system to perform a retransmission of the write command or a subsequent access command. In some instances, aspects of operation 715 may be performed by the command management component 535 referenced Figure 5 and described in FIGS.

[0104] In some instances, a device described herein may perform one or several methods such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure or any combination thereof:

[0105] Aspect 9: A method, apparatus, or non-transitory computer-readable medium includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: transmitting a write command from a host system indicating data to be written to one or more memory cells of a memory system; polling a mode register of the memory system at least in part based on the write command, wherein a value of the mode register indicates the validity of a write operation at the memory system; and determining whether to issue a command to the memory system to perform a retransmission of the write command or a subsequent access command at least in part based on the value of the mode register.

[0106] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of aspect 9, further including operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: determining that the value of the mode register includes a first value indicating the write operation is valid at least in part based on polling the mode register; and resetting the value of the mode register from the first value to a second value at least in part based on determining that the value of the mode register includes the first value.

[0107] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 9-10, wherein determining whether to issue the command to the memory system includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: determining to transmit the subsequent access command to the memory system at least in part based on the value of the mode register indicating the write operation is valid, wherein the subsequent access command includes a read command indicating the data is to be read from the one or more memory cells or a second write command indicating second data is to be written to the one or more memory cells.

[0108] Aspect 12: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 9-11, wherein determining whether to issue the command to the memory system includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: determining to transmit the retransmission of the write command to the memory system at least in part based on the value of the mode register including a second value indicating the write operation is invalid.

[0109] Aspect 13: The method, apparatus, or non-transitory computer-readable medium of aspect 12, further including operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: transmitting an erase command to erase the data from the one or more memory cells at least in part based on the write operation being invalid; and transmitting the retransmission of the write command at least in part based on the erase command.

[0110] Aspect 14: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 12 to 13 further includes operations, features, circuitry, logic, components, or instructions, or any combination thereof for: at least partially suspending the execution of an application associated with the write command based on the invalidity of the write operation.

[0111] Aspect 15: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 12 to 14 further includes operations, features, circuitry, logic, components, or instructions, or any combination thereof for: at least partially deactivating an address space associated with the one or more memory cells based on the invalidity of the write operation, wherein the retransmission of the write command indicates that the data is written to one or more second memory cells of the memory system different from the one or more memory cells at least partially based on deactivating the address space.

[0112] Aspect 16: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 9 to 15 further includes operations, features, circuitry, logic, components, or instructions, or any combination thereof for: receiving, via a pin, a signal indicating the validity of the write operation, wherein determining whether to issue the command is at least partially based on receiving the signal.

[0113] Aspect 17: The method, apparatus, or non-transitory computer-readable medium according to Aspect 16, wherein the pin includes a decoded status flag or an alert pin.

[0114] Figure 8 FIG. 800 is a flow diagram illustrating a method for detecting a valid write operation of a memory device in accordance with an example disclosed herein. The operations of method 800 may be implemented by the memory system or components thereof described herein. For example, the operations of method 800 may be performed by the memory system referenced Figures 1 to 4 described. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0115] At 805, the method may include receiving a write command indicating data to be written to one or more memory cells of a memory system. In some instances, aspects of operation 805 may be performed by the command receiving component 425 referenced Figure 4 described.

[0116] At 810, the method may include initiating a write operation to write the data to the one or more memory cells at least partially based on the write command. In some instances, aspects of operation 810 may be performed by the command initiating component 430 referenced Figure 4 described.

[0117] At 815, the method can include biasing a pin from a first value to a second value at least in part based on initiating a write operation, where the value of the pin indicates the validity of the write operation. In some instances, aspects of operation 815 can be performed by the pin biasing component 440 described with reference to Figure 4 FIG.

[0118] In some instances, the devices described herein can perform one or more methods such as method 800. The device can include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure or any combination thereof:

[0119] Aspect 18: A method, device, or non-transitory computer-readable medium includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a write command indicating data to be written to one or more memory cells of a memory system; initiating a write operation at least in part based on the write command to write the data to the one or more memory cells; and biasing a pin from a first value to a second value at least in part based on initiating the write operation, where the value of the pin indicates the validity of the write operation.

[0120] Aspect 19: The method, device, or non-transitory computer-readable medium according to aspect 18, further includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: decoding the write command at least in part based on receiving the write command, where biasing the pin includes biasing the pin to the second value at least in part based on decoding and initiating the write operation, where the second value indicates that the write operation is valid.

[0121] Aspect 20: The method, device, or non-transitory computer-readable medium according to any one of aspects 18 to 19, further includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: completing the write operation at least in part based on initiating the write operation; and biasing the pin to the second value at least in part based on completing the write operation, where the second value indicates that the write operation is valid.

[0122] Aspect 21: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 18 to 20, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: after adjusting the pin back to the first value, receiving a second write command indicating that second data is written to one or more second memory cells of the memory system; and avoiding adjusting the bias of the pin from the first value to the second value at least in part based on a failure to decode the second write command, wherein the first value indicates that the write operation is invalid.

[0123] Aspect 22: The method, apparatus, or non-transitory computer-readable medium according to aspect 21, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a retransmission of the second write command indicating that the second data is written to the one or more second memory cells of the memory system at least in part based on avoiding adjusting the bias of the pin.

[0124] Aspect 23: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 18 to 22, wherein the pin includes a decode status flag or an alert pin.

[0125] Note that the aspect descriptions herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, parts from two or more of the methods may be combined.

[0126] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate the signal as a single signal; however, the signal may represent a bus of signals, where the bus may have various bit widths.

[0127] The terms "electronically communicate", "electrically contact", "connect", and "couple" can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be electronically communicating (e.g., electrically contacting, connecting, coupling) with each other if there is any circuit path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. Based on the operation of the device that includes the connected components, the conductive path between components that are electronically communicating (e.g., electrically contacting, connecting, coupling) can be an open circuit or a closed circuit. The conductive path between the connected components can be a direct conductive path between the components or can be an indirect conductive path that includes intermediate components (e.g., switches, transistors, or other components). In some instances, the flow of signals between the connected components can be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0128] The switching components (e.g., transistors) discussed herein can be field effect transistors (FETs) and can include a source (e.g., source terminal), a drain (e.g., drain terminal), a channel between the source and the drain, and a gate (e.g., gate terminal). The conductivity of the channel can be controlled (e.g., modulated) by applying a voltage to the gate, which in some instances can cause the channel to become conductive. The switching component can be an example of an n-type FET or a p-type FET.

[0129] The example configurations described herein are described in conjunction with the accompanying drawings and do not represent all examples that can be implemented or that are within the scope of the claims. The detailed description includes specific details to provide an understanding of the described techniques. However, the techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0130] In the drawings, like components or features can have the same reference numeral. Like components can be distinguished by following the reference numeral with one or more dashes and an additional numeral that differentiates the like components. If only the first reference numeral is used in the specification, the description applies to any one of the like components having the same first reference numeral, regardless of the additional reference numerals.

[0131] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions (e.g., code). Because of the nature of software, the functions described herein may be implemented using software, hardware, firmware, hardwiring, or any combination of these. The features implementing the functions may be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations.

[0132] The illustrative blocks and modules described herein may be implemented or executed with one or more processors (e.g., DSP, ASIC, FPGA), discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof designed to perform the functions described herein. The processor may be an example of a microprocessor, controller, microcontroller, state machine, or other type of processor. The processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0133] As used herein (including in the claims), the "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0134] As used herein (including in the claims), the article "a" before a noun is open-ended and should be understood to refer to "at least one" of those nouns or "one or more" of those nouns. Thus, the terms "a", "at least one", "one or more", "at least one of one or more" are interchangeable. For example, if a claim recites "a component" that performs one or more functions, then each of the individual functions may be performed by a single component or any combination of multiple components. Thus, the term "a component" with a particular or performing function may refer to "at least one of one or more components" having a particular characteristic or performing a particular function. Subsequently using the term "the / said" to refer to a component introduced with the article "a" may refer to any or all of one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components", and subsequently referring to "the component" in the claim may be understood as equivalent to referring to "at least one of one or more components". Similarly, subsequently using the term "the / said" to refer to a component introduced as "one or more components" may refer to any or all of one or more components. For example, subsequently referring to "one or more components" in the claim may be understood as equivalent to referring to "at least one of one or more components".

[0135] A computer-readable medium includes both a non-transitory computer storage medium and a communication medium, which includes any medium that facilitates transfer of a computer program from one location to another. The non-transitory storage medium can be any available medium or combination of media accessible by a computer. By way of example, and not limitation, a non-transitory computer-readable medium can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage, or other magnetic storage devices, or any other non-transitory medium or combination of media that can be used to carry or store desired program code instructions or data structures in the form of and accessible by a computer or processor.

[0136] Descriptions and schematics are provided to enable one of ordinary skill in the art to make or use the present disclosure. One of ordinary skill in the art will appreciate various modifications to the present disclosure, and without departing from the scope of the present disclosure, the techniques disclosed herein can be applied to other variations. Thus, the present disclosure is not limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, comprising: processing circuitry associated with one or more memory devices and configured to cause the apparatus to: receive a write command indicating data to be written to one or more memory cells of a memory system; initiate a write operation to write the data to the one or more memory cells at least in part based on the write command; and adjust a value of a mode register from a first value to a second value at least in part based on initiating the write operation, wherein the value of the mode register indicates the validity of the write operation.

2. The apparatus of claim 1, wherein the processing circuitry is further configured to cause the apparatus to: decode the write command at least in part based on receiving the write command, wherein, to adjust the value of the mode register, the processing circuitry is configured to cause the apparatus to: adjust the value of the mode register to the second value at least in part based on decoding the write command and initiating the write operation, wherein the second value indicates that the write operation is valid.

3. The apparatus of claim 1, wherein the processing circuitry is further configured to cause the apparatus to: complete the write operation at least in part based on initiating the write operation, wherein, to adjust the value of the mode register, the processing circuitry is configured to cause the apparatus to: adjust the value of the mode register to the second value at least in part based on completing the write operation, wherein the second value indicates that the write operation is valid.

4. The apparatus of claim 1, wherein the processing circuitry is further configured to cause the apparatus to: after adjusting the mode register back to the first value, receive a second write command indicating second data to be written to one or more second memory cells of the memory system; and avoid adjusting the value of the mode register from the first value to the second value at least in part based on a failure to decode the second write command, wherein the first value indicates that the write operation is invalid.

5. The apparatus of claim 4, wherein the processing circuitry is further configured to cause the apparatus to: receive a retransmission of the second write command indicating the second data to be written to the one or more second memory cells of the memory system at least in part based on avoiding adjusting the value of the mode register.

6. The apparatus of claim 1, wherein the processing circuitry is further configured to cause the apparatus to: transmit a signal indicating the validity of the write operation to a host device via a pin and at least in part based on adjusting the value of the mode register to the second value.

7. The apparatus of claim 6, wherein the pin includes a decode status flag or an alert pin.

8. The apparatus of claim 1, wherein the first value includes a first binary value of the mode register and the second value includes a second binary value of the mode register.

9. An apparatus, comprising: processing circuitry associated with one or more memory devices and configured to cause the apparatus to: Transmit a write command from a host system indicating data to be written to one or more memory cells of a memory system; Poll a mode register of the memory system at least in part based on the write command, wherein a value of the mode register indicates the validity of a write operation at the memory system; And Determine whether to issue a command to the memory system to perform a retransmission of the write command or a subsequent access command at least in part based on the value of the mode register.

10. The apparatus according to claim 9, wherein the processing circuitry is further configured to cause the apparatus to: Determine that the value of the mode register includes a first value indicating the write operation is valid at least in part based on polling the mode register; and Reset the value of the mode register from the first value to a second value at least in part based on determining that the value of the mode register includes the first value.

11. The apparatus according to claim 9, wherein to determine whether to issue the command to the memory system, the processing circuitry is configured to cause the apparatus to: Determine to transmit the subsequent access command to the memory system at least in part based on the value of the mode register indicating the write operation is valid, wherein the subsequent access command includes a read command indicating the data is to be read from the one or more memory cells or a second write command indicating second data is to be written to the one or more memory cells.

12. The apparatus according to claim 9, wherein to determine whether to issue the command to the memory system, the processing circuitry is configured to cause the apparatus to: Determine to transmit the retransmission of the write command to the memory system at least in part based on the value of the mode register including a second value indicating the write operation is invalid.

13. The apparatus according to claim 12, wherein the processing circuitry is further configured to cause the apparatus to: Transmit an erase command to erase the data from the one or more memory cells at least in part based on the write operation being invalid; and Transmit the retransmission of the write command at least in part based on the erase command.

14. The apparatus according to claim 12, wherein the processing circuitry is further configured to cause the apparatus to: Pause execution of an application associated with the write command at least in part based on the write operation being invalid.

15. The apparatus according to claim 12, wherein the processing circuitry is further configured to cause the apparatus to: Deactivate an address space associated with the one or more memory cells at least in part based on the write operation being invalid, wherein the retransmission of the write command indicates the data is to be written to one or more second memory cells of the memory system different from the one or more memory cells at least in part based on deactivating the address space.

16. The apparatus according to claim 9, wherein the processing circuitry is further configured to cause the apparatus to: Receive a signal via a pin indicating the validity of the write operation, wherein determining whether to issue the command is at least partially based on receiving the signal.

17. The apparatus of claim 16, wherein the pin comprises a decoded status flag or an alert pin.

18. An apparatus comprising: Processing circuitry associated with one or more memory devices and configured to cause the apparatus to: Receive a write command indicating data to be written to one or more memory cells of a memory system; Initiate a write operation to write the data to the one or more memory cells at least partially based on the write command; And Bias a pin from a first value to a second value at least partially based on initiating the write operation, wherein the value of the pin indicates the validity of the write operation.

19. The apparatus of claim 18, wherein the processing circuitry is further configured to cause the apparatus to: Decode the write command at least partially based on receiving the write command, wherein to bias the pin, the processing circuitry is configured to cause the apparatus to: Bias the pin to the second value at least partially based on decoding and initiating the write operation, wherein the second value indicates that the write operation is valid.

20. The apparatus of claim 18, wherein the processing circuitry is further configured to cause the apparatus to: Complete the write operation at least partially based on initiating the write operation, wherein to bias the pin, the processing circuitry is configured to cause the apparatus to: Bias the pin to the second value at least partially based on completing the write operation, wherein the second value indicates that the write operation is valid.

21. The apparatus of claim 18, wherein the processing circuitry is further configured to cause the apparatus to: After adjusting the pin back to the first value, receive a second write command indicating second data to be written to one or more second memory cells of the memory system; and Avoid adjusting the bias of the pin from the first value to the second value at least partially based on a failure to decode the second write command, wherein the first value indicates that the write operation is invalid.

22. The apparatus of claim 21, wherein the processing circuitry is further configured to cause the apparatus to: Receive a retransmission of the second write command indicating the second data to be written to the one or more second memory cells of the memory system at least partially based on avoiding adjusting the bias of the pin.

23. The apparatus of claim 18, wherein the pin comprises a decoded status flag or an alert pin.

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