Preparation method of interlayer insulating layer
By performing low-temperature plasma treatment and TEOS film layer formation after high-density plasma vapor deposition process, the problem of uneven charge of interlayer insulating layers is solved, and the reliability and electrical performance of MOS devices are improved.
Patent Information
- Application Number
- CN202510379658.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-11
AI Technical Summary
During the preparation of the interlayer insulating layer of MOS devices, the high-density plasma vapor deposition process leads to uneven charges in the local area of the wafer surface, resulting in breakdown of the gate oxide layer, affecting device reliability.
After the oxidation dielectric layer is formed by a high-density plasma vapor deposition process, a low-temperature plasma treatment is performed, and a TEOS film layer is then formed on the oxidation dielectric layer. The surface charge of the oxidation dielectric layer is released through the low-temperature plasma treatment, reducing the potential difference and improving charge inhomogeneity.
Improves the reliability and electrical performance of the device and improves the yield of the device.
Smart Images
Figure CN120299984A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and particularly to a method for preparing an interlayer insulating layer. Background Art
[0002] In the manufacturing process of the interlayer insulating dielectric layer (ILD) of MOS devices, the mainstream manufacturing method is usually the high-density plasma chemical vapor deposition (HDP CVD) process. The plasma in the HDP CVD process will cause uneven charge in local areas of the wafer surface. The non-uniform charge will generate a relatively large local electric field, which will cause the gate oxide layer of the MOS device to be broken down, thereby affecting the reliability of the device and causing device failure. Summary of the Invention
[0003] This application provides a method for preparing an interlayer insulating layer, which can solve the problem that uneven charge in local areas of the wafer surface is caused during the preparation of the interlayer insulating layer of traditional MOS devices, resulting in the breakdown of the gate oxide layer and thus device failure.
[0004] An embodiment of this application provides a method for preparing an interlayer insulating layer, including:
[0005] Providing a substrate, in which an active region and a drain region are formed, a gate oxide layer is formed on the surface of the substrate, a gate electrode is located on the gate oxide layer, and sidewall structures are located on both sides of the gate electrode. The source region and the drain region are respectively located in the substrate on both sides of the sidewall structures;
[0006] Forming a barrier layer, the barrier layer covering the gate electrode, the sidewall structures and the substrate;
[0007] Forming an oxide dielectric layer by using the high-density plasma chemical vapor deposition process, the oxide dielectric layer covering the barrier layer;
[0008] Performing low-temperature plasma treatment on the semiconductor structure after forming the oxide dielectric layer;
[0009] Forming a TEOS film layer, the TEOS film layer covering the oxide dielectric layer, wherein the barrier layer, the oxide dielectric layer and the TEOS film layer constitute the interlayer insulating layer.
[0010] Optionally, in the method for preparing the interlayer insulating layer, during the process of performing low-temperature plasma treatment on the semiconductor structure after forming the oxide dielectric layer, the process temperature does not exceed 300°C, the gas participating in the plasma treatment is oxygen, and the treatment duration is 10 s to 600 s.
[0011] Optionally, in the method for preparing the interlayer insulating layer, during the process of forming the oxide dielectric layer by using a high-density plasma chemical vapor deposition process, the process temperature is 300°C to 800°C, and the reaction gases include silane and oxygen.
[0012] Optionally, in the method for preparing the interlayer insulating layer, the thickness of the oxide dielectric layer is
[0013]
[0014] Optionally, in the method for preparing the interlayer insulating layer, a TEOS film layer is formed by using a plasma-enhanced chemical vapor deposition process.
[0015] Optionally, in the method for preparing the interlayer insulating layer, after the TEOS film layer is formed, the method for preparing the interlayer insulating layer further includes:
[0016] Grinding a certain thickness of the TEOS film layer by using a chemical mechanical polishing process to planarize the surface of the interlayer insulating layer.
[0017] Optionally, in the method for preparing the interlayer insulating layer, the barrier layer is formed by using a chemical vapor deposition process.
[0018] Optionally, in the method for preparing the interlayer insulating layer, the material of the barrier layer is silicon nitride.
[0019] Optionally, in the method for preparing the interlayer insulating layer, the thickness of the barrier layer is
[0020] The technical solution of the present application has at least the following advantages:
[0021] The present application provides a method for preparing an interlayer insulating layer. After forming a barrier layer covering the gate, an oxide dielectric layer is formed by using a high-density plasma chemical vapor deposition process. Subsequently, the semiconductor structure after forming the oxide dielectric layer is subjected to low-temperature plasma treatment. Finally, a TEOS film layer is formed on the oxide dielectric layer. By performing one-step low-temperature plasma treatment after using the high-density plasma chemical vapor deposition process to prepare the oxide dielectric layer, through the low-temperature plasma treatment, the surface charges of the oxide dielectric layer can be released, the surface potential difference of the oxide dielectric layer can be reduced, and the negative charges in the oxide dielectric layer can be removed, thereby improving the uneven charges in the oxide dielectric layer, improving the reliability of the device, and increasing the yield and electrical performance of the device. Description of the Drawings
[0022] To more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0023] Figure 1 is a flowchart of the method for preparing the interlayer insulating layer according to an embodiment of the present invention;
[0024] Figures 2 - 5 is a schematic diagram of the semiconductor structure in each process step of preparing the interlayer insulating layer according to an embodiment of the present invention;
[0025] Among them, the reference numerals are explained as follows:
[0026] 10 - Substrate, 11 - First well region, 12 - Second well region, 13 - First lightly doped drain region, 14 - Second lightly doped drain region, 15 - First source region, 16 - First drain region, 17 - Second source region, 18 - Second drain region, 20 - Shallow trench isolation structure, 21 - First gate oxide layer, 22 - Second gate oxide layer, 31 - First gate electrode, 32 - Second gate electrode, 41 - First sidewall, 42 - Second sidewall, 43 - Third sidewall, 50 - Barrier layer, 60 - Oxide dielectric layer, 70 - TEOS film layer. Specific embodiments
[0027] The following will clearly and completely describe the technical solutions in the present application with reference to the drawings. Obviously, the described embodiments are some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.
[0028] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0029] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection through an intermediate medium, and it may also be the communication inside two components. It may be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.
[0030] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0031] An embodiment of the present application provides a method for preparing an interlayer insulating layer. Refer to Figure 1 , Figure 1 which is a flowchart of the method for preparing the interlayer insulating layer according to the embodiment of the present invention. The method for preparing the interlayer insulating layer includes:
[0032] First, perform step S1: Refer to Figure 2 , Figure 2 which is a schematic diagram of a semiconductor structure after forming a gate and sidewall structures. Provide a substrate, in which an active region and a drain region are formed. A gate oxide layer, a gate located on the gate oxide layer, and sidewall structures located on both sides of the gate are formed on the surface of the substrate. The source region and the drain region are respectively located in the substrate on both sides of the sidewall structures.
[0033] In this embodiment, taking the substrate 10 including two MOS device regions as an example, different MOS device regions are separated by a shallow trench isolation structure 20. A first well region 11 is formed in the substrate 10 of the left MOS device region; a second well region 12 is formed in the substrate 10 of the right MOS device region.
[0034] Further, on the substrate 10 of the left MOS device region, at least include: a first gate oxide layer 21, a first gate 31, a first sidewall 41, a second sidewall 42, and a third sidewall 43. The first gate oxide layer 21 is located on the substrate 10 of the left MOS device region, and the first gate 31 is located on the first gate oxide layer 21; on the substrate 10 of the right MOS device region, at least include: a second gate oxide layer 22, a second gate 32, a first sidewall 41, a second sidewall 42, and a third sidewall 43. The second gate oxide layer 22 is located on the substrate 10 of the left MOS device region, the second gate 32 is located on the second gate oxide layer 22, and the first sidewall 41, the second sidewall 42, and the third sidewall 43 are respectively located on both sides of the first gate 31 and the second gate 32.
[0035] In this embodiment, an active region 15, a drain region 16, and a first lightly doped drain region 13 are formed in the substrate 10 of the left MOS device region. The first lightly doped drain region 13 is located in the substrate 10 on both sides of the first gate 31. The source region 15 and the drain region 16 are located in the substrate 10 on both sides of the first gate 31, and a part of the source region 15 and a part of the drain region 16 are located in the first lightly doped drain region 13. In the substrate 10 of the right MOS device region, an active region 17, a drain region 18, and a second lightly doped drain region 14 are formed. The second lightly doped drain region 14 is located in the substrate 10 on both sides of the second gate 32. The source region 17 and the drain region 18 are located in the substrate 10 on both sides of the second gate 32, and a part of the source region 17 and a part of the drain region 18 are located in the second lightly doped drain region 14.
[0036] Among them, the sidewall 41, the sidewall 42, and the sidewall 43 constitute the sidewall structure.
[0037] Then, step S2 is executed: Refer to Figure 3 , Figure 3 is a schematic diagram of the semiconductor structure after forming the barrier layer in the embodiment of the present application. A barrier layer 50 is formed, and the barrier layer 50 covers the first gate 31, the sidewall structure, and the substrate 10.
[0038] Preferably, the barrier layer 50 is formed by a chemical vapor deposition process.
[0039] In this embodiment, the material of the barrier layer 50 is silicon nitride.
[0040] Preferably, the thickness of the barrier layer 50 is
[0041] Next, step S3 is executed: Refer to Figure 4 , Figure 4 is a schematic diagram of the semiconductor structure after forming the oxidation dielectric layer in the embodiment of the present application. An oxidation dielectric layer 60 is formed by a high-density plasma chemical vapor deposition process, and the oxidation dielectric layer 60 covers the barrier layer 50.
[0042] Preferably, during the process of forming the oxidation dielectric layer 60 by the high-density plasma chemical vapor deposition process, the process temperature is 300°C to 800°C, and the reaction gases include silane and oxygen.
[0043] Preferably, the thickness of the oxidation dielectric layer 60 is
[0044] Furthermore, step S4 is executed: The semiconductor structure after forming the oxidation dielectric layer 60 is subjected to low-temperature plasma treatment.
[0045] Preferably, during the low-temperature plasma treatment of the semiconductor structure after forming the oxidation medium layer 60, the process temperature does not exceed 300°C, the gas participating in the plasma treatment is oxygen, and the treatment duration is 10 s to 600 s.
[0046] In this embodiment, during the low-temperature plasma treatment of the semiconductor structure after forming the oxidation medium layer 60, the process temperature is 80°C to 100°C.
[0047] In this application, after preparing the oxidation medium layer by using the high-density plasma chemical vapor deposition process, a step of low-temperature plasma treatment is performed. Through the low-temperature plasma treatment, the surface charge of the oxidation medium layer can be released, the surface potential difference of the oxidation medium layer can be reduced, and the negative charges in the oxidation medium layer can be removed, thereby improving the uneven charges in the oxidation medium layer, improving the reliability of the device, and increasing the yield and electrical performance of the device.
[0048] Finally, perform step S5: Refer to Figure 5 , Figure 5 FIG. is a schematic diagram of the semiconductor structure after forming the TEOS film layer in the embodiment of the present application. The TEOS film layer 70 is formed, and the TEOS film layer 70 covers the oxidation medium layer. Among them, the barrier layer 50, the oxidation medium layer 60, and the TEOS film layer 70 constitute an interlayer insulating layer.
[0049] Preferably, the TEOS film layer 70 is formed by using a plasma-enhanced chemical vapor deposition process.
[0050] Further, after forming the TEOS film layer 70, the method for preparing the interlayer insulating layer may further include: grinding a certain thickness of the TEOS film layer 70 by using a chemical mechanical polishing process to planarize the surface of the interlayer insulating layer.
[0051] Obviously, the above embodiments are only examples clearly described and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. The obvious changes or modifications derived therefrom still fall within the protection scope of the present invention.
Claims
1. A method for preparing an interlayer insulating layer, characterized in that, Including: Providing a substrate, an active region and a drain region are formed in the substrate, a gate oxide layer is formed on the surface of the substrate, a gate electrode is located on the gate oxide layer, and sidewall structures are located on both sides of the gate electrode. The source region and the drain region are respectively located in the substrate on both sides of the sidewall structures; Forming a barrier layer, the barrier layer covering the gate electrode, the sidewall structures and the substrate; Forming an oxidation dielectric layer by using a high-density plasma chemical vapor deposition process, the oxidation dielectric layer covering the barrier layer; Performing low-temperature plasma treatment on the semiconductor structure after forming the oxidation dielectric layer; Forming a TEOS film layer, the TEOS film layer covering the oxidation dielectric layer, wherein the barrier layer, the oxidation dielectric layer and the TEOS film layer constitute an interlayer insulating layer.
2. The method for preparing the interlayer insulating layer according to claim 1, wherein During the process of performing low-temperature plasma treatment on the semiconductor structure after forming the oxidation dielectric layer, the process temperature does not exceed 300 °C, the gas participating in the plasma treatment is oxygen, and the treatment duration is 10 s to 600 s.
3. The preparation method of the interlayer insulating layer according to claim 1, characterized in that, During the process of forming the oxidation dielectric layer by using a high-density plasma chemical vapor deposition process, the process temperature is 300 °C to 800 °C, and the reaction gases include silane and oxygen.
4. The method for preparing the interlayer insulating layer according to claim 1, wherein, The thickness of the oxidation medium layer is 5. The method for preparing the interlayer insulating layer according to claim 1, wherein, Forming the TEOS film layer by using a plasma-enhanced chemical vapor deposition process.
6. The method for preparing an interlayer insulating layer according to claim 1, wherein After forming the TEOS film layer, the method for preparing the interlayer insulating layer further includes: Using a chemical mechanical polishing process to polish a certain thickness of the TEOS film layer to planarize the surface of the interlayer insulating layer.
7. The method for preparing the interlayer insulating layer according to claim 1, wherein, Forming the barrier layer by using a chemical vapor deposition process.
8. The method for preparing an interlayer insulating layer according to claim 1, wherein, The material of the barrier layer is silicon nitride.
9. The method for preparing an interlayer insulating layer according to claim 1, wherein The thickness of the barrier layer is