Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, in the preparation method, a first interlayer dielectric layer, a second interlayer dielectric layer and an anti-reflection layer are formed on the surface of an etching barrier layer as new passivation layers, and the anti-reflection layer is used as a top barrier layer to etch a contact hole. In this way, it can be guaranteed that the plasma cannot bombard the top metal layer and the second interlayer dielectric layer at the same time, the situation that chelate which is difficult to remove both dry etching and wet etching / cleaning is formed in the contact hole etching process is avoided, no photomask is additionally added, the requirement of customers for saving edition is met, meanwhile, the requirement for mass production is met, and the production efficiency is improved. And the chip packaging reliability is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The passivation layer is the last process in the wafer manufacturing process and is used to protect the entire chip. The film layer structure of the passivation layer is usually stacked silicon dioxide and silicon nitride (from bottom to top). Since the top copper metal layer has good electrical conductivity, it has good performance in automotive-grade electronic applications.

[0003] Currently, chip manufacturers usually cancel the aluminum pad between the top copper metal layer and the passivation layer in the back-end process of the wafer. This can not only save costs but also achieve chip functions. Therefore, many current chip manufacturers directly cover the passivation layer on the surface of the top copper metal layer, and connect the metal leads to the top copper metal layer after the passivation layer is etched. However, there is a difficulty in the back-end process. Before opening the barrier layer (NDC) on the surface of the top copper metal layer, the photoresist mask must be consumed by O2. In the over-etching step of etching this barrier layer, in order to ensure sufficient over-etching amount, the dissociation electrons will bombard both the top copper metal layer and the silicon nitride in the passivation layer at the same time. Etching the silicon nitride will form serious N / F / O polymers, which adhere to the sidewalls and the bottom. And after etching to open the barrier layer to expose the top copper metal layer, the N / F / O polymers will react with the top copper metal layer and form chelates CuxNyFz at the bottom of the contact hole that are difficult to remove by both dry and wet methods, thus affecting the reliability of subsequent chip packaging. Summary of the Invention

[0004] This application provides a semiconductor device and a method for manufacturing the same, which can solve the problem that in the back-end process of the wafer, during the process of etching the passivation layer to form a contact hole, chelates CuxNyFz that are difficult to remove are formed on the bottom wall of the contact hole, thus affecting the reliability of chip packaging.

[0005] On the one hand, an embodiment of this application provides a method for manufacturing a semiconductor device, including:

[0006] Providing a semiconductor structure in which a top metal layer is formed;

[0007] Forming an etching barrier layer that covers the semiconductor structure and the top metal layer;

[0008] Forming a first interlayer dielectric layer that covers the etching barrier layer;

[0009] Forming a second interlayer dielectric layer that covers the first interlayer dielectric layer;

[0010] An anti-reflection layer is formed, and the anti-reflection layer covers the second interlayer dielectric layer;

[0011] A photoresist layer is coated on the surface of the anti-reflection layer;

[0012] Through a photolithography process, a contact hole pattern is defined on the photoresist layer to obtain the patterned photoresist layer;

[0013] Using the patterned photoresist layer as a mask, the anti-reflection layer, the second interlayer dielectric layer, and the first interlayer dielectric layer are etched to the surface of the etch stop layer to form a trench;

[0014] In the trench, the etch stop layer is etched to the surface of the top metal layer to form a contact hole;

[0015] The patterned photoresist layer is removed;

[0016] A metal material layer is formed, and the metal material layer fills the contact hole.

[0017] Optionally, in the method for manufacturing the semiconductor device, the material of the anti-reflection layer is SiON.

[0018] Optionally, in the method for manufacturing the semiconductor device, the thickness of the anti-reflection layer is 500 angstroms to 600 angstroms.

[0019] Optionally, in the method for manufacturing the semiconductor device, a dry etching process is used to etch the anti-reflection layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to the surface of the etch stop layer to form a trench, and the gas participating in the etching at least includes: fluorocarbon.

[0020] Optionally, in the method for manufacturing the semiconductor device, a dry etching process is used to etch the etch stop layer to the surface of the top metal layer to form a contact hole, and the gas participating in the etching at least includes: fluorocarbon.

[0021] Optionally, in the method for manufacturing the semiconductor device, after removing the patterned photoresist layer and before forming the metal material layer, the method for manufacturing the semiconductor device further includes:

[0022] Performing a wet cleaning process on the semiconductor structure after forming the contact hole.

[0023] Optionally, in the method for manufacturing the semiconductor device, after forming the metal material layer, the method for manufacturing the semiconductor device further includes:

[0024] Grinding and removing the anti-reflection layer and the metal material layer that exceed the surface of the second interlayer dielectric layer.

[0025] On the other hand, an embodiment of the present application further provides a semiconductor device, including:

[0026] A semiconductor structure in which a top metal layer is formed;

[0027] An etch stop layer covering the semiconductor structure and the top metal layer;

[0028] A first interlayer dielectric layer covering the etch stop layer;

[0029] A second interlayer dielectric layer covering the first interlayer dielectric layer;

[0030] An anti-reflection layer covering the second interlayer dielectric layer;

[0031] A contact hole located in the anti-reflection layer, the second interlayer dielectric layer, the first interlayer dielectric layer and the etch stop layer and exposing the top metal layer;

[0032] A metal material layer filling the contact hole.

[0033] The technical solution of the present application has at least the following advantages:

[0034] In the present application, a first interlayer dielectric layer, a second interlayer dielectric layer and an anti-reflection layer are formed on the surface of the etch stop layer as a new passivation layer. In the present application, the anti-reflection layer is used as the top stop layer for etching the contact hole, so that it can be ensured that the plasma will not bombard the top metal layer and the second interlayer dielectric layer at the same time, avoiding the formation of chelates (CuxNyFz) that are difficult to remove by both dry etching and wet etching / cleaning during the process of etching the contact hole, and will not additionally increase the photomask, realizing the customer's demand for saving the mask, and at the same time meeting the mass production requirements and improving the chip packaging reliability. Description of the Drawings

[0035] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0037] Figures 2 - 6 is a schematic diagram of a semiconductor structure in each process step of manufacturing a semiconductor device according to an embodiment of the present invention;

[0038] Among them, the reference signs are explained as follows:

[0039] 10 - semiconductor structure, 11 - top metal layer, 12 - etch stop layer, 13 - first interlayer dielectric layer, 14 - second interlayer dielectric layer, 15 - antireflection layer, 16 - photoresist layer, 17 - opening, 18 - trench, 19 - contact hole, 20 - metal material layer. Detailed implementation manners

[0040] Next, the technical solutions in the present application will be clearly and completely described in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts fall within the scope of protection of the present application.

[0041] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0042] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0043] In addition, the technical features involved in different implementation manners of the present application described below can be combined with each other as long as they do not conflict with each other.

[0044] The embodiment of the present application provides a method for manufacturing a semiconductor device. Refer to Figure 1 , Figure 1 is a flowchart of the method for manufacturing a semiconductor device according to the embodiment of the present invention. The method for manufacturing a semiconductor device includes:

[0045] First, perform step S1: Refer to Figure 2 ,Figure 2 It is a schematic diagram of a semiconductor structure after forming an antireflection layer according to an embodiment of the present application. A semiconductor structure 10 is provided, and a top metal layer 11 is formed in the semiconductor structure 10.

[0046] In this embodiment, the material of the top metal layer 11 is copper.

[0047] It should be noted that the semiconductor structure 10 can be a semiconductor structure after the front-end and middle-end processes of any conventional semiconductor chip. The present application does not make any limitation on the specific film layers of the semiconductor structure 10, as long as it is ensured that a top metal layer 11 is formed on the surface of the semiconductor structure 10.

[0048] Then, perform step S2: Continue to refer to Figure 2 , and form an etch stop layer 12, where the etch stop layer 12 covers the semiconductor structure 10 and the top metal layer 11.

[0049] In this embodiment, the material of the etch stop layer 12 is NDC (nitrogen-doped silicon carbide).

[0050] In this embodiment, the thickness of the etch stop layer 12 is 700 angstroms.

[0051] Next, perform step S3: Continue to refer to Figure 2 , and form a first interlayer dielectric layer 13, where the first interlayer dielectric layer 13 covers the etch stop layer 12.

[0052] In this embodiment, the first interlayer dielectric layer 13 is a TEOS layer.

[0053] In this embodiment, the thickness of the first interlayer dielectric layer 13 is 4000 angstroms.

[0054] Furthermore, perform step S4: Continue to refer to Figure 2 , and form a second interlayer dielectric layer 14, where the second interlayer dielectric layer 14 covers the first interlayer dielectric layer 13.

[0055] In this embodiment, the material of the second interlayer dielectric layer 14 is silicon nitride.

[0056] In this embodiment, the thickness of the second interlayer dielectric layer 14 is 4000 angstroms.

[0057] Next, perform step S5: Continue to refer to Figure 2 , and form an antireflection layer 15, where the antireflection layer 15 covers the second interlayer dielectric layer 14.

[0058] In this embodiment, the material of the antireflection layer 15 is SiON.

[0059] Preferably, the thickness of the anti-reflection layer 15 is 500 Å to 600 Å.

[0060] Further, perform step S6: Refer to Figure 3 , Figure 3 is a schematic diagram of a semiconductor structure after forming an opening in the photoresist layer. A photoresist layer 16 is coated on the surface of the anti-reflection layer 15.

[0061] Next, perform step S7: Continue to refer to Figure 3 , and through a photolithography process, an opening 17 is formed in the photoresist layer 16, thereby defining a contact hole pattern on the photoresist layer 16 to obtain the patterned photoresist layer 16.

[0062] Further, perform step S8: Refer to Figure 4 , Figure 4 is a schematic diagram of a semiconductor structure after forming a trench in an embodiment of the present application. Using the patterned photoresist layer 16 as a mask, the anti-reflection layer 15, the second interlayer dielectric layer 14, and the first interlayer dielectric layer 13 are etched to the surface of the etch stop layer 12 to form a trench 18.

[0063] Preferably, a dry etching process is used to etch the anti-reflection layer 15, the second interlayer dielectric layer 14, and the first interlayer dielectric layer 13 to the surface of the etch stop layer 12 to form a trench 18. The gas participating in the etching at least includes: carbon fluoride compound CxFy, where the carbon fluoride compound CxFy is CF4 or CHF3.

[0064] Among them, since the material of the anti-reflection layer 15 is SiON, the specific chemical formula for etching the anti-reflection layer 15, the second interlayer dielectric layer 14, and the first interlayer dielectric layer 13 is: SION + CxFy → SIF4(g) + CO + N2; it can be seen that due to the blocking of the anti-reflection layer 15, the carbon fluoride compound CxFy will not come into large-area contact with the second interlayer dielectric layer 14, so polymers CxNyFz will not accumulate on the bottom wall of the contact hole, and thus there will be no reaction between the polymers CxNyFz and the top copper metal layer at the bottom of the contact hole to generate chelates CuxNyFz that are difficult to remove.

[0065] Next, perform step S9: Refer to Figure 5 , Figure 5 is a schematic diagram of a semiconductor structure after forming a contact hole in an embodiment of the present application. The etch stop layer 12 is etched in the trench to the surface of the top metal layer 11 to form a contact hole 19.

[0066] Preferably, a dry etching process is used to etch the etch stop layer 12 to the surface of the top metal layer 11 to form contact holes 19. The gas participating in the etching includes at least: a carbon fluoride compound CxFy, where the carbon fluoride compound CxFy is CF4 or CHF3.

[0067] Further, step S10 is performed: Refer to Figure 6 , Figure 6 is a schematic diagram of a semiconductor structure after forming a metal material layer in an embodiment of the present application, and the patterned photoresist layer 16 is removed.

[0068] In this embodiment, an ashing process is used to remove the patterned photoresist layer 16.

[0069] Further, after removing the patterned photoresist layer 16 and before forming the metal material layer 20, the method for manufacturing the semiconductor device further includes: performing a wet cleaning process on the semiconductor structure after forming the contact holes 19 to completely remove impurities and polymers at the bottom of the contact holes 19.

[0070] Finally, step S11 is performed: Continue to refer to Figure 6 , a metal material layer 20 is formed. The metal material layer 20 fills the contact holes 19, and the metal material layer 20 is in contact with the top metal layer 11 to form a metal interconnect structure.

[0071] In the present application, a first interlayer dielectric layer, a second interlayer dielectric layer, and an antireflection layer are formed on the surface of the etch stop layer as a new passivation layer. In the present application, the antireflection layer is used as the top stop layer for etching the contact holes, so that it can be ensured that the plasma will not bombard the top metal layer and the second interlayer dielectric layer at the same time, avoiding the formation of chelates (CuxNyFz) that are difficult to remove by both dry etching and wet etching during the process of etching the contact holes, and no additional photomask is required, meeting the customer's demand for saving masks, and at the same time meeting the mass production requirements and improving the reliability of chip packaging.

[0072] Based on the same inventive concept, an embodiment of the present application also provides a semiconductor device. Refer to Figure 6 , the semiconductor device includes:

[0073] A semiconductor structure 10 in which a top metal layer 11 is formed;

[0074] An etch stop layer 12 that covers the semiconductor structure 10 and the top metal layer 11;

[0075] A first interlayer dielectric layer 13 that covers the etch stop layer 12;

[0076] The second interlayer dielectric layer 14, and the second interlayer dielectric layer 14 covers the first interlayer dielectric layer 13;

[0077] An anti-reflection layer 15, and the anti-reflection layer 15 covers the second interlayer dielectric layer 14;

[0078] A contact hole 19, and the contact hole 19 is located in the anti-reflection layer 15, the second interlayer dielectric layer 14, the first interlayer dielectric layer 13, and the etch stop layer 12 and exposes the top metal layer 11;

[0079] A metal material layer 20, and the metal material layer 20 fills the contact hole 19.

[0080] Obviously, the above embodiments are only examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a semiconductor structure in which a top metal layer is formed; Forming an etch stop layer that covers the semiconductor structure and the top metal layer; Forming a first interlayer dielectric layer that covers the etch stop layer; Forming a second interlayer dielectric layer that covers the first interlayer dielectric layer; Forming an anti-reflection layer that covers the second interlayer dielectric layer; Coating a photoresist layer on the surface of the anti-reflection layer; Defining a contact hole pattern on the photoresist layer through a photolithography process to obtain the patterned photoresist layer; Using the patterned photoresist layer as a mask to etch the anti-reflection layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to the surface of the etch stop layer to form a trench; Etching the etch stop layer in the trench to the surface of the top metal layer to form a contact hole; Removing the patterned photoresist layer; Forming a metal material layer that fills the contact hole.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The anti-reflection layer is made of SiON.

3. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The thickness of the anti-reflection layer is 500 Å to 600 Å.

4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Using a dry etching process to etch the anti-reflection layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to the surface of the etch stop layer to form a trench, and the gas participating in the etching at least includes: fluorocarbon.

5. The method for manufacturing a semiconductor device according to claim 1, wherein Using a dry etching process to etch the etch stop layer to the surface of the top metal layer to form a contact hole, and the gas participating in the etching at least includes: fluorocarbon.

6. The manufacturing method of the semiconductor device according to claim 1, characterized in that, After removing the patterned photoresist layer and before forming the metal material layer, the method for manufacturing the semiconductor device further includes: Performing a wet cleaning process on the semiconductor structure after forming the contact hole.

7. A semiconductor device, characterized in that, Comprising: A semiconductor structure in which a top metal layer is formed; An etch stop layer that covers the semiconductor structure and the top metal layer; A first interlayer dielectric layer that covers the etch stop layer; A second interlayer dielectric layer that covers the first interlayer dielectric layer; An anti-reflection layer that covers the second interlayer dielectric layer; A contact hole that is located in the anti-reflection layer, the second interlayer dielectric layer, the first interlayer dielectric layer, and the etch stop layer and exposes the top metal layer; A metal material layer that fills the contact hole.

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