Packaging structure, packaging method, communication system, radio frequency front-end module and electronic equipment

Abstract

The invention provides a packaging structure, a packaging method, a communication system, a radio frequency front-end module and electronic equipment, which not only can reduce electromagnetic interference in a chip and improve signal isolation, but also is simple in process and low in cost. The package structure may include a substrate, a first chip, and a metal layer. The first chip and the substrate can be stacked in the first direction. The first chip may be wrapped by an encapsulation material, and the metal layer may cover the encapsulation material in a second direction. Wherein the first direction may be perpendicular to the second direction. The package structure may also include a first spacer. A first end of the first spacer may be connected to the first surface of the first chip, and a second end of the first spacer may be connected to the metal layer. The first surface of the first chip can also be connected with the substrate. Wherein the first surface of the first chip can be used for indicating the surface, deviating from the substrate, of the first chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a packaging structure, a packaging method, a communication system, a radio frequency front-end module, and an electronic device. Background Art

[0002] With the increase in the functions of electronic devices such as mobile phones, the number of devices in electronic devices is increasing continuously, and the performance requirements for the devices are also getting higher and higher. Along with the miniaturization and modularization of electronic devices, due to packaging, the electromagnetic interference (EMI) inside the chip or between different chips is becoming more and more serious, resulting in the influence on the functions of electronic devices.

[0003] In order to shield electromagnetic interference, the packaging structures provided by related technologies can set wave-absorbing materials such as resin on the inner wall of the metal frame. Since the wave-absorbing material has the function of absorbing or greatly weakening the electromagnetic wave energy, the electromagnetic interference inside the chip can be reduced to a certain extent. However, the setting process of the wave-absorbing material is complex and the cost is high.

[0004] Therefore, there is an urgent need for a technical solution that can reduce the electromagnetic interference inside the chip, has a simple process, and is low in cost. Summary of the Invention

[0005] The present application provides a packaging structure, a packaging method, a communication system, a radio frequency front-end module, and an electronic device, which can not only reduce the electromagnetic interference inside the chip, improve the signal isolation degree, but also have a simple process and low cost.

[0006] In a first aspect, the present application provides a packaging structure, which may include a substrate, a first chip, and a metal layer.

[0007] Optionally, the first chip may be stacked with the substrate in a first direction. The first chip may be wrapped by a packaging material, that is, the first chip is located inside the packaging material. The metal layer may cover the packaging material in a second direction. Wherein, the first direction may be perpendicular to the second direction. For example, the first direction may be the Y direction, and the second direction may be the X direction.

[0008] The packaging structure may further include a first isolation member. The first end of the first isolation member may be connected to the first surface of the first chip, and the second end of the first isolation member may be connected to the metal layer. The first surface of the first chip may also be connected to the substrate. Wherein, the first surface of the first chip may be used to indicate the surface of the first chip facing away from the substrate.

[0009] In the packaging structure provided by the present application, the isolation wall formed by the metal layer, the first isolator, the first chip, and the substrate can divide the packaging structure including the first chip into two independent parts. The isolation wall prevents interference between the two parts. That is to say, the present application can reduce the electromagnetic interference inside the first chip through the isolation wall and improve the signal isolation degree of the first chip. Compared with the related art of setting absorbing materials, the setting process of the first isolator in the present application is simple, reducing the cost of the packaging structure.

[0010] In a possible implementation, the packaging structure may further include a first bonding wire. The first end of the first bonding wire can be connected to the first surface of the first chip, and the second end of the first bonding wire can be connected to the substrate. It can be seen that the connection between the first surface of the first chip and the substrate can be achieved through the first bonding wire.

[0011] In another possible implementation, the packaging structure may further include a second isolator.

[0012] The second isolator can be located inside the first chip and arranged along the first direction. The first end of the second isolator can be connected to the first end of the first isolator, and the second end of the second isolator can be connected to the substrate. It can be seen that the connection between the first surface of the first chip and the substrate can also be achieved through the second isolator.

[0013] Optionally, the second isolator can be made of a metal material such as copper. Of course, the second isolator can also be made of other materials, which is not limited in the present application.

[0014] Furthermore, the packaging structure may further include a second chip and a third isolator.

[0015] The second chip and the substrate can be stacked along the first direction. The second chip can be wrapped by the encapsulation material. That is to say, the second chip can also be located inside the encapsulation material.

[0016] The third isolator can be located between the first chip and the second chip and can be arranged along the first direction. The first end of the third isolator can be connected to the substrate, and the second end of the third isolator can be connected to the metal layer.

[0017] It can be seen that the isolation wall formed by the metal layer, the third isolator, and the substrate can divide the packaging structure including the first chip and the second chip into two independent parts. One part includes the first chip, and the other part includes the second chip. The isolation wall prevents interference between the two parts. That is to say, the present application can reduce the electromagnetic interference between the first chip and the second chip through the isolation wall and improve the signal isolation degree between the first chip and the second chip. Moreover, the setting process of the third isolator in the present application is simple, further reducing the cost of the packaging structure.

[0018] Exemplarily, the first spacer can be made of the second bonding wire or a metal material. Of course, in order to achieve the connection between the metal layer and the first chip, the first spacer can also be of other types, which is not limited in this application.

[0019] Similarly, the third spacer is also made of the second bonding wire or a metal material. Of course, in order to isolate the first chip from the second chip by connecting the metal layer to the substrate, the third spacer can also be of other types, which is not limited in this application.

[0020] Further, the first spacer can be used to conduct the heat generated by the first chip to the metal layer.

[0021] The metal layer can be used to dissipate the heat generated by the first chip.

[0022] It can be seen that the metal layer can act as a heat sink and play a role in dissipating the heat of the first chip. That is to say, this application can achieve the heat dissipation of the first chip through the first spacer and the metal layer.

[0023] Similarly, the third spacer can be used to conduct the heat generated by the substrate to the metal layer.

[0024] The metal layer can be used to dissipate the heat generated by the substrate.

[0025] It can be seen that the metal layer can act as a heat sink and play a role in dissipating the heat of the substrate. That is to say, this application can achieve the heat dissipation of the substrate through the third spacer and the metal layer.

[0026] In a second aspect, this application provides a packaging structure, which may include a substrate, a first chip, a second chip, and a metal layer.

[0027] The substrate and the metal layer can form a first cavity. The substrate, the second chip, and the first chip can be stacked in a first direction inside the first cavity.

[0028] A fourth spacer is provided inside the first chip, and a fifth spacer is provided inside the second chip. Among them, both the fourth spacer and the fifth spacer can be arranged in the first direction. The first end of the fourth spacer can be connected to the metal layer, the second end of the fourth spacer can be connected to the first end of the fifth spacer, and the second end of the fifth spacer can be connected to the substrate.

[0029] It can be seen that in the packaging structure provided by this application, the isolation wall formed by the metal layer, the fourth spacer, the fifth spacer, and the substrate can reduce the electromagnetic interference inside the first chip and the second chip respectively, and improve the signal isolation degree of the first chip and the second chip respectively. Moreover, the setting process of the fourth spacer and the fifth spacer in this application is simple, reducing the cost of the packaging structure.

[0030] Exemplarily, both the fourth isolation member and the fifth isolation member can be made of a metal material, etc. The metal material can be copper, etc. Of course, the fourth isolation member and the fifth isolation member can also be made of other materials, which are not limited in this application.

[0031] In a third aspect, this application provides a packaging method, which may include: fixing a first chip on a substrate along a first direction. Wrapping the first chip with a packaging material, and forming a first isolation member inside the packaging material along the first direction. Forming a metal layer outside the packaging material along a second direction.

[0032] Wherein, the first direction is perpendicular to the second direction. The first end of the first isolation member can be connected to the first surface of the first chip, and the second end of the first isolation member can be connected to the metal layer. The first surface of the first chip can be used to indicate the surface of the first chip facing away from the substrate.

[0033] In the manufacturing method provided by this application, a first isolation member is formed inside the packaging material between the first chip and the metal layer. The isolation wall formed by the metal layer, the first isolation member, the first chip, and the substrate can divide the packaging structure including the first chip into two independent parts. The isolation wall prevents interference between the two parts. That is to say, this application can reduce the electromagnetic interference inside the first chip through the isolation wall and improve the signal isolation degree of the first chip. Compared with the related art of setting an absorbing material, moreover, the setting process of the first isolation member in this application is simple, reducing the cost of the packaging structure.

[0034] In a possible implementation, the packaging method may further include: setting a first bonding wire between the first surface of the first chip and the substrate by means of wire bonding. Wherein, the first end of the first bonding wire can be connected to the first surface of the first chip, and the second end of the first bonding wire can be connected to the substrate. It can be seen that the connection between the first surface of the first chip and the substrate can be realized through the first bonding wire.

[0035] In another possible implementation, the packaging method may further include: forming a second isolation member inside the first chip along the first direction. Wherein, the first end of the second isolation member can be connected to the first end of the first isolation member, and the second end of the second isolation member can be connected to the substrate. It can be seen that the connection between the first surface of the first chip and the substrate can also be realized through the second isolation member.

[0036] Of course, in addition to setting the first bonding wire or the second isolation member, other methods can also be used to realize the connection between the first surface of the first chip and the substrate, which are not limited in this application.

[0037] Optionally, the second isolation member can be made of a metal material, etc. The metal material can be copper, etc. Of course, the second isolation member can also be made of other materials, which are not limited in this application.

[0038] Further, the encapsulation method provided by the present application may further include: fixing the second chip on the substrate along the first direction. Wrapping the second chip with an encapsulation material. Forming a third spacer along the first direction between the first chip and the second chip. Wherein, the first end of the third spacer may be connected to the substrate, and the second end of the third spacer may be connected to the metal layer.

[0039] It can be seen that the isolation wall formed by the metal layer, the third spacer and the substrate can divide the encapsulation structure including the first chip and the second chip into two independent parts. One part includes the first chip, and the other part includes the second chip. The electromagnetic interference between the first chip and the second chip can be reduced, and the isolation degree of the signal between the first chip and the second chip can be improved. Moreover, the setting process of the third spacer in the encapsulation method provided by the present application is simple, further reducing the cost of the encapsulation structure.

[0040] Exemplarily, the first spacer may adopt a second bonding wire or a metal material. Of course, in order to realize the connection between the metal layer and the first chip, the first spacer may also adopt other types, which are not limited in the present application.

[0041] Similarly, the third spacer also adopts a second bonding wire or a metal material. Of course, in order to isolate the first chip and the second chip by connecting the metal layer and the substrate, the third spacer may also adopt other types, which are not limited in the present application.

[0042] Since the first end of the first spacer can be connected to the first surface of the first chip and the second end of the first spacer can be connected to the metal layer, it can be imagined that the first spacer can be used to conduct the heat generated by the first chip to the metal layer. The metal layer can be used to dissipate the heat generated by the first chip.

[0043] It can be seen that the metal layer can act as a heat sink and play a role in dissipating heat from the first chip. That is to say, the encapsulation structure encapsulated by the encapsulation method provided by the present application can dissipate the heat of the first chip through the first spacer and the metal layer.

[0044] Similarly, since the first end of the third spacer can be connected to the substrate and the second end of the third spacer can be connected to the metal layer, it can be imagined that the third spacer can be used to conduct the heat generated by the substrate to the metal layer. The metal layer can be used to dissipate the heat generated by the substrate.

[0045] It can be seen that the metal layer can act as a heat sink and play a role in dissipating heat from the substrate. That is to say, the encapsulation structure encapsulated by the encapsulation method provided by the present application can dissipate the heat of the substrate through the third spacer and the metal layer.

[0046] Fourthly, the present application provides a communication system, which may include a circuit board and the packaging structure provided by the first aspect and its possible implementation manners, or include a circuit board and the packaging structure provided by the second aspect and its possible implementation manners. The packaging structure is disposed on the circuit board.

[0047] Further, the communication system may further include an antenna and a housing. The circuit board and the housing may form a second cavity. The circuit board may include a first surface and a second surface which are oppositely disposed. The packaging structure is located inside the second cavity and may be disposed on the first surface of the circuit board, and the antenna may be disposed on the second surface of the circuit board.

[0048] Optionally, the communication system may be a base station, a satellite transceiver, a radar, etc., which is not limited in the present application.

[0049] Fifthly, the present application provides a radio frequency front-end module, which includes passive devices and the packaging structure provided by the first aspect and its possible implementation manners, or includes passive devices and the packaging structure provided by the second aspect and its possible implementation manners. The passive devices may be connected to the packaging structure.

[0050] Optionally, the passive devices may be resistors, capacitors, etc., which is not limited in the present application.

[0051] Sixthly, the present application provides an electronic device, which includes a power supply and the radio frequency front-end module provided by the fifth aspect and its possible implementation manners. The power supply may be connected to the radio frequency front-end module to supply power to the radio frequency module.

[0052] It should be understood that the technical solutions of the second aspect to the sixth aspect of the present application are consistent with those of the first aspect of the present application, and the beneficial effects obtained by each aspect and the corresponding feasible implementation manners are similar, which will not be elaborated herein. Description of the Drawings

[0053] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0054] Figure 1 It is a schematic structural diagram of an electronic device in an embodiment of the present application;

[0055] Figure 2 It is a schematic structural diagram of an AAU in an embodiment of the present application;

[0056] Figure 3 It is a schematic structural diagram of a packaging structure in an embodiment of the present application;

[0057] Figure 4 Another schematic structural diagram of the packaging structure in the embodiment of the present application;

[0058] Figure 5 Another schematic structural diagram of the packaging structure in the embodiment of the present application;

[0059] Figure 6 Another schematic structural diagram of the packaging structure in the embodiment of the present application;

[0060] Figure 7 Another schematic structural diagram of the packaging structure in the embodiment of the present application;

[0061] Figure 8 Another schematic structural diagram of the packaging structure in the embodiment of the present application;

[0062] Figure 9a A schematic structural diagram of the packaging structure including multiple chips in the embodiment of the present application;

[0063] Figure 9b Another schematic structural diagram of the packaging structure including multiple chips in the embodiment of the present application;

[0064] Figure 9c Another schematic structural diagram of the packaging structure including multiple chips in the embodiment of the present application;

[0065] Figure 10 A schematic structural diagram of the packaging structure in the embodiment of the present application;

[0066] Figure 11a A schematic structural diagram of the packaging structure including a single chip in the embodiment of the present application;

[0067] Figure 11b Another schematic structural diagram of the packaging structure including a single chip in the embodiment of the present application;

[0068] Figure 11c Another schematic structural diagram of the packaging structure including a single chip in the embodiment of the present application;

[0069] Figure 12 A schematic structural diagram of the packaging structure in the embodiment of the present application;

[0070] Figure 13 A schematic flow chart of the packaging process in the embodiment of the present application;

[0071] Figure 14 A schematic structural diagram of the packaging structure in the embodiment of the present application;

[0072] Figure 15Another schematic structural diagram of the encapsulation structure in the embodiments of the present application;

[0073] Figure 16 A schematic flow chart of the encapsulation process in the embodiments of the present application;

[0074] Figure 17 A schematic flow chart of the encapsulation process in the embodiments of the present application;

[0075] Figure 18 Another schematic structural diagram of the encapsulation process in the embodiments of the present application;

[0076] Figure 19 A schematic structural diagram of the encapsulation structure in the embodiments of the present application;

[0077] Figure 20 A schematic flow chart of the encapsulation process in the embodiments of the present application;

[0078] Figure 21 A schematic structural diagram of the encapsulation process in the embodiments of the present application;

[0079] Figure 22 A schematic structural diagram of the encapsulation structure provided by the related art;

[0080] Figure 23 A schematic comparison diagram of the signal isolation degree of the encapsulation structure provided by the embodiments of the present application and the signal isolation degree of the encapsulation structure provided by the related art. Detailed implementation manners

[0081] Next, the technical solutions in the present application will be described with reference to the accompanying drawings.

[0082] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings in the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0083] Terms such as "first" and "second" in the embodiments of the specification, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, terms such as "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a series of steps or units included. A method, system, product or device does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0084] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (individual) of the following" or its similar expression refers to any combination of these items, including any combination of single item (individual) or plural items (individuals). For example, at least one (individual) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0085] An embodiment of this application provides an electronic device, which can be any electronic product provided with a storage chip. The electronic device can be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc. The embodiment of this application does not limit the form of the electronic device.

[0086] Illustratively, the above-mentioned consumer electronic product can be a mobile phone, a tablet computer, a laptop computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (such as a smart watch, a smart bracelet, etc.), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, etc. The home electronic product can be a smart door lock, a TV, a smart speaker, a refrigerator, a floor cleaning robot, etc. The vehicle-mounted electronic product can be a vehicle navigator, a vehicle-mounted display, etc. The financial terminal product can be an automated teller machine (ATM), an electronic device for self-service business handling, etc. The communication electronic product can be a communication device such as a server, a memory, a radar, a base station, etc.

[0087] According to actual needs, other devices electrically connected to the storage device, such as a printed circuit board (PCB; also called a printed wiring board) and an input / output device, can also be provided in the above-mentioned electronic device. This application does not limit this.

[0088] Illustratively, taking the above-mentioned electronic device as a mobile phone as an example. Refer to Figure 1As shown in the figure, the mobile phone 1000 may include a bus 101, a system on chip (SoC) 110 connected to the bus 101, a second RAM 120, a communication chip 130, and a power supply 140.

[0089] Among them, the SoC 110 can be used to process data, such as processing data of application programs, processing image data, and caching temporary data. The SoC 110 may include an application processor (AP) 111 for processing application programs, a graphics processing unit (GPU) 112 for processing image data, and a first RAM (random access memory) 113 for caching high-speed data. The AP 111, GPU 112, and the first RAM 113 may be integrated in one die or may be separately provided in multiple dies. The first RAM 113 may be a dynamic random access memory (DRAM). The second RAM 120 may be a dynamic random access memory (DRAM). The power supply 140 can be used to supply power to other chips.

[0090] The above communication chip 130 may adopt the radio frequency front-end module (RF FEM) provided in the embodiments of the present application. The RF FEM provided in the embodiments of the present application may include passive devices and a packaging structure. The passive devices may be connected to the packaging structure. The passive devices may be devices such as capacitors and inductors.

[0091] The embodiments of the present application also provide a communication system, which may be a base station (BS), a satellite transceiver, a radar, etc. Taking the BS as an example, as Figure 2 shown, the active antenna unit (AAU) in the BS may include a shell (abbreviated as S in Figure 2 ), a circuit board (which may be a printed circuit board (PCB)), a plurality of packaging structures 10 (i.e., a plurality of chips), and a plurality of antennas (abbreviated as ANT in Figure 2 ). The PCB and the shell S may form a cavity (i.e., the second cavity).

[0092] The PCB may include a first surface arranged oppositely (which may be Figure 2the front surface of the PCB) and the second surface (which can be Figure 2 the back surface of the PCB). A plurality of encapsulation structures 10 are located inside the cavity and disposed on the first surface, and a plurality of ANTs can be disposed on the second surface. Of course, in addition to the AAU, the BS may further include other parts, which will not be elaborated in detail in the embodiments of the present application.

[0093] The encapsulation structure provided by the embodiments of the present application will be introduced below.

[0094] As Figures 3 to 8 shown, the encapsulation structure 10 may include a substrate 1, a die 2 (i.e., the first chip), and a metal layer 3.

[0095] Optionally, the die 2 and the substrate 1 may be stacked along a first direction (such as the Y direction). The die 2 may be wrapped by a molding material (molding, which may be encapsulation resin, etc.) 4, that is, the die 2 is located inside the encapsulation material 4. The metal layer 3 may cover the encapsulation material 4 along a second direction (such as the X direction). Wherein, the Y direction may be perpendicular to the X direction.

[0096] The encapsulation structure 10 may further include a spacer 51 (i.e., the first spacer). The first end of the spacer 51 may be connected to the upper surface of the die 2 (i.e., the first surface, indicating the surface of the die 2 facing away from the substrate 1), and the second end of the spacer 51 may be connected to the metal layer 3. The upper surface of the die 2 may also be indirectly connected to the substrate 1.

[0097] In the encapsulation structure 10 provided by the embodiments of the present application, the isolation wall formed by the metal layer 3, the spacer 51, the die 2, and the substrate 1 may divide the encapsulation structure 10 including the die 2 into two independent parts. The isolation wall prevents interference between the two parts. That is to say, the embodiments of the present application can reduce the electromagnetic interference inside the die 2 through the isolation wall and improve the signal isolation degree of the die 2. Compared with the related art of setting wave-absorbing materials, the setting process of the spacer 51 in the present application is simple, reducing the cost of the encapsulation structure 10.

[0098] Furthermore, the encapsulation component 10 provided by the embodiments of the present application may further include a die 6 (i.e., the second chip) and a spacer 7 (i.e., the third spacer).

[0099] The die 6 and the substrate 1 may be stacked along the Y direction. The die 6 may be wrapped by the encapsulation material 4. That is to say, the die 6 may also be located inside the encapsulation material 4.

[0100] The spacer 7 may be located between the die 2 and the die 6 and may be disposed along the Y direction. The first end of the spacer 7 may be connected to the substrate 1, and the second end of the spacer 7 may be connected to the metal layer 3.

[0101] It can be seen that the isolation wall formed by the metal layer 3, the isolator 7, and the substrate 1 can divide the package structure including the chip 2 and the chip 6 into two independent parts. One part includes the chip 2, and the other part includes the chip 6. The electromagnetic interference between the chip 2 and the chip 6 can be reduced, and the signal isolation degree between the chip 2 and the chip 6 can be improved. Moreover, the setting process of the isolator 7 in the embodiment of the present application is simple, further reducing the cost of the package structure 10.

[0102] As Figure 3 shown, the package component 10 provided by the embodiment of the present application may further include an isolator 52. Similar to the isolator 51, the first end of the isolator 52 may be connected to the upper surface (i.e., the first surface, indicating the surface of the chip 6 facing away from the substrate 1) of the chip 6, and the second end of the isolator 52 may be connected to the metal layer 3. The upper surface of the chip 6 may also be indirectly connected to the substrate 1.

[0103] It can be seen that the isolation wall formed by the metal layer 3, the isolator 52, the chip 6, and the substrate 1 can divide the package structure 10 including the chip 2 into two independent parts. The electromagnetic interference inside the chip 2 can be reduced, and the signal isolation degree of the chip 2 can be improved. Moreover, the setting process of the isolator 51 in the embodiment of the present application is simple, reducing the cost of the package structure 10.

[0104] Exemplarily, the isolator 51 and the isolator 52 may adopt bonding wires or metal materials. Of course, in order to realize the connection between the metal layer 3 and the chip 2, the isolator 51 may also adopt other types. In order to realize the connection between the metal layer 3 and the chip 6, the isolator 52 may also adopt other types. The embodiment of the present application does not limit the types of the isolator 51 and the isolator 52.

[0105] For example, in the package structure 10 where the isolator 51 and the isolator 52 adopt bonding wires, the isolator 51 and the isolator 52 can be formed by a vertical wire bonding process, and then the connection between the metal layer 3 and the chip 2 and the connection between the metal layer 3 and the chip 6 can be realized through the isolator 51 and the isolator 52.

[0106] For another example, in the packaging structure 10 where the spacers 51 and 52 are made of a metal material, the spacers 51 and 52 can be formed by a trench filling process. Alternatively, holes can be drilled and metal pillars (i.e., the holes are filled with metal material) or metal walls (i.e., metal layers are formed on the hole walls) can be formed inside the holes to obtain the spacers 51 and 52. Therefore, it can be understood that the spacers 51 and 52 are formed by using the through package via (TPV) process. The TPV can be a through silicon via (TSV) or a deep silicon via (DSV), etc., and the embodiments of the present application do not make any limitations.

[0107] Similarly, the spacer 7 can be made of bonding wires or a metal material. Of course, in order to realize the connection between the metal layer 3 and the substrate 1, the spacer 7 can also be of other types, and the embodiments of the present application do not make any limitations.

[0108] The spacer 7 can also be formed by a vertical wire bonding process or by a trench filling process. Of course, it can also be obtained by drilling holes and forming metal pillars (i.e., the holes are filled with metal material) or metal walls (i.e., metal layers are formed on the hole walls) inside the holes. The embodiments of the present application do not make any limitations on the formation process of the spacer 7.

[0109] In some embodiments, referring to Figure 3 , the substrate 1 may include a surface metal 11. The chip 2 may include a frontside metal 21 and a backside metal 22. The frontside metal 21 may be connected to the second end of the spacer 51, and the backside metal 22 may be connected to the surface metal 11.

[0110] Similarly, the chip 6 may include a frontside metal 61 and a backside metal 62. The frontside metal 61 may be connected to the second end of the spacer 52, and the backside metal 62 may be connected to the surface metal 11.

[0111] The packaging structure 10 may further include bonding wires BL11 (i.e., the first bonding wire), bonding wires BL12 (i.e., the first bonding wire), bonding wires BL13, and bonding wires BL14.

[0112] Among them, the first ends of the bonding wires BL11 and BL12 can be connected to the first surface of the chip 2, and the second ends of the bonding wires BL11 and BL12 can be connected to the substrate 1. It can be seen that the connection between the first surface of the chip 2 and the substrate 1 can be realized through the bonding wires BL11 and BL12. It can be seen that the connection between the first surface of the chip 2 and the substrate 1 can be realized through the bonding wires BL11 and BL12.

[0113] Similarly, the first ends of the bonding wires BL13 and BL14 can be connected to the first surface of the chip 6 respectively, and the second ends of the bonding wires BL13 and BL14 can be connected to the substrate 1. It can be seen that the connection between the first surface of the chip 6 and the substrate 1 can be realized through the bonding wires BL13 and BL14. It can be seen that the connection between the first surface of the chip 6 and the substrate 1 can be realized through the bonding wires BL13 and BL14.

[0114] Exemplarily, the packaging structure 10 provided by the embodiments of the present application may include a positioning member GP (ground pad) 2 and a positioning member GP6, as Figure 4 shown. Among them, the positioning member GP2 can be connected to the front metal 21 of the chip 2 and also connected to the second end of the isolation member 51. Among them, the positioning member GP6 can be connected to the front metal 61 of the chip 6 and also connected to the second end of the isolation member 52.

[0115] It can be seen that the embodiments of the present application Figure 3 and Figure 4 can be a packaging structure obtained by wire bonding a III-V group chip such as gallium arsenide GaAs.

[0116] In other embodiments, referring to Figure 5 , the packaging component 10 provided by the embodiments of the present application may further include an isolation member 81 (i.e., the second isolation member) and an isolation member 82.

[0117] The isolation member 81 can be located inside the chip 2 and arranged along the Y direction. The first end of the isolation member 81 can be connected to the first end of the isolation member 51, and the second end of the isolation member 81 can be connected to the substrate 1. It can be seen that the connection between the first surface of the chip 2 and the substrate 1 can also be realized through the isolation member 81.

[0118] Similarly, the isolation member 82 can be located inside the chip 6 and arranged along the Y direction. The first end of the isolation member 82 can be connected to the first end of the isolation member 52, and the second end of the isolation member 82 can be connected to the substrate 1. It can be seen that the connection between the first surface of the chip 6 and the substrate 1 can also be realized through the isolation member 82.

[0119] Optionally, the isolation members 81 and 82 can be made of a metal material or the like. The metal material can be copper or the like. Of course, the isolation member 81 can also be made of other materials, which is not limited in the present application.

[0120] Exemplarily, the isolation members 81 and 82 can also be formed by a trench filling process. Of course, it is also possible to form metal posts (i.e., the holes are filled with metal materials) or metal walls (i.e., metal layers are formed on the hole walls) in the holes by drilling to obtain the isolation members 81 and 82. The embodiments of the present application do not limit the formation process of the isolation members 81 and 82.

[0121] It can be seen that the embodiments of the present application Figure 5 can be a packaging structure 10 obtained by wire bonding a silicon-based chip.

[0122] The embodiments of the present application also provide a packaging structure 10 for packaging a flip chip (which can be called FC packaging), such as Figure 6 and Figure 7 shown. In the packaging structure 10, the front sides of the chips 2 and 6 face the substrate 1 respectively, and the back sides face the metal layer 3 respectively. That is to say, the front metal 21 of the chip 2 can be close to the substrate 1, and the back metal 22 can be close to the metal layer 3. Similarly, the front metal 61 of the chip 6 can be close to the substrate 1, and the back metal 62 can be close to the metal layer 3. The chips 2 and 6 can be fixed on the substrate 1 through solder balls SB.

[0123] In one example, the isolation member 51 and the isolation member 81 can be located on the same straight line in the Y direction, and the isolation member 52 and the isolation member 82 can be located on the same straight line in the Y direction, such as Figure 6 shown. That is to say, the isolation member 51 and the isolation member 81 can be aligned in the Y direction, and the isolation member 52 and the isolation member 82 can be aligned in the Y direction.

[0124] In another example, the isolation member 51 and the isolation member 81 can be located on different straight lines in the Y direction, and the isolation member 52 and the isolation member 82 can be located on different straight lines in the Y direction, such as Figure 7 shown. The isolation member 51 and the isolation member 81 can be offset in the Y direction, and the isolation member 52 and the isolation member 82 can be offset in the Y direction.

[0125] Through Figure 6 and Figure 7 It can be seen that the packaging structure 10 provided by the embodiments of the present application can improve the flexibility of the layout of the isolation member 51, the isolation member 52, the isolation member 81, and the isolation member 82 to avoid conflicts between the isolation member 81 and the internal circuit of the chip 2 and conflicts between the isolation member 82 and the internal circuit of the chip 6.

[0126] For the relevant introductions of the isolation member 51, the isolation member 52, the isolation member 81, the isolation member 82, and the isolation member 7, reference can be made to the above, and the embodiments of the present application will not elaborate.

[0127] Exemplarily, referring toFigures 3 to 7 , the metal layer 3 can be a metal frame structure. Of course, the metal layer 3 can also be the Figure 8 structure shown.

[0128] For Figures 3 to 8 the packaging structure 10 shown, the spacer 51 can be used to conduct the heat generated by the chip 2 to the metal layer 3. The spacer 52 can be used to conduct the heat generated by the chip 6 to the metal layer 3. The metal layer 3 can be used to dissipate the heat generated by the chip 2 and the heat generated by the chip 6. It can be seen that the metal layer 3 can act as a heat sink and play a role in dissipating the heat of the chip 2 and the chip 6. That is to say, the embodiment of the present application can achieve the heat dissipation of the chip 2 through the spacer 51 and the metal layer 3, and can also achieve the heat dissipation of the chip 5 through the spacer 52 and the metal layer 3, that is, achieve the heat dissipation of the packaging structure 10.

[0129] Similarly, the spacer 7 can be used to conduct the heat generated by the substrate 1 to the metal layer 3. The metal layer 3 can be used to dissipate the heat generated by the substrate 1. It can be seen that the metal layer 3 can act as a heat sink and play a role in dissipating the heat of the substrate 1. That is to say, the embodiment of the present application can achieve the heat dissipation of the substrate 1 through the third spacer 7 and the metal layer 3, that is, achieve the heat dissipation of the packaging structure 10.

[0130] In some embodiments, in order to eliminate low-frequency resonance and reduce electromagnetic interference between the chip 2 and the chip 6, the packaging structure 10 can include the spacer 51, the spacer 52 and the spacer 7, as Figure 9a shown. That is to say, the packaging structure 10 can include a single spacer 51 for the chip 2, a single spacer 52 for the chip 6, and a single spacer 7.

[0131] In other embodiments, in order to eliminate low-frequency resonance and intermediate-frequency resonance and reduce electromagnetic interference between the chip 2 and the chip 6, the packaging structure 10 can include a plurality of spacers 51 ( Figures 3 to 8 only one is shown in Figures 3 to 8 ), a plurality of spacers 52 ( Figures 3 to 8 only one is shown in Figure 9b ), and a plurality of spacers 7 (

[0132] only one is shown in Figures 3 to 8 ), as Figures 3 to 8(only one is shown in the figure) and multiple spacers 7( Figures 3 to 8 (only one is shown in the figure), such as Figure 9c shown. The multiple spacers 51, the multiple spacers 52, and the multiple spacers 7 can be arranged evenly in a multi-point irregular manner.

[0133] Optionally, the encapsulation structure 10 can include a single chip (i.e., chip 2), such as Figure 10 shown. Then:

[0134] In some embodiments, in order to eliminate low-frequency resonance, the encapsulation structure 10 can include a spacer 51, such as Figure 11a shown. That is to say, the encapsulation structure 10 can include a single spacer 51 for chip 2.

[0135] In some other embodiments, in order to eliminate low-frequency resonance and intermediate-frequency resonance, the encapsulation structure 10 can include multiple spacers 51( Figure 10 (only one is shown in the figure), such as Figure 11b shown. The multiple spacers 51 can be arranged evenly, and the spacing between different spacers can be determined according to the target frequency band and the like.

[0136] In still some other embodiments, in order to eliminate low-frequency resonance, intermediate-frequency resonance, and high-frequency resonance (i.e., in order to eliminate broadband resonance), the encapsulation structure 10 can include multiple spacers 51( Figure 10 (only one is shown in the figure) and multiple spacers 7( Figure 10 (only one is shown in the figure), such as Figure 11c shown. The multiple spacers 51 and the multiple spacers 7 can be arranged evenly, and the spacing between different spacers can be determined according to the target frequency band and the like.

[0137] The embodiments of the present application provide another encapsulation structure, such as Figure 12 shown. The encapsulation structure 10 can include a substrate 1, a chip 2, a chip 6, a chip 9, and a metal layer 3.

[0138] The substrate 1 can be provided with a surface metal 11. The chip 6 can be provided with a front metal 61, and the chip 9 can be provided with a front metal 91.

[0139] The substrate 1 and the metal layer 3 can form a cavity (i.e., the first cavity). The substrate 1, the chip 6, and the chip 1 can be stacked along the Y direction inside the cavity. Similarly, the chip 9 and the chip 1 can also be stacked.

[0140] Inside the chip 2, there is an isolator 20 (i.e., the fifth isolator), inside the chip 6, there is an isolator 60 (i.e., the fourth isolator), and inside the chip 9, there is an isolator 90. Among them, the isolator 20, the isolator 60, and the isolator 90 can all be arranged along the Y direction. The first end of the isolator 60 can be connected to the metal layer 3 (i.e., the front metal 61 is connected to the metal layer 3), the first end of the isolator 90 can be connected to the metal layer 3 (i.e., the front metal 91 is connected to the metal layer 3), the second end of the isolator 60 can be connected to the first end of the isolator 20 through the solder ball SB, the second end of the isolator 90 can be connected to the first end of the isolator 20 through the solder ball SB, and the second end of the isolator 20 can be connected to the front metal 11 through the solder ball SB (i.e., the second end of the isolator 20 can be connected to the substrate 1 through the solder ball SB).

[0141] It can be seen that in the packaging structure 10 provided by the present application, the isolation walls formed by the metal layer 3, the isolator 60, the isolator 20, and the substrate 1 and the isolation walls formed by the metal layer 3, the isolator 90, the isolator 20, and the substrate 1 can reduce the electromagnetic interference inside the chips 2, 6, and 9 respectively, and improve the signal isolation degree of the chips 2, 6, and 9 respectively. Moreover, in the embodiments of the present application, the setting process of the isolator 20, the isolator 60, and the isolator 90 is simple, reducing the cost of the packaging structure 10.

[0142] Optionally, the isolator 20, the isolator 60, and the isolator 90 can be made of metal materials, etc. The metal material can be copper, etc. Of course, the isolator 20, the isolator 60, and the isolator 90 can also be made of other materials, which are not limited in the present application.

[0143] Exemplarily, the isolator 20, the isolator 60, and the isolator 90 can also be formed by the trench filling process. Of course, it is also possible to form metal columns (i.e., the holes are filled with metal materials) or metal walls (i.e., metal layers are formed on the hole walls) in the holes by drilling to obtain the isolator 20, the isolator 60, and the isolator 90. The embodiments of the present application do not limit the formation process of the isolator 20, the isolator 60, and the isolator 90.

[0144] The embodiments of the present application provide a packaging method, which can be used to prepare the above-mentioned packaging structure 10. As Figure 13 shown, the packaging process 200 can be implemented according to the following steps:

[0145] Step S201: Fix the chips 2 and 6 on the substrate 1 along the Y direction, as Figure 14 shown.

[0146] Step S202: Wrap the chips 2 and 6 with packaging materials, and form an isolator 51 and an isolator 52 inside the packaging materials along the Y direction, as Figure 15 shown.

[0147] In one example, the chip 2 and the chip 6 can be wrapped with a packaging material first, and then the spacers 51 and 52 are formed in the Y direction inside the packaging material. Among them, the first end of the spacer 51 can be connected to the surface of the chip 2 facing away from the substrate 1, and the second end of the spacer 51 can be connected to the metal layer 3. Similarly, the first end of the spacer 52 can be connected to the surface of the chip 6 facing away from the substrate 1, and the second end of the spacer 52 can be connected to the metal layer 3.

[0148] Exemplarily, the spacers 51 and 52 can be bonding wires or metal materials. Of course, in order to realize the connection between the metal layer 3 and the chip 2, the spacer 51 can also be of other types. In order to realize the connection between the metal layer 3 and the chip 6, the spacer 52 can also be of other types. The embodiments of the present application do not limit the types of the spacers 51 and 52.

[0149] Furthermore, the spacers 51 and 52 can be formed by a trench filling process. Alternatively, holes can be drilled and metal posts (i.e., the holes are filled with metal materials) or metal walls (i.e., metal layers are formed on the hole walls) can be formed inside the holes to obtain the spacers 51 and 52. Therefore, it can be understood that the spacers 51 and 52 are formed by a through package via (TPV) process. The TPV can be a through silicon via (TSV), a deep silicon via (DSV), etc., and the embodiments of the present application do not limit it.

[0150] In another example, the spacers 51 and 52 are formed in the Y direction inside the packaging material, and then the chip 2, the chip 6, the spacers 51 and 52 are wrapped with the packaging material. Among them, the first end of the spacer 51 can be connected to the surface of the chip 2 facing away from the substrate 1, and the second end of the spacer 51 can be connected to the metal layer 3. Similarly, the first end of the spacer 52 can be connected to the surface of the chip 6 facing away from the substrate 1, and the second end of the spacer 52 can be connected to the metal layer 3.

[0151] Furthermore, the spacers 51 and 52 can be formed by a vertical wire bonding process, and then the connection between the metal layer 3 and the chip 2 and the connection between the metal layer 3 and the chip 6 are realized through the spacers 51 and 52.

[0152] Step S203: Form the metal layer 3 in the X direction outside the packaging material, as Figures 3 to 8 shown.

[0153] In the manufacturing method provided by the embodiments of the present application, a separator 51 is formed inside the encapsulation material between the chip 2 and the metal layer 3, and a separator 52 is formed inside the encapsulation material between the chip 6 and the metal layer 3. The isolation wall formed by the metal layer 3, the separator 51, the chip 2, and the substrate 1 can divide the encapsulation structure including the chip 2 into two independent parts. The isolation wall formed by the metal layer 3, the separator 52, the chip 6, and the substrate 1 can divide the encapsulation structure including the chip 6 into two independent parts. Therefore, the electromagnetic interference inside the chip 2 and the chip 6 can be reduced respectively, and the signal isolation degree of the chip 2 and the chip 6 can be improved. Moreover, the encapsulation method provided by the embodiments of the present application has a simple process and can reduce the cost of the encapsulation structure 10.

[0154] In some embodiments, as Figure 16 shown, the manufacturing method provided by the embodiments of the present application may further include the following steps before step S203:

[0155] Step S204: Use wire bonding encapsulation to set the bonding wires BL11 and BL12 between the chip 2 and the substrate 1, and use wire bonding encapsulation to set the bonding wires BL13 and BL14 between the chip 6 and the substrate 1, as Figure 3 and Figure 4 shown.

[0156] Wherein, the first ends of the bonding wires BL11 and BL12 can be connected to the surface of the chip 2 facing away from the substrate 1, and the second ends of the bonding wires BL11 and BL12 can be connected to the substrate 1. Similarly, the first ends of the bonding wires BL13 and BL14 can be connected to the surface of the chip 6 facing away from the substrate 1, and the second ends of the bonding wires BL13 and BL14 can be connected to the substrate 1.

[0157] It can be seen that the connection between the surface of the chip 2 facing away from the substrate 1 and the substrate 1 can be realized through the bonding wires BL11 and BL12, and the connection between the surface of the chip 6 facing away from the substrate 1 and the substrate 1 can be realized through the bonding wires BL13 and BL14.

[0158] Of course, in order to realize the connection between the upper surface of the chip 2 and the substrate 1, as Figure 17 shown, step S204 may also be executed according to the following process before step S202:

[0159] Step S204: An isolator 81 can be formed along the Y direction inside the chip 2, and an isolator 82 can be formed along the Y direction inside the chip 6, as Figure 18As shown. Among them, the first end of the spacer 81 can be connected to the first end of the spacer 51, and the second end of the spacer 81 can be connected to the substrate 1. The first end of the spacer 82 can be connected to the first end of the spacer 52, and the second end of the spacer 82 can be connected to the substrate 1. It can be seen that the connection between the surface of the chip 2 facing away from the substrate 1 and the substrate 1 can also be achieved through the spacer 81, and the connection between the surface of the chip 6 facing away from the substrate 1 and the substrate 1 can also be achieved through the spacer 82.

[0160] Of course, in addition to setting the bonding wires (i.e., the bonding wire BL11 and the bonding wire BL12) or the spacers 81 and 82 (i.e., the second spacers), other methods can also be used to achieve the connection between the surface of the chip 2 facing away from the substrate 1 and the substrate 1 and the connection between the surface of the chip 6 facing away from the substrate 1 and the substrate 1. The embodiments of the present application do not make any limitations.

[0161] Optionally, the spacers 81 and 82 can be made of a metal material, etc. The metal material can be copper, etc. Of course, the spacers 81 and 82 can also be made of other materials. The embodiments of the present application do not make any limitations.

[0162] In still other embodiments, as Figure 16 and Figure 17 shown, the manufacturing method provided by the embodiments of the present application may further include the following steps before step S203:

[0163] Step S205: Form a spacer 7 (i.e., the third spacer) in the Y direction between the chip 2 and the chip 6, as Figure 19 shown. Among them, the first end of the spacer 7 can be connected to the substrate 1, and the second end of the spacer 7 can be connected to the metal layer 3.

[0164] Exemplarily, the spacer 7 can be a bonding wire or a metal material. Of course, in order to achieve the connection between the metal layer 3 and the substrate 1, the spacer 7 can also be of other types. The embodiments of the present application do not make any limitations.

[0165] The spacer 7 can be obtained by punching holes and forming metal posts (i.e., the holes are filled with metal materials) or metal walls (i.e., metal layers are formed on the hole walls) inside the holes. The embodiments of the present application do not make any limitations on the formation process of the spacer 7.

[0166] It can be seen that the isolation wall formed by the metal layer 3, the spacer 7 and the substrate 1 can divide the package structure including the chip 2 and the chip 6 into two independent parts. One part includes the chip 2, and the other part includes the chip 6. The electromagnetic interference between the chip 2 and the chip 6 can be reduced, and the isolation degree of the signal between the chip 2 and the chip 6 can be improved. Moreover, the setting process of the spacer 7 in the packaging method provided by the embodiments of the present application is simple, further reducing the cost of the package structure 10.

[0167] An embodiment of the present application provides a packaging method, as Figure 20 shown. The packaging process 300 can be implemented according to the following steps:

[0168] Step 301: Fix the chip 2 and the chip 6 on the substrate 1 along the Y direction, as Figure 14 shown.

[0169] Step 302: Form a separator 81 inside the chip 2 along the Y direction, and form a separator 82 inside the chip 6 along the Y direction, as Figure 18 shown.

[0170] Step 303: Wrap the chip 2 and the chip 6 with a packaging material, and form a separator 51 and a separator 52 inside the packaging material along the Y direction, as Figure 21 shown.

[0171] Step 304: Form a separator 7 inside the packaging material between the chip 2 and the chip 6 along the Y direction, as Figure 19 shown.

[0172] Step 305: Form a metal layer 3 outside the packaging material along the X direction, as Figure 5 shown.

[0173] In the packaging structure 10 formed by encapsulating through the above packaging process 200 or packaging process 300, the separator 51 can be used to conduct the heat generated by the chip 2 to the metal layer 3. The separator 52 can be used to conduct the heat generated by the chip 6 to the metal layer 3. The metal layer 3 can be used to dissipate the heat generated by the chip 2 and the heat generated by the chip 6. It can be seen that the metal layer 3 can be used as a heat sink, playing a role in dissipating the heat of the chip 2 and the chip 6. That is to say, the embodiment of the present application can realize the heat dissipation of the chip 2 through the separator 51 and the metal layer 3, and can also realize the heat dissipation of the chip 5 through the separator 52 and the metal layer 3, that is, realize the heat dissipation of the packaging structure 10.

[0174] Similarly, the separator 7 can be used to conduct the heat generated by the substrate 1 to the metal layer 3. The metal layer 3 can be used to dissipate the heat generated by the substrate 1. It can be seen that the metal layer 3 can be used as a heat sink, playing a role in dissipating the heat of the substrate 1. That is to say, the embodiment of the present application can realize the heat dissipation of the substrate 1 through the third separator 7 and the metal layer 3, that is, realize the heat dissipation of the packaging structure 10.

[0175] It should be understood that in various embodiments of the present application, the magnitude of the serial numbers of the above processes does not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0176] The encapsulation structure 20 provided by the related art may include a substrate 1, a chip 2, a chip 6, an encapsulation material 4, and a metal layer 3, as Figure 22 shown. The substrate 1 may be provided with a surface metal 11. The chip 2 and the substrate 1 are stacked in the Y direction, and the chip 6 and the substrate 1 may also be stacked in the Y direction. The chip 2 and the chip 6 may be wrapped by the encapsulation material 4. The metal layer 3 may cover the encapsulation material 4 in the X direction. The surface of the chip 2 facing away from the substrate 1 is connected to the substrate 1 through bonding wires BL11 and BL12. The surface of the chip 6 facing away from the substrate 1 is connected to the substrate 1 through bonding wires BL13 and BL14.

[0177] The signal isolation degree of the encapsulation structure 10 provided by the embodiment of the present application, as shown in Figures 3 to 8 shown, and the signal isolation degree of the encapsulation structure 20 provided by the related art, as shown in Figure 22 shown, are compared in the schematic diagram as shown in Figure 23 shown. Figure 23 In the figure, the abscissa represents the frequency, and the unit is GHz. The ordinate represents the isolation degree, and the unit is dB. The curve F1 represents the signal isolation degree of the encapsulation structure 10 provided by the embodiment of the present application, and the curve F2 represents the signal isolation degree of the encapsulation structure 20 provided by the related art. It can be seen from Figure 23 the figure that the signal isolation degree of the encapsulation structure 10 provided by the embodiment of the present application can be increased by 30 dB to 70 dB, which is significantly better than the signal isolation degree of the encapsulation structure 20 provided by the related art. That is to say, the embodiment of the present application can improve the signal isolation degree of the encapsulation structure 20.

[0178] As described above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An encapsulation structure, characterized in that, Comprising a substrate, a first chip, and a metal layer; The first chip is stacked with the substrate in a first direction, the first chip is wrapped by a packaging material, and the metal layer covers the packaging material in a second direction; wherein, the first direction is perpendicular to the second direction; The packaging structure further includes a first spacer, a first end of the first spacer is connected to a first surface of the first chip, and a second end of the first spacer is connected to the metal layer; the first surface of the first chip is also connected to the substrate; wherein, the first surface of the first chip is used to indicate the surface of the first chip facing away from the substrate.

2. The encapsulation structure according to claim 1, wherein The packaging structure further includes a first bonding wire; A first end of the first bonding wire is connected to the first surface of the first chip, and a second end of the first bonding wire is connected to the substrate.

3. The encapsulation structure according to claim 1, characterized in that The packaging structure further includes a second spacer; The second spacer is located inside the first chip and is arranged along the first direction, a first end of the second spacer is connected to the first end of the first spacer, and a second end of the second spacer is connected to the substrate.

4. The encapsulation structure according to any one of claims 1 to 3, characterized in that The packaging structure further includes a second chip and a third spacer; The second chip is stacked with the substrate in the first direction, and the second chip is wrapped by the packaging material; The third spacer is located between the first chip and the second chip and is arranged along the first direction, a first end of the third spacer is connected to the substrate, and a second end of the third spacer is connected to the metal layer.

5. The encapsulation structure according to claim 4, wherein The first spacer is made of a second bonding wire or a metal material; The third spacer is made of a second bonding wire or a metal material.

6. The encapsulation structure according to claim 3, characterized in that, The second spacer is made of a metal material.

7. The packaging structure according to any one of claims 1 to 6, characterized in that The first spacer is configured to: conduct heat generated by the first chip to the metal layer; The metal layer is configured to: dissipate heat generated by the first chip.

8. The packaging structure according to claim 4 or 5, characterized in that The third spacer is configured to: conduct heat generated by the substrate to the metal layer; The metal layer is configured to: dissipate heat generated by the substrate.

9. An encapsulation structure, characterized in that: Comprising a substrate, a first chip, a second chip, and a metal layer; The substrate and the metal layer form a first cavity, and the substrate, the second chip, and the first chip are stacked in a first direction inside the first cavity; A fourth spacer is provided inside the first chip, and a fifth spacer is provided inside the second chip; both the fourth spacer and the fifth spacer are arranged along the first direction, a first end of the fourth spacer is connected to the metal layer, a second end of the fourth spacer is connected to a first end of the fifth spacer, and a second end of the fifth spacer is connected to the substrate.

10. A packaging method, characterized in that, Including: Fixing a first chip on a substrate in a first direction; Wrap the first chip with a packaging material, and form a first isolation member inside the packaging material along the first direction; wherein, the first end of the first isolation member is connected to the first surface of the first chip, and the first surface of the first chip is used to indicate the surface of the first chip facing away from the substrate; Form a metal layer outside the packaging material along the second direction; wherein, the first direction is perpendicular to the second direction, and the second end of the first isolation member is connected to the metal layer.

11. The encapsulation method according to claim 10, characterized in that, The packaging method further includes: Set a first bonding wire between the first surface of the first chip and the substrate by means of wire bonding; wherein, the first end of the first bonding wire is connected to the first surface of the first chip, and the second end of the first bonding wire is connected to the substrate.

12. The encapsulation method according to claim 10, wherein The packaging method further includes: Form a second isolation member inside the first chip along the first direction; wherein, the first end of the second isolation member is connected to the first end of the first isolation member, and the second end of the second isolation member is connected to the substrate.

13. The encapsulation method according to any one of claims 10 to 12, characterized in that, The packaging method further includes: Fix the second chip on the substrate along the first direction; Wrap the second chip with a packaging material; Form a third isolation member between the first chip and the second chip along the first direction; wherein, the first end of the third isolation member is connected to the substrate, and the second end of the third isolation member is connected to the metal layer.

14. The encapsulation method according to claim 13, wherein The first isolation member is made of a second bonding wire or a metal material; The third isolation member is made of a second bonding wire or a metal material.

15. The encapsulation method according to claim 12, wherein The second isolation member is made of a metal material.

16. A communication system, characterized in that, Comprising a circuit board and a packaging structure according to any one of claims 1 to 9; the packaging structure is disposed on the circuit board.

17. A radio frequency front-end module, characterized in that, Comprising a passive device and a packaging structure according to any one of claims 1 to 9; the passive device is connected to the packaging structure.

18. An electronic device, characterized in that, Comprising a power supply and a radio frequency front-end module according to claim 17; the power supply is connected to the radio frequency front-end module.

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