A neutral point voltage self-balancing three-level inverter and modulation method

Abstract

The application provides a neutral point voltage self-balancing three-level inverter and a modulation method, which comprises a capacitor balancing voltage dividing circuit and a T-type three-phase full-bridge inverter circuit; the capacitor balancing voltage dividing circuit can balance the neutral point voltage through parallel discharge design; the T-type full-bridge inverter circuit can generate three-phase three-level voltage; through the combination of the capacitor balancing voltage dividing circuit and the T-type three-phase full-bridge inverter circuit, three-phase voltage output is realized. Meanwhile, according to the characteristics of the inverter, an SVPWM modulation strategy capable of automatically balancing the neutral point voltage is provided. The application can realize three-phase three-level output, solve the problem of unbalanced neutral point voltage in traditional NPC-type and T-type three-level inverters, and effectively improve the quality and stability of the inverter output waveform.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power electronic DC / AC conversion, and particularly relates to a neutral point voltage self-balancing three-level inverter and a modulation method. BACKGROUND

[0002] As a core device in the field of medium and high voltage and large power electric energy conversion, the optimization of the topology structure of the three-level inverter has always been the research focus in the field of power electronics. The traditional T-type and neutral point clamped three-level inverter has long been facing the problem of neutral point potential imbalance due to its inherent topological characteristics. This phenomenon is particularly pronounced under low modulation ratio conditions, and its essence lies in the unbalanced characteristics of the charging and discharging current of the DC bus capacitor. The continuous shift of the neutral point potential will lead to an increase in the harmonic distortion rate of the output voltage, causing chain reactions such as the intensification of motor torque ripple and the deterioration of electromagnetic noise, and in severe cases, it will cause the overvoltage failure of the DC bus capacitor, significantly reducing the system reliability. To solve this problem, researchers have proposed a flying capacitor three-level inverter. This topology theoretically eliminates the neutral point shift through the dynamic balancing mechanism of the capacitor voltage by introducing a flying capacitor. However, in actual engineering applications, it is found that the flying capacitor must be equipped with a high-precision voltage sampling circuit and a complex space vector pulse width modulation strategy, resulting in an increase in the complexity of the control system and severely restricting its application in cost-sensitive industrial scenarios. SUMMARY

[0003] To solve the above problems, the application proposes a neutral point voltage self-balancing three-level inverter and a modulation method. The inverter includes a capacitor balancing voltage dividing circuit and a T-type full-bridge inverter circuit, wherein the capacitor balancing voltage dividing circuit is responsible for eliminating the neutral point voltage shift; and the T-type full-bridge inverter circuit is responsible for converting three voltage levels into three-phase voltage. Through the combination of the capacitor balancing voltage dividing circuit and the T-type three-phase bridge arm, three-phase voltage output is achieved.

[0004] In the first aspect, the application discloses a voltage self-balancing three-level inverter, which comprises a capacitor balancing voltage dividing circuit and a T-type three-phase full-bridge inverter circuit; wherein the capacitor balancing voltage dividing circuit is composed of a switch tube S1, a diode D1, a diode D2, a diode D3, a capacitor C1 and a capacitor C2; wherein one end of the switch tube S1 is connected to the positive electrode of a DC voltage source V dc , and the other end is connected to the diode D1, the capacitor C2 and the T-type three-phase full-bridge inverter circuit respectively, the other end of the diode D1 is connected to the capacitor C1 and the diode D2 respectively; and the other end of the capacitor C1 and the diode D3 is connected to the power supply V dcThe other end of the diode D2 is connected with the capacitor C2, the diode D3 and the T-type three-phase full-bridge inverter circuit respectively; the other end of the capacitor C2 is connected with the T-type three-phase full-bridge inverter circuit; and the T-type three-phase full-bridge inverter circuit is composed of A, B and C three-phase bridge arms.

[0005] The T-type three-phase full-bridge inverter circuit comprises:

[0006] The A-phase bridge arm is composed of the switch tube S a1 , the switch tube S a2 , the switch tube S a3 and the switch tube S a4 .

[0007] The B-phase bridge arm is composed of the switch tube S b1 , the switch tube S b2 , the switch tube S b3 and the switch tube S b4 .

[0008] The C-phase bridge arm is composed of the switch tube S c1 , the switch tube S c2 , the switch tube S c3 and the switch tube S c4 .

[0009] The A-phase bridge arm, the B-phase bridge arm and the C-phase bridge arm are connected in parallel.

[0010] The three-phase full-bridge inverter circuit adopts a space vector pulse width modulation strategy, decomposes a voltage reference vector into an alpha-beta coordinate system, and realizes three-phase alternating current output through synthesis of basic voltage vectors.

[0011] Preferably, the neutral point voltage self-balancing three-level device further comprises:

[0012] When the switch tube S1 is turned on, the capacitor C1 and the capacitor C2 are charged in series, and the output voltage of the capacitor balancing voltage dividing circuit is V dc . Ignoring the on-voltage drop of the diode D2, when the capacitor C1 and the capacitor C2 are fully charged, the output voltage of the capacitor C2 is about 0.5V dc .

[0013] When the switch tube S1 is turned off, the capacitor C1 and the capacitor C2 are discharged in parallel, and the output voltage of the capacitor balancing voltage dividing circuit is 0.5V dcTwo voltage dividing capacitors (C1 and C2) of the DC bus can be directly connected in parallel to supply power to the T-type three-phase full-bridge inverter, so as to realize automatic voltage balancing, i.e. the charge flows from the capacitor with high voltage to the capacitor with low voltage until the voltages of the two capacitors are equal, when the voltages of the two capacitors are unbalanced due to working conditions. In addition, the two capacitors provide current for the load after balancing the voltage, and the discharge rates are consistent, thereby avoiding over-discharge of a single capacitor. Through the ingenious design of the topology structure, the potential offset of the neutral point of the inverter is eliminated when the inverter is running after the final voltage balancing.

[0014] Preferably, when the switch tube S1 is turned on, the positive output voltage of the capacitor C2 is V dc , and the negative output voltage of the capacitor C2 is 0.5V dc . If the switch tube S a1 and the switch tube S a2 are turned on, the switch tube S a3 and the switch tube S a4 are turned off; the switch tube S b1 and the switch tube S b2 are turned on, the switch tube S b3 and the switch tube S b4 are turned off; the switch tube S c1 and the switch tube S c2 are turned on, the switch tube S c3 and the switch tube S c4 are turned off, the three-phase voltages U an , U bn and U cn of the inverter stages A, B and C passing through the T-type three-phase full-bridge inverter circuit are all V dc .

[0015] Preferably, when the switch tube S1 is turned on, the positive output voltage of the capacitor C2 is V dc , and the negative output voltage of the capacitor C2 is 0.5V dc . If the switch tube S a3 and the switch tube S a4 are turned on, the switch tube S a1 and the switch tube S a2 are turned off; the switch tube S b3 and the switch tube S b4 are turned on, the switch tube S b1 and the switch tube S b2 are turned off; the switch tube S c3 and the switch tube S c4 are turned on, the switch tube S c1 and the switch tube S c2 are turned off, the three-phase voltages U an , U bn and U cn of the inverter stages A, B and C passing through the T-type three-phase full-bridge inverter circuit are all 0.

[0016] Preferably, both of the above states are zero vector generating states, for charging the capacitors C1 and C2, and not affecting the neutral point voltage.

[0017] Preferably, when the switch S1 is off, the capacitors C1 and C2 are discharged in parallel, and the output voltage is 0.5V dc If the switch S a1 and the switch S a2 are on, the switch S a3 and the switch S a4 are off; the switch S b1 and the switch S b2 are on, the switch S b3 and the switch S b4 are off; the switch S c3 and the switch S c4 are on, the switch S c1 and the switch S c2 are off, then the three-phase voltages U an , U bn and U cn of the inverter stages A, B and C are V dc / 6, V dc / 6 and -V dc / 3 respectively through the T-type three-phase full-bridge inverter circuit.

[0018] Preferably, when the switch S1 is off, the capacitors C1 and C2 are discharged in parallel, and the output voltage is 0.5V dc If the switch S a1 and the switch S a2 are on, the switch S a3 and the switch S a4 are off; the switch S b3 and the switch S b4 are on, the switch S b1 and the switch S b2 are off; the switch S c3 and the switch S c4 are on, the switch S c1 and the switch S c2 are off, then the three-phase voltages U an , U bn and U cn of the inverter stages A, B and C are V dc / 3, -V dc / 6 and -V dc / 6 respectively through the T-type three-phase full-bridge inverter circuit.

[0019] Preferably, both the above two states are short vector generating states, the capacitor C1 and the capacitor C2 are discharged in parallel, and the neutral point voltage is automatically balanced.

[0020] Preferably, when the switch S1 is turned on, the positive output voltage of the capacitor C2 is V dc , the negative output voltage of the capacitor C2 is 0.5V dc , the switch S a1 and the switch S a2 are turned on, the switch S a3 and the switch S a4 are turned off; the switch S b1 and the switch S b2 are turned on, the switch S b3 and the switch S b4 are turned off; the switch S c3 and the switch S c4 are turned on, the switch S c1 and the switch S c2 are turned off, the three-phase voltages U an , U bn and U cn of the inverter stages A, B and C passing through the T-type three-phase full-bridge inverter circuit are respectively V dc / 3, V dc / 3 and -2V dc / 3.

[0021] Preferably, when the switch S1 is turned on, the positive output voltage of the capacitor C2 is V dc , the negative output voltage of the capacitor C2 is 0.5V dc , the switch S a1 and the switch S a2 are turned on, the switch S a3 and the switch S a4 are turned off; the switch S b3 and the switch S b4 are turned on, the switch S b1 and the switch S b2 are turned off; the switch S c3 and the switch S c4 are turned on, the switch S c1 and the switch S c2 are turned off, the three-phase voltages U an , U bn and U cn of the inverter stages A, B and C passing through the T-type three-phase full-bridge inverter circuit are respectively 2V dc / 3, -V dc / 3 and -V dc / 3.

[0022] Preferably, the above two states are long vector generating states, used for charging the capacitors C1 and C2 and outputting long vectors, and the potential of the neutral point is not affected.

[0023] Preferably, when the switch S1 is turned on, the positive output voltage of the capacitor C2 is V dc , the negative output voltage of the capacitor C2 is 0.5V dc , if the switch S a1 and the switch S a2 are turned on, the switch S a3 and the switch S a4 are turned off; the switch S b2 and the switch S b3 are turned on, the switch S b1 and the switch S b4 are turned off; the switch S c3 and the switch S c4 are turned on, the switch S c1 and the switch S c2 are turned off, then the three-phase voltage U an , U bn and U cn of the inverter stages A, B and C through the T-type three-phase full-bridge inverter circuit are respectively V dc / 2, 0 and -V dc / 2.

[0024] Preferably, the above state is a medium vector generating state, used for charging the capacitors C1 and C2 and outputting medium vectors, and the potential of the neutral point is affected.

[0025] Preferably, when the traditional T-type and NPC-type three-level inverters adopt the SVPWM modulation strategy, the selection of short vectors and medium vectors will affect the potential of the neutral point, but the application introduces the mechanism of discharging in parallel of two voltage balancing capacitors, and combines the modulation strategy to make the capacitor voltage naturally charge and discharge balanced, so that the zero vector, the short vector and the long vector do not affect the neutral point voltage balance, only the medium vector will affect the neutral point voltage. Since the application adopts seven-segment symmetrical wave generation, the influence of the medium vector on the neutral point voltage will be quickly eliminated by the short vector generated by the discharging of the two capacitors in parallel, so that a good effect of balancing the neutral point potential can be achieved.

[0026] In the second aspect, the application further provides a modulation strategy of a neutral point voltage self-balancing three-level inverter, comprising:

[0027] Definition: for the switch capacitor voltage regulation circuit of the previous stage, P represents that the switch S1 is turned on, the capacitors C1 and C2 are charged in series, and the positive output voltage of the capacitor C2 is V dc, the negative electrode output voltage of the capacitor C2 is 0.5V dc ; N indicates that the switch S1 is off, the capacitor C1 and the capacitor C2 are discharged in parallel, and the output voltage is 0.5V dc , and the effect of automatic voltage balance can be achieved; for the T-type three-phase inverter circuit in the rear stage, P indicates that the switch S x1 and the switch S x2 are turned on, and the switch S x3 and the switch S x4 are turned off; N indicates that the switch S x1 and the switch S x2 are turned off, and the switch S x3 and the switch S x4 are turned on; O indicates that the switch S x2 and the switch S x3 are turned on, and the switch S x1 and the switch S x4 are turned off (x=a, b, c);

[0028] According to the amplitude |u ref | of the target output voltage, the components of the reference vector in the α-β coordinate system are calculated: u α =|u ref |sin(wt), and u β =|u ref |cos(wt), and the sector in which the reference vector is located is determined, wherein the sector in which the reference vector is located includes 6 large sectors, and each large sector contains 4 small sectors. The three-level inverter space vector pulse width modulation method disclosed by the present application is based on a basic voltage vector system containing 2 zero vectors, 6 short vectors, 6 middle vectors and 6 long vectors. Each switch state has a one-to-one correspondence with the basic vector, and the method is characterized by the following modulation strategies:

[0029] (1) In terms of short vector selection, the short vector combination that forms a parallel discharge circuit of the capacitors C1 and C2 is preferentially selected;

[0030] (2) The selection of the zero vector needs to meet two conditions: ① has no disturbance influence on the balance of the neutral point potential of the DC bus; ② realizes the cooperative charging of the capacitors C1 and C2;

[0031] (3) The long vector has the characteristics of charging the capacitors C1 and C2 and keeping the neutral point potential stable;

[0032] (4) The middle vector will cause the neutral point potential to deviate when realizing the capacitor charging function, and therefore the dynamic combination strategy of the middle vector and the parallel discharge type short vector of C1 and C2 is adopted, the switch state is switched quickly through seven-segment symmetrical wave generation, the voltage balance of the short vector is used to offset the potential deviation introduced by the middle vector, and finally the dual control targets of DC bus capacitor voltage balance and neutral point potential stability are achieved.

[0033] When the reference vector is in the first small sector in the first large sector, the vector PNNN, the vector PPPP, the vector NPPN and the vector NPNN are synthesized;

[0034] Wherein, the basic vector PNNN and the vector PPPP are equivalent zero vectors, and the duty ratio is uniformly denoted as

[0035] The duty ratio of the vector NPPN is:

[0036] The duty ratio of the vector NPNN is:

[0037] When the reference vector is in the second small sector in the first large sector, the vector NPNN, the vector PPPN, the vector PPNN are synthesized;

[0038] Wherein:

[0039] The duty ratio of the vector NPNN is:

[0040]

[0041] The duty ratio of the vector PPPN is:

[0042]

[0043] The duty ratio of the vector PPNN is:

[0044]

[0045] When the reference vector is in the third small sector in the first large sector, the vector NPPN, the vector NPNN, the vector PPPN are synthesized;

[0046] Wherein:

[0047] The duty ratio of the vector NPPN is:

[0048]

[0049] The duty ratio of the vector NPNN is:

[0050]

[0051] The duty ratio of the vector PPPN is:

[0052]

[0053] When the reference vector is in the fourth small sector in the first large sector, the vector NPPN, the vector PPPN, the vector PPPN are synthesized;

[0054] Wherein:

[0055] The duty cycle of the vector NPPN is:

[0056]

[0057] The duty cycle of the vector PPPN is:

[0058]

[0059] The duty cycle of the vector PPON is:

[0060]

[0061] The duty cycle of the basic vector of other sectors only needs to be rotated to the first large sector in the alpha-beta coordinate system, and the same expression is used for solving; according to the reference vector synthesis order set by the first large sector, the synthesis path of the reference vector in other large sectors can be determined: the vector synthesis path of the third large sector and the fifth large sector is the same as that of the first large sector, and the vector synthesis path of the second large sector, the fourth large sector and the sixth large sector is opposite to that of the first large sector.

[0062] Compared with the prior art, the present application has the following beneficial effects:

[0063] The present application is a neutral point voltage self-balancing three-level inverter circuit, which effectively solves the problem of neutral point potential imbalance in midpoint clamping type and T-type three-level inverters, and effectively solves the problem of multiple sampling circuits and excessive use of components in flying capacitor type three-level inverters. The key innovations include the setting of the dual-function constraint condition of the zero vector, the dynamic compensation and cooperative mechanism of the middle vector and the short vector, and the fast state switching control method based on seven-segment modulation.

[0064] This technology is particularly suitable for fields with certain requirements for the stability, volume and heat dissipation of inverters, such as new energy vehicle electric drive systems and outdoor photovoltaic inverters. BRIEF DESCRIPTION OF DRAWINGS

[0065] Figure 1 is a schematic diagram of the topology of the neutral point voltage self-balancing three-level inverter of the present application.

[0066] Figure 2 is a simplified topology of the capacitor equalization voltage dividing circuit of the present application working in mode 1.

[0067] Figure 3 is a simplified topology of the capacitor equalization voltage dividing circuit of the present application working in mode 2.

[0068] Figure 4 is a circuit diagram of the present application under the switch state PPPP.

[0069] Figure 5 This is a circuit diagram of the present invention when the switch state is PNNN.

[0070] Figure 6 This is a circuit diagram of the present invention when the switch state is NPPN.

[0071] Figure 7 This is a circuit diagram of the present invention when the switch state is NPNN.

[0072] Figure 8 This is a circuit diagram of the present invention when the switch state is PPPN.

[0073] Figure 9 This is a circuit diagram of the present invention when the switch state is PPNN.

[0074] Figure 10 This is a circuit diagram of the present invention when the switch state is PPON.

[0075] Figure 11 It is the three-level SVPWM voltage vector diagram of the present invention.

[0076] Figure 12 is the reference vector u of the present invention ref Voltage composite diagram located in the first largest sector. DETAILED DESCRIPTION

[0077] The following description is intended to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are merely examples, and those skilled in the art may conceive of other obvious variations.

[0078] Example 1, as Figure 1 As shown, the present invention provides a three-level inverter with self-balancing neutral point voltage, comprising: a capacitor balancing voltage divider circuit and a T-type three-phase full-bridge inverter circuit; wherein the capacitor balancing voltage divider circuit is composed of a switch tube S1, a diode D1, a diode D2, a diode D3, a capacitor C1 and a capacitor C2; wherein one end of the switch tube S1 is connected to a DC voltage source V dc The positive electrode of the diode D1 is connected to the capacitor C2 and the T-type three-phase full-bridge inverter circuit respectively. The other end of the diode D1 is connected to the capacitor C1 and the diode D2 respectively; the other end of the capacitor C1 and the diode D3 is connected to the power supply V dc and the negative electrode of the T-type three-phase full-bridge inverter circuit, and the other end of the diode D2 is also connected to the capacitor C2, the diode D3 and the T-type three-phase full-bridge inverter circuit respectively; the other end of the capacitor C2 is connected to the T-type three-phase full-bridge inverter circuit; the T-type three-phase full-bridge inverter circuit is composed of three-phase bridge arms A, B, and C.

[0079] The three-phase bridge arm comprises:

[0080] A phase bridge arm, composed of switch S a1 , switch S a2 , switch S a3 and switch S a4 ;

[0081] B phase bridge arm, composed of switch S b1 , switch S b2 , switch S b3 and switch S b4 ;

[0082] C phase bridge arm, composed of switch S c1 , switch S c2 , switch S c3 and switch S c4 ;

[0083] Wherein, the A phase bridge arm, B phase bridge arm and C phase bridge arm are connected in parallel between them.

[0084] The neutral point voltage self-balancing three-level inverter adopts space vector pulse width modulation strategy, decomposes voltage reference vector to α-β coordinate system, and realizes three-phase alternating current output through synthesis of basic voltage vector.

[0085] Preferably, the capacitor equalization voltage dividing circuit described in the application has two working modes, Figure 2 , Figure 3 The circuit topological graph of the topology structure working in two working modes respectively, specifically includes:

[0086] Mode 1:

[0087] When the switch S1 is turned on, the capacitor C1 and C2 are in series charging state at this time, and the output voltage of the capacitor equalization voltage dividing circuit is maximum V dc ; ignoring the conduction voltage drop of diode D2, when the capacitor C1 and C2 are fully charged, the output voltage of the negative electrode of capacitor C2 is about 0.5V dc .

[0088] Mode 2:

[0089] When the switch S1 is turned off, the capacitor C1 and C2 are converted into parallel discharge state, and the discharge voltage is 0.5V dc, two voltage dividing capacitors (C1 and C2) of the DC bus are directly connected in parallel to supply power to the T-type three-phase full-bridge inverter, so that automatic voltage balancing can be realized, i.e. charges flow from the capacitor with high voltage to the capacitor with low voltage until the voltages of the two capacitors are equal. In addition, after the voltage balancing, the two capacitors together provide current to the load, and the discharge rate is consistent, avoiding over-discharge of a single capacitor. Through the ingenious design of the topology structure, after the final voltage balancing, the potential offset of the neutral point of the inverter during operation is eliminated.

[0090] By combining mode 1 and mode 2, the characteristics of the capacitor voltage cannot be abruptly changed are utilized to maintain the voltage balance of C1 and C2 during the charging and discharging process, without the need for additional voltage sampling or closed-loop control. A high switching frequency is set to achieve self-balancing voltage regulation of the capacitor, and the T-type three-phase full-bridge inverter circuit is combined to output line voltages of 0, ±0.5V dc , ±V dc five levels.

[0091] Preferably, as shown in Figure 4 , when the switch tube S1 is turned on, the capacitor balancing voltage dividing circuit works in mode 1 state, the positive output voltage of the capacitor C2 is V dc , and the negative output voltage of the capacitor C2 is 0.5V dc . If the switch tube S a1 and the switch tube S a2 are turned on, the switch tube S a3 and the switch tube S a4 are turned off; the switch tube S b1 and the switch tube S b2 are turned on, the switch tube S b3 and the switch tube S b4 are turned off; the switch tube S c1 and the switch tube S c2 are turned on, and the switch tube S c3 and the switch tube S c4 are turned off, then through the T-type three-phase full-bridge inverter circuit, the three-phase voltages U an , U bn and U cn of the inverter stages A, B and C are all V dc .

[0092] Preferably, as shown in Figure 5 , when the switch tube S1 is turned on, the capacitor balancing voltage dividing circuit works in mode 1 state, the positive output voltage of the capacitor C2 is V dc , and the negative output voltage of the capacitor C2 is 0.5V dc . If the switch tube S a3 and the switch tube S a4 are turned on, the switch tube S a1 and the switch tube S a2Turn off; switch tube S b3 and switch tube S b4 Turn on, switch tube S b1 and switch tube S b2 Turn off; switch tube S c3 and switch tube S c4 Turn on, switch tube S c1 and switch tube S c2 If the inverter is turned off, the three-phase voltage U of the inverter stages A, B and C will be an , U bn and U cn Both are 0.

[0093] Preferably, the above two states are both states of generating a zero vector, which is used to charge the capacitors C1 and C2 and has no effect on the potential of the neutral point.

[0094] Preferably, Figure 6 As shown, when the switch tube S1 is turned off, the capacitor balancing voltage divider circuit works in mode 2, the capacitors C1 and C2 are discharged in parallel, and the output voltage is 0.5V dc , if the switch tube S a1 and switch tube S a2 Turn on, switch tube S a3 and switch tube S a4 Turn off; switch tube S b1 and switch tube S b2 Turn on, switch tube S b3 and switch tube S b4 Turn off; switch tube S c3 and switch tube S c4 Turn on, switch tube S c1 and switch tube S c2 If the inverter is turned off, the three-phase voltage U of the inverter stages A, B and C will be an , U bn and U cn V dc / 6, V dc / 6, -V dc / 3.

[0095] Preferably, Figure 7 As shown, when the switch tube S1 is turned off, the capacitor balancing voltage divider circuit works in mode 2, the capacitors C1 and C2 are discharged in parallel, and the output voltage is 0.5V dc , if the switch tube S a1 and switch tube S a2 Turn on, switch tube S a3 and switch tube S a4 Turn off; switch tube S b3 and switch tube S b4Turn on, switch tube S b1 and switch tube S b2 Turn off; switch tube S c3 and switch tube S c4 Turn on, switch tube S c1 and switch tube S c2 If the inverter is turned off, the three-phase voltage U of the inverter stages A, B and C will be an , U bn and U cn V dc / 3, -V dc / 6, -V dc / 6.

[0096] Preferably, the above two states are both states in which a short vector is generated, the capacitor C1 and the capacitor C2 are discharged in parallel, and the neutral point voltage is automatically balanced.

[0097] Preferably, Figure 8 As shown, when the switch tube S1 is turned on, the capacitor balancing voltage divider circuit works in mode 1, and the positive output voltage of the capacitor C2 is V dc , the output voltage of the negative electrode of capacitor C2 is 0.5V dc , if the switch tube S a1 and switch tube S a2 Turn on, switch tube S a3 and switch tube S a4 Turn off; switch tube S b1 and switch tube S b2 Turn on, switch tube S b3 and switch tube S b4 Turn off; switch tube S c3 and switch tube S c4 Turn on, switch tube S c1 and switch tube S c2 If the inverter is turned off, the three-phase voltage U of the inverter stages A, B and C will be an , U bn and U cn V dc / 3, V dc / 3, -2V dc / 3.

[0098] Preferably, Figure 9 As shown, when the switch tube S1 is turned on, the capacitor balancing voltage divider circuit works in mode 1, and the positive output voltage of the capacitor C2 is V dc , the output voltage of the negative electrode of capacitor C2 is 0.5V dc , if the switch tube S a1 and switch tube S a2 Turn on, switch tube S a3 and switch tube Sa4 Turn off; switch tube S b3 and switch tube S b4 Turn on, switch tube S b1 and switch tube S b2 Turn off; switch tube S c3 and switch tube S c4 Turn on, switch tube S c1 and switch tube S c2 If the inverter is turned off, the three-phase voltage U of the inverter stages A, B and C will be an , U bn and U cn 2V respectively dc / 3, -V dc / 3, -V dc / 3.

[0099] Preferably, the above two states are both states of generating a long vector, which is used to charge the capacitor C1 and the capacitor C2 and output a long vector, and has no effect on the potential of the neutral point.

[0100] Preferably, Figure 10 As shown, when the switch tube S1 is turned on, the capacitor balancing voltage divider circuit works in mode 1, and the positive output voltage of the capacitor C2 is V dc , the output voltage of the negative electrode of capacitor C2 is 0.5V dc , if the switch tube S a1 and switch tube S a2 Turn on, switch tube S a3 and switch tube S a4 Turn off; switch tube S b2 and switch tube S b3 Turn on, switch tube S b1 and switch tube S b4 Turn off; switch tube S c3 and switch tube S c4 Turn on, switch tube S c1 and switch tube S c2 If the inverter is turned off, the three-phase voltage U of the inverter stages A, B and C will be an , U bn and U cn V dc / 2,0,-V dc / 2.

[0101] Preferably, the above state is a state of generating a neutral vector, which is used to charge the capacitors C1 and C2 and output the neutral vector to affect the potential of the neutral point.

[0102] Preferably, the traditional T-type and NPC-type three-level inverters adopt the SVPWM modulation strategy, the selection of short vectors and medium vectors will affect the neutral point potential, but the application introduces two voltage-sharing capacitors in parallel discharge mechanism, and the modulation strategy makes the capacitor voltage naturally charge and discharge balance, which can achieve zero vector, short vector, long vector, and medium vector, which will not affect the neutral point voltage. The influence of medium vector on the neutral point voltage will be quickly eliminated by the short vector generated by the parallel discharge of the two capacitors due to the use of seven-segment symmetrical wave generation and fast switching state switching, so that the effect of balancing the neutral point potential can be achieved.

[0103] Embodiment two: the application also proposes a modulation strategy of a neutral point voltage self-balancing three-level inverter, comprising:

[0104] Definition: for the front-stage switching capacitor voltage regulation circuit, P represents that the switch S1 is turned on, the capacitor C1 and the capacitor C2 are connected in series to charge, the positive electrode output voltage of the capacitor C2 is V dc , and the negative electrode output voltage of the capacitor C2 is 0.5V dc ; N represents that the switch S1 is turned off, the capacitor C1 and the capacitor C2 are connected in parallel to discharge, and the output voltage is 0.5V dc , and the effect of automatically balancing the voltage can be achieved; for the rear-stage T-type three-phase inverter circuit, P represents that the switch S x1 and the switch S x2 are turned on, and the switch S x3 and the switch S x4 are turned off; N represents that the switch S x1 and the switch S x2 are turned off, and the switch S x3 and the switch S x4 are turned on; O represents that the switch S x2 and the switch S x3 are turned on, and the switch S x1 and the switch S x4 are turned off (x=a, b, c);

[0105] According to the amplitude |u ref | of the target output voltage, the components of the target output voltage in the alpha-beta coordinate system are calculated: u α =|u ref |sin(wt), u β =|u ref |cos(wt), and the sector where the reference vector is located is determined, wherein the sector where the reference vector is located includes six large sectors, and each large sector contains four small sectors; for example Figure 11As shown, the three-level inverter space vector pulse width modulation method of the present application involves a basic voltage vector system containing 2 zero vectors, 6 short vectors, 6 medium vectors and 6 long vectors. Each switching state has a one-to-one correspondence with the basic vectors, and is characterized by the following modulation strategy:

[0106] (1) In terms of short vector selection, preferentially select the short vector combination that forms a parallel discharge circuit for capacitors C1 and C2;

[0107] (2) The selection of zero vectors needs to meet two conditions: ① has no disturbance effect on the balance of the DC bus neutral point potential; ② realizes the coordinated charging of capacitors C1 and C2;

[0108] (3) The long vector has the characteristics of charging capacitors C1 and C2 and maintaining the stability of the neutral point potential;

[0109] (4) The medium vector will produce a neutral point potential deviation when realizing the capacitor charging function. Therefore, a dynamic combination strategy of medium vectors and C1, C2 parallel discharge type short vectors is adopted, the switching state is quickly switched through seven-segment symmetrical wave generation, the voltage balance of the short vector is used to offset the potential deviation introduced by the medium vector, and finally the dual control objectives of DC bus capacitor voltage balance and neutral point potential stability are achieved.

[0110] The technical advantage of the present scheme is that, by optimizing the vector selection strategy and dynamic combination mechanism, the problems of capacitor voltage imbalance and neutral point potential drift existing in traditional three-level inverters are effectively solved, and the key innovations include the setting of the dual-function constraint condition of zero vectors, the dynamic compensation and coordination mechanism of medium vectors and short vectors, and the fast state switching control method based on seven-segment modulation.

[0111] As shown in Figure 11 , a space vector hexagon is formed using 20 basic vectors, the space vector hexagon is divided into six large sectors, each large sector is divided into four small areas, any vector can be synthesized by the basic vectors in the small area where it is located, the size of the basic vectors cannot be changed, the action time of each basic vector can be calculated according to the volt-second balance principle, thereby synthesizing the reference vector, and each basic vector is formed as follows:

[0112] Take the first large sector as an example:

[0113] When the switching state is PNNN, the switching tubes S1, S a3 , S a4 , S b3 , S b4 , S c3 , S c4 are turned on, and the switching tubes S a1 , S a2 , S b1 , Sb2 , S c1 , S c2 off, at this time the capacitor C1, C2 and power supply in series, the power supply through the switch tube S1 and diode D2 to the capacitor C1, C2 charging, D1 and D3 reverse cut-off, capacitor equalization voltage dividing circuit output voltage is V dc , and as the input of the inverter stage, through the T type three-phase full-bridge inverter, the three-phase voltage U an , U bn , U cn are 0.

[0114] Similarly, when the switch state is PPPP, switch S1, S a1 , S a2 , S b1 , S b2 , S c1 , S c2 on, switch S a3 , S a4 , S b3 , S b4 , S c3 , S c4 off, at this time the capacitor C1, C2 and power supply in series, the power supply through the switch tube S1 and diode D2 to the capacitor C1, C2 charging, D1 and D3 reverse cut-off, capacitor equalization voltage dividing circuit output voltage is V dc , and as the input of the inverter stage, through the T type three-phase full-bridge inverter, the three-phase voltage U an , U bn , U cn are V dc .

[0115] When the switch state is NPPN, switch S a1 , S a2 , S b1 , S b2 , S c3 , S c4 on, switch S1, S a3 , S a4 , S b3 , S b4 , S c1 , S c2 off, at this time the capacitor C1, C2 parallel discharge, capacitor C1 through the diode D1 discharge, capacitor C2 through the diode D3 discharge, at this time the diode D2 reverse cut-off, capacitor equalization voltage dividing circuit output voltage is 0.5V dc , the capacitor voltage is automatically balanced, and as the input of the inverter stage, through the T type three-phase full-bridge inverter, the three-phase voltage U an , Ubn , U cn , V dc / 6, V dc / 6, -V dc / 3.

[0116] When the switch state is NPNN, the switch tube S a1 , S a2 , S b3 , S b4 , S c3 , S c4 is turned on, the switch tube S1, S a3 , S a4 , S b1 , S b2 , S c1 , S c2 is turned off, at this time, the capacitor C1, C2 is discharged in parallel, the capacitor C1 is discharged through the diode D1, the capacitor C2 is discharged through the diode D3, at this time, the diode D2 is reverse cut-off, the output voltage of the capacitor voltage automatic balancing circuit is 0.5V dc , the capacitor voltage is automatically balanced and serves as the input of the inverter stage, through the action of the T-type three-phase full-bridge inverter, the three-phase voltage U an , U bn , U cn is: V dc / 3, -V dc / 6, -V dc / 6.

[0117] When the switch state is PPNN, the switch tube S1, S a1 , S a2 , S b3 , S b4 , S c3 , S c4 is turned on, the switch tube S a3 , S a4 , S b1 , S b2 , S c1 , S c2 is turned off, at this time, the capacitor C1, C2 is connected in series with the power supply, the power supply charges the capacitor C1, C2 through the switch tube S1 and the diode D2, D1 and D3 are reverse cut-off, the output voltage of the capacitor voltage automatic balancing circuit is V dc , and serves as the input of the inverter stage, through the action of the T-type three-phase full-bridge inverter, the three-phase voltage U an , U bn , U cn is: 2V dc / 3, -V dc / 3, -V dc / 3.

[0118] When the switch state is PPPN, the switch tubes S1, S a1 , S a2 , S b1 , S b2 , S c3 , S c4 are turned on, and the switch tubes S a3 , S a4 , S b3 , S b4 , S c1 , S c2 are turned off, at this time, the capacitors C1 and C2 are connected in series with the power supply, the power supply charges the capacitors C1 and C2 through the switch tube S1 and the diode D2, D1 and D3 are reverse-biased, the output voltage of the capacitor equalization voltage dividing circuit is V dc , and serves as the input of the inverter stage, through the action of the T-type three-phase full-bridge inverter, the three-phase voltages U an , U bn , U cn of the inverter stages A, B and C are V dc / 3, V dc / 3 and -2V dc / 3 in turn.

[0119] When the switch state is PPON, the switch tubes S1, S a1 , S a2 , S b2 , S b3 , S c3 , S c4 are turned on, and the switch tubes S a3 , S a4 , S b1 , S b4 , S c1 , S c2 are turned off, at this time, the capacitors C1 and C2 are connected in series with the power supply, the power supply charges the capacitors C1 and C2 through the switch tube S1 and the diode D2, D1 and D3 are reverse-biased, the positive output voltage of the capacitor C2 is V dc , and the negative output voltage of the capacitor C2 is 0.5V dc , and serves as the input of the inverter stage, through the action of the T-type three-phase full-bridge inverter, the three-phase voltages U an , U bn , U cn of the inverter stages A, B and C are V dc / 2, 0 and -V dc / 2 in turn.

[0120] Further, the space vector modulation strategy is adopted, as shown in Figure 12 , taking the first large sector as an example, when When the reference voltage vector is located in the first small sector, the voltage reference vector u ref is synthesized by the basis vectors u0, u1, u2; when the reference voltage vector is located in the second small sector, the voltage reference vector u ref is synthesized by the basis vectors u1, u3, u4; when the reference voltage vector is located in the fourth small sector, the voltage reference vector u ref is synthesized by the basis vectors u2, u4, u5; in addition to the above cases, the reference voltage vector is located in the third small sector, the voltage reference vector u ref is synthesized by the basis vectors u1, u2, u4.

[0121] When synthesizing the voltage reference vector, the following conditions should be met as much as possible: (1) When the short vector is configured as the parallel discharge mode of capacitors C1 and C2, the zero vector that can establish the series charging path of the two capacitors is selected synchronously, and through the cooperative action of the discharge-charge vector, the dynamic balance of the capacitor voltage is realized; (2) When the middle vector that causes the neutral point potential deviation is introduced, its action period must be coupled with the short vector that balances the neutral point voltage, and through the potential deviation of the vector pair, real-time compensation is realized to ensure that the neutral point potential deviation is completely eliminated within a single switching period; (3) Based on the symmetrically distributed pulse sequence structure, the action intervals of the capacitor charging vector, the discharge vector and the neutral point potential balancing vector are evenly distributed on the time axis, so that the functional vectors form a synergistic optimization relationship in terms of spatial symmetry and time sequence duty ratio, thereby improving the dynamic stability of the neutral point potential. (4) Within a switching period, the same basis voltage vector at the beginning and end is ensured to avoid the action of the switching tube when the switching period is connected in the same sector.

[0122] The above four measures can effectively reduce switching loss, reduce the adverse effects of neutral point voltage deviation, maintain capacitor voltage self-balance, and improve the reliability of circuit operation. Therefore, the modulation strategy adopts seven-segment symmetric wave emission, and the action sequence of the basis voltage vectors of each sector is summarized in Table 1.

[0123] Table 1 Action sequence table of basis voltage vectors

[0124]

[0125]

[0126] For the first large sector:

[0127] The reference voltage u ref is decomposed into the α-β axis as: u α = |u ref |sin(wt), u β = |u ref |cos(wt);

[0128] When the reference vector is in the first small sector in the first large sector, the vector PNNN, the vector PPPP, the vector NPPN and the vector NPNN are synthesized;

[0129] Wherein, the basis vector PNNN and the vector PPPP are equivalent zero vectors, and the duty ratio is uniformly denoted as

[0130] The duty ratio of the vector NPPN is:

[0131] The duty ratio of the vector NPNN is:

[0132] When the reference vector is in the second small sector in the first large sector, the vector NPNN, the vector PPPN, the vector PPNN are synthesized;

[0133] Wherein:

[0134] The duty ratio of the vector NPNN is:

[0135]

[0136] The duty ratio of the vector PPPN is:

[0137]

[0138] The duty ratio of the vector PPNN is:

[0139]

[0140] When the reference vector is in the third small sector in the first large sector, the vector NPPN, the vector NPNN, the vector PPPN are synthesized;

[0141] Wherein:

[0142] The duty ratio of the vector NPPN is:

[0143]

[0144] The duty ratio of the vector NPNN is:

[0145]

[0146] The duty ratio of the vector PPPN is:

[0147]

[0148] When the reference vector is in the fourth small sector in the first large sector, the vector NPPN, the vector PPPN, the vector PPPN are synthesized;

[0149] Wherein:

[0150] The duty cycle of the vector NPPN is:

[0151]

[0152] The duty cycle of the vector PPPN is:

[0153]

[0154] The duty cycle of the vector PPON is:

[0155]

[0156] The duty cycle of the basic vector of other sectors only needs to be rotated to the first large sector in the α-β coordinate system and solved by the same expression; according to the reference vector synthesis order set by the first large sector, the synthesis path of the reference vector in other large sectors can be determined: the vector synthesis path of the third large sector and the fifth large sector is the same as that of the first large sector, and the vector synthesis path of the second large sector, the fourth large sector and the sixth large sector is opposite to that of the first large sector.

[0157] The basic principle, main features and advantages of the present application are shown and described above. It should be understood by those skilled in the art that the present application is not limited by the above examples, and the above examples and descriptions in the specification are only the principles of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the claimed present application. The scope of protection required by the present application is defined by the appended claims and their equivalents.

Claims

1. A three-level inverter with self-balancing neutral point voltage, characterized in that: include: Capacitor balanced voltage divider circuit and T-type three-phase full-bridge inverter circuit; wherein, the capacitor balanced voltage divider circuit is composed of a switch tube S1, a diode D1, a diode D2, a diode D3, a capacitor C1 and a capacitor C2; wherein, one end of the switch tube S1 is connected to a DC voltage source V dc The positive electrode of the diode D1 is connected to the capacitor C2 and the T-type three-phase full-bridge inverter circuit respectively. The other end of the diode D1 is connected to the capacitor C1 and the diode D2 respectively; the other end of the capacitor C1 and the diode D3 is connected to the power supply V dc and the negative electrode of the T-type three-phase full-bridge inverter circuit, the other end of the diode D2 is also connected to the capacitor C2, the diode D3 and the T-type three-phase full-bridge inverter circuit respectively; the other end of the capacitor C2 is connected to the T-type three-phase full-bridge inverter circuit; the T-type three-phase full-bridge inverter circuit is composed of three-phase bridge arms A, B, and C; The T-type three-phase full-bridge inverter circuit comprises: Phase A bridge arm consists of switch tube S a1 , switch tube S a2 , switch tube S a3 and switch tube S a4 Composition: B phase bridge arm, consisting of switch tube S b1 , switch tube S b2 , switch tube S b3 and switch tube S b4 Composition; C phase bridge arm, consisting of switch tube S c1 , switch tube S c2 , switch tube S c3 and switch tube S c4 Composition; wherein the A-phase bridge arm, the B-phase bridge arm and the C-phase bridge arm are connected in parallel; When the switch tube S1, the switch tube S a3 , switch tube S a4 , switch tube S b3 , switch tube S b4 , switch tube S c3 And the switch tube S c4 Turn on, switch tube S a1 , switch tube S a2 , switch tube S b1 , switch tube S b2 , switch tube S c1 And the switch tube S c2 Turn off. At this time, capacitors C1 and C2 are connected in series with the power supply. The power supply charges capacitors C1 and C2 through switch tube S1 and diode D2. Diodes D1 and D3 are reverse-blocked. The output voltage of the capacitor balancing voltage divider circuit is V dc , and as the input of the inverter stage, after the action of T-type three-phase full-bridge inverter, the three-phase voltage U of the inverter stage A, B, and C an , U bn , U cn All are 0; When the switch tube S a1 , switch tube S a2 , switch tube S b1 , switch tube S b2 , switch tube S c3 , and the switch tube S c4 On, switch tube S1, switch tube S a3 , switch tube S a4 , switch tube S b3 , switch tube S b4 , switch tube S c1 , and the switch tube S c2 Turn off, at this time capacitor C1 and capacitor C2 discharge in parallel, capacitor C1 discharges through diode D1, capacitor C2 discharges through diode D3, at this time diode D2 is reverse cutoff, the output voltage of the capacitor balancing voltage divider circuit is 0.5V dc The capacitor voltage is automatically balanced and used as the input of the inverter stage. After the T-type three-phase full-bridge inverter, the three-phase voltage U of the inverter stage A, B, and C is an , U bn , U cn In order: V dc / 6, V dc / 6, -V dc / 3.

2. The three-level inverter with self-balancing neutral point voltage according to claim 1, characterized in that: The neutral point voltage self-balancing three-level inverter adopts a space vector pulse width modulation strategy, decomposes the voltage reference vector into an α-β coordinate system, and realizes three-phase AC output by synthesizing basic voltage vectors.

3. A three-level inverter with self-balancing neutral point voltage according to any one of claims 1-2, characterized in that: Also includes: When the switch S1 is turned on, capacitors C1 and C2 are charged in series, and the output voltage of the capacitor balancing voltage divider circuit is V dc Ignoring the conduction voltage drop of diode D2, when capacitors C1 and C2 are fully charged, the output voltage at the negative electrode of capacitor C2 is 0.5V. dc ; When the switch S1 is turned off, the capacitors C1 and C2 are discharged in parallel, and the output voltage of the capacitor balancing voltage divider circuit is 0.5V. dc ; When the voltages of the two voltage-dividing capacitors C1 and C2 of the DC bus are unbalanced, they are directly connected in parallel to power the T-type three-phase full-bridge inverter, so that the charge flows from the high-voltage capacitor to the low-voltage capacitor until the voltages of the two capacitors are equal. Among them, after balanced voltage division, capacitor C1 and capacitor C2 jointly provide current to the load, and the discharge rate is consistent.

4. The three-level inverter with self-balancing neutral point voltage according to claim 3, characterized in that: When the switch tube S1, the switch tube S a1 , switch tube S a2 , switch tube S b1 , switch tube S b2 , switch tube S c1 , and the switch tube S c2 Turn on, switch tube S a3 , switch tube S a4 , switch tube S b3 , switch tube S b4 , switch tube S c3 and switch tube S c4 Turn off. At this time, capacitors C1 and C2 are connected in series with the power supply. The power supply charges capacitors C1 and C2 through switch tube S1 and diode D2. Diodes D1 and D3 are reverse-blocked. The output voltage of the capacitor balancing voltage divider circuit is V dc , and as the input of the inverter stage, after the action of T-type three-phase full-bridge inverter, the three-phase voltage U of the inverter stage A, B, C an , U bn , U cn Both are V dc .

5. The three-level inverter circuit with self-balancing neutral point voltage according to claim 4, characterized in that: When the switch tube S a1 , switch tube S a2 , switch tube S b3 , switch tube S b4 , switch tube S c3 , switch tube S c4 On, switch tube S1, switch tube S a3 , switch tube S a4 , switch tube S b1 , switch tube S b2 , switch tube S c1 , and the switch tube S c2 Turn off, at this time capacitor C1 and capacitor C2 discharge in parallel, capacitor C1 discharges through diode D1, capacitor C2 discharges through diode D3, at this time diode D2 is reverse cutoff, the output voltage of the capacitor balancing voltage divider circuit is 0.5V dc The capacitor voltage is automatically balanced and used as the input of the inverter stage. After the T-type three-phase full-bridge inverter, the three-phase voltage U of the inverter stage A, B, and C is an , U bn , U cn In order: V dc / 3, -V dc / 6, -V dc / 6.

6. The three-level inverter with self-balancing neutral point voltage according to claim 5, characterized in that: When the switch tube S1, the switch tube S a1 , switch tube S a2 , switch tube S b3 , switch tube S b4 , switch tube S c3 , switch tube S c4 Turn on, switch tube S a3 , switch tube S a4 , switch tube S b1 , switch tube S b2 , switch tube S c1 , switch tube S c2 Turn off. At this time, capacitors C1 and C2 are connected in series with the power supply. The power supply charges capacitors C1 and C2 through switch tube S1 and diode D2. Diodes D1 and D3 are reverse-blocked. The output voltage of the capacitor balancing voltage divider circuit is V dc , and as the input of the inverter stage, after the action of T-type three-phase full-bridge inverter, the three-phase voltage U of the inverter stage A, B, and C an , U bn 、U cn In order: 2V dc / 3, -V dc / 3, -V dc / 3; When the switch tube S1, the switch tube S a1 , switch tube S a2 , switch tube S b1 , switch tube S b2 , switch tube S c3 and switch tube S c4 Turn on, switch tube S a3 , switch tube S a4 , switch tube S b3 , switch tube S b4 , switch tube S c1 and switch tube S c2 Turn off. At this time, capacitors C1 and C2 are connected in series with the power supply. The power supply charges capacitors C1 and C2 through switch tube S1 and diode D2. Diodes D1 and D3 are reverse-blocked. The output voltage of the capacitor balancing voltage divider circuit is V dc , and as the input of the inverter stage, after the action of T-type three-phase full-bridge inverter, the three-phase voltage U of the inverter stage A, B, and C an , U bn , U cn In order: V dc / 3, V dc / 3, -2V dc / 3.

7. The three-level inverter with self-balancing neutral point voltage according to claim 6, characterized in that: When the switch tube S1, the switch tube S a1 , switch tube S a2 , switch tube S b2 , switch tube S b3 , switch tube S c3 and switch tube S c4 Turn on, switch tube S a3 , switch tube S a4 , switch tube S b1 , switch tube S b4 , switch tube S c1 and switch tube S c2 Turn off. At this time, capacitors C1 and C2 are connected in series with the power supply. The power supply charges capacitors C1 and C2 through switch tube S1 and diode D2. Diodes D1 and D3 are reverse-blocked. The positive output voltage of capacitor C2 is V dc , the output voltage of the negative electrode of capacitor C2 is 0.5V dc , and as the input of the inverter stage, after the action of T-type three-phase full-bridge inverter, the three-phase voltage U of the inverter stage A, B, and C an , U bn , U cn In order: V dc / 2,0,-V dc / 2.

8. A modulation method for a three-level inverter with self-balancing neutral point voltage according to any one of claims 1 to 7, characterized in that: Definition: For the capacitor balanced voltage divider circuit of the previous stage, P means that the switch tube S1 is turned on, the capacitors C1 and C2 are charged in series, and the positive output voltage of the capacitor C2 is V dc , the output voltage of the negative electrode of capacitor C2 is 0.5V dc ; N means that the switch tube S1 is turned off, the capacitors C1 and C2 are discharged in parallel, and the output voltage is 0.5V dc , and can achieve the effect of automatic voltage balancing; for the subsequent T-type three-phase full-bridge inverter circuit, P represents the switch tube S x1 and switch tube S x2 The switch tube S is turned on x3 and switch tube S x4 Turn off; N represents the switch tube S x1 and switch tube S x2 Turn off and switch S x3 and switch tube S x4 On; O indicates switch tube S x2 and switch tube S x3 The switch tube S is turned on x1 and switch tube S x4 Turn off; where x = a, b, c; According to the target output voltage amplitude |u ref |Calculate its component in the α-β coordinate system: u α =|u ref |sin(wt),u β =|u ref |cos(wt), determine the sector where the reference vector is located, where the sector where the reference vector is located includes 6 large sectors, each of which contains 4 small sectors; When the reference vector is the first small sector in the first large sector, it is composed of the vector PNNN, the vector PPPP, the vector NPPN and the vector NPNN; Among them, the basic vector PNNN and the vector PPPP are equivalent zero vectors, and their duty cycles are uniformly recorded as The duty cycle of the vector NPPN is: The duty cycle of the vector NPNN is: When the reference vector is the second small sector in the first large sector, it is synthesized by vector NPNN, vector PPON, and vector PPNN; in: The duty cycle of the vector NPNN is: The duty cycle of vector PPON is: The duty cycle of the vector PPNN is: When the reference vector is the third small sector in the first large sector, it is composed of vector NPPN, vector NPNN, and vector PPON; in: The duty cycle of the vector NPPN is: The duty cycle of the vector NPNN is: The duty cycle of vector PPON is: When the reference vector is the fourth small sector in the first large sector, it is composed of vector NPPN, vector PPPN, and vector PPON; in: The duty cycle of the vector NPPN is: The duty cycle of the vector PPPN is: The duty cycle of vector PPON is: The basic vector duty cycle of other sectors only needs to be rotated to the first largest sector in the α-β coordinate system and solved using the same expression; according to the reference vector synthesis order set for the first largest sector, the synthesis path of the reference vectors in other large sectors is determined: the vector synthesis path of the third and fifth largest sectors is the same as that of the first largest sector, and the vector synthesis path of the second, fourth and sixth largest sectors is opposite to that of the first largest sector.

9. The modulation method according to claim 8, characterized in that: In terms of short vector selection, a short vector combination is selected that forms a parallel discharge circuit between capacitors C1 and C2; The zero vector selection must simultaneously meet the following requirements: no disturbance to the DC bus neutral point potential balance; and coordinated charging of capacitors C1 and C2; The middle vector selects a dynamic combination strategy of short vectors that discharge in parallel with capacitors C1 and C2. Through seven-segment symmetrical wave generation, the switching state is completed. The voltage balance of the short vector is used to offset the potential deviation introduced by the middle vector, ultimately achieving DC bus capacitor voltage balance and neutral point potential stability.

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