Radio frequency switch control circuit, chip and radio frequency front-end module

Abstract

The invention relates to the technical field of integrated radio frequency front ends, in particular to a radio frequency switch control circuit, a chip and a radio frequency front end module, a first delay module is used for performing first delay processing on an overturning edge of a first control signal to output a first delay signal with a first control signal segment; the second delay module is used for performing second delay processing on the overturning edge of the second control signal to output a second delay signal with a second control signal segment; the signal output module is used for outputting a clock frequency control signal according to the first delay signal and the second delay signal; the first delay module and the second delay module are adapted to different control scenes, and control signal segments with different delay durations are generated according to the flipping edges of different control signals, so that the clock signal has high-frequency clock segments with different durations in different control scenes. A high-frequency clock segment with relatively long duration is provided for a control scene with relatively low voltage, and the stabilization speed of the control voltage can be improved.

Description

Technical Field

[0001] This application relates to the technical field of radio frequency front-ends, and in particular, to a radio frequency switch control circuit, a chip, and a radio frequency front-end module. Background Art

[0002] The conduction or cutoff of a radio frequency switch requires a relatively high control voltage, which can be provided by a charge pump circuit. When the charge pump circuit operates, it requires a clock signal. The higher the frequency of the clock signal, the faster the charge pump circuit raises the voltage, and the control voltage output by the charge pump circuit can reach the voltage stable state faster.

[0003] Currently, the method of providing a clock signal for the charge pump cannot adapt to different control scenarios, which is not conducive to improving the stable speed of the control voltage. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a radio frequency switch control circuit, a chip, and a radio frequency front-end module to solve the above technical problem of not being conducive to improving the stable speed of the control voltage.

[0005] In a first aspect, an embodiment of this application provides a radio frequency switch control circuit, including:

[0006] A first delay module, configured to perform a first delay process on the flip edge of a first control signal and output a first delay signal. The first delay signal includes a first control signal segment in a first level state. The starting moment of the first control signal segment is the flip edge moment of the first control signal, and the width of the first control signal segment is a first delay time;

[0007] A second delay module, configured to perform a second delay process on the flip edge of a second control signal and output a second delay signal. The second delay signal includes a second control signal segment in a first level state. The starting moment of the second control signal segment is the flip edge moment of the second control signal, and the width of the second control signal segment is a second delay time, where the second delay time is greater than the first delay time;

[0008] A signal output module, configured to output a clock frequency control signal according to the first delay signal and the second delay signal. The clock frequency control signal is used to control the frequency of a clock signal, and the clock signal is used to generate a radio frequency switch control signal through a charge pump circuit.

[0009] Optionally, the first delay module includes:

[0010] A first frequency division unit, configured to perform a first frequency division process on a target clock signal and output a first divided clock signal;

[0011] The first triggering unit includes a first clock terminal, a first reset terminal, a first input terminal, and a first output terminal. The first clock terminal is used to receive the first divided-frequency clock signal, the first reset terminal is used to receive a first reset signal, the first input terminal is used to receive an input signal in a second level state, and the first output terminal is used to output the first delay signal. The first reset signal is obtained according to the first control signal, and the first reset signal resets the first delay signal to a first level state at the transition edge of the first control signal.

[0012] Optionally, the second delay module includes:

[0013] A second frequency division unit for performing a second frequency division process on the target clock signal to output a second divided-frequency clock signal, and the frequency of the second divided-frequency clock signal is less than the frequency of the first divided-frequency clock signal;

[0014] A second triggering unit includes a second clock terminal, a second reset terminal, a second input terminal, and a second output terminal. The second clock terminal is used to receive the second divided-frequency clock signal, the second reset terminal is used to receive the second control signal, the second input terminal is used to receive an input signal in a second level state, and the second output terminal is used to output the second delay signal. The second triggering unit is started at the transition edge of the second control signal, and the second delay signal is initialized to a first level state.

[0015] Optionally, the first frequency division unit includes a plurality of cascaded third flip-flops. The input terminal of the third flip-flop is connected to its inverted output terminal, the inverted output terminal of the previous-stage third flip-flop is connected to the clock terminal of the next-stage third flip-flop. The clock terminal of the first-stage third flip-flop is used to receive the target clock signal, and the output terminal of the last-stage third flip-flop is used to output the first divided-frequency clock signal.

[0016] Optionally, the second frequency division unit includes a plurality of cascaded fourth flip-flops. The input terminal of the fourth flip-flop is connected to its inverted output terminal, the inverted output terminal of the previous-stage fourth flip-flop is connected to the clock terminal of the next-stage fourth flip-flop. The clock terminal of the first-stage fourth flip-flop is used to receive the target clock signal, and the output terminal of the last-stage fourth flip-flop is used to output the second divided-frequency clock signal; the number of the fourth flip-flops is greater than the number of the third flip-flops.

[0017] Optionally, the reset terminals of the third flip-flop and the fourth flip-flop are respectively used to receive the first reset signal.

[0018] Optionally, the first frequency division unit includes N cascaded third flip - flops, and the second frequency division unit includes M cascaded fourth flip - flops, where M is greater than N, and the N third flip - flops are multiplexed as the first N fourth flip - flops among the M cascaded fourth flip - flops.

[0019] Optionally, the radio frequency switch control circuit further includes a reset signal generation module, and the reset signal generation module includes:

[0020] A first delay unit, configured to output a first adjustment signal. When receiving the falling edge or rising edge of the first control signal, it flips the level state of the first adjustment signal to the first level state and maintains it for a first set duration, and the first set duration is less than the first delay time.

[0021] A first AND operation unit, configured to perform an AND operation on the first adjustment signal and the second adjustment signal to output the first reset signal, where the second adjustment signal is obtained according to the second control signal.

[0022] Optionally, the reset signal generation module further includes:

[0023] A second delay unit, configured to delay the falling edge or rising edge of the second control signal for a second set duration to output the second adjustment signal. The second adjustment signal includes an adjustment signal segment with the first level state, the starting moment of the adjustment signal segment is the moment of the falling edge or rising edge of the second control signal, and the time difference between the ending moment of the adjustment signal segment and the moment of the falling edge or rising edge of the second control signal is the second set duration.

[0024] The first AND operation unit is configured to perform an AND operation on the first adjustment signal and the second adjustment signal to output the first reset signal.

[0025] Optionally, the first delay unit includes:

[0026] An inverting delay sub - unit, configured to delay the inverted signal of the first control signal for the first set duration to output an inverted delay signal.

[0027] An exclusive - OR operation sub - unit, configured to perform an exclusive - OR operation on the first control signal and the inverted delay signal to output the first adjustment signal.

[0028] Optionally, the first delay module includes:

[0029] A first inverting delay unit, configured to delay the inverted signal of the first control signal for the first delay time to output a first inverted delay control signal.

[0030] The first exclusive OR operation unit is configured to perform an exclusive OR operation on the first control signal and the first inverted delay control signal, and output the first delay signal.

[0031] Optionally, the second delay module includes:

[0032] An RC delay unit, whose delay time is equal to the second delay time, is configured to delay the second control signal by the second delay time to generate the second delay signal.

[0033] Optionally, the signal output module includes:

[0034] The second AND operation unit is configured to perform an AND operation on the first delay signal and the second delay signal, and output the clock frequency control signal.

[0035] Optionally, the RF switch control circuit further includes:

[0036] A clock generation module is configured to generate a target clock signal according to the clock frequency control signal, and the level state of the clock frequency control signal is used to indicate the frequency of the target clock signal.

[0037] Optionally, the first control signal is used to indicate the state of the RF switch, and the second control signal is used to indicate the power-on reset state.

[0038] In a second aspect, an embodiment of the present application provides a chip, which includes the above-mentioned RF switch control circuit.

[0039] In a third aspect, an embodiment of the present application provides a RF front-end module, which includes the above-mentioned RF switch control circuit or the above-mentioned chip.

[0040] Optionally, the RF front-end module includes a control chip and a switch chip; the control chip includes:

[0041] The RF switch control circuit is configured to output a clock frequency control signal;

[0042] An oscillator is configured to control the frequency of the clock signal according to the clock frequency control signal and output the clock signal;

[0043] A charge pump circuit is configured to generate a RF switch control signal according to the clock signal;

[0044] The switch chip includes at least one RF switch, and the control end of the RF switch is used to receive the RF switch control signal.

[0045] The radio frequency switch control circuit, chip and radio frequency front-end module provided by the embodiments of the present application. The first delay module is used to perform a first delay process on the rising or falling edge of the first control signal to output a first delay signal having a first control signal segment, and the first control signal segment is in a first level state that lasts for a first delay time starting from the edge moment; the second delay module is used to perform a second delay process on the rising or falling edge of the second control signal to output a second delay signal having a second control signal segment, and the second control signal segment is in a first level state that lasts for a second delay time starting from the edge moment; the signal output module is used to output a clock frequency control signal according to the first delay signal and the second delay signal, and the clock frequency control signal is used to control the frequency of a clock signal, and this clock signal is used to generate a radio frequency switch control signal through a charge pump circuit; by adapting different control scenarios through the first delay module and the second delay module, control signal segments with different delay durations are generated according to the rising or falling edges of different control signals, so that the clock signal has high-frequency clock segments with different durations in different control scenarios, realizing providing a relatively longer high-frequency clock segment for a control scenario with a relatively lower voltage, which is beneficial to improving the stable speed of the control voltage.

[0046] These aspects or other aspects of the present application will be more clearly understood in the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 The structural schematic diagram of the radio frequency switch control circuit provided by the embodiments of the present application is shown.

[0048] Figure 2 The timing schematic diagram of each signal in the radio frequency switch control circuit provided by the embodiments of the present application is shown.

[0049] Figure 3 The structural schematic diagram of another implementation manner of the radio frequency switch control circuit provided by the embodiments of the present application is shown.

[0050] Figure 4 The structural schematic diagram of another implementation manner of the radio frequency switch control circuit provided by the embodiments of the present application is shown.

[0051] Figure 5 The structural schematic diagram of another implementation manner of the radio frequency switch control circuit provided by the embodiments of the present application is shown.

[0052] Figure 6 The structural schematic diagram of another implementation manner of the radio frequency switch control circuit provided by the embodiments of the present application is shown.

[0053] Figure 7 Shows Figure 6 The signal timing schematic diagram of the first delay unit in the shown radio frequency switch control circuit.

[0054] Figure 8 The structural schematic diagram of another embodiment of the RF switch control circuit provided by the embodiment of the present application is shown.

[0055] Figure 9 The structural schematic diagram of another embodiment of the RF switch control circuit provided by the embodiment of the present application is shown.

[0056] Figure 10 The structural schematic diagram of the chip provided by the embodiment of the present application is shown.

[0057] Figure 11 The structural schematic diagram of the RF front-end module provided by the embodiment of the present application is shown.

[0058] Figure 12 The structural schematic diagram of another RF front-end module provided by the embodiment of the present application is shown. Specific embodiments

[0059] The following describes in detail the embodiments of the present application. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below with reference to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.

[0060] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.

[0061] In the embodiments of the present application, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0062] Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0063] In the description of the embodiments of the present application, words such as "example" or "for example" are used to give examples, explanations, or descriptions. Any embodiment or design solution described as "for example" or "for instance" in the embodiments of the present application is not construed as being more preferred or having more advantages than another embodiment or design solution. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0064] In addition, "a plurality of" in the embodiments of the present application means two or more. In view of this, "a plurality of" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two, or more. For example, including at least one means including one, two, or more, and it does not limit which ones are included. For example, including at least one of A, B, and C, then what can be included is A, B, C, A and B, A and C, B and C, or A, B, and C.

[0065] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally represents an "or" relationship between the front and rear associated objects.

[0066] It should be pointed out that "connection" in the embodiments of the present application can be understood as electrical connection. The connection of two electrical components can be a direct or indirect connection between the two electrical components. For example, when A is connected to B, it can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0067] The radio frequency switch control circuit of the embodiments of the present application can be applied in a radio frequency front-end module. A control chip and a switch chip are provided in the radio frequency front-end module. The radio frequency switch control circuit is provided in the control chip. The control chip also includes a charge pump circuit. At least one radio frequency switch is provided in the switch chip. The control chip is used to provide a control voltage for the radio frequency switch. Among them, the radio frequency switch control circuit is used to output a clock frequency control signal, and the clock frequency control signal is used to control the frequency of the clock signal output to the charge pump circuit. The charge pump circuit generates the control voltage of the radio frequency switch in the switch chip according to the clock signal.

[0068] An embodiment of the present application provides a radio frequency switch control circuit 100. Please refer to Figure 1 As shown, the radio frequency switch control circuit 100 of this embodiment includes a first delay module 11, a second delay module 12, and a signal output module 13.

[0069] Among them, the first delay module 11 is used to perform a first delay process on the rising or falling edge of the first control signal and output a first delay signal. The first delay signal includes a first control signal segment with a first level state. The starting moment of the first control signal segment is the moment of the rising or falling edge of the first control signal, and the width of the first control signal segment is the first delay time. The first control signal corresponds to a first control scenario, and the rising or falling edge of the first control signal is used to indicate the change of the control state in the first control scenario.

[0070] Specifically, the first control scenario can be the control scenario when the radio frequency switch state is switched. The rising or falling edge of the first control signal IN is used to indicate the change of the radio frequency switch state, such as switching from on to off, or from off to on. Please refer to Figure 2 As shown, starting from the moment of the rising or falling edge of the first control signal IN, the first delay signal t1_2 generates a first level state that lasts for the first delay time. Exemplarily, in Figure 2 it, the rising or falling edge of the first control signal is the rising edge, and the first level state is the low level state.

[0071] Among them, the second delay module 12 is used to perform a second delay process on the rising or falling edge of the second control signal and output a second delay signal. The second delay signal includes a second control signal segment with a first level state. The starting moment of the second control signal segment is the moment of the rising or falling edge of the second control signal, and the width of the second control signal segment is the second delay time. The second control signal corresponds to a second control scenario, and the rising or falling edge of the second control signal is used to indicate the change of the control state in the second control scenario.

[0072] Specifically, the second control scenario is the power-on startup control scenario. Please refer to Figure 2 As shown, the second control signal POR is a power-on reset signal. The rising or falling edge of the second control signal POR is the rising edge. The rising edge of the second control signal POR is used to indicate the moment when the radio frequency switch control circuit 100 has completed power-on and released the power-on reset signal.

[0073] Starting from the moment of the rising or falling edge of the second control signal POR, the second delay signal t2_3 generates a first level state that lasts for the second delay time. Exemplarily, in Figure 2Among them, the first level state is a low level state. It can be understood that before the rising edge of the second control signal POR appears, the radio frequency switch control circuit 100 is in an unstarted state. Therefore, the port corresponding to the second control signal POR presents a low level, and other signals obtained according to the second control signal POR, such as the second delay signal t2_3, also present a low level. Before power-on startup, the low level state of the second delay signal t2_3 is not caused by the operation of the second delay module 12. Therefore, before the rising edge of the second control signal POR appears, the low level state of the second delay signal t2_3 is not included in the second delay duration. In other words, in Figure 2 Among them, the second delay time refers to the time between the rising edge moment of the second control signal POR and the rising edge moment of the second delay signal t2_3.

[0074] The signal output module 13 is used to output a clock frequency control signal according to the first delay signal and the second delay signal. The clock frequency control signal is used to control the frequency of the clock signal, and the clock signal is used to generate a radio frequency switch control signal through a charge pump circuit.

[0075] When the clock frequency control signal is in the first level state, the clock signal is a high-frequency clock signal, and the voltage of the radio frequency switch control signal increases until it reaches a stable state; subsequently, the clock frequency control signal switches from the first level state to the second level state, the clock signal switches to a low-frequency clock signal, and the radio frequency switch control signal is in a stable state.

[0076] The flip edge of the first control signal indicates that the control state of the first control scenario changes. The first control signal segment (the first level state of the first delay time) in the first delay signal corresponds to the first high-frequency clock time period of the clock frequency control signal. The first control signal segment in the first delay signal corresponds to the high-frequency clock segment of the clock signal during the first delay time. When the flip edge of the first control signal appears, the clock signal remains a high-frequency clock signal within the first delay time.

[0077] The flip edge of the second control signal indicates that the control state of the second control scenario changes. The second control signal segment (the first level state of the second delay time) in the second delay signal corresponds to the high-frequency clock time period of the clock frequency control signal. The second control signal segment in the second delay signal corresponds to the high-frequency clock segment of the clock signal during the second delay time. When the flip edge of the second control signal appears, the corresponding clock signal remains a high-frequency clock signal within the second delay time.

[0078] Among them, the second delay time is greater than the first delay time, and the duration of the high-frequency clock segment corresponding to the change of the control state in the second control scenario is greater than the duration of the high-frequency clock segment corresponding to the change of the control state in the first control scenario.

[0079] Exemplarily, after the power-on of the radio frequency switch and the radio frequency switch control circuit 100 is completed, that is, after the power supply voltage is stabilized at a high level, the radio frequency switch control circuit 100 will enter the second control scenario and output the first control signal segment with a second delay time to control the oscillator to generate a high-frequency clock with a duration of the second delay time; after the end of the second delay time, the clock frequency control signal output by the radio frequency switch control circuit 100 switches to another level state, so that the output signal of the oscillator switches to a low-frequency clock until the state of the radio frequency switch needs to change, and then enters the first control scenario. In the first control scenario, the radio frequency switch control circuit outputs the second control signal segment with a first delay time to control the oscillator to generate a high-frequency clock with a duration of the first delay time; after the end of the first delay time, the clock frequency control signal output by the radio frequency switch control circuit 100 switches to another level state until the state of the radio frequency switch needs to be switched again, that is, enters the next first control scenario.

[0080] Those skilled in the art should understand that the oscillator can generate clock signals with at least two frequencies. For any two of these clock signals, the clock signal with a higher frequency is the high-frequency clock, and the clock signal with a lower frequency is the low-frequency clock. The high-frequency clock and the low-frequency clock only need to satisfy the difference in frequency. There is no limit to the frequency difference between the high-frequency clock and the low-frequency clock, nor is there any limit to the upper and lower frequency limits of the high-frequency clock and the upper and lower frequency limits of the low-frequency clock.

[0081] In this embodiment, the first delay module and the second delay module are adapted to different control scenarios, and control signal segments with different delay durations are generated according to the inversion edges of different control signals, so that the clock signal has high-frequency clock segments with different durations in different control scenarios, realizing providing a relatively longer high-frequency clock segment for the control scenario with a relatively lower voltage, which is beneficial to improving the stable speed of the control voltage.

[0082] As an implementation manner, please refer to Figure 3 As shown, the first delay module 11 includes a first frequency division unit 111 and a first trigger unit 112.

[0083] The first frequency division unit 111 is used to perform a first frequency division process on the target clock signal and output a first frequency division clock signal.

[0084] The first trigger unit 112 includes a first clock terminal CK1, a first reset terminal R1, a first input terminal D1, and a first output terminal Q1. The first clock terminal CK1 is used to receive the first frequency division clock signal output by the first frequency division unit 111, the first reset terminal R1 is used to receive the first reset signal, the first input terminal D1 is used to receive the input signal of the second level state, and the first output terminal Q1 is used to output the first delay signal. Exemplarily, the first trigger unit 121 can be a D flip-flop.

[0085] Among them, the first reset signal RST is obtained according to the first control signal IN, and the first reset signal RST resets the first delay signal t1_2 to the first level state at the inversion edge moment of the first control signal IN.

[0086] The first reset signal RST is in the second level state before the inversion edge of the first control signal IN appears, and the first delay signal t1_2 is also in the second level state before the inversion edge of the first control signal appears. The first reset signal RST switches to the first level state when the inversion edge of the first control signal IN appears, and the first delay signal is reset to the first level state until the first reset signal RST switches back to the second level state again. And after the first reset signal RST switches to the second level state, at the valid edge of the first divided clock signal, the first delay signal t1_2 switches back to the second level state again. The valid edge can be the rising edge or the falling edge. The first delay time t1 is the duration of the first level state in the first delay signal t1_2, that is, the sum of the duration of the first level state in the first reset signal RST and the first timing time. The first timing time is the duration between the first moment when the first reset signal RST switches back to the second level state again and the first valid edge moment of the first divided clock signal after the first moment.

[0087] Exemplarily, as shown in Figure 2 the first level state can be the low level state, and the second level state can be the high level state.

[0088] In this embodiment, the first divided clock signal is provided for the first trigger unit by the first dividing unit, and the output of the first delay signal is realized by the first trigger unit. Since both the first dividing unit and the first trigger unit are digital circuits, the occupied area is much smaller than that of an analog delay circuit capable of delaying the same duration. Therefore, it is beneficial to reduce the overall area of the radio frequency switch control circuit. In addition, using the first dividing unit and the first trigger unit to realize the delay, compared with using an analog delay circuit, can make the first delay time more convergent, that is, under the condition of power supply voltage or other fluctuations, the first delay time can be more stably maintained at the set value and is not prone to deviation.

[0089] As an implementation manner, please continue to refer to Figure 3 shown in the figure, the second delay module 12 includes a second dividing unit 121 and a second trigger unit 122.

[0090] The second dividing unit 121 is used to perform second dividing processing on the target clock signal CLK and output a second divided clock signal, and the frequency of the second divided clock signal is less than the frequency of the first divided clock signal.

[0091] The second trigger unit 122 includes a second clock terminal CK2, a second reset terminal R2, a second input terminal D2, and a second output terminal Q2. The second clock terminal CK2 is used to receive a second divided clock signal, the second reset terminal R2 is used to receive a second control signal POR, the second input terminal D2 is used to receive an input signal in a second level state, and the second output terminal Q2 is used to output a second delay signal t2_3. The second trigger unit 122 is started at the falling edge moment of the second control signal POR, and the second delay signal t2_3 is initialized to a first level state. Exemplarily, the second trigger unit 122 can be a D flip-flop.

[0092] After the falling edge of the second control signal POR appears, that is, after the second control signal POR starts to be in the second level state, the second trigger unit 122 is started. The starting moment of the second trigger unit 122 is the falling edge moment of the second control signal POR, while the starting moment of the first frequency division unit 121 can be the falling edge moment of the second control signal POR or later than the falling edge moment of the second control signal POR. Starting from the starting moment of the second trigger unit 122, the second delay signal t2_3 is initialized to the first level state until a valid edge appears in the second divided clock signal, and the second delay signal t2_3 switches to the second level state. The valid edge can be a rising edge or a falling edge. The second delay time t2 is the duration of the first level state in the second delay signal t2_3. The second delay time t2 is the second timing time, and the second timing time is the duration between the second moment when the second trigger unit 122 is started and the first valid edge moment of the second divided clock signal after the second moment. Among them, the frequency of the second divided clock signal is less than the frequency of the first divided clock signal, and the period of the second divided signal is greater than the period of the first divided signal. Therefore, the second timing time is much greater than the first timing time, and the second timing time can be easily configured to be greater than the sum of the duration of the first level state in the first reset signal RST and the first timing time, so that the second delay time t2 is greater than the first delay time t1.

[0093] In this embodiment, the second divided clock signal is provided for the second trigger unit by the second frequency division unit, and the output of the second delay signal is realized by the second trigger unit. Since both the second frequency division unit and the second trigger unit are digital circuits, the occupied area is much smaller than that of an analog delay circuit capable of delaying the same duration. Therefore, it is beneficial to reduce the overall circuit area of the RF switch control circuit. In addition, using the second frequency division unit and the second trigger unit to achieve delay, compared with using an analog delay circuit, can make the second delay time more convergent, that is, under the condition of power supply voltage or other fluctuations, the second delay time can be more stably maintained at the set value and is not prone to deviation.

[0094] In some embodiments, please refer to Figure 4As shown, the first frequency division unit 111 includes a plurality of cascaded third flip-flops 1111. The input terminal D3 of the third flip-flop 1111 is connected to its inverted output terminal Q3'. The inverted output terminal Q3' of the previous-stage third flip-flop 111 is connected to the clock terminal CK3 of the next-stage third flip-flop 1111. The clock terminal CK3 of the first-stage third flip-flop 1111 is used to receive the target clock signal, and the output terminal of the last-stage third flip-flop 1111 is used to output the first frequency-divided clock signal. Exemplarily, the third flip-flop 1111 is a D flip-flop.

[0095] Wherein, the frequency of the first frequency-divided clock signal is related to the number of the third flip-flops 1111. The more the number of the third flip-flops 1111, the smaller the frequency and the longer the period of the first frequency-divided clock signal, and the longer the first delay time corresponding to the first delay signal output after passing through the first trigger unit 112.

[0096] In this embodiment, the first frequency division unit is constructed by cascading third flip-flops. Since each third flip-flop is a digital circuit, the occupied area is much smaller than that of the analog frequency division circuit for frequency division. Therefore, it is beneficial to reduce the overall area of the radio frequency switch control circuit.

[0097] In some embodiments, please continue to refer to Figure 4 As shown, the second frequency division unit 121 includes a plurality of cascaded fourth flip-flops 1211. The input terminal D4 of the fourth flip-flop 1211 is connected to its inverted output terminal Q4'. The inverted output terminal Q4' of the previous-stage fourth flip-flop 1211 is connected to the clock terminal CK4 of the next-stage fourth flip-flop 1211. The clock terminal CK4 of the first-stage fourth flip-flop 1211 is used to receive the target clock signal, and the output terminal of the last-stage fourth flip-flop 1211 is used to output the second frequency-divided clock signal Exemplarily, the fourth flip-flop 1211 is a D flip-flop.

[0098] Wherein, the frequency of the second frequency-divided clock signal is related to the number of the fourth flip-flops 1211. The more the number of the fourth flip-flops 1211, the smaller the frequency and the longer the period of the second frequency-divided clock signal, and the longer the second delay time corresponding to the second delay signal output after passing through the second trigger unit 122.

[0099] Wherein, the number of the fourth flip-flops 1211 is greater than the number of the third flip-flops 1111, so that the frequency of the second frequency-divided clock signal is less than the frequency of the first frequency-divided clock signal, and further the second delay duration is greater than the first delay duration.

[0100] In this embodiment, the second frequency division unit is constructed by cascading fourth flip-flops. Since each fourth flip-flop is a digital circuit, the occupied area is much smaller than that of the analog frequency division circuit for frequency division. Therefore, it is beneficial to reduce the overall area of the radio frequency switch control circuit.

[0101] In some embodiments, the reset terminal R3 of the third flip-flop 1111 and the reset terminal of the fourth flip-flop 1211 are respectively used to receive the first reset signal RST.

[0102] In this embodiment, the first reset signal RST is simultaneously used as the reset signal for the third flip-flop 1111 and the fourth flip-flop 1211, without the need to set other reset signal generation devices, which is beneficial to simplifying the circuit structure.

[0103] Exemplarily, the first reset signal RST can be obtained according to the first control signal IN and the second control signal POR. The third flip-flop 1111 and the fourth flip-flop 1211 are started at the rising edge of the second control signal POR and reset at the rising edge of the first control signal IN.

[0104] In some embodiments, please refer to Figure 5 As shown, the first frequency division unit 111 includes N cascaded third flip-flops 1111, and the second frequency division unit 121 includes M cascaded fourth flip-flops 1211, where M is greater than N, and the N third flip-flops 1111 are multiplexed as the first N fourth flip-flops 1211 in the M cascaded fourth flip-flops 1211.

[0105] In this embodiment, by multiplexing the third flip-flop, the number of flip-flops can be reduced, further reducing the circuit area.

[0106] As an embodiment, please refer to Figure 6 As shown, the radio frequency switch control circuit 100 of this embodiment further includes a reset signal generation module 14, and the reset signal generation module 14 includes a first delay unit 141 and a first AND operation unit 142.

[0107] Please also refer to Figure 2 As shown, the first delay unit 141 is used to output the first adjustment signal t2_1 / t1_1. When the first delay unit 141 receives the rising edge of the first control signal IN, it flips the level state of the first adjustment signal t2_1 / t1_1 to the first level state and maintains it for the first set duration, and the first set duration is less than the first delay time t1.

[0108] The first AND operation unit 142 is used to perform an AND operation on the first adjustment signal t2_1 / t1_1 and the second adjustment signal t2_2, and output the first reset signal RST, and the second adjustment signal t2_2 is obtained according to the second control signal POR.

[0109] In this embodiment, the first adjustment signal t2_1 / t1_1 provides a part of the first reset signal RST. Starting from the falling edge moment of the first control signal IN through the first delay unit, the level state of the first adjustment signal t2_1 / t1_1 is flipped to the first level state within the first set duration. In the first control scenario, the signal segment of the first level state within the first set duration is used as a part of the first reset signal RST. The first set duration is the duration of the first level state in the first reset signal RST. The first set duration is a part of the first delay time t1. The first control signal IN participates in the configuration of the first delay signal t1_2, which is beneficial to simplifying the first delay module.

[0110] In some embodiments, please continue to refer to Figure 6 As shown, the reset signal generation module 14 further includes a second delay unit 143.

[0111] The second delay unit 143 is used to delay the falling edge of the second control signal POR for a second set duration and output a second adjustment signal t2_2. The second adjustment signal t2_2 includes an adjustment signal segment of the first level state. The starting moment of this adjustment signal segment is the falling edge moment of the second control signal POR, and the time difference between the ending moment of this adjustment signal segment and the falling edge moment of the second control signal POR is the second set duration.

[0112] In this embodiment, the second adjustment signal t2_2 provides a part of the first reset signal RST. By delaying the falling edge of the second control signal POR for the second set duration, thus, the falling edge of the first reset signal RST appears with a delay of the second set duration in the second control scenario. The starting moment of the second trigger unit 122 is the falling edge moment of the second control signal POR, while the starting moment of the first frequency division unit 121 is later than the falling edge moment of the second control signal POR by the second set duration. Starting from the starting moment of the second trigger unit 122, the second delay signal t2_3 is initialized to the first level state until a valid edge of the second frequency division clock signal appears, and the second delay signal t2_3 switches to the second level state. The second delay time t2 is the duration between the second moment when the second trigger unit 122 starts and the first valid edge moment of the second frequency division clock signal after the second moment. The delay of the second set duration makes the generation of the second frequency division clock signal later than the second moment by the second set duration, delaying the appearance moment of the valid edge of the second frequency division clock signal, which is beneficial to extending the second delay time t2.

[0113] In some embodiments, please refer to Figure 6 and Figure 7 As shown, the first delay unit 141 includes an inverting delay sub-unit 1411 and an exclusive-OR operation sub-unit 1412.

[0114] The inverting delay sub-unit 1411 is used to delay the inverted signal of the first control signal IN for a first set duration and output an inverted delay signal.

[0115] The exclusive-OR operation sub-unit 142 is used to perform an exclusive-OR operation on the first control signal IN and the inverted delay signal and output a first adjustment signal t2_1 / t1_1.

[0116] In this embodiment, the first adjustment signal is obtained by performing an exclusive-OR operation on the inverted delay signal of the first control signal and the first control signal, which is beneficial to simplifying the circuit structure of the first delay unit.

[0117] Of course, in some other embodiments, the first delay unit 141 can also be implemented using an RC (resistor-capacitor) circuit. The duration for which the first adjustment signal t2_1 / t1_1 is maintained at the first level state (i.e., the first set duration) can be configured to be a relatively short time, so as to save the circuit area required when using the RC circuit to implement the delay of the first set duration.

[0118] As an embodiment, please refer to Figure 8 As shown, the first delay module 11 includes a first inverting delay unit 113 and a first exclusive-OR operation unit 114.

[0119] The first inverting delay unit 113 is used to delay the inverted signal of the first control signal IN for a first delay time t1 and output a first inverted delay control signal.

[0120] The first exclusive-OR operation unit 114 is used to perform an exclusive-OR operation on the first control signal IN and the first inverted delay control signal and output a first delay signal t1_2.

[0121] In this embodiment, the first delay signal is obtained by performing an exclusive-OR operation on the inverted delay signal of the first control signal and the first control signal, which is beneficial to simplifying the circuit structure of the first delay module.

[0122] As an embodiment, please continue to refer to Figure 8 As shown, the second delay module 12 includes an RC delay unit 123. The delay time of the RC delay unit 123 is equal to the second delay time t2 and is used to delay the second control signal POR for the second delay time t2 to generate the second delay signal t2_3.

[0123] Among them, the RC delay unit 123 includes an equivalent capacitor and an equivalent resistor. The delay time of the RC delay unit 123 is proportional to the product of the capacitance value and the resistance value. Therefore, the capacitance value and the resistance value in the RC delay unit 123 can be set according to the required second delay time t2.

[0124] Exemplarily, before power-on startup, the second control signal POR is in the first level state. At the moment of the transition edge of the second control signal POR, the second control signal POR switches to the second level state. However, the transition of the output signal of the RC delay unit 123 (i.e., the second delay signal t2_3) lags behind the transition of the second control signal POR by the second delay time t2. Therefore, starting from the transition edge of the second control signal POR, within the second delay time, the second delay signal t2_3 remains in the first level state. After the second delay time, the second delay signal t2_3 flips to the second level state. Thus, the second delay signal t2_3 output by the RC delay unit 123 includes a section of the second control signal that remains in the first level state within the second delay time.

[0125] In this embodiment, obtaining the second delay signal through the RC delay unit is beneficial to simplifying the circuit structure of the second delay module.

[0126] As an embodiment, please refer to Figure 5 As shown, the signal output module 13 includes a second AND operation unit 131, which is used to perform an AND operation on the first delay signal and the second delay signal and output a clock frequency control signal.

[0127] Among them, the clock frequency control signal OUT includes a high-frequency clock section for the first control scenario and a high-frequency clock section for the second control scenario, and the durations of the two are different.

[0128] In this embodiment, outputting the clock frequency control signal through the AND operation of the first delay signal and the second delay signal is beneficial to simplifying the circuit structure of the signal output module and further reducing the circuit area.

[0129] As an embodiment, please refer to Figure 9 As shown, the radio frequency switch control circuit 100 further includes a clock generation module 15, which is used to generate a target clock signal CLK according to the clock frequency control signal OUT. The level state of the clock frequency control signal OUT is used to indicate the frequency of the target clock signal CLK.

[0130] Among them, the clock generation module 15 can be an oscillator. When the clock frequency control signal OUT is in the first level state, the target clock signal CLK is a high-frequency clock signal; when the clock frequency control signal OUT is in the second level state, the target clock signal CLK is a low-frequency clock signal.

[0131] As an alternative embodiment, one or more capacitive elements are provided inside the oscillator, and whether the capacitive element is connected to the oscillator can be controlled by a switch. When the clock frequency control signal OUT is in the first level state (e.g., low level state), the clock frequency control signal OUT can control the switch connected to the capacitor to disconnect, so that the capacitive element is not connected to the oscillator, thereby enabling the oscillator to output a clock with a higher frequency. Conversely, when the clock frequency control signal OUT is in the second level state (e.g., high level state), the clock frequency control signal OUT can control the switch connected to the capacitor to conduct, so that the capacitive element is connected to the oscillator, thereby enabling the oscillator to output a clock with a lower frequency.

[0132] An embodiment of the present application provides a chip 200. Please refer to Figure 10 As shown, the chip 200 includes the above-mentioned radio frequency switch control circuit 100.

[0133] In this embodiment, different control scenarios are adapted through the first delay module and the second delay module, and control signal segments with different delay durations are generated according to the flip edges of different control signals, so that the clock signal has high-frequency clock segments with different durations in different control scenarios, realizing providing a relatively longer high-frequency clock segment for a control scenario with a relatively lower voltage, which is beneficial to improving the stable speed of the control voltage.

[0134] An embodiment of the present application provides a radio frequency front-end module 300. Please refer to Figure 11 As shown, the radio frequency front-end module 300 includes the above-mentioned radio frequency switch control circuit 100 or the above-mentioned chip 200.

[0135] Specifically, the radio frequency front-end module 300 can be applied in electronic devices (e.g., 4G and 5G communication devices such as smart phones, tablet computers, smart watches, etc.) to realize the reception and transmission of radio frequency signals. In addition, with the development of 5G technology, the requirements for the performance of the radio frequency front-end module are getting higher and higher. The technical solution of the present application can be applied to a 5G radio frequency front-end module to improve the communication performance of 5G communication devices.

[0136] In some embodiments, the radio frequency front-end module 300 may include a substrate (not shown in the figure) and radio frequency switches and the above-mentioned chip 200 disposed on the substrate. The above-mentioned chip 200 can be used as a control chip of the radio frequency front-end module 300, and is at least used to control the conduction or cut-off of each switch path in the radio frequency switch. Specifically, the chip 200 can be a CMOS control chip, an RF-SOI control chip, etc., and this embodiment does not limit this.

[0137] Optionally, the above radio frequency switch may be an antenna tuning switch for switching the tuning elements connected to the antenna port. Alternatively, the above radio frequency switch may be a switching switch for multiple signal transmission / reception paths within the radio frequency front-end module, for switching the signal transmission path / signal reception path connected to the antenna port among multiple signal transmission paths / signal reception paths of different frequency bands.

[0138] In some possible examples, the radio frequency front-end module 300 may further include a multiplexer or a filter (not shown in the figure), a power amplifier (not shown in the figure), and / or a low-noise amplifier (not shown in the figure). The power amplifier and / or the low-noise amplifier may be connected to the antenna port through the multiplexer / filter and the radio frequency switch in sequence to filter the radio frequency signal output by the power amplifier and then send it to the antenna port, and / or filter the radio frequency signal received by the antenna port and then transmit it to the low-noise amplifier. Among them, the control chip may be used to control the conduction or cut-off of multiple switch paths in the radio frequency switch, so as to control the on / off of the signal transmission path between the power amplifier and the antenna port; and / or control the on / off of the signal reception path between the low-noise amplifier and the antenna port.

[0139] In this embodiment, the first delay module and the second delay module are adapted to different control scenarios, and control signal segments with different delay durations are generated according to the flip edges of different control signals, so that the clock signal has high-frequency clock segments with different durations in different control scenarios, realizing providing a relatively longer high-frequency clock segment for a control scenario with a relatively lower voltage, which is beneficial to improving the stable speed of the control voltage.

[0140] As an implementation manner, the radio frequency front-end module 300 includes a control chip 31 and a switch chip 32.

[0141] Among them, the control chip 31 includes a radio frequency switch control circuit 100, an oscillator 311, and a charge pump circuit 312. The radio frequency switch control circuit 100 is used to output a clock frequency control signal; the oscillator 311 is used to control the frequency of the clock signal according to the clock frequency control signal and output the clock signal; the charge pump circuit 312 is used to generate a radio frequency switch control signal according to the clock signal.

[0142] Among them, the switch chip 32 includes at least one radio frequency switch 321, and the control end of the radio frequency switch 321 is used to receive the radio frequency switch control signal.

[0143] The radio frequency switch control circuit, chip and radio frequency front-end module according to the embodiments of the present application provide control signal segments with different delay durations for different control scenarios. Compared with the technical solution in which the duration of the high-frequency clock segment in the clock signal provided to the charge pump circuit is the same under different control scenarios, in the control scenario with relatively low voltage, it avoids the relatively long time for the control voltage output by the charge pump circuit to reach the voltage stable state due to the relatively insufficient duration of the high-frequency clock segment, and can improve the stable speed of the control voltage.

[0144] The above are only the implementation manners of the present application. It should be noted here that for those of ordinary skill in the art, without departing from the inventive concept of the present application, improvements can still be made, but these all belong to the protection scope of the present application.

Claims

1. A radio frequency switch control circuit, characterized in that Comprising: A first delay module, configured to perform a first delay process on the falling edge of a first control signal and output a first delay signal. The first delay signal includes a first control signal segment in a first level state. The starting moment of the first control signal segment is the falling edge moment of the first control signal, and the width of the first control signal segment is a first delay time; A second delay module, configured to perform a second delay process on the falling edge of a second control signal and output a second delay signal. The second delay signal includes a second control signal segment in a first level state. The starting moment of the second control signal segment is the falling edge moment of the second control signal, and the width of the second control signal segment is a second delay time, where the second delay time is greater than the first delay time; A signal output module, configured to output a clock frequency control signal according to the first delay signal and the second delay signal. The clock frequency control signal is used to control the frequency of a clock signal, and the clock signal is used to generate a radio frequency switch control signal through a charge pump circuit.

2. The radio frequency switch control circuit according to claim 1, wherein The first delay module includes: A first frequency division unit, configured to perform a first frequency division process on a target clock signal and output a first divided clock signal; A first trigger unit, including a first clock terminal, a first reset terminal, a first input terminal, and a first output terminal. The first clock terminal is configured to receive the first divided clock signal, the first reset terminal is configured to receive a first reset signal, the first input terminal is configured to receive an input signal in a second level state, and the first output terminal is configured to output the first delay signal. The first reset signal is obtained according to the first control signal, and the first reset signal resets the first delay signal to a first level state at the falling edge moment of the first control signal.

3. The radio frequency switch control circuit according to claim 2, characterized in that, The second delay module includes: A second frequency division unit, configured to perform a second frequency division process on the target clock signal and output a second divided clock signal, where the frequency of the second divided clock signal is less than the frequency of the first divided clock signal; A second trigger unit, including a second clock terminal, a second reset terminal, a second input terminal, and a second output terminal. The second clock terminal is configured to receive the second divided clock signal, the second reset terminal is configured to receive the second control signal, the second input terminal is configured to receive an input signal in a second level state, and the second output terminal is configured to output the second delay signal. The second trigger unit is started at the falling edge moment of the second control signal, and the second delay signal is initialized to a first level state.

4. The radio frequency switch control circuit according to claim 3, wherein The first frequency division unit includes a plurality of cascaded third flip-flops. The input terminal of the third flip-flop is connected to its inverted output terminal. The inverted output terminal of the previous-stage third flip-flop is connected to the clock terminal of the next-stage third flip-flop. The clock terminal of the first-stage third flip-flop is configured to receive the target clock signal, and the output terminal of the last-stage third flip-flop is configured to output the first divided clock signal.

5. The RF switch control circuit according to claim 4, characterized in that The second frequency division unit includes a plurality of cascaded fourth flip - flops. The input terminal of the fourth flip - flop is connected to its inverted output terminal. The inverted output terminal of the previous - stage fourth flip - flop is connected to the clock terminal of the next - stage fourth flip - flop. The clock terminal of the first - stage fourth flip - flop is used to receive the target clock signal, and the output terminal of the last - stage fourth flip - flop is used to output the second divided - frequency clock signal; the number of the fourth flip - flops is greater than the number of the third flip - flops.

6. The RF switch control circuit according to claim 5, wherein The reset terminal of the third flip - flop and the reset terminal of the fourth flip - flop are respectively used to receive the first reset signal.

7. The RF switch control circuit according to claim 5, wherein The first frequency division unit includes N cascaded third flip - flops, and the second frequency division unit includes M cascaded fourth flip - flops, where M is greater than N, and the N third flip - flops are multiplexed as the first N fourth flip - flops among the M cascaded fourth flip - flops.

8. The radio frequency switch control circuit according to any one of claims 2 to 7, characterized in that, The radio - frequency switch control circuit further includes a reset signal generation module, and the reset signal generation module includes: A first delay unit, which is used to output a first adjustment signal. When receiving the flip - flop edge of the first control signal, it flips the level state of the first adjustment signal to the first level state and maintains it for a first set duration, and the first set duration is less than the first delay time. A first AND operation unit, which is used to perform an AND operation on the first adjustment signal and the second adjustment signal to output the first reset signal, and the second adjustment signal is obtained according to the second control signal.

9. The radio frequency switch control circuit according to claim 8, wherein The reset signal generation module further includes: A second delay unit, which is used to delay the flip - flop edge of the second control signal for a second set duration to output the second adjustment signal. The second adjustment signal includes an adjustment signal segment with the first level state. The start time of the adjustment signal segment is the flip - flop edge time of the second control signal, and the time difference between the end time of the adjustment signal segment and the flip - flop edge time of the second control signal is the second set duration.

10. The RF switch control circuit according to claim 8, wherein The first delay unit includes: An inverted - phase delay sub - unit, which is used to delay the inverted signal of the first control signal for a first set duration to output an inverted - phase delay signal. An exclusive - OR operation sub - unit, which is used to perform an exclusive - OR operation on the first control signal and the inverted - phase delay signal to output the first adjustment signal.

11. The RF switch control circuit according to claim 1, wherein, The first delay module includes: A first inverted - phase delay unit, which is used to delay the inverted signal of the first control signal by the first delay time to output a first inverted - phase delay control signal. A first exclusive - OR operation unit, which is used to perform an exclusive - OR operation on the first control signal and the first inverted - phase delay control signal to output the first delay signal.

12. The radio frequency switch control circuit according to claim 1, wherein The second delay module includes: An RC delay unit, the delay time of the RC delay unit is equal to the second delay time, and it is used to delay the second control signal by the second delay time to generate the second delay signal.

13. The RF switch control circuit according to claim 1, characterized in that, The signal output module includes: A second AND operation unit, which is used to perform an AND operation on the first delay signal and the second delay signal to output the clock frequency control signal.

14. The RF switch control circuit according to claim 1, wherein The radio - frequency switch control circuit further includes: A clock generation module, configured to generate a target clock signal according to the clock frequency control signal, and a level state of the clock frequency control signal is used to indicate a frequency of the target clock signal.

15. The RF switch control circuit according to claim 1, wherein, The first control signal is used to indicate a state of a radio frequency switch, and the second control signal is used to indicate a power-on reset state.

16. A chip, characterized in that, It includes the radio frequency switch control circuit according to any one of claims 1 to 15.

17. A radio frequency front-end module, characterized in that, It includes the radio frequency switch control circuit according to any one of claims 1 to 15 or the chip according to claim 16.

18. The radio frequency front-end module according to claim 17, wherein The radio frequency front-end module includes a control chip and a switch chip; the control chip includes: The radio frequency switch control circuit, configured to output a clock frequency control signal; An oscillator, configured to control a frequency of a clock signal according to the clock frequency control signal and output the clock signal; A charge pump circuit, configured to generate a radio frequency switch control signal according to the clock signal; The switch chip includes at least one radio frequency switch, and a control end of the radio frequency switch is configured to receive the radio frequency switch control signal.

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