Signal processing method, signal processing device, electronic equipment, computer storage medium and computer program product

Abstract

The embodiment of the invention provides a signal processing method, a signal processing device, electronic equipment, a computer storage medium and a computer program product. The signal processing method comprises the following steps: acquiring an input signal value of at least one discrete moment of a current discrete moment and a previous time period and an output signal value of at least one discrete moment of the previous time period; performing fitting processing on a plurality of to-be-fitted signal values in the input signal values of at least one discrete moment of the current discrete moment and the previous time period and the output signal values of at least one discrete moment of the previous time period to obtain a predicted output signal value of the next discrete moment; and performing up-sampling processing on a plurality of to-be-sampled signal values in the input signal value of at least one discrete moment of the current discrete moment and the previous time period, the output signal value of at least one discrete moment of the previous time period and the predicted output signal value of the next discrete moment to obtain a plurality of to-be-sampled signal values.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer technologies, and in particular, to a signal processing method, a signal processing device, an electronic device, a computer storage medium, and a computer program product. Background Art

[0002] In a chip system composed of chips with different functions, for example, between an upstream controller chip and a downstream driver chip, signal transmission is performed through communication protocols such as UART, SPI, I2C, USB, DDR, PCIe, SATA, etc. During the signal transmission process, in order to improve the transmission efficiency, the upstream controller chip samples the signal and transmits it to the downstream driver chip through the above communication protocols. Signals with a lower signal sampling rate will limit the algorithm processing performance in the subsequent downstream driver chip in fields such as automation control, signal processing, and signal analysis.

[0003] For a given communication protocol, it is desirable to balance the algorithm processing accuracy inside the downstream driver chip and the signal transmission efficiency between chips. Generally speaking, when the sampling rate of the output signal of the upstream controller is too low, resulting in a decline in the algorithm performance of the downstream driver chip, if signal upsampling is performed inside the downstream driver chip, it can not only improve the algorithm processing accuracy inside the chip but also ensure the signal transmission efficiency.

[0004] However, the current accuracy of signal upsampling is relatively low, and there is still room for improvement in the algorithm processing performance of the downstream driver chip. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a signal processing method, a signal processing device, an electronic device, a computer storage medium, and a computer program product to solve the above problems.

[0006] According to a first aspect of the embodiments of the present invention, a signal processing method is provided, including: obtaining input signal values at a current discrete moment and at least one discrete moment in a previous time period from a controller, as well as output signal values at at least one discrete moment in the previous time period; performing fitting processing on a plurality of signal values to be fitted among the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at at least one discrete moment in the previous time period to obtain a predicted output signal value at the next discrete moment; performing upsampling processing on a plurality of signal values to be sampled among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment to obtain a plurality of upsampled signal values for driving signal processing.

[0007] In some other implementation manners of the present invention, obtaining the input signal values of the current discrete moment and at least one discrete moment in the previous time period, and the output signal values of at least one discrete moment in the previous time period includes: caching the input signal values of the current discrete moment and at least one discrete moment in the previous time period and the output signal values of at least one discrete moment in the previous time period into a preset cache area, where the preset cache area is used to output the multiple signal values to be fitted and the multiple signal values to be sampled when the fitting process and the upsampling process are executed.

[0008] In some other implementation manners of the present invention, performing a fitting process on multiple signal values to be fitted among the input signal values of the current discrete moment and at least one discrete moment in the previous time period and the output signal values of at least one discrete moment in the previous time period to obtain the predicted output signal value of the next discrete moment includes: inputting the input signal values of the current discrete moment and at least one discrete moment in the previous time period to the input end of a first operation unit, inputting the output signal values of at least one discrete moment in the previous time period to the input end of a second operation unit, and obtaining the predicted output signal value of the next discrete moment from the output end of a third operation unit; where the output end of the first operation unit and the output end of the second operation unit are respectively connected to the first input end and the second input end of the third operation unit, and the first operation unit, the second operation unit, and the third operation unit are configured with corresponding fitting parameters.

[0009] In some other implementation manners of the present invention, inputting the input signal values of the current discrete moment and at least one discrete moment in the previous time period to the input end of a first operation unit, inputting the output signal values of at least one discrete moment in the previous time period to the input end of a second operation unit, and obtaining the predicted output signal value of the next discrete moment from the output end of a third operation unit includes: determining, from the input signal values of the current discrete moment and at least one discrete moment in the previous time period and the output signal values of at least one discrete moment in the previous time period, the first input channels corresponding to the multiple signal values to be fitted in the first operation unit and the second operation unit respectively; inputting the input signal values of the current discrete moment and at least one discrete moment in the previous time period to the first input channel of the first operation unit, inputting the output signal values of at least one discrete moment in the previous time period to the first input channel of the second operation unit, and outputting the predicted output signal value of the next discrete moment from the first output channel of the third operation unit.

[0010] In some other implementation manners of the present invention, the fitting parameter includes a fitting scaling coefficient matched with the target prediction algorithm. Correspondingly, performing fitting processing on multiple signal values to be fitted among the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at at least one discrete moment in the previous time period to obtain the predicted output signal value at the next discrete moment further includes: configuring the first input channels corresponding to the multiple signal values to be fitted by using the fitting scaling coefficients corresponding to the first operation unit and the second operation unit, and configuring the first output channel by using the fitting scaling coefficient corresponding to the third operation unit.

[0011] In some other implementation manners of the present invention, performing upsampling processing on multiple signal values to be sampled among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment to obtain multiple upsampled signal values for driving signal processing, including: inputting the input signal values at the current discrete moment and at least one discrete moment in the previous time period into the input end of a fourth operation unit, inputting the output signal values at at least one discrete moment in the previous time period and the predicted output signal value at the next discrete moment into the input end of a fifth operation unit, and obtaining the multiple upsampled signal values from the output end of a sixth operation unit; wherein, the output end of the fourth operation unit and the output end of the fifth operation unit are respectively connected to the first input end and the second input end of the sixth operation unit, and the fourth operation unit, the fifth operation unit, and the sixth operation unit are configured with corresponding upsampling parameters.

[0012] In some other implementation manners of the present invention, inputting the input signal values at the current discrete moment and at least one discrete moment in the previous time period into the input end of a fourth operation unit, inputting the output signal values at at least one discrete moment in the previous time period and the predicted output signal value at the next discrete moment into the input end of a fifth operation unit, and obtaining the multiple upsampled signal values from the output end of a sixth operation unit, including: determining the second output channels corresponding to the multiple signal values to be sampled in the fifth operation unit and the sixth operation unit respectively from among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment; inputting the input signal values at the current discrete moment and at least one discrete moment in the previous time period into the second input channel of the fourth operation unit, inputting the output signal values at at least one discrete moment in the previous time period and the predicted output signal value at the next discrete moment into the second input channel of the fifth operation unit, and outputting the multiple upsampled signal values from the second output channel of the sixth operation unit.

[0013] In some other implementation manners of the present invention, the upsampling parameter includes an upsampling scaling factor matching the target upsampling algorithm. Accordingly, for multiple to-be-sampled signal values among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment, an upsampling process is performed to obtain multiple upsampled signal values for driving signal processing, and it further includes: configuring the second input channels corresponding to the multiple to-be-sampled signal values with the upsampling scaling factors corresponding to the fourth operation unit and the fifth operation unit, and configuring the second output channel with the upsampling scaling factor corresponding to the sixth operation unit.

[0014] According to a second aspect of the embodiments of the present invention, a signal processing device is provided, including: an acquisition module configured to acquire input signal values at the current discrete moment and at least one discrete moment in the previous time period, and output signal values at at least one discrete moment in the previous time period from a controller; a prediction module configured to perform a fitting process on multiple to-be-fitted signal values among the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at at least one discrete moment in the previous time period, so as to obtain a predicted output signal value at the next discrete moment; an upsampling module configured to perform an upsampling process on multiple to-be-sampled signal values among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment, so as to obtain multiple upsampled signal values for driving signal processing.

[0015] According to a third aspect of the embodiments of the present invention, an electronic device is provided, including: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the method as described in the first aspect.

[0016] According to a fourth aspect of the embodiments of the present invention, a computer storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the method as described in the first aspect is implemented.

[0017] According to a fifth aspect of the embodiments of the present invention, a computer program product is provided, including computer instructions, and when the computer instructions are executed by a processor, the method as described in the first aspect is implemented.

[0018] In the solution of the embodiment of the present invention, the predicted output signal value at the next discrete moment is obtained by performing fitting processing on multiple signal values to be fitted among the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at at least one discrete moment in the previous time period, so that the predicted output signal value at the next discrete moment carries effective information from the prior signal values. Therefore, when performing upsampling processing on multiple signal values to be sampled among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment, the obtained multiple upsampled signal values include the effective information carried by the predicted output signal at the next discrete moment, improving the accuracy of the upsampling processing through a simple signal processing flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings.

[0020] Figure 1 It is a schematic structural diagram of a signal processing system applicable to some embodiments of the present invention.

[0021] Figure 2 It is a flowchart of the steps of a signal processing method according to other embodiments of the present invention.

[0022] Figure 3A For Figure 2 It is a schematic structural diagram of the fitting processing process of some examples of the embodiments.

[0023] Figure 3B For Figure 3A It is a schematic structural diagram of the fitting processing process of some examples of the embodiments.

[0024] Figure 4A And Figure 4B It is a waveform diagram of the prediction results of the fitting processing process of some examples.

[0025] Figure 5A For Figure 2 It is a schematic structural diagram of the upsampling processing process of some examples of the embodiments.

[0026] Figure 5B For Figure 5A It is a schematic structural diagram of the upsampling processing process of some examples of the embodiments.

[0027] Figure 6A AndFigure 6B The upsampling waveform diagram of the upsampling processing procedure for some other examples.

[0028] Figure 7A and Figure 7B The upsampling waveform diagram of the upsampling processing procedure for some other examples.

[0029] Figure 8A and Figure 8B The upsampling waveform diagram of the upsampling processing procedure for some other examples.

[0030] Figure 9 The schematic structural diagram of the signal processing device according to some other embodiments of the present invention.

[0031] Figure 10 The structural schematic diagram of the electronic device according to some other embodiments of the present invention. Specific embodiments

[0032] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art shall fall within the protection scope of the embodiments of the present invention.

[0033] The following further illustrates the specific implementation of the embodiments of the present invention with reference to the accompanying drawings of the embodiments of the present invention.

[0034] Figure 1 Shows the signal processing system applicable to some embodiments of the present invention. Figure 1The signal processing system 100 includes a controller 110, a driving chip 120, and a controlled object 130. Specifically, the driving chip 120 may include a digital driving circuit 20 and a digital-to-analog conversion circuit 30. In some examples, the driving chip 120 may be a downstream chip of the chip where the controller 110 is set. Digital signals may be transmitted between the controller 110 and the digital driving circuit 20 through communication protocols such as UART, SPI, I2C, USB, DDR, PCIe, SATA, etc. The digital driving circuit 20 receives a control signal sequence from the controller 110 based on the above communication protocol. A signal processing device may be provided in the digital driving circuit 20 to perform upsampling on each signal value in the control signal sequence and perform driving processing on the upsampled control signal sequence to output a digital driving signal. The digital-to-analog conversion circuit 30 performs analog-to-digital conversion on the digital driving signal to obtain an analog driving signal, and the analog driving signal is used to be sent to drive the controlled object. The controlled object 130 may include, but is not limited to, motors, water pumps, valves, etc. The controlled object 130 may also include cooperating devices, instruments, apparatuses, etc., and a voltage source matching the controlled object 130. Alternatively, the digital driving circuit 20 and the digital-to-analog conversion circuit 30 may also be provided as discrete units instead of being integrated in the driving chip 120.

[0035] For a given communication protocol, it is desirable to balance the algorithm processing accuracy inside the downstream driving chip and the signal transmission efficiency between chips. Generally speaking, in the case where the sampling rate of the output signal of the upstream controller is low, resulting in a decline in the algorithm performance of the downstream driving chip, if signal upsampling is performed inside the downstream driving chip, it can not only improve the algorithm processing accuracy inside the chip but also ensure the signal transmission efficiency. In traditional upsampling algorithms, equal-value interpolation processing is often performed on the input signal of the downstream driving chip for upsampling, so that the obtained signal carries fewer effective features and cannot effectively optimize the algorithm processing performance of the downstream driving chip. That is, the accuracy of signal upsampling is relatively low, and there is still room for improvement in the algorithm processing performance of the downstream driving chip. Each embodiment of the present invention can improve the effective features carried by the signal and improve the accuracy of upsampling processing.

[0036] Specifically, in combination with Figure 2 the signal processing method of some other embodiments of the present invention will be described. Figure 2 The signal processing method 200 may be executed by a signal processing device. The signal processing device may be provided in the above-mentioned driving chip 120, for example, provided between the digital driving circuit 20 and the controller 110.

[0037] Specifically, the signal processing method 200 includes:

[0038] S210: Obtain the input signal values at the current discrete moment and at least one discrete moment in the previous time period from the controller, as well as the output signal values at at least one discrete moment in the previous time period.

[0039] It should be understood that the signal values in the text can be digital signal values or analog signal values, and the embodiments of the present invention do not limit this. For example, signal data related to the current discrete moment, the input signal values at at least one discrete moment in the previous time period, and the output signal values at at least one discrete moment in the previous time period can be collected. For another example, the collected signal values can be cached in a preset cache area or a preset cache area in the chip where the signal processing device is located.

[0040] S220: Perform fitting processing on multiple signal values to be fitted among the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at at least one discrete moment in the previous time period, so as to obtain the predicted output signal value at the next discrete moment.

[0041] It should be understood that a target prediction algorithm can be used to analyze the amplitudes of the input signals and output signals at the obtained discrete moments to obtain the predicted output signal value at the next discrete moment. The multiple signal values to be fitted can be all the signal values at the obtained discrete moments or partial signal values at the obtained discrete moments. In the case where the target prediction algorithm requires partial signal values, it is beneficial to improve the signal processing efficiency. That is to say, the fitting processing performed on the signal values utilizes the amplitudes and dynamic characteristics of the signals to establish an internal relationship model between the signal values, and predicts the output signal value at the next discrete moment through calculation, providing an estimate of the future signal state for the chip so that subsequent modules can perform further processing based on this prediction result.

[0042] S230: Perform upsampling processing on multiple signal values to be sampled among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment, to obtain multiple upsampled signal values for driving signal processing.

[0043] It should be understood that the multiple signal values to be sampled can at least include the predicted output signal value at the next discrete moment. The upsampling processing performed on the signal values improves the signal sampling rate, making the signal values denser on the time axis. The upsampling processing can improve the resolution of the signal, enabling the signal to more finely reflect its dynamic characteristics in subsequent processing. Through the upsampling processing, the algorithm processing performance of the chip where the signal processing device is located can be optimized.

[0044] In the solution of the embodiment of the present invention, the predicted output signal value at the next discrete moment is obtained by performing a fitting process on multiple signal values to be fitted among the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at least one discrete moment in the previous time period, so that the predicted output signal value at the next discrete moment carries effective information from the prior signal values. Therefore, when performing an upsampling process on multiple signal values to be sampled among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment, the multiple upsampled signal values obtained include the effective information carried by the predicted output signal at the next discrete moment, improving the accuracy of the upsampling process through a simple signal processing flow.

[0045] In other words, the input signal values at the current discrete moment and at least one discrete moment in the previous time period, and the output signal values at least one discrete moment in the previous time period are obtained from the controller as a control signal sequence, and the multiple upsampled signal values obtained by upsampling are used as an input signal sequence for digital drive processing, which is compatible with the communication protocol between the controller as the upstream chip and the downstream chip where the signal processing device is located, and at the same time improves the accuracy of the upsampling process by using a low-cost simplified signal processing configuration.

[0046] In some embodiments, in order for the signal processing device to obtain the input signal values at the current discrete moment and at least one discrete moment in the previous time period, and the output signal values at least one discrete moment in the previous time period, the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at least one discrete moment in the previous time period can be cached in a preset cache area, where the preset cache area is used to output multiple signal values to be fitted and multiple signal values to be sampled when the fitting process and the upsampling process are executed. That is to say, storing the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at least one discrete moment in the previous time period in the preset cache area is beneficial to obtaining multiple signal values to be fitted that match the target preset algorithm and multiple signal values to be sampled that match the target upsampling algorithm before the fitting process and the upsampling process are executed.

[0047] In other embodiments, when performing a fitting process on multiple signal values to be fitted, the input signal values at the current discrete moment and at least one discrete moment in the previous time period can be input to the input end of the first arithmetic unit, the output signal values at least one discrete moment in the previous time period can be input to the input end of the second arithmetic unit, and the predicted output signal value at the next discrete moment can be obtained from the output end of the third arithmetic unit. For example, as Figure 3AAs shown, the prediction module that performs fitting processing may include a first arithmetic unit 221, a second arithmetic unit 222, and a third arithmetic unit 223. The first arithmetic unit 221, the second arithmetic unit 222, and the third arithmetic unit 223 are configured with corresponding fitting parameters for performing digital differential operations or digital integral operations. The output terminals of the first arithmetic unit 221 and the second arithmetic unit 222 are respectively connected to the first input terminal and the second input terminal of the third arithmetic unit 223. That is to say, the first arithmetic unit 221, the second arithmetic unit 222, and the third arithmetic unit 223 are convenient to be implemented by digital circuits, thereby improving the efficiency of signal value prediction.

[0048] In some examples, multiple signal values to be fitted can be determined from the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at at least one discrete moment in the previous time period, and the corresponding first input channels in the first arithmetic unit and the second arithmetic unit can be determined respectively. Then, the input signal values at the current discrete moment and at least one discrete moment in the previous time period are input into the first input channel of the first arithmetic unit, the output signal values at at least one discrete moment in the previous time period are input into the first input channel of the second arithmetic unit, and the predicted output signal value at the next discrete moment is output from the first output channel of the third arithmetic unit. As Figure 3A shown, the fitting parameters include fitting scaling coefficients that match the target prediction algorithm. The first input channel of the first arithmetic unit 221, the first input channel of the second arithmetic unit 222, and the first output channel of the third arithmetic unit 223 are configured with corresponding fitting scaling coefficients. That is to say, by using fitting scaling coefficients that match the target prediction algorithm to configure each first input channel and the first output channel, it is beneficial to match the fitting scaling coefficients with the first input channel and the first output channel. The first input channel and the first output channel are convenient to be implemented by branches of digital circuits, improving the efficiency of the branch configuration of digital circuits, and thereby improving the efficiency of signal value prediction.

[0049] More specifically, X[n-N], …, X[n-1] represent N-1 input signal values from the discrete moment n-N to the discrete moment n-1, as an example of the input signal values at at least one discrete moment in the previous time period; X[n] represents the input signal at the current discrete moment; Y[n-N], …, Y[n-1] represent N output signal values from the discrete moment n-N to the discrete moment n-1; Y[n] represents the predicted output signal value at the next discrete moment.

[0050] Furthermore, Num1, Num2, …, Num N and Den1, Den2, …, Den NThe fitting scaling coefficients representing the input signal values or output signal values at the corresponding discrete moments, and the calculation methods of the fitting scaling coefficients correspond to different target prediction algorithms.

[0051] Further, in Figure 3B example, each fitting scaling coefficient takes the following values: Num2, Num3, …, Num N takes the value 0; Den3, …, Den N takes the value 0; Num1 and Den2 take the value 1; Correspondingly, the fitting scaling coefficient K of Den1 can be calculated using the following formula (1):

[0052]

[0053] Among them, coefficient K1, coefficient K2, and coefficient K3 determine the prediction ability of the signal value fitting process.

[0054] In some examples, coefficient K1 = 0.1, coefficient K2 = 0.6, coefficient K3 = 1.4. In some other examples, coefficient K1 = 0.1, coefficient K2 = 0.6, coefficient K3 = 1.0. As Figure 4A and Figure 4B shown, by comparing the input signal with the prediction results of some examples and the prediction results of some other examples, Figure 4B the waveform diagram of Figure 4A is a partial enlarged view of the waveform diagram of

[0055] Without loss of generality, the fitting scaling coefficients corresponding to the first operation unit and the second operation unit can be used to configure the first input channels corresponding to multiple signal values to be fitted, and the fitting scaling coefficient corresponding to the third operation unit can be used to configure the first output channel.

[0056] In some other embodiments, when performing upsampling processing on multiple signal values to be sampled, the input signal values at the current discrete moment and at least one discrete moment in the previous time period can be input to the input end of the fourth operation unit, the output signal values at at least one discrete moment in the previous time period and the predicted output signal value at the next discrete moment can be input to the input end of the fifth operation unit, and multiple upsampled signal values can be obtained from the output end of the sixth operation unit. For example, as Figure 5AAs shown, the upsampling module that performs upsampling processing may include a fourth arithmetic unit 231, a fifth arithmetic unit 232, and a sixth arithmetic unit 233. The fourth arithmetic unit 231, the fifth arithmetic unit 232, and the sixth arithmetic unit 233 are configured with corresponding upsampling parameters for performing digital integration operations or digital differentiation operations. The output ends of the fourth arithmetic unit 231 and the fifth arithmetic unit 232 are respectively connected to the first input end and the second input end of the sixth arithmetic unit 233. That is to say, the fourth arithmetic unit, the fifth arithmetic unit, and the sixth arithmetic unit are convenient to be implemented by digital circuits, thereby improving the efficiency of upsampling processing.

[0057] In some examples, multiple signal values to be sampled can be determined from the input signal values of at least one discrete moment of the current discrete moment and its previous time period, the output signal values of at least one discrete moment of the previous time period, and the predicted output signal value of the next discrete moment, and the corresponding second output channels in the fifth arithmetic unit and the sixth arithmetic unit are respectively determined. Then, the input signal values of at least one discrete moment of the current discrete moment and its previous time period are input into the second input channel of the fourth arithmetic unit, the output signal values of at least one discrete moment of the previous time period and the predicted output signal value of the next discrete moment are input into the second input channel of the fifth arithmetic unit, and multiple upsampled signal values are output from the second output channel of the sixth arithmetic unit.

[0058] That is to say, by using upsampling parameters to configure each second input channel and second output channel, it is beneficial to match the upsampling parameters with the second input channel and the second output channel. The second input channel and the second output channel are convenient to be implemented by branches of digital circuits, improving the efficiency of the branch configuration of digital circuits, and thereby improving the efficiency of upsampling processing.

[0059] Furthermore, as Figure 5A shown, the upsampling parameters include an upsampling scaling coefficient matching the target upsampling algorithm. The second input channel of the fourth arithmetic unit 231, the second input channel of the fifth arithmetic unit 232, and the second output channel of the sixth arithmetic unit 233 are configured with corresponding upsampling scaling coefficients.

[0060] Specifically, X[n - N], …, X[n - 1] represent N - 1 input signal values from the discrete moment n - N to the discrete moment n - 1, as an example of the input signal values of at least one discrete moment of the previous time period; X[n] represents the input signal of the current discrete moment; Y[n - N], …, Y[n - 1] represent N output signal values from the discrete moment n - N to the discrete moment n - 1; Y[n] represents the predicted output signal value of the next discrete moment.

[0061] Furthermore, G1, G2, …, G 2NAn upsampling scaling factor characterizing the input signal value or output signal value corresponding to a discrete moment, and the calculation method of the upsampling scaling factor corresponds to different target upsampling algorithms.

[0062] In some examples, among multiple signal values to be sampled, there may be at least an output signal value predicted for the next discrete moment. In addition, the number of multiple signal values to be fitted may be greater than the number of multiple signal values to be sampled. When the output signal value predicted for the next discrete moment is included among the multiple signal values to be sampled, the efficiency of the upsampling process can be improved while ensuring the prediction accuracy.

[0063] In other examples, among multiple signal values to be sampled, there may be at least an output signal value predicted for the next discrete moment. In addition, the fitting scaling factor (e.g., scaling weight) of the signal value to be fitted corresponding to the first discrete moment of the previous time period is greater than the upsampling scaling factor (e.g., scaling weight) of the signal value to be sampled at the first discrete moment. The fitting scaling factor of the signal value to be fitted corresponding to the first discrete moment of the previous time period is greater than the upsampling scaling factor of the signal value to be sampled at the first discrete moment. The fitting scaling factor of the signal value to be fitted corresponding to the second discrete moment of the previous time period is less than the upsampling scaling factor of the signal value to be sampled at the second discrete moment. The first discrete moment is a discrete moment before the second discrete moment. Therefore, the output signal value of the next discrete moment is accurately predicted on a larger time scale, and the upsampling process is sensitively performed on a smaller time scale.

[0064] Furthermore, in Figure 5B example, among each upsampling scaling factor, G N+1 and G N+2 take the value of 1, and other values are 0. Among them, each signal value is input to the differential unit of the filtering unit configured with the upsampling multiple of the target upsampling algorithm, and multiple upsampled signal values for driving signal processing are obtained from the output end of the integration unit of the filtering unit. Among them, the above upsampling multiple G = 1 / (f2 / f1), where f1 is the sampling rate before upsampling processing, and f1 is the sampling rate after upsampling processing.

[0065] In some examples, as Figure 6A and Figure 6B shown, the signal frequency of the input signal value is 10 Hz, f1 = 1 kHz, and f2 = 10 kHz. A waveform diagram after sampling with the signal value on the vertical axis and the sampling discrete moment on the horizontal axis can be obtained. Figure 6B The waveform diagram of Figure 6A is a partial enlarged view of the waveform diagram of

[0066] In some other examples, such as Figure 7A and Figure 7B shown, the signal frequency of the input signal value is 50 Hz, f1 = 1 kHz, f2 = 10 kHz. A sampled waveform diagram with the signal value on the vertical axis and the sampled discrete time on the horizontal axis can be obtained. Figure 7B The waveform diagram of Figure 7A is a partial enlarged view of the waveform diagram of

[0067] In some other examples, such as Figure 8A and Figure 8B shown, the signal frequency of the input signal value is 100 Hz, f1 = 1 kHz, f2 = 10 kHz. A sampled waveform diagram with the signal value on the vertical axis and the sampled discrete time on the horizontal axis can be obtained. Figure 8B The waveform diagram of Figure 8A is a partial enlarged view of the waveform diagram of

[0068] That is to say, in the case of the upsampling multiple (for example, 1 / 10 in the above example) matching the target upsampling algorithm, the accuracy of upsampling signals with different frequency values is improved through more accurate prediction results.

[0069] Without loss of generality, the upsampling scaling coefficients corresponding to the fourth operation unit and the fifth operation unit are used to configure the second input channels corresponding to multiple signal values to be sampled, and the upsampling scaling coefficient corresponding to the sixth operation unit is used to configure the second output channel.

[0070] Next, the signal processing device of some other embodiments of the present invention will be described in conjunction with Figure 9 The signal processing device 900 of Figure 9 corresponds to the signal processing method 200 of Figure 2 and includes:

[0071] An acquisition module 910 that acquires input signal values at at least one discrete time of the current discrete time and its previous time period and output signal values at at least one discrete time of the previous time period from the controller;

[0072] A prediction module 920 that performs fitting processing on multiple signal values to be fitted among the input signal values at at least one discrete time of the current discrete time and its previous time period and the output signal values at at least one discrete time of the previous time period to obtain a predicted output signal value at the next discrete time;

[0073] The upsampling module 930 performs upsampling processing on multiple signal values to be sampled among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal values at the next discrete moment, to obtain multiple upsampled signal values for driving signal processing.

[0074] In the solution of the embodiment of the present invention, the predicted output signal values at the next discrete moment are obtained by performing fitting processing on multiple signal values to be fitted among the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at at least one discrete moment in the previous time period, so that the predicted output signal values at the next discrete moment carry effective information from the prior signal values. Therefore, when performing upsampling processing on multiple signal values to be sampled among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal values at the next discrete moment, the multiple upsampled signal values obtained include the effective information carried by the predicted output signal at the next discrete moment, improving the accuracy of the upsampling processing through a simple signal processing flow.

[0075] In some other embodiments, the acquisition module is specifically configured to: cache the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at at least one discrete moment in the previous time period into a preset cache area, where the preset cache area is used to output multiple signal values to be fitted and multiple signal values to be sampled when the fitting processing and the upsampling processing are performed.

[0076] In some other embodiments, the prediction module is specifically configured to: input the input signal values at the current discrete moment and at least one discrete moment in the previous time period into the input end of the first arithmetic unit, input the output signal values at at least one discrete moment in the previous time period into the input end of the second arithmetic unit, and obtain the predicted output signal values at the next discrete moment from the output end of the third arithmetic unit; wherein, the output end of the first arithmetic unit and the output end of the second arithmetic unit are respectively connected to the first input end and the second input end of the third arithmetic unit, and the first arithmetic unit, the second arithmetic unit, and the third arithmetic unit are configured with corresponding fitting parameters.

[0077] In some other embodiments, the prediction module is specifically configured to: determine first input channels corresponding to multiple signal values to be fitted in the first arithmetic unit and the second arithmetic unit respectively from the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at at least one discrete moment in the previous time period; input the input signal values at the current discrete moment and at least one discrete moment in the previous time period into the first input channels of the first arithmetic unit, input the output signal values at at least one discrete moment in the previous time period into the first input channels of the second arithmetic unit, and output the predicted output signal value at the next discrete moment from the first output channel of the third arithmetic unit.

[0078] In some other embodiments, the fitting parameter includes a fitting scaling coefficient matching the target prediction algorithm. Accordingly, the prediction module is further configured to: configure the first input channels corresponding to multiple signal values to be fitted with the fitting scaling coefficients corresponding to the first arithmetic unit and the second arithmetic unit, and configure the first output channel with the fitting scaling coefficient corresponding to the third arithmetic unit.

[0079] In some other embodiments, the upsampling module is specifically configured to: input the input signal values at the current discrete moment and at least one discrete moment in the previous time period into the input end of the fourth arithmetic unit, input the output signal values at at least one discrete moment in the previous time period and the predicted output signal value at the next discrete moment into the input end of the fifth arithmetic unit, and obtain multiple upsampled signal values from the output end of the sixth arithmetic unit; wherein, the output end of the fourth arithmetic unit and the output end of the fifth arithmetic unit are respectively connected to the first input end and the second input end of the sixth arithmetic unit, and the fourth arithmetic unit, the fifth arithmetic unit and the sixth arithmetic unit are configured with corresponding upsampling parameters.

[0080] In some other embodiments, the upsampling module is specifically configured to: determine second output channels corresponding to multiple signal values to be sampled in the fifth arithmetic unit and the sixth arithmetic unit respectively from the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment; input the input signal values at the current discrete moment and at least one discrete moment in the previous time period into the second input channels of the fourth arithmetic unit, input the output signal values at at least one discrete moment in the previous time period and the predicted output signal value at the next discrete moment into the second input channels of the fifth arithmetic unit, and output multiple upsampled signal values from the second output channel of the sixth arithmetic unit.

[0081] In some other embodiments, the upsampling parameter includes an upsampling scaling factor that matches the target upsampling algorithm. Accordingly, the upsampling module is further configured to: configure the second input channels corresponding to multiple signal values to be sampled by using the upsampling scaling factors corresponding to the fourth arithmetic unit and the fifth arithmetic unit, and configure the second output channel by using the upsampling scaling factor corresponding to the sixth arithmetic unit.

[0082] Referring Figure 10 , a schematic structural diagram of an electronic device according to another embodiment of the present invention is shown. The specific implementation of the electronic device in the specific embodiments of the present invention is not limited.

[0083] As Figure 10 shown, the electronic device may include: a processor 1002 for executing program 1010, a communications interface 1004, a memory 1006, and a communication bus 1008.

[0084] The processor, the communication interface, and the memory complete mutual communication through the communication bus.

[0085] The communication interface is used to communicate with other electronic devices or servers.

[0086] The processor is used to execute the program, and specifically may execute the relevant steps in the above method embodiments.

[0087] Specifically, the program may include program code, and the program code includes computer operation instructions.

[0088] The processor may be a CPU, or a specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention. One or more processors included in the intelligent device may be of the same type of processor, such as one or more CPUs; or may be of different types of processors, such as one or more CPUs and one or more ASICs.

[0089] The memory is used to store the program. The memory may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory.

[0090] The program may include multiple computer instructions. Specifically, the program may cause the processor to execute the signal processing method described in any one of the foregoing multiple method embodiments through the multiple computer instructions.

[0091] For the specific implementation of each step in the program, reference may be made to the corresponding descriptions in the corresponding steps, modules or units in the foregoing method embodiments, and they have corresponding beneficial effects, which will not be elaborated herein. Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the above-described devices, equipment or modules can refer to the corresponding process descriptions in the foregoing method embodiments, which will not be elaborated herein again.

[0092] An embodiment of the present invention further provides a computer storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the method described in any one of the foregoing multiple method embodiments. The computer storage medium includes but is not limited to: Compact Disc Read-Only Memory (CD-ROM), Random Access Memory (RAM), floppy disk, hard disk or magneto-optical disk, etc.

[0093] An embodiment of the present invention further provides a computer program product, including computer instructions, and the computer instructions instruct a computing device to execute the signal processing method in the above multiple method embodiments.

[0094] In addition, it should be noted that the information related to users (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data for training the model, data for analysis, stored data, displayed data, etc.) involved in the embodiments of the present invention are all information and data authorized by the users or fully authorized by all parties, and the collection, use and processing of the relevant data need to comply with the relevant regulations and standards, and a corresponding operation entry is provided for the users to select to authorize or refuse.

[0095] It should be pointed out that according to the needs of implementation, the various components / steps described in the embodiments of the present invention can be split into more components / steps, or two or more components / steps or partial operations of the components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present invention.

[0096] The method according to the embodiments of the present invention can be implemented in hardware, firmware, or can be implemented as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or can be implemented as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium and downloaded through a network and to be stored in a local recording medium, so that the method described herein can be stored in such a software process on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA)). It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component (such as a Random Access Memory (RAM), a Read-Only Memory (ROM), a flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the method shown herein, the execution of the code converts the general-purpose computer into a dedicated computer for executing the method shown herein.

[0097] Those of ordinary skill in the art can realize that the units and method steps of each example described in combination with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods for each specific application to implement the described functions, but such an implementation should not be considered to exceed the scope of the embodiments of the present invention.

[0098] The above embodiments are only used to illustrate the embodiments of the present invention, rather than to limit the embodiments of the present invention. Those of ordinary skill in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present invention. The patent protection scope of the embodiments of the present invention shall be defined by the claims.

Claims

1. A signal processing method, characterized in that, Including: Obtaining input signal values of the current discrete moment and at least one discrete moment in the previous time period from a controller, as well as output signal values of at least one discrete moment in the previous time period; Performing fitting processing on multiple signal values to be fitted among the input signal values of the current discrete moment and at least one discrete moment in the previous time period and the output signal values of at least one discrete moment in the previous time period to obtain a predicted output signal value for the next discrete moment; Performing upsampling processing on multiple signal values to be sampled among the input signal values of the current discrete moment and at least one discrete moment in the previous time period, the output signal values of at least one discrete moment in the previous time period, and the predicted output signal value for the next discrete moment to obtain multiple upsampled signal values for driving signal processing.

2. The method according to claim 1, wherein Obtaining input signal values of the current discrete moment and at least one discrete moment in the previous time period, as well as output signal values of at least one discrete moment in the previous time period, includes: Caching the input signal values of the current discrete moment and at least one discrete moment in the previous time period and the output signal values of at least one discrete moment in the previous time period into a preset cache area, where the preset cache area is used to output the multiple signal values to be fitted and the multiple signal values to be sampled when fitting processing and upsampling processing are performed.

3. The method according to claim 1, wherein Performing fitting processing on multiple signal values to be fitted among the input signal values of the current discrete moment and at least one discrete moment in the previous time period and the output signal values of at least one discrete moment in the previous time period to obtain a predicted output signal value for the next discrete moment, includes: Inputting the input signal values of the current discrete moment and at least one discrete moment in the previous time period to the input end of a first arithmetic unit, inputting the output signal values of at least one discrete moment in the previous time period to the input end of a second arithmetic unit, and obtaining a predicted output signal value for the next discrete moment from the output end of a third arithmetic unit; Wherein, the output end of the first arithmetic unit and the output end of the second arithmetic unit are respectively connected to the first input end and the second input end of the third arithmetic unit, and the first arithmetic unit, the second arithmetic unit, and the third arithmetic unit are configured with corresponding fitting parameters.

4. The method according to claim 3, characterized in that, Inputting the input signal values of the current discrete moment and at least one discrete moment in the previous time period to the input end of a first arithmetic unit, inputting the output signal values of at least one discrete moment in the previous time period to the input end of a second arithmetic unit, and obtaining a predicted output signal value for the next discrete moment from the output end of a third arithmetic unit, includes: Determining first input channels corresponding to multiple signal values to be fitted in the first arithmetic unit and the second arithmetic unit respectively from among the input signal values of the current discrete moment and at least one discrete moment in the previous time period and the output signal values of at least one discrete moment in the previous time period; Input the input signal values at the current discrete moment and at least one discrete moment in the previous time period into the first input channel of the first arithmetic unit, input the output signal values at at least one discrete moment in the previous time period into the first input channel of the second arithmetic unit, and output the predicted output signal value at the next discrete moment from the first output channel of the third arithmetic unit.

5. The method according to claim 4, characterized in that The fitting parameters include fitting scaling coefficients matching the target prediction algorithm. Correspondingly, for multiple signal values to be fitted among the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at at least one discrete moment in the previous time period, perform fitting processing to obtain the predicted output signal value at the next discrete moment, further including: Configure the first input channels corresponding to the multiple signal values to be fitted with the fitting scaling coefficients corresponding to the first arithmetic unit and the second arithmetic unit, and configure the first output channel with the fitting scaling coefficient corresponding to the third arithmetic unit.

6. The method according to claim 1, wherein Perform upsampling processing on multiple signal values to be sampled among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment to obtain multiple upsampled signal values for driving signal processing, including: Input the input signal values at the current discrete moment and at least one discrete moment in the previous time period into the input end of the fourth arithmetic unit, input the output signal values at at least one discrete moment in the previous time period and the predicted output signal value at the next discrete moment into the input end of the fifth arithmetic unit, and obtain the multiple upsampled signal values from the output end of the sixth arithmetic unit; Wherein, the output end of the fourth arithmetic unit and the output end of the fifth arithmetic unit are respectively connected to the first input end and the second input end of the sixth arithmetic unit, and the fourth arithmetic unit, the fifth arithmetic unit, and the sixth arithmetic unit are configured with corresponding upsampling parameters.

7. The method according to claim 6, wherein Input the input signal values at the current discrete moment and at least one discrete moment in the previous time period into the input end of the fourth arithmetic unit, input the output signal values at at least one discrete moment in the previous time period and the predicted output signal value at the next discrete moment into the input end of the fifth arithmetic unit, and obtain the multiple upsampled signal values from the output end of the sixth arithmetic unit, including: Determine the second output channels corresponding to the multiple signal values to be sampled in the fifth arithmetic unit and the sixth arithmetic unit respectively from among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment; Input the input signal values at the current discrete moment and at least one discrete moment in the previous time period into the second input channel of the fourth arithmetic unit, input the output signal values at at least one discrete moment in the previous time period and the predicted output signal value at the next discrete moment into the second input channel of the fifth arithmetic unit, and output the plurality of upsampled signal values from the second output channel of the sixth arithmetic unit.

8. The method according to claim 7, characterized in that, The upsampling parameter includes an upsampling scaling coefficient matching the target upsampling algorithm. Correspondingly, performing upsampling processing on a plurality of signal values to be sampled among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment to obtain a plurality of upsampled signal values for driving signal processing further includes: Configuring the second input channels corresponding to the plurality of signal values to be sampled with the upsampling scaling coefficients corresponding to the fourth arithmetic unit and the fifth arithmetic unit, and configuring the second output channel with the upsampling scaling coefficient corresponding to the sixth arithmetic unit.

9. A signal processing device, characterized in that, Comprising: An acquisition module that acquires the input signal values at the current discrete moment and at least one discrete moment in the previous time period from a controller, and the output signal values at at least one discrete moment in the previous time period; A prediction module that performs fitting processing on a plurality of signal values to be fitted among the input signal values at the current discrete moment and at least one discrete moment in the previous time period and the output signal values at at least one discrete moment in the previous time period to obtain the predicted output signal value at the next discrete moment; An upsampling module that performs upsampling processing on a plurality of signal values to be sampled among the input signal values at the current discrete moment and at least one discrete moment in the previous time period, the output signal values at at least one discrete moment in the previous time period, and the predicted output signal value at the next discrete moment to obtain a plurality of upsampled signal values for driving signal processing.

10. An electronic device, characterized in that, Comprising: A processor, a memory, a communication interface, and a communication bus, where the processor, the memory, and the communication interface complete communication with each other through the communication bus; The memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the method according to any one of claims 1-8.

11. A computer storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method according to any one of claims 1-8.

12. A computer program product, characterized in that, Including computer instructions, which implement the method according to any one of claims 1-8 when executed by the processor.

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