Three-dimensional heterogeneous integrated T / R micro module and preparation method thereof
Through the design of three-dimensional heterogeneous integrated T/R micromodule, the silicon-based module, chip and circulator are integrated together, and vertical interconnection is achieved using multi-layer silicon dielectric substrate and through-silicon holes, solving the problems of large size, difficult device matching and large insertion loss in the existing T/R micromodule, and achieving the effects of miniaturization and high integration.
Patent Information
- Application Number
- CN202510438753.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-09
- Publication Date
- 2025-07-11
AI Technical Summary
The existing T/R micromodules have problems such as large size, difficulty in matching devices, and large insertion losses.
The three-dimensional heterogeneous integration method is used to integrate the silicon-based module, chip and circulator, and vertical interconnection is achieved through multi-layer silicon dielectric substrate and through-silicon holes. A cavity is installed in the silicon-based module to assemble the chip and circulator, and a magnetic circuit is formed using ferrite, permanent magnets and magnetic conduction carriers to optimize circuit performance.
It realizes the miniaturization of micro modules, improves integration, reduces device matching difficulty, reduces insertion loss, and improves assembly efficiency and circuit performance.
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Figure CN120301446A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technologies, and particularly to a three-dimensional heterogeneous integrated T / R micromodule and a preparation method thereof. Background Art
[0002] A T / R (Transmit / Receive) micromodule is used to complete the functions of receiving and transmitting radio frequency signals in a wireless transceiver system. Its indicators such as size and gain have a relatively significant impact on the entire system. A circulator is an indispensable part of a microwave communication system. The rapid development of communication devices has put forward requirements for the circulator such as miniaturization, light weight, and easy integration.
[0003] In related technologies, a circulator is usually assembled in a T / R micromodule in the form of an independent device. This radio frequency link built by discrete devices has problems such as a relatively large volume, difficult device matching, and a relatively large insertion loss. Summary of the Invention
[0004] Embodiments of this application provide a three-dimensional heterogeneous integrated T / R micromodule and a preparation method thereof to solve the problems of relatively large volume, difficult device matching, and relatively large insertion loss existing in the T / R micromodule in related technologies.
[0005] In a first aspect, embodiments of this application provide a three-dimensional heterogeneous integrated T / R micromodule, including a silicon-based module, a chip, and a circulator;
[0006] The silicon-based module includes multiple layers of silicon dielectric substrates, and through-silicon vias are included in each layer of silicon dielectric substrates; corresponding metal patterns are prepared on the top surface and the bottom surface of each layer of silicon dielectric substrates;
[0007] A cavity for assembling the chip and the circulator is provided in the silicon-based module;
[0008] The chip and the circulator are assembled in corresponding cavities in the silicon-based module.
[0009] In a possible implementation manner, the silicon-based module includes multiple layers of silicon dielectric substrates arranged in ascending order from bottom to top;
[0010] The circulator includes a ferrite, a permanent magnet, a magnetic carrier, a first radio frequency transmission line, and a silicon dielectric substrate between the permanent magnet and the magnetic carrier;
[0011] A radio frequency trace layer is prepared on the bottom surface of the fourth layer of silicon dielectric substrate, and the metal pattern required for the first radio frequency transmission line is prepared on the radio frequency trace layer;
[0012] The ferrite is disposed below the radio frequency trace layer and is located in a corresponding cavity of the third layer of silicon dielectric substrate;
[0013] The permanent magnet is disposed in the corresponding cavity of the fifth-layer silicon dielectric substrate, directly above the ferrite, and bonded to the top surface of the fourth-layer silicon dielectric substrate;
[0014] The magnetic carrier is disposed in the cavity directly below the ferrite, forming a magnetic circuit with the permanent magnet.
[0015] In a possible implementation, the first radio frequency transmission line and the second radio frequency transmission line led out from the chip are located on the same layer.
[0016] In a possible implementation, complementary metal patterns are prepared in the overlapping portion of the third-layer silicon dielectric substrate and the fourth-layer silicon dielectric substrate;
[0017] Ground is prepared on the top and bottom surfaces of each silicon dielectric substrate in the area where no corresponding metal pattern is prepared.
[0018] In a possible implementation, the silicon-based module includes multiple silicon dielectric substrates arranged in ascending order from bottom to top;
[0019] The chip is disposed in the corresponding cavity of the third-layer silicon dielectric substrate and the fourth-layer silicon dielectric substrate; the chip is interconnected with the transmission line in the silicon-based module through bonding wires;
[0020] The fifth-layer silicon dielectric substrate serves as a cover plate to isolate the chip from the external environment.
[0021] In a second aspect, an embodiment of the present application provides a method for manufacturing a three-dimensional heterogeneous integrated T / R micro-module, including:
[0022] Obtain a plurality of silicon dielectric substrates, and etch the plurality of silicon dielectric substrates to obtain a plurality of etched silicon dielectric substrates; wherein, each etched silicon dielectric substrate includes silicon vias; there are cavities for assembling chips and circulators after bonding the plurality of etched silicon dielectric substrates;
[0023] Prepare metal seed layers on the top and bottom surfaces of each etched silicon dielectric substrate, and prepare metal patterns to obtain a plurality of first silicon dielectric substrates; the plurality of first silicon dielectric substrates include at least one cover plate and at least two second silicon dielectric substrates;
[0024] Bond the at least two second silicon dielectric substrates to form a silicon-based module with cavities for assembling chips and circulators;
[0025] Assemble the chip in the silicon-based module, and cap it with the cover plate to isolate the chip from the external environment;
[0026] Assemble the circulator in the silicon-based module after capping to obtain a T / R micro-module.
[0027] In a possible implementation, the silicon-based module includes multiple silicon dielectric substrates arranged in ascending order from bottom to top; the circulator includes a ferrite, a permanent magnet, a magnetic carrier, a first radio frequency transmission line, and a silicon dielectric substrate located between the permanent magnet and the magnetic carrier; a radio frequency trace layer is fabricated on the bottom surface of the fourth silicon dielectric substrate, and the metal pattern required for the first radio frequency transmission line is fabricated on the radio frequency trace layer;
[0028] Assembling the circulator in the silicon-based module after capping includes:
[0029] Assembling the ferrite in the cavity below the radio frequency trace layer; the cavity below the radio frequency trace layer is located in the corresponding cavity of the third silicon dielectric substrate;
[0030] Assembling the permanent magnet in the corresponding cavity of the fifth silicon dielectric substrate; the permanent magnet is located directly above the ferrite and is bonded to the top surface of the fourth silicon dielectric substrate;
[0031] Sintering the magnetic carrier in the cavity directly below the ferrite; the magnetic carrier and the permanent magnet form a magnetic circuit.
[0032] In a possible implementation, the first radio frequency transmission line and the second radio frequency transmission line led out from the chip are on the same layer.
[0033] In a possible implementation, etching the multiple silicon dielectric substrates to obtain multiple etched silicon dielectric substrates includes:
[0034] For each silicon dielectric substrate, fabricating a mask barrier layer on the silicon dielectric substrate, etching to form an etching groove at the positions where the chip and the circulator need to be assembled, removing the mask barrier layer, and etching to form silicon vias in the silicon dielectric substrate to obtain the corresponding etched silicon dielectric substrate.
[0035] In a possible implementation, assembling the circulator in the silicon-based module after capping to obtain a T / R micro-module includes:
[0036] Assembling the circulator in the silicon-based module after capping to obtain a silicon-based module assembled with the circulator;
[0037] Dividing the silicon-based module assembled with the circulator through dicing and film expansion processes to obtain the T / R micro-module.
[0038] In the embodiments of the present application, the three-dimensional heterogeneous integrated T / R micromodule includes a silicon-based module, a chip, and a circulator; a cavity for assembling the chip and the circulator is provided in the silicon-based module; the chip and the circulator are assembled in the corresponding cavities in the silicon-based module, so as to realize a three-dimensional heterogeneous integrated T / R micromodule with integrated circulator, which is equivalent to a heterogeneous integrated radio frequency micromodule with a circulator integrated in the micromodule, having the advantages of miniaturization and high integration degree, which can reduce the volume of the micromodule, reduce the device matching difficulty, improve the assembly efficiency, and reduce the insertion loss; in addition, the silicon-based module includes multiple layers of silicon dielectric substrates, and each layer of silicon dielectric substrate includes silicon through holes, which can realize vertical interconnection and improve the integration degree; corresponding metal patterns are prepared on the top and bottom surfaces of each layer of silicon dielectric substrate, which can form IPD (Integrated Passive Devices) devices, optimize the circuit performance, reduce the number of discrete components, and further reduce the volume of the module. Description of the Drawings
[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0040] Figure 1 is a schematic structural diagram of a three-dimensional heterogeneous integrated T / R micromodule provided by an embodiment of the present application;
[0041] Figure 2 is a flowchart of the implementation of a method for manufacturing a three-dimensional heterogeneous integrated T / R micromodule provided by an embodiment of the present application;
[0042] Figure 3 is a flowchart of the implementation of a method for manufacturing a three-dimensional heterogeneous integrated T / R micromodule provided by another embodiment of the present application. Detailed Embodiments
[0043] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.
[0044] To make the objectives, technical solutions, and advantages of the present application clearer, the following will be described through specific embodiments with reference to the drawings.
[0045] Figure 1This is a schematic diagram of the structure of the 3D heterogeneous integrated T / R micromodule provided by the embodiments of the present application. Refer to Figure 1 , the 3D heterogeneous integrated T / R micromodule includes a silicon-based module 10, a chip 20, and a circulator 30;
[0046] The silicon-based module 10 includes multiple layers of silicon dielectric substrates 11, and each layer of silicon dielectric substrate 11 includes through-silicon vias (TSVs) 12; metal patterns are prepared on the top and bottom surfaces of each layer of silicon dielectric substrate 11.
[0047] A cavity for assembling the chip 20 and the circulator 30 is provided in the silicon-based module 10.
[0048] The chip 20 and the circulator 30 are assembled in the corresponding cavities in the silicon-based module 10.
[0049] Refer to Figure 1 , the silicon-based module 10 includes multiple layers of silicon dielectric substrates 11. Among them, the silicon dielectric substrate 11 can be composed of high-resistance silicon. The silicon dielectric substrate 11 can also be called a silicon substrate, a wafer, a silicon interposer, etc.
[0050] The embodiments of the present application do not specifically limit the number of layers of the silicon dielectric substrate 11, and any achievable number of layers can be used. For example, it can be 5 layers, 6 layers, or 7 layers, etc.
[0051] In each layer of silicon dielectric substrate 11, multiple silicon vias 12 are included to achieve vertical interconnection between the layers of the micromodule, break the limitations of the 2D integration structure, expand the circuit layout into the three-dimensional space, improve the integration degree, and ensure good grounding of the micromodule.
[0052] Corresponding metal patterns can be prepared on the top and bottom surfaces of each layer of silicon dielectric substrate 11 to form IPD devices. For example, it can include transmission lines, matching networks, etc. In the areas where the above metal patterns are not prepared on the top and bottom surfaces of each layer of silicon dielectric substrate 11, ground can be prepared, that is, a large area of ground is set, so as to ensure good grounding of the micromodule. Exemplarily, refer to Figure 1 , the above metal patterns and ground can be provided between adjacent silicon dielectric substrates 11.
[0053] For each layer of silicon dielectric substrate 11, its top surface can also be called the upper surface, which is the surface in contact with the upper layer of silicon dielectric substrate 11, and its bottom surface can also be called the lower surface, which is the surface in contact with the lower layer of silicon dielectric substrate 11.
[0054] Refer to Figure 1, a cavity for assembling the chip 20 and the circulator 30 is provided in the silicon-based module 10, and the chip 20 and the circulator 30 are assembled in different cavities. The cavity can be a closed cavity or an open cavity. For example, the cavity for assembling the chip 20 can be a closed cavity, and the cavity for assembling the circulator 30 can be an open cavity.
[0055] The chip 20 can be a chip required for the T / R micromodule. For example, it can be a microwave chip, and can include at least one of chips such as a amplitude-phase control chip, an amplifier chip, and a driver chip for the amplitude-phase control chip. Among them, the amplitude-phase control chip and the amplifier chip can be prepared by GaAs process, and the driver chip for the amplitude-phase control chip can be prepared by CMOS (Complementary Metal-Oxide-Semiconductor) process.
[0056] The chip 20 can be a heterogeneous chip; the circulator 30 can be a MEMS (Micro-Electro-Mechanical Systems) circulator, and further a silicon-based MEMS circulator.
[0057] The three-dimensional heterogeneous integrated T / R micromodule provided by the embodiment of the present application includes a silicon-based module 10, a chip 20, and a circulator 30; a cavity for assembling the chip 20 and the circulator 30 is provided in the silicon-based module 10; the chip 20 and the circulator 30 are assembled in the corresponding cavities in the silicon-based module 10, so that a three-dimensional heterogeneous integrated T / R micromodule with integrated circulator 30 can be realized, which is equivalent to a heterogeneous integrated radio frequency micromodule with integrated circulator 30 in the micromodule, having the advantages of miniaturization and high integration degree, can reduce the volume of the micromodule, reduce the device matching difficulty, improve the assembly efficiency, and reduce the insertion loss; in addition, the silicon-based module 10 includes multiple layers of silicon dielectric substrates 11, and through-silicon vias 12 are included in each layer of silicon dielectric substrate 11, which can realize vertical interconnection and improve the integration degree; metal patterns corresponding to the top surface and the bottom surface of each layer of silicon dielectric substrate 11 are prepared, which can form IPD (Integrated Passive Devices) devices, optimize the circuit performance, reduce the number of discrete components, and further reduce the volume of the module.
[0058] In some embodiments, refer to Figure 1 , the silicon-based module 10 includes multiple layers of silicon dielectric substrates 11 arranged in ascending order from bottom to top;
[0059] The circulator 30 includes a ferrite 31, a permanent magnet 32, a magnetic carrier 33, a first radio frequency transmission line, and a silicon dielectric substrate 11 located between the permanent magnet 32 and the magnetic carrier 33;
[0060] A radio frequency wiring layer 34 is prepared on the bottom surface of the fourth silicon dielectric substrate, and the radio frequency wiring layer 34 is prepared with a metal pattern required for the first radio frequency transmission line;
[0061] The ferrite 31 is arranged below the radio frequency wiring layer 34 and is located in the corresponding cavity of the third silicon dielectric substrate;
[0062] The permanent magnet 32 is disposed in the corresponding cavity of the fifth silicon dielectric substrate, located directly above the ferrite 31, and bonded to the top surface of the fourth silicon dielectric substrate;
[0063] The magnetic carrier 33 is disposed in a cavity directly below the ferrite 31 , and forms a magnetic circuit with the permanent magnet 32 .
[0064] In some embodiments, the first RF transmission line and the second RF transmission line derived from the chip 20 are located in the same layer.
[0065] In some embodiments, a complementary metal pattern is prepared on the overlapping portion of the third silicon dielectric substrate and the fourth silicon dielectric substrate;
[0066] The top and bottom surfaces of each layer of the silicon dielectric substrate 11 are provided with ground in areas where no corresponding metal patterns are provided.
[0067] In the embodiment of the present application, the multi-layer silicon dielectric substrates 11 included in the silicon-based module 10 are arranged in order from small to large from bottom to top, that is, the bottom layer is the first silicon dielectric substrate, and upwards are the second silicon dielectric substrate, the third silicon dielectric substrate, the fourth silicon dielectric substrate, the fifth silicon dielectric substrate, and so on.
[0068] Exemplarily, the silicon-based module 10 may include five layers of silicon dielectric substrates 11, the fifth layer of silicon dielectric substrate may be a cover plate, used to isolate the chip 20 from the external environment, and to achieve electromagnetic shielding of the module by paving a large area; the fourth layer of silicon dielectric substrate and the third layer of silicon dielectric substrate may be chip 20 mounting layers, wherein there is a cavity for mounting the chip 20; the second layer of silicon dielectric substrate and the first layer of silicon dielectric substrate may be a structural support layer and a redistribution layer 13 (RDL) for assembling the chip 20. Figure 1 A redistribution layer 13 may be provided between the first silicon dielectric substrate and the second silicon dielectric substrate, and between the second silicon dielectric substrate and the third silicon dielectric substrate. The five silicon dielectric substrates 11 together constitute the mounting cavity of the chip 20, and provide structural support and heat dissipation paths for the module. The upper and lower surfaces of each silicon dielectric substrate 11 are electroplated with metal patterns to form an IPD device, and the rest is a large area of ground. A large number of TSVs are distributed in each silicon dielectric substrate 11 to achieve vertical interconnection and ensure good module grounding.
[0069] Figure 1The parts outlined by the dashed lines are all circulators 30, which may include a ferrite 31, a permanent magnet 32, a magnetic carrier 33, a first radio frequency transmission line, and a silicon dielectric substrate 11 located between the permanent magnet 32 and the magnetic carrier 33. It should be noted that the circulator 30 includes the silicon dielectric substrate 11 located between the permanent magnet 32 and the magnetic carrier 33, which means the silicon dielectric substrate 11 located between the permanent magnet 32 and the magnetic carrier 33 and prepared with metal patterns and ground.
[0070] The first radio frequency transmission line is the radio frequency transmission line of the circulator 30 for signal transmission and is located on the radio frequency trace layer 34. The radio frequency trace layer 34 may be located on the bottom surface of the fourth silicon dielectric substrate, that is, between the third silicon dielectric substrate and the fourth silicon dielectric substrate, as Figure 1 shown.
[0071] The second radio frequency transmission line is the radio frequency transmission line led out from the chip 20 for signal transmission. To reduce the transmission insertion loss and improve the module performance, the first radio frequency transmission line of the circulator 30 and the second radio frequency transmission line of the chip 20 are preferably located on the same layer, that is, they can both be located on the above-mentioned radio frequency trace layer 34. Therefore, the chip 20 installation layer determines the layer required for the distribution of the circulators 30 integrated in the module. The second radio frequency transmission line led out from the chip 20 is located on the top surface, that is, the upper surface, of the third silicon dielectric substrate. From the structure of the circulator 30, it is necessary to fabricate a cavity downward from the first radio frequency transmission line plane to place the ferrite 31, so the lower surface of the fourth silicon dielectric substrate is selected to electroplate the metal patterns required for the first radio frequency transmission line of the circulator 30.
[0072] Complementary metal patterns are electroplated on the overlapping part of the third silicon dielectric substrate and the fourth silicon dielectric substrate, which can ensure normal interlayer connection, prevent short circuits, and realize interlayer interconnection through thermocompression ultrasonic bonding, ensuring that the radio frequency transmission lines are distributed on the same layer.
[0073] To improve the performance of the circulator 30, part of the fifth silicon dielectric substrate is removed, and the permanent magnet 32 is bonded above the upper surface of the fourth silicon dielectric substrate and directly above the ferrite 31. A cavity is fabricated directly below the ferrite 31 to sinter the magnetic carrier 33, and the magnetic carrier 33 and the permanent magnet 32 form a magnetic circuit.
[0074] A large area of ground is laid and thick gold is electroplated on the lower surface of the third silicon dielectric substrate above the magnetic carrier 33 to ensure the sintering reliability of the magnetic carrier 33 and good grounding performance.
[0075] In some embodiments, referring to Figure 1 , the silicon-based module 10 includes multiple silicon dielectric substrates 11 arranged in ascending order from bottom to top;
[0076] The chip 20 is disposed in corresponding cavities in the third-layer silicon dielectric substrate and the fourth-layer silicon dielectric substrate; the chip 20 is interconnected with the transmission line in the silicon-based module 10 through bonding wires 21;
[0077] The fifth-layer silicon dielectric substrate serves as a cover plate to isolate the chip 20 from the external environment.
[0078] See Figure 1 , the chip 20 is assembled in the chip 20 mounting cavity above the third-layer silicon dielectric substrate and is interconnected with the transmission line (such as the second radio frequency transmission line) in the silicon-based module 10 through micro-assembly processes such as bonding wires 21, realizing the heterogeneous integration of chips 20 with different materials and different thicknesses inside the silicon-based module 10. The chip 20, the IPD device, and the bonding wires 21 constitute the circuit interconnection system of the T / R micro-module, and the large-area grounding metal layer and a large number of grounding TSVs constitute the electromagnetic shielding and grounding system of the module.
[0079] The three-dimensional heterogeneous integrated T / R micro-module provided by the embodiment of the present application internally integrates a silicon-based MEMS circulator 30, which is jointly designed by a variety of heterogeneous chips 20 and passive IPD devices such as the integrally designed MEMS circulator 30. The microwave chip 20 in the heterogeneous integrated module. The silicon-based module 10 obtains a high-precision and low-loss passive transmission structure through processes such as MEMS etching and electroplating on the silicon-based dielectric substrate, realizing the interconnection between the chip 20 and the chip 20, and between the chip 20 and the MEMS circulator 30.
[0080] Exemplarily, the above three-dimensional heterogeneous integrated T / R micro-module can be a three-dimensional heterogeneous integrated T / R micro-module in the X band or a three-dimensional heterogeneous integrated T / R micro-module in other bands, which is not specifically limited herein.
[0081] Corresponding to the above three-dimensional heterogeneous integrated T / R micro-module, the embodiment of the present application also provides a preparation method for a three-dimensional heterogeneous integrated T / R micro-module, which is used to prepare the above three-dimensional heterogeneous integrated T / R micro-module. That is to say, the above three-dimensional heterogeneous integrated T / R micro-module is prepared by the preparation method of the three-dimensional heterogeneous integrated T / R micro-module.
[0082] See Figure 2 , the preparation method of the above three-dimensional heterogeneous integrated T / R micro-module includes:
[0083] In S201, a plurality of silicon dielectric substrates are obtained, and the plurality of silicon dielectric substrates are etched to obtain a plurality of etched silicon dielectric substrates; wherein, each of the etched silicon dielectric substrates includes silicon through holes; there are cavities for assembling chips and circulators after bonding the plurality of etched silicon dielectric substrates.
[0084] In the embodiments of the present application, after cleaning each silicon dielectric substrate, etching may be performed on each silicon dielectric substrate. Etching is performed at a preset position on each silicon dielectric substrate to obtain a plurality of etched silicon dielectric substrates. Each of the etched silicon dielectric substrates includes a plurality of through-silicon vias, and sufficient space is left at the chip mounting position and the circulator mounting position in each of the etched silicon dielectric substrates, so that a cavity for assembling a chip and a circulator can exist after bonding a plurality of etched silicon dielectric substrates.
[0085] Exemplarily, the plurality of etched silicon dielectric substrates after S201 may be as shown in Figure 3 41 in, that is Figure 3 41 in gives a schematic diagram of a plurality of etched silicon dielectric substrates.
[0086] In S202, a metal seed layer is prepared on the top and bottom surfaces of each etched silicon dielectric substrate, and a metal pattern is prepared to obtain a plurality of first silicon dielectric substrates; the plurality of first silicon dielectric substrates include at least one cover plate and at least two second silicon dielectric substrates.
[0087] A metal seed layer is sputtered on the top and bottom surfaces of each etched silicon dielectric substrate respectively, and a metal pattern is prepared through photolithography and electroplating processes to obtain a plurality of first silicon dielectric substrates. In the embodiments of the present application, for the convenience of distinction, the silicon dielectric substrate on which the metal seed layer is sputtered and the metal pattern is prepared is called a first silicon dielectric substrate.
[0088] In the embodiments of the present application, IPD devices and redistribution layers are realized through metallization.
[0089] Exemplarily, the plurality of first silicon dielectric substrates after S202 may be as shown in Figure 3 42 in, that is Figure 3 42 in gives a schematic diagram of a plurality of first silicon dielectric substrates. Among them, the topmost first silicon dielectric substrate may be a cover plate, and the remaining first silicon dielectric substrates may be second silicon dielectric substrates. That is, the first silicon dielectric substrate to be used as a cover plate is called a cover plate, and the other first silicon dielectric substrates are called second silicon dielectric substrates.
[0090] In S203, at least two second silicon dielectric substrates are bonded to form a silicon-based module with a cavity for assembling a chip and a circulator.
[0091] Using a thermocompression ultrasonic bonding process, the above-mentioned plurality of second silicon dielectric substrates are bonded to form a silicon-based module with a cavity for mounting a chip and a MESM circulator. That is, the silicon dielectric substrates except the cover plate are bonded.
[0092] The embodiments of the present application achieve wafer-level bonding and substrate stacking.
[0093] Exemplarily, the silicon-based module after S203 can be as shown in Figure 3 43 in Figure 3 43 in
[0094] gives a schematic diagram of the silicon-based module. Among them, the top cover plate is not bonded together, and the other silicon dielectric substrates are bonded together.
[0095] Adopting the micro-assembly process, the chip is assembled in the cavity corresponding to the chip in the silicon-based module, and high-precision assembly can be achieved. The silicon-based module after assembling the chip is as shown in Figure 3 44 in
[0096] Among them, the chip can be a heterogeneous chip. Figure 3 After that, capping is performed through the cover plate, that is, all the silicon dielectric substrates are stacked to complete the micro-module capping, realizing wafer-level capping, so that the chip is isolated from the external environment. The silicon-based module after capping is as shown in
[0097] 45 in
[0098] After capping, a circulator is assembled in the silicon-based module to obtain a T / R micro-module.
[0099] By the micro-assembly process, a circulator is assembled in the silicon-based module after capping, so that a T / R micro-module can be obtained, and high-precision assembly can be achieved.
[0100] The above-mentioned assembling the circulator in the silicon-based module after capping may include:
[0101] Assembling the ferrite in the cavity below the radio frequency trace layer; the cavity below the radio frequency trace layer is located in the corresponding cavity of the third silicon dielectric substrate;
[0102] Assembling the permanent magnet in the corresponding cavity of the fifth silicon dielectric substrate; the permanent magnet is located directly above the ferrite and is bonded to the top surface of the fourth silicon dielectric substrate;
[0103] Sintering the magnetic conductor carrier in the cavity directly below the ferrite; the magnetic conductor carrier and the permanent magnet form a magnetic circuit.
[0104] Exemplarily, referring to Figure 1, the magnetic carrier can be located in the corresponding cavities of the first silicon dielectric substrate and the second silicon dielectric substrate directly below the ferrite. The ferrite and the magnetic carrier can be in contact.
[0105] For a detailed description of the embodiments of the present application, reference can be made to the relevant descriptions in the foregoing embodiments, which will not be elaborated herein.
[0106] In some embodiments, the first radio frequency transmission line and the second radio frequency transmission line led out from the chip are located on the same layer.
[0107] By locating the first radio frequency transmission line and the second radio frequency transmission line led out from the chip on the same layer, the transmission insertion loss can be reduced and the module performance can be improved.
[0108] In some embodiments, the etching of the multiple silicon dielectric substrates to obtain multiple etched silicon dielectric substrates may include:
[0109] For each silicon dielectric substrate, a mask barrier layer is prepared on the silicon dielectric substrate, and after etching to form an etching groove at the positions where the chip and the circulator need to be assembled, the mask barrier layer is removed, and a through-silicon via is etched in the silicon dielectric substrate to obtain the corresponding etched silicon dielectric substrate.
[0110] In the embodiments of the present application, a SiO2 passivation layer can be prepared on the silicon dielectric substrate as a mask barrier layer. Photoresist is coated on the top surface of the silicon dielectric substrate, lithographed, developed, and etched to form an etching groove or an etching through-hole at the positions where the chip and the circulator need to be assembled. After the etching is completed, the mask barrier layer is removed; then, glue is coated, lithographed, and developed on the top surface of the silicon dielectric substrate to obtain the etching pattern required for preparing the TSV, and through ICP (Inductively Coupled Plasma) etching, etching is performed at the positions where the TSV is required to form a TSV structure.
[0111] The silicon dielectric substrate can be prepared by a silicon-based three-dimensional heterogeneous integration process, and the semiconductor process based on mask lithography used ensures the high-precision requirements of silicon-based processing.
[0112] In some embodiments, the assembly of the circulator in the silicon-based module after capping to obtain a T / R micromodule may include:
[0113] Assemble the circulator in the silicon-based module after capping to obtain a silicon-based module with a circulator assembled;
[0114] Through the dicing and film expansion processes, the silicon-based module with a circulator assembled is divided to obtain a T / R micromodule.
[0115] See Figure 3 , the silicon-based module after assembling the circulator as Figure 3As shown in 46 therein. If a single T / R micro-module is prepared, the silicon-based module after assembling the circulator can be regarded as the T / R micro-module; if multiple T / R micro-modules are prepared, the silicon-based module assembled with the circulator needs to be segmented through processes such as dicing and die expansion to obtain a T / R micro-module integrated with SiP (System In a Package) with a complete radio frequency link and functions, as shown in Figure 3 47 therein.
[0116] In some possible implementation manners, after obtaining the T / R micro-module, it can be tested.
[0117] It should be noted that for the specific description of the preparation method of the three-dimensional heterogeneous integrated T / R micro-module, reference can be made to the relevant descriptions in the foregoing embodiments of the three-dimensional heterogeneous integrated T / R micro-module, which will not be elaborated herein.
[0118] In the embodiment of the present application, a variety of IPD devices including MEMS circulators are integrally manufactured directly on a heterogeneous silicon-based module prepared based on a silicon-based three-dimensional heterogeneous integration process, further improving the integration degree and assembly efficiency of the micro-module; the prepared heterogeneous integrated T / R micro-module has the advantages of perfect functions, compact structure and high integration degree.
[0119] The embodiment of the present application prepares a three-dimensional heterogeneous integrated T / R micro-module integrating a circulator in the micro-module based on a silicon-based three-dimensional heterogeneous integration process and a micro-assembly process, which has the characteristics of small volume and high integration degree. The design and preparation method of integrally integrating a MEMS circulator in the micro-module proposed in the embodiment of the present application can be extended to lower or higher frequency bands and applied to T / R micro-modules with different uses and functions, providing a new idea for the miniaturization and high integration of T / R micro-modules and having broad application prospects.
[0120] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
[0121] In the above embodiments, the descriptions of each embodiment have their own focuses. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. Without special instructions and logical conflicts, the terms and / or descriptions between different embodiments are consistent and can be mutually referred to, and the technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.
[0122] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.
Claims
1. A three-dimensional heterogeneous integrated T / R micro-module, characterized in that It includes a silicon-based module, a chip and a circulator; The silicon-based module includes multiple layers of silicon dielectric substrates, and each layer of silicon dielectric substrate includes through-silicon vias; metal patterns corresponding to the top and bottom surfaces of each layer of silicon dielectric substrate are fabricated; A cavity for assembling the chip and the circulator is provided in the silicon-based module; The chip and the circulator are assembled in the corresponding cavities in the silicon-based module.
2. The three-dimensional heterogeneous integrated T / R micro-module according to claim 1, wherein The silicon-based module includes multiple layers of silicon dielectric substrates arranged in ascending order from bottom to top; The circulator includes a ferrite, a permanent magnet, a magnetic carrier, a first radio frequency transmission line, and a silicon dielectric substrate located between the permanent magnet and the magnetic carrier; A radio frequency trace layer is fabricated on the bottom surface of the fourth layer of silicon dielectric substrate, and the metal patterns required for the first radio frequency transmission line are fabricated on the radio frequency trace layer; The ferrite is disposed below the radio frequency trace layer and is located in the corresponding cavity of the third layer of silicon dielectric substrate; The permanent magnet is disposed in the corresponding cavity of the fifth layer of silicon dielectric substrate, directly above the ferrite, and is bonded to the top surface of the fourth layer of silicon dielectric substrate; The magnetic carrier is disposed in the cavity directly below the ferrite to form a magnetic circuit with the permanent magnet.
3. The three-dimensional heterogeneous integrated T / R micro-module according to claim 2, characterized in that, The first radio frequency transmission line and the second radio frequency transmission line led out from the chip are on the same layer.
4. The three-dimensional heterogeneous integrated T / R micromodule according to claim 3, wherein, Complementary metal patterns are fabricated in the overlapping portion of the third layer of silicon dielectric substrate and the fourth layer of silicon dielectric substrate; Ground is fabricated in the regions where the top and bottom surfaces of each layer of silicon dielectric substrate do not have corresponding metal patterns.
5. The three-dimensional heterogeneous integrated T / R micro-module according to any one of claims 1 to 4, characterized in that The silicon-based module includes multiple layers of silicon dielectric substrates arranged in ascending order from bottom to top; The chip is disposed in the corresponding cavity in the third layer of silicon dielectric substrate and the fourth layer of silicon dielectric substrate; the chip is interconnected with the transmission line in the silicon-based module through bonding wires; The fifth layer of silicon dielectric substrate serves as a cover to isolate the chip from the external environment.
6. A preparation method of a three-dimensional heterogeneous integrated T / R micro-module, characterized in that, It includes: Obtain multiple silicon dielectric substrates, and etch the multiple silicon dielectric substrates to obtain multiple etched silicon dielectric substrates; wherein, each etched silicon dielectric substrate includes through-silicon vias; cavities for assembling the chip and the circulator exist after bonding the multiple etched silicon dielectric substrates; Fabricate metal seed layers on the top and bottom surfaces of each etched silicon dielectric substrate, and fabricate metal patterns to obtain multiple first silicon dielectric substrates; the multiple first silicon dielectric substrates include at least one cover and at least two second silicon dielectric substrates; Bond the at least two second silicon dielectric substrates to form a silicon-based module with cavities for assembling the chip and the circulator; Assemble the chip in the silicon-based module, and cap it with the cover to isolate the chip from the external environment; Assemble the circulator in the silicon-based module after capping to obtain a T / R micro-module.
7. The manufacturing method of the three-dimensional heterogeneous integrated T / R micromodule according to claim 6, wherein The silicon-based module includes multiple layers of silicon dielectric substrates arranged in ascending order from bottom to top; the circulator includes a ferrite, a permanent magnet, a magnetic carrier, a first radio frequency transmission line, and a silicon dielectric substrate located between the permanent magnet and the magnetic carrier; a radio frequency trace layer is fabricated on the bottom surface of the fourth layer of silicon dielectric substrate, and the metal patterns required for the first radio frequency transmission line are fabricated on the radio frequency trace layer; Assembling the circulator in the silicon-based module after capping includes: Assembling the ferrite in the cavity below the RF trace layer; the cavity below the RF trace layer is located in the corresponding cavity of the third silicon dielectric substrate; Assembling the permanent magnet in the corresponding cavity of the fifth silicon dielectric substrate; the permanent magnet is located directly above the ferrite and is bonded to the top surface of the fourth silicon dielectric substrate; Sintering the magnetic carrier in the cavity directly below the ferrite; the magnetic carrier and the permanent magnet form a magnetic circuit.
8. The preparation method of the three-dimensional heterogeneous integrated T / R micromodule according to claim 7, wherein The first RF transmission line and the second RF transmission line led out from the chip are on the same layer.
9. The preparation method of the three-dimensional heterogeneous integrated T / R micro-module according to claim 6, wherein, Etching a plurality of silicon dielectric substrates to obtain a plurality of etched silicon dielectric substrates, including: For each silicon dielectric substrate, preparing a mask blocking layer on the silicon dielectric substrate, etching to form an etching groove at the positions where the chip and the circulator need to be assembled, removing the mask blocking layer, and etching to form silicon vias in the silicon dielectric substrate to obtain the corresponding etched silicon dielectric substrate.
10. The preparation method of the three-dimensional heterogeneous integrated T / R micromodule according to any one of claims 6 to 9, characterized in that Assembling the circulator in the silicon-based module after capping to obtain a T / R micro-module, including: Assembling the circulator in the silicon-based module after capping to obtain a silicon-based module assembled with a circulator; Dividing the silicon-based module assembled with a circulator through a dicing and film expansion process to obtain a T / R micro-module.