Digital image exchange system for optical measurement equipment based on VPX architecture

Abstract

The present invention relates to a digital image exchange system for optical measurement equipment based on the VPX architecture, which belongs to the field of image processing technology and solves the problem of realizing the distribution of digital image data of optical measurement equipment using the VPX system architecture. The present invention includes a digital image exchange board that complies with the VPX standard, which is based on an FPGA chip, integrates an ARM chip, and is provided with a front panel output interface and a rear VPX connector output interface connected to the VPX backplane bus. The FPGA chip changes the current working mode of the system according to the external control information sent by the ARM chip, and realizes free switching between the real-time data flow mode and the post-injection data flow mode to meet the needs of different scenarios. The present invention uses the VPX backplane bus to replace traditional optical fiber splitters or Camera Link cables, which not only reduces the number of external cables and the complexity of wiring, but also realizes efficient and reliable exchange and distribution of digital images of optical measurement equipment.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and in particular to a digital image exchange system for optical measurement equipment based on a VPX architecture. Background Art

[0002] Large optical measurement equipment (abbreviated as optical measurement equipment) typically contains three or more digital image sensors. The uncompressed raw data from these digital image sensors needs to be distributed to digital image processing and storage systems after being transmitted via optical fibers. Traditional digital image distribution in optical measurement equipment primarily involves distributing raw digital images to storage and processing subsystems via fiber splitters or camera link cables. This results in complex wiring and numerous cables, resulting in low system integration and reliability.

[0003] VPX systems, with their high bandwidth, high-speed data transmission, excellent connector performance, improved power and cooling solutions, modular design, robust mechanical structure, and suitability for harsh environments, are widely used in various fields. While the VPX system architecture allows for the transmission of high-speed digital images via the VPX backplane bus, achieving optical-to-electrical conversion of digital images and distributing image data across the VPX backplane's high-speed bus remains a technological gap. Summary of the Invention

[0004] In order to fill the technical gap of using the VPX system architecture to realize the distribution of digital image data of optical measurement equipment and solve the problems of complex lines and large number of cables in traditional digital image distribution of optical measurement equipment, the present invention provides an optical measurement equipment digital image exchange system based on the VPX architecture to realize efficient and reliable exchange and distribution of digital images of optical measurement equipment.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0006] A digital image exchange system for optical measurement equipment based on the VPX architecture includes a digital image exchange board designed based on the VPX standard architecture. The digital image exchange board includes:

[0007] The FPGA chip, serving as the system's data interaction core, is used to receive, parse, and distribute digital image data; the oven-controlled crystal oscillator serves as the system's high-precision clock reference source; the Flash chip serves as the FPGA program storage chip; the high-speed differential crystal oscillator serves as the reference clock CLK for the system's GTX high-speed communication; the PHY chip serves as a converter for FPGA network communication; the 422 interface chip serves as an interface for interaction within the VPX system; and the ARM chip serves as an interface for external network communication. The ARM chip and the FPGA chip directly exchange data via the SPI bus, while retaining a set of IO ports as an interaction interface for INT interrupt signals.

[0008] The digital image exchange board also includes an external interface, which includes a panel front interface and a VPX connector rear interface. The panel front interface includes an SFP+ optical fiber interface, an LED indicator, an RJ45 network interface, a signal monitoring interface, and a JTAG debugging interface. The VPX connector rear interface is connected to the backplane bus through three VPX standard connectors. The three VPX standard connectors are P0, P1, and P4, where P0 is a DC power supply interface and includes a group of I2C communication interfaces; P1 is a high-speed communication interface, including three groups of 10G high-speed differential interfaces; P4 is an auxiliary communication interface, including a 1000M network interface and three groups of 422 communication interfaces.

[0009] The digital image exchange board receives external control information through the RJ45 network interface, and the ARM chip sends the external control information to the FPGA chip through the SPI bus. The FPGA chip changes the current working mode of the system according to the external control information, realizing free switching between the real-time data stream mode and the post-injection data stream mode.

[0010] Compared with the prior art, the present invention has the following beneficial effects:

[0011] The digital image exchange system for optical measurement equipment proposed in the present invention adopts a digital image exchange board designed based on the VPX standard architecture. The board is designed based on domestic components and adopts a domestic FPGA chip as the core component for data exchange. The VPX backplane bus is used to replace traditional optical fiber splitters or Camera Link cables, which not only reduces the number of external cables and the complexity of wiring, but also enables high-speed digital image transmission. At the same time, the digital image exchange board is equipped with a domestic ARM chip for external network data communication of the board and internal status monitoring of the board. The FPGA chip receives external control information through the network interface of the ARM chip, thereby changing the current working mode of the system according to the external control instructions, realizing free switching between real-time data stream mode and post-injection data stream mode to meet the needs of different scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 1 is a hardware schematic diagram of a digital image exchange board according to an embodiment of the present invention;

[0013] Figure 2 Schematic diagram of data flow corresponding to the real-time data flow mode;

[0014] Figure 3 The data flow diagram corresponding to the post-injection data flow mode;

[0015] Figure 4 This is a schematic diagram of the external interaction interface of the digital image exchange board. DETAILED DESCRIPTION

[0016] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

[0017] This embodiment provides a digital image exchange system for optical measurement equipment based on VPX architecture. The system includes a digital image exchange board. Figure 1 The digital image exchange board is designed based on the VPX standard architecture and is equipped with external interfaces, including the front panel interface and the VPX connector rear interface. The front panel interface mainly includes SFP+ fiber optic interfaces (4), LED indicators (8), RJ45 network interface (1), signal monitoring interfaces (2), and JTAG debugging interface (1). The VPX connector rear interface is connected to the backplane bus through three VPX standard connectors: P0, P1, and P4. P0 is mainly used as a DC power supply interface with an output voltage of 12V and includes an I2C communication interface for connection to the BMC; P1 is a high-speed communication interface, mainly including three 10G high-speed differential interfaces (Aurora X4); P4 is an auxiliary communication interface, mainly including a 1000M network interface and three 422 communication interfaces.

[0018] The digital image exchange board's internal chips primarily include: a domestically produced FPGA chip, such as the JFM7K325T, serving as the system's data exchange core for receiving, parsing, and distributing digital image data; an oven-controlled crystal oscillator (OCR) serving as the system's high-precision clock reference source; a Flash chip serving as the FPGA program storage chip; a high-speed differential crystal oscillator serving as the reference clock (CLK) for the system's GTX high-speed communication; a physical physical layer (PHY) chip serving as the FPGA network communication converter; a set of 422 interface chips serving as the internal interface to the VPX system; and a domestically produced ARM (GD32) chip serving as the external network communication interface. The ARM chip and FPGA exchange data directly via the SPI bus, while a set of IO ports are reserved as the INT interrupt signal interface to ensure real-time data exchange between the FPGA and ARM chips. External indicators, such as LEDs, are directly driven by the FPGA chip's IO ports.

[0019] Digital image data flows for large optical measurement equipment can be either real-time or post-injection. In real-time data flow, the digital image output by the image sensor is transmitted via optical fiber to the digital image exchange board, which processes and replicates it before distributing it to the various processing subsystems, or processing boards. In post-injection data flow, digital images are already recorded in the storage subsystem, or storage board. To facilitate subsequent analysis or simulation training, the digital images are re-injected from the storage subsystem to the digital image exchange board, which then distributes them to the various processing systems.

[0020] In real-time data streaming mode, such as Figure 2As shown, digital image data transmitted via LC-fiber is connected to the digital image exchange board via an SFP+ fiber optic interface and then to the GTX high-speed interface within the FPGA chip as a CML differential pair. The FPGA chip uses the Aurora high-speed parsing protocol. After parsing, the data stream is converted from a high-speed serial differential signal to a stream data stream containing valid data, end-of-packet indicator bits, and 64-bit parallel data. Each data packet corresponds to a row of data in the digital image and also includes a first-row indicator, ensuring that continuous data can be accurately restored to a complete digital image after parsing. The FPGA chip receives external overlay data, such as sensor information, that needs to be added to the digital image from the ARM chip and overlays this external overlay data into the data stream, completing the data fusion between the digital image and the external sensor. Due to the limited processing power of back-end processors, high-speed digital images are often required to be frame-extracted. To ensure that key frames can be extracted and processed at the specified time, the FPGA chip receives a synchronization signal from the external 422 communication interface. Using the rising edge of the synchronization signal as the reference time, the chip transmits the complete digital image data stream received after the rising edge to the back-end, thus completing the digital image frame extraction process. The frame-extracted data stream is packaged using the Aurora protocol and output via the GTX high-speed interface. The CML differential pairs output by the FPGA chip are connected to the VPX high-speed connector as high-speed differential lines. They are then connected to the back-end digital image processing board and other processing boards via the backplane.

[0021] In post-injection data stream mode, such as Figure 3 As shown, the storage card connects digital image data to the GTX high-speed interface inside the FPGA chip via a VPX high-speed connector in the form of CML differential pairs. After the data stream is parsed using the Aurora protocol, it is converted from a high-speed serial differential signal to a stream data stream. The stream data stream is then packaged using the Aurora protocol and output through the GTX high-speed interface. The CML differential pairs output by the FPGA chip are connected to the VPX high-speed connector as high-speed differential lines. They are then connected to back-end processing boards such as the digital image processing board via the backplane.

[0022] like Figure 4 As shown, the digital image exchange board has an integrated design. A single board can receive up to four channels of 10Gb bandwidth digital images, connect to up to four storage boards at high speed, and distribute data information to up to eight processing boards, laying the foundation for subsequent data distribution and processing of large-scale optical measurement equipment.

[0023] The digital image exchange board can receive external control information through the RJ45 network interface on the front panel. The ARM chip sends the external control information to the FPGA chip through the SPI bus. The FPGA chip changes the current working mode of the system according to the external control information, realizing free switching between real-time data stream mode and post-injection data stream mode, thereby meeting the needs of different scenarios.

[0024] Furthermore, the digital image exchange board is designed based on the VPX standard, adopts a standard 6U size, and adopts an air-cooling and conduction-cooling compatible design. By replacing the external cold plate, air-cooling and conduction-cooling can be switched.

[0025] The proposed digital image exchange system for optical measurement equipment utilizes a digital image exchange board designed based on the VPX standard architecture, addressing the complex wiring and numerous cables required for digital image distribution. Designed using domestic components, the board employs a domestically produced FPGA chip as the core data exchange component and utilizes the VPX backplane bus instead of traditional fiber optic splitters or Camera Link cables. This reduces the number of external cables and wiring complexity while enabling efficient and reliable exchange and distribution of digital images from optical measurement equipment. The board also incorporates a domestically produced ARM chip for external network data communication and internal status monitoring. The FPGA receives external control information through the ARM chip's network interface, changing the system's current operating mode based on external control commands. This allows for flexible switching between real-time data streaming and post-injection data streaming modes to meet diverse application scenarios. Through the integrated design of the VPX architecture, high-speed data distribution capabilities, and flexible dual-mode switching, the system significantly improves system performance, stability, and a wide range of applicable scenarios. While balancing localization and cost control requirements, the system possesses outstanding technological advancement and industrial application value.

[0026] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0027] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A digital image exchange system for optical measurement equipment based on VPX architecture, characterized in that: The digital image exchange board is designed based on the VPX standard architecture, and includes: The FPGA chip, serving as the system's data interaction core, is used to receive, parse, and distribute digital image data; the oven-controlled crystal oscillator serves as the system's high-precision clock reference source; the Flash chip serves as the FPGA program storage chip; the high-speed differential crystal oscillator serves as the reference clock CLK for the system's GTX high-speed communication; the PHY chip serves as a converter for FPGA network communication; the 422 interface chip serves as an interface for interaction within the VPX system; and the ARM chip serves as an interface for external network communication. The ARM chip and the FPGA chip directly exchange data via the SPI bus, while retaining a set of IO ports as an interaction interface for INT interrupt signals. The digital image exchange board also includes an external interface, which includes a panel front interface and a VPX connector rear interface. The panel front interface includes an SFP+ optical fiber interface, an LED indicator, an RJ45 network interface, a signal monitoring interface, and a JTAG debugging interface. The VPX connector rear interface is connected to the backplane bus through three VPX standard connectors. The three VPX standard connectors are P0, P1, and P4, where P0 is a DC power supply interface and includes a group of I2C communication interfaces; P1 is a high-speed communication interface, including three groups of 10G high-speed differential interfaces; P4 is an auxiliary communication interface, including a 1000M network interface and three groups of 422 communication interfaces. The digital image exchange board receives external control information through the RJ45 network interface, and the ARM chip sends the external control information to the FPGA chip through the SPI bus. The FPGA chip changes the current working mode of the system according to the external control information, realizing free switching between the real-time data stream mode and the post-injection data stream mode.

2. The optical measurement equipment digital image exchange system based on VPX architecture according to claim 1, characterized in that: The real-time data flow mode is that the digital image output by the image sensor in real time is transmitted to the digital image exchange board via optical fiber, and the digital image exchange board processes and copies and distributes it to various processing subsystems.

3. The optical measurement equipment digital image exchange system based on VPX architecture according to claim 2, characterized in that: In real-time data stream mode, digital image data is connected to the digital image exchange board through the SFP+ optical fiber interface, and is connected to the GTX high-speed interface inside the FPGA chip in the form of a CML differential pair. The Aurora high-speed parsing protocol is used inside the FPGA chip. After the data stream is parsed by the Aurora protocol, it is converted from a high-speed serial differential signal to a Stream data stream. The Stream data stream contains valid data, a data packet end indicator bit, and 64-bit parallel data. The FPGA chip receives sensor information that needs to be attached to the digital image from the ARM chip, and superimposes the sensor information on the data stream. The high-speed digital image is framed to obtain a framed data stream. The framed data stream is packaged using the Aurora protocol and output to the outside through the GTX high-speed interface. The CML differential pair output by the FPGA chip is connected to the VPX high-speed connector in the form of a high-speed differential line, and then connected to the back-end processing board through the backplane.

4. The optical measurement equipment digital image exchange system based on VPX architecture according to claim 3, characterized in that: When performing frame extraction processing on high-speed digital images, the FPGA chip receives a synchronization signal from the outside through the 422 communication interface. Taking the rising edge of the synchronization signal as the reference moment, it sends the complete frame of digital image data stream received after the rising edge to the back end to form a data stream after frame extraction.

5. The optical measurement equipment digital image exchange system based on VPX architecture according to any one of claims 1 to 4, characterized in that: The post-injection data stream mode is to re-inject the digital image that has been recorded in the storage subsystem into the digital image exchange board, and distribute it to each processing subsystem by the digital image exchange board.

6. The optical measurement equipment digital image exchange system based on VPX architecture according to claim 5, characterized in that: In the post-injection data stream mode, the storage board connects the digital image data to the GTX high-speed interface inside the FPGA chip in the form of a CML differential pair through the VPX high-speed connector. After the data stream is parsed by the Aurora protocol, it is converted from a high-speed serial differential signal to a Stream data stream. The Stream data stream is packaged according to the Aurora protocol and output to the outside through the GTX high-speed interface. The CML differential pair output by the FPGA chip is connected to the VPX high-speed connector in the form of a high-speed differential line, and then connected to the back-end processing board through the backplane.

7. The optical measurement equipment digital image exchange system based on VPX architecture according to any one of claims 1 to 4, characterized in that: The digital image exchange board receives up to 4 channels of digital images with a bandwidth of 10Gb, connects to up to 4 storage boards at high speed, and distributes data information to up to 8 processing boards.

8. The optical measurement equipment digital image exchange system based on VPX architecture according to any one of claims 1 to 4, characterized in that: The number of the SFP+ optical fiber interface, the LED indicator light, the RJ45 network interface, the signal monitoring interface and the JTAG debugging interface are set to 4, 8, 1, 2 and 1 respectively.

9. The optical measurement equipment digital image exchange system based on VPX architecture according to any one of claims 1 to 4, characterized in that: The LED indicator light is directly driven by the IO port of the FPGA chip.

10. The optical measurement equipment digital image exchange system based on VPX architecture according to any one of claims 1 to 4, characterized in that: The FPGA chip is JFM7K325T.

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