Intelligent control multilayer circuit board

Abstract

The invention belongs to the technical field of electronic circuit integration, and particularly relates to an intelligent control multilayer circuit board. Comprising a multi-layer composite structure, and the multi-layer composite structure comprises a first signal layer, a second signal layer, a third signal layer and a fourth signal layer which are sequentially stacked from top to bottom, a first dielectric layer disposed under the first signal layer; the second signal layer is arranged below the first dielectric layer, is a copper layer with the thickness of 2 microns and is used for transmitting intermediate frequency signals; the intelligent dielectric layer is arranged below the second signal layer; the third signal layer is arranged below the intelligent dielectric layer; a second dielectric layer; a fourth signal layer disposed under the second dielectric layer; the substrate layer is arranged below the fourth signal layer, and the surface of the substrate layer is provided with a bionic cobweb supporting structure; and the dielectric constants of the multilayer circuit board are in gradient distribution along the thickness direction. According to the invention, the real-time dynamic adjustment of the dielectric property of the circuit board is realized, the electromagnetic property can be optimized according to different working frequencies or signal requirements, and the signal transmission quality in a high-frequency / high-speed scene is remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuit integration, and particularly relates to an intelligent regulation multi-layer circuit board. Background Art

[0002] The current multi-layer PCB technology faces the following three major technical bottlenecks.

[0003] 1. Static dielectric distribution: The existing regional dielectric design can only achieve planar material distribution and cannot meet the electromagnetic requirements under dynamic working conditions.

[0004] 2. Thermal-electric coupling imbalance: The thermal expansion coefficients of high-dielectric materials (such as BaTiO3) and low-dielectric materials (such as PTFE) are significantly different, resulting in interlayer cracking. For example, when the thermal stress exceeds 200 MPa, the failure rate is as high as 15%.

[0005] 3. Nanoscale out-of-control: Traditional manufacturing processes are difficult to achieve precise control of the dielectric layer with a thickness less than 100 nm, resulting in severe high-frequency signal loss. For example, the insertion loss exceeds 3 dB / cm at 10 GHz.

[0006] The above problems limit the performance of PCB in high-frequency / high-speed scenarios and urgently require innovative technologies to solve them. Summary of the Invention

[0007] The present invention aims at the defects existing in the prior art and provides an intelligent regulation multi-layer circuit board.

[0008] To achieve the above object, the present invention adopts the following technical solution. An intelligent regulation multi-layer circuit board includes a multi-layer composite structure, and the multi-layer composite structure includes, from top to bottom in sequence: A first signal layer, which is a copper layer with a thickness of 2 μm and a line width of 20 μm, and is used for high-frequency signal transmission.

[0009] A first dielectric layer, which is arranged below the first signal layer, is a fixed dielectric layer made of PTFE, with a relative dielectric constant ε_r = 3 and a thickness of 0.5 mm.

[0010] A second signal layer, which is arranged below the first dielectric layer, is a copper layer with a thickness of 2 μm and is used for medium-frequency signal transmission.

[0011] An intelligent dielectric layer, which is arranged below the second signal layer, has a thickness of 0.8 mm. The relative dielectric constant of the intelligent dielectric layer is adjusted in real time by an external regulation signal, and the adjustable range of the relative dielectric constant of the intelligent dielectric layer is ε_r = 12 to 20.

[0012] A third signal layer, which is arranged below the intelligent dielectric layer, is a copper layer with a thickness of 2 μm and is used for low-frequency signal transmission.

[0013] The second dielectric layer is disposed below the third signal layer and is a fixed dielectric layer with a relative dielectric constant ε_r = 25 and a thickness of 0.5 mm.

[0014] The fourth signal layer is disposed below the second dielectric layer and is a copper layer with a thickness of 2 μm, which is used for grounding and shielding.

[0015] The substrate layer is disposed below the fourth signal layer and is an aluminum substrate with a thickness of 1.6 mm, and its surface has a bionic spider web support structure.

[0016] Moreover, the relative dielectric constant of the multi-layer circuit board is distributed in a gradient along the thickness direction.

[0017] Furthermore, the intelligent dielectric layer adopts a nanocomposite material, and the nanocomposite material includes a matrix material and nano-additives dispersed therein.

[0018] Furthermore, it further includes a regulation system, and the regulation system includes a CMOS regulation chip and microelectrodes. Among them, the CMOS regulation chip is used to output a DC voltage of 0 - 10 V; the microelectrodes are connected to the CMOS regulation chip and are used to apply the DC voltage to the intelligent dielectric layer; among them, the intelligent dielectric layer realizes real-time adjustment of the relative dielectric constant by applying a 5V bias voltage.

[0019] Furthermore, the nano-additive is BaTiO3 nanowires wrapped with PVDF. The diameter of the nanowires is 50 nm, and the aspect ratio is 20:1; the matrix material is niobium-doped strontium titanate (Nb-SrTiO3), and its basic relative dielectric constant ε_r = 15.

[0020] Furthermore, the first signal layer, the second signal layer, the third signal layer and the fourth signal layer are electrically connected to the adjacent dielectric layer or intelligent dielectric layer through micro-holes with a diameter of 10 μm.

[0021] Furthermore, the bionic spider web support structure of the substrate layer is a micro-hole array formed by an ultraviolet laser etching process. The parameters of the ultraviolet laser etching process include: the laser wavelength is 355 nm, the power is 50 W, the pulse frequency is 50 kHz, the scanning speed is 500 mm / s, the single etching depth is 50 μm, the total etching depth is 200 μm, and nitrogen is used for protection during the etching process, and the gas flow rate is 2 L / min.

[0022] The beneficial effects of the present invention compared with the prior art.

[0023] The present invention has the ability of dynamic dielectric regulation. Through the combination of the intelligent dielectric layer (the adjustable range of the relative dielectric constant ε_r = 12 - 20) and the CMOS regulation system, the real-time dynamic adjustment of the dielectric performance of the circuit board is realized, and the electromagnetic performance can be optimized according to different working frequencies or signal requirements, significantly improving the signal transmission quality in high-frequency / high-speed scenarios.

[0024] The bionic spider web support structure of the substrate layer of the present invention significantly reduces the concentration of thermal stress, reduces the local thermal stress, and reduces the risk of interlayer cracking. The nanocomposite material of the intelligent dielectric layer (PVDF-wrapped BaTiO3 nanowires + strontium titanate niobate matrix) has a capacitance fluctuation of <2% in the range of -55°C to 200°C, ensuring the reliability and stability in a high-temperature environment.

[0025] The dielectric constant of the multi-layer circuit board of the present invention is gradient-distributed along the thickness direction (ε_r = 3 on the surface layer to ε_r = 25 on the bottom layer), effectively reducing the impedance mismatch and reflection loss between signal layers. Brief Description of the Drawings

[0026] The present invention will be further described below in conjunction with the drawings and specific embodiments. The protection scope of the present invention is not limited to the description of the following content.

[0027] Figure 1 It is a schematic diagram of the dielectric structure of the intelligent regulated multi-layer circuit board.

[0028] Figure 2 It is a schematic diagram of the intelligent dielectric layer.

[0029] Figure 3 It is a schematic diagram of the bionic spider web support structure of the substrate layer.

[0030] Figure 4a It is a comparison chart of insertion loss in performance testing.

[0031] Figure 4b It is a graph of the change of dielectric constant with voltage in performance testing.

[0032] Figure 4c It is a graph of the change of capacitance fluctuation with temperature in performance testing. Detailed Embodiments

[0033] To make the objectives, technical solutions, and beneficial effects of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention.

[0034] Core layer structure: An intelligent regulated multi-layer circuit board, including a multi-layer composite structure. The multi-layer composite structure includes, from top to bottom in sequence: a first signal layer, which is a copper layer with a thickness of 2μm, having a line width of 20μm and a pitch of 25μm, for high-frequency signal transmission; a first dielectric layer, arranged below the first signal layer, which is a fixed dielectric layer made of PTFE material, with a dielectric constant ε_r = 3 and a thickness of 0.5mm; a second signal layer, arranged below the first dielectric layer, which is a copper layer with a thickness of 2μm, for medium-frequency signal transmission; an intelligent dielectric layer, arranged below the second signal layer, with a thickness of 0.8mm. The dielectric constant of the intelligent dielectric layer is adjusted in real time by an external regulation signal, and the adjustable range of the dielectric constant of the intelligent dielectric layer is ε_r = 12 to 20; a third signal layer, arranged below the intelligent dielectric layer, which is a copper layer with a thickness of 2μm, for low-frequency signal transmission; a second dielectric layer, arranged below the third signal layer, which is a fixed dielectric layer, with a dielectric constant ε_r = 25 and a thickness of 0.5mm; a fourth signal layer, arranged below the second dielectric layer, which is a copper layer with a thickness of 2μm, for grounding and shielding; a substrate layer, arranged below the fourth signal layer, which is an aluminum substrate with a thickness of 1.6mm, having a bionic spider web support structure on its surface; and the dielectric constant of the multi-layer circuit board is distributed in a gradient along the thickness direction. As Figure 1 shown, through the gradient distribution of the dielectric constant along the Z-axis direction (ε_r gradually changing from 3 to 25) of this multi-layer composite structure, the self-adaptive optimization of the electromagnetic field is achieved.

[0035] As Figure 2 shown, introduction to the intelligent dielectric layer: 1. The intelligent dielectric layer uses a nanocomposite material, with the matrix being niobium-doped strontium titanate (Nb-SrTiO3, ε_r = 15), and BaTiO3 nanowires (diameter 50nm, aspect ratio 20:1) wrapped by dispersed PVDF.

[0036] 2. The regulation mechanism of the intelligent dielectric layer is: The CMOS regulation chip outputs a 0 - 10V DC voltage (step 0.1V, response time < 1ms), which is applied to the microelectrodes (copper, 50μm × 50μm) on both sides of the intelligent dielectric layer, driving the BaTiO3 nanowires to be aligned along the electric field direction, achieving dynamic adjustment of the dielectric constant (ε_r = 12 ~ 20).

[0037] 3. Manufacturing process: The BaTiO3 nanowires are synthesized by the solvothermal method (reaction conditions: 180°C, 12 hours). Subsequently, PVDF (concentration 10wt%) is uniformly wrapped on the surface of the nanowires by the solution coating method, with a coating thickness of about 5nm, a drying temperature of 80°C, and a time of 2 hours, ensuring the uniform dispersion of the nanowires in the matrix (standard deviation < 10%).

[0038] As Figure 3As shown below, the structure and principle of the bionic spider web support layer are as follows: The substrate layer is formed with a bionic spider web micropore array by ultraviolet laser etching. Among them, the micropore parameters are: diameter 50μm, pitch 200μm, arranged in a 60° staggered pattern, and the etching depth is 200μm. Among them, the micropore array covers the entire surface of the substrate to form a spider web structure. The simulation results show that the thermal stress is reduced from the local concentration value of 200MPa to an average of 45MPa, and the stress gradient at the micropore edge is reduced by 50%, effectively preventing interlayer cracking.

[0039] The process of the bionic spider web support layer structure is as follows: Use an ultraviolet laser with a wavelength of 355nm to etch micropores on the surface of the aluminum substrate. Specifically: Use an ultraviolet laser with a wavelength of 355nm, power 50W, pulse frequency 50kHz, scanning speed 500mm / s, single-etching depth 50μm, and reach a total depth of 200μm through 4 cycles of etching. Nitrogen protection is used during the etching process, and the gas flow rate is 2L / min to avoid oxidation and thermal damage.

[0040] Example 1, millimeter-wave radar PCB: Adopt an 8-layer composite structure with a total thickness of 3.2mm; dielectric gradient: the surface layer uses PTFE (ε_r = 3), and the bottom layer is a BaTiO3 composite material (ε_r = 25).

[0041] The manufacturing process is as follows: Step 1: Substrate pretreatment: Use laser etching on the aluminum substrate to form a bionic spider web support structure with an etching depth of 200μm.

[0042] Step 2: ALD deposition: Sequentially deposit the basic interface of the composite dielectric layer of Ta2O5 (thickness 50nm) and Al2O3 (thickness 20nm). Use a thermal ALD device (such as Oxford FlexAL). When depositing Ta2O5, the precursors are tantalum pentaethoxide (Ta(OC2H5)5) and water vapor, the temperature is 250°C, each cycle deposits 0.3nm, and a total of 167 cycles are deposited, with a total thickness of 50nm. When depositing Al2O3, the precursors are trimethylaluminum (TMA) and water vapor, the temperature is 200°C, each cycle deposits 0.3nm, and a total of 67 cycles are deposited, with a total thickness of 20nm. The vacuum is maintained at 10⁻² Torr to ensure the layer thickness uniformity (±1nm).

[0043] Step 3: Nanocomposite: Spray a PVDF solution containing 5 vol% BaTiO3 nanowires (particle size distribution D50 = 80 nm). Use an ultrasonic spraying device (such as Sono-Tek ExactaCoat) to spray a PVDF solution containing 5 vol% BaTiO3 nanowires (the solvent is DMF, concentration 10 wt%), spraying pressure 0.1 MPa, nozzle diameter 0.5 mm, spraying speed 10 cm / s, single spraying thickness 10 μm, and spray 8 times in total to 80 μm. Curing is carried out in a vacuum oven at a temperature of 120 °C for 30 minutes and a pressure of 10⁻¹ Torr to ensure complete evaporation of the solution.

[0044] Step 4: Intelligent integration: Embed a CMOS regulation chip (size 1 mm × 1 mm, power consumption less than 10 mW), and communicate with the main control system through the I2C interface.

[0045] Function of the CMOS regulation chip: Receive instructions from the main control system, output a 0 - 10 V DC voltage, and apply it to the microelectrodes on both sides of the fourth dielectric layer to achieve dynamic adjustment of the dielectric constant.

[0046] Specific implementation: A. The CMOS chip is fixed at the reserved position on the first signal layer by soldering. The CMOS chip (model such as TI DRV8833, size 1 mm × 1 mm, power consumption < 10 mW) is fixed on the reserved solder pads of the first signal layer by reflow soldering, soldering temperature 260 °C, time 10 seconds, using lead-free solder (Sn96.5Ag3Cu0.5). The chip pins are connected to the microelectrodes on the third and fifth layers through 0.1 mm diameter copper wires, and the connection uses ultrasonic soldering technology, with a soldering strength > 5 N.

[0047] B. Connect the output end of the chip to the microelectrodes on the third and fifth signal layers through copper wires.

[0048] C. The main control system sends an I2C signal to the CMOS chip, specifying the voltage value as 0 - 10 V.

[0049] D. The CMOS chip applies the voltage signal to the dielectric layer to regulate the arrangement state of the nanowires.

[0050] Performance testing is as follows: High-frequency performance: As Figure 4a shown, use a vector network analyzer (Keysight N5247B) to test the high-frequency performance, frequency range 1 - 40 GHz, the test sample is a 50 mm long straight transmission line, environmental temperature 25 °C ± 2 °C, humidity 50% ± 5%. The results show that the insertion loss is 0.8 dB / cm, while that of traditional PCBs is 3 dB / cm, and the performance is improved by about 62%.

[0051] Dynamic adjustment: As Figure 4bAs shown, the dielectric constant was measured using an LCR meter (such as Keysight E4980A). A bias voltage of 0 - 10V was applied with a step of 0.5V, the frequency was 1kHz, and the capacitance change was measured to calculate ε_r. The response time was <0.5s, and the stable adjustment range was ε_r = 15 ± 0.2 at a bias voltage of 5V.

[0052] Thermal stability: As Figure 4c shown, the capacitance change was tested in the range of -55°C to 200°C, and the fluctuation was less than 2%, which was significantly better than traditional materials. The thermal stability was tested in an environmental test chamber with a temperature range of -55°C to 200°C, a heating rate of 2°C / min, a holding time of 1 hour per temperature point, 5 cycles, 10 test samples, the average capacitance fluctuation was 1.8%, and the standard deviation was <0.3%.

[0053] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "preferred embodiments", "specific implementation manners", or "preferred implementation manners", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0054] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; thus, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope defined by the claims of the present invention.

Claims

1. An intelligent regulation multi-layer circuit board, including a multi-layer composite structure, characterized in that, The multi-layer composite structure includes, from top to bottom in sequence: The first signal layer, which is a copper layer with a thickness of 2 μm and a line width of 20 μm, and is used for high-frequency signal transmission; The first dielectric layer, which is arranged below the first signal layer, is a fixed dielectric layer made of PTFE, with a relative dielectric constant ε_r = 3 and a thickness of 0.5 mm; The second signal layer, which is arranged below the first dielectric layer, is a copper layer with a thickness of 2 μm and is used for medium-frequency signal transmission; The intelligent dielectric layer, which is arranged below the second signal layer, has a thickness of 0.8 mm. The relative dielectric constant of the intelligent dielectric layer is adjusted in real time by a regulation signal, and the adjustable range of the relative dielectric constant of the intelligent dielectric layer is ε_r = 12 to 20; The third signal layer, which is arranged below the intelligent dielectric layer, is a copper layer with a thickness of 2 μm and is used for low-frequency signal transmission; The second dielectric layer, which is arranged below the third signal layer, is a fixed dielectric layer, with a relative dielectric constant ε_r = 25 and a thickness of 0.5 mm; The fourth signal layer, which is arranged below the second dielectric layer, is a copper layer with a thickness of 2 μm and is used for grounding and shielding; The substrate layer, which is arranged below the fourth signal layer, is an aluminum substrate with a thickness of 1.6 mm, and its surface has a bionic spider web support structure; And the relative dielectric constant of the multi-layer circuit board is distributed in a gradient along the thickness direction.

2. The intelligent regulation multi-layer circuit board according to claim 1, wherein: The intelligent dielectric layer adopts a nanocomposite material, and the nanocomposite material includes a matrix material and nano-additives dispersed therein.

3. The intelligent regulation multi-layer circuit board according to claim 1, characterized in that: It also includes a regulation system, which includes a CMOS regulation chip and microelectrodes. Among them, the CMOS regulation chip is used to output a DC voltage of 0 - 10 V; the microelectrodes are connected to the CMOS regulation chip and are used to apply the DC voltage to the intelligent dielectric layer; among them, the intelligent dielectric layer realizes real-time adjustment of the relative dielectric constant by applying a 5 V bias voltage.

4. The intelligent regulation multi-layer circuit board according to claim 2, wherein: The nano-additive is BaTiO3 nanowires wrapped by PVDF. The diameter of the nanowires is 50 nm, and the aspect ratio is 20:1; the matrix material is strontium titanate doped with niobium, and its basic relative dielectric constant ε_r = 15.

5. The intelligent regulation multi-layer circuit board according to claim 1, wherein: The first signal layer, the second signal layer, the third signal layer and the fourth signal layer are electrically connected to the adjacent dielectric layer or the intelligent dielectric layer through micro-holes, and the diameter of the micro-holes is 10 μm.

6. The intelligent regulation multi-layer circuit board according to claim 1, wherein: The bionic spider web support structure of the substrate layer is a micro-hole array formed by an ultraviolet laser etching process. The parameters of the ultraviolet laser etching process include: the laser wavelength is 355 nm, the power is 50 W, the pulse frequency is 50 kHz, the scanning speed is 500 mm / s, the single etching depth is 50 μm, the total etching depth is 200 μm, and nitrogen is used for protection during the etching process, and the gas flow rate is 2 L / min.

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