Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment. The semiconductor device comprises a substrate and at least one transistor arranged on the substrate, the transistor comprises a gate electrode and a semiconductor layer; the semiconductor layer comprises a first semiconductor sub-layer and a second semiconductor sub-layer, the first semiconductor sub-layer at least partially surrounds the gate electrode, the second semiconductor sub-layer is arranged on the side, away from the gate electrode, of the first semiconductor sub-layer, and the doping concentration of the second semiconductor sub-layer is larger than that of the first semiconductor sub-layer; the second semiconductor sub-layer comprises a first part and a second part which are arranged on the surface, away from the gate electrode, of the first semiconductor sub-layer in a spaced mode. According to the scheme provided by the embodiment of the invention, the high-doping-concentration sub-layer is arranged on the outer side wall of the low-doping-concentration sub-layer, so that the low-doping-concentration sub-layer and the high-doping-concentration sub-layer can be conveniently formed respectively, additional doping operation is avoided, and the process is simplified.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present application provides a semiconductor device that can simplify the process.

[0006] The present application provides a semiconductor device, comprising:

[0007] a substrate, and at least one transistor disposed on the substrate;

[0008] The transistor includes a gate electrode and a semiconductor layer; the semiconductor layer includes a first semiconductor sublayer that at least partially surrounds the gate electrode and a second semiconductor sublayer that is arranged on a side of the first semiconductor sublayer away from the gate electrode, the doping concentration of the second semiconductor sublayer is greater than the doping concentration of the first semiconductor sublayer, and the second semiconductor sublayer includes a first part and a second part that are spaced apart on a surface of the first semiconductor sublayer away from the gate electrode.

[0009] In some embodiments, along a direction perpendicular to the substrate, gate electrodes of a plurality of transistors are interconnected to form a word line perpendicular to the substrate, and semiconductor layers of the plurality of transistors are spaced apart.

[0010] In some embodiments, the second semiconductor sublayer extends in a direction parallel to the substrate.

[0011] In some embodiments, the first portion and the second portion are spaced apart along a first direction, the first portion extends along a second direction, the second portion extends along the second direction, and the first direction and the second direction intersect and are both parallel to the substrate.

[0012] In some embodiments, the transistor includes only one gate electrode; along a plane parallel to the substrate, the cross-section of the first semiconductor sub-layer is a closed loop.

[0013] In some embodiments, the transistor includes a first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode are spaced apart along the second direction, the first gate electrodes of the plurality of transistors are connected to each other to form an integral structure extending along a direction perpendicular to the substrate, the second gate electrodes of the plurality of transistors are connected to each other to form an integral structure extending along a direction perpendicular to the substrate, the first semiconductor sub-layer partially surrounds the first gate electrode, and the first semiconductor sub-layer partially surrounds the second gate electrode.

[0014] In some embodiments, the semiconductor device further includes:

[0015] Insulating layers and conductive layers alternately distributed along a direction perpendicular to the substrate; a first hole penetrating through the insulating layer and the conductive layer; the conductive layer includes a first electrode and a second electrode of the transistor, the first electrode is connected to the first portion, and the second electrode is connected to the second portion.

[0016] In some embodiments, the first hole includes a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, and the orthographic projection of the first sub-hole on the substrate falls within the orthographic projection of the second sub-hole on the substrate.

[0017] In some embodiments, the semiconductor device further includes:

[0018] Insulating layers and conductive layers alternately distributed along a direction perpendicular to the substrate; a third hole and a fourth hole penetrating through the insulating layer and the conductive layer; the third hole and the fourth hole communicate with each other in the conductive layer.

[0019] In some embodiments, the first semiconductor sub-layer, a first gate insulating layer, and the first gate electrode are sequentially distributed from outside to inside in the third hole;

[0020] The first semiconductor sub-layer, a second gate insulating layer, and the second gate electrode are sequentially distributed from outside to inside in the fourth hole.

[0021] In some embodiments, the third hole includes a fifth sub-hole located in the insulating layer and a sixth sub-hole located in the conductive layer, and the orthographic projection of the fifth sub-hole on the substrate falls within the orthographic projection of the sixth sub-hole on the substrate;

[0022] The fourth hole includes a seventh sub-hole located in the insulating layer and the sixth sub-hole located in the conductive layer, and the orthographic projection of the seventh sub-hole on the substrate falls within the orthographic projection of the sixth sub-hole on the substrate.

[0023] In some embodiments, the semiconductor device further includes: a multi-layer memory cell array distributed in a direction perpendicular to the substrate, each layer of the memory cell array including a plurality of rows and columns of memory cells distributed in a first direction and a second direction respectively, the memory cells including the transistors, and the second electrodes of the transistors in the same column distributed in the second direction in the same layer being interconnected to form a bit line extending in the second direction.

[0024] In some embodiments, the second portions of the transistors in the same column distributed in the second direction in the same layer are interconnected to form an integral structure, and the first portions of the transistors in the same column distributed in the second direction in the same layer are separated from each other.

[0025] In some embodiments, the semiconductor device further includes:

[0026] a second hole penetrating through the insulating layer and the conductive layer; the second hole includes a third sub-hole located in the insulating layer and a fourth sub-hole located in the conductive layer, and the fourth sub-hole has a groove extending in a horizontal direction with respect to the third sub-hole.

[0027] In some embodiments, the semiconductor device further includes: a plurality of capacitors, the capacitors including a first capacitor electrode and a second capacitor electrode, and the first electrode is multiplexed with the first capacitor electrode.

[0028] In some embodiments, the second capacitor electrode includes a first sub-electrode; in the second hole, the first capacitor electrode surrounding the first sub-electrode, a first dielectric layer surrounding the first sub-electrode, and the first sub-electrode are sequentially distributed from outside to inside.

[0029] In some embodiments, the first capacitor electrode is distributed on the inner wall of the groove, and the first sub-electrode extends in a direction perpendicular to the substrate and has an extension extending into the groove.

[0030] In some embodiments, the second capacitor electrode further includes a second sub-electrode;

[0031] The second sub-electrode is distributed on the side of the first capacitor electrode facing away from the substrate, the side facing the substrate, and the side facing away from the second semiconductor sub-layer, and a second dielectric layer is provided between the second sub-electrode and the first capacitor electrode.

[0032] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including:

[0033] providing a substrate, and forming a stacked structure including alternately arranged semiconductor structure layers and sacrificial layers on the substrate;

[0034] Pattern the stacked structure to form first trenches penetrating through the layers, the first trenches extending in a first direction; a transistor region is included between adjacent first trenches spaced apart in a second direction; the first direction and the second direction intersect and are parallel to the substrate;

[0035] Form holes in the transistor region that penetrate the stacked structure in a direction perpendicular to the substrate, etch away the sacrificial layer through the holes, and replace the sacrificial layer with an insulating layer; etch the semiconductor structure layer in a direction parallel to the substrate based on the holes to form a second semiconductor sublayer, the second semiconductor sublayer including a first part and a second part that are disconnected from each other; form a plurality of gate electrodes arranged in a direction perpendicular to the substrate and a plurality of first semiconductor sublayers surrounding the gate electrodes in the holes, the plurality of gate electrodes being connected to form an integral structure, and the plurality of first semiconductor sublayers being separated from each other.

[0036] In some embodiments, the forming holes in the transistor region that penetrate the stacked structure in a direction perpendicular to the substrate includes: forming a third hole and a fourth hole in the same transistor region that penetrate the stacked structure in a direction perpendicular to the substrate;

[0037] The etching the semiconductor structure layer in a direction parallel to the substrate based on the holes includes:

[0038] Etch the semiconductor structure layer in a direction parallel to the substrate in the third hole such that the orthographic projection of the sub-hole of the third hole in the insulating layer on the substrate falls within the orthographic projection of the sub-hole of the semiconductor structure layer on the substrate; laterally etch the semiconductor structure layer in the fourth hole such that the orthographic projection of the sub-hole of the fourth hole in the insulating layer on the substrate falls within the orthographic projection of the sub-hole of the semiconductor structure layer on the substrate, and the sub-holes of the third hole and the fourth hole in the semiconductor structure layer communicate;

[0039] The forming a plurality of gate electrodes arranged in a direction perpendicular to the substrate and a plurality of first semiconductor sublayers surrounding the gate electrodes in the holes includes:

[0040] Form a plurality of first gate electrodes extending in a direction perpendicular to the substrate in the third hole, form a plurality of second gate electrodes extending in a direction perpendicular to the substrate in the fourth hole, and form the first semiconductor sublayer in the sub-holes of the third hole and the fourth hole in the semiconductor structure layer.

[0041] In some embodiments, the forming a plurality of first semiconductor sublayers surrounding the gate electrodes in the holes includes: forming a plurality of first semiconductor sublayers surrounding the gate electrodes by epitaxial growth in the holes.

[0042] An embodiment of the present disclosure provides an electronic device, including the semiconductor device described in any of the above embodiments.

[0043] This application includes a semiconductor device, a manufacturing method thereof, and an electronic device. The semiconductor device includes: a substrate, and at least one transistor disposed on the substrate; the transistor includes a gate electrode and a semiconductor layer; the semiconductor layer includes a first semiconductor sub-layer at least partially surrounding the gate electrode and a second semiconductor sub-layer disposed on a side of the first semiconductor sub-layer away from the gate electrode. The doping concentration of the second semiconductor sub-layer is greater than that of the first semiconductor sub-layer. The second semiconductor sub-layer includes a first portion and a second portion spaced apart on a surface of the first semiconductor sub-layer away from the gate electrode. The solution provided by the embodiment of this application arranges the sub-layer with a high doping concentration on the outer sidewall of the sub-layer with a low doping concentration, which facilitates the formation of the sub-layer with a low doping concentration and the sub-layer with a high doping concentration respectively in advance, avoiding additional and relatively complex doping operations during the manufacturing process of the semiconductor device and simplifying the process.

[0044] Other features and advantages of this application will be described in the subsequent specification, and part of them will become obvious from the specification, or will be understood by implementing this application. Other advantages of this application can be realized and obtained through the solutions described in the specification and the drawings.

[0045] Other aspects can be understood after reading and understanding the drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The drawings are used to provide an understanding of the technical solutions of this application, and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application, and do not constitute a limitation to the technical solutions of this application.

[0047] Figure 1A A top view of a semiconductor device provided for some embodiments, Figure 1B is a cross-sectional view perpendicular to the substrate along the Figure 1A AA' direction in; Figure 1C is a cross-sectional view parallel to the substrate along the Figure 1B DD' direction in;

[0048] Figure 2A A top view of a formed stacked structure provided for some embodiments, Figure 2B is a cross-sectional view perpendicular to the substrate along the Figure 2A AA' direction in;

[0049] Figure 3A A top view of a formed first trench and a first insulating layer provided for some embodiments, Figure 3B is a cross-sectional view perpendicular to the substrate along the Figure 3ACross-sectional view perpendicular to the substrate in the CC' direction;

[0050] Figure 4A Top view after forming the first hole for some embodiments, Figure 4B For along Figure 4A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0051] Figure 5A Top view after forming the second insulating layer for some embodiments, Figure 5B For along Figure 5A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0052] Fig. 6A Top view after exposing the first hole for some embodiments, Figure 6B For along Fig. 6A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0053] Fig. 7A Top view after forming the first groove for some embodiments, Figure 7B For along Fig. 7A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0054] Fig. 8A Top view after forming the first semiconductor structure layer for some embodiments, Figure 8B For along Fig. 8A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0055] Fig.9A Top view after forming the word line and the gate insulating layer for some embodiments, Fig. 9B For along Fig.9A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0056] Fig. 10A Top view after forming the second trench for some embodiments, Fig. 10B For along Fig. 10A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0057] Fig.11A Top view after forming the second groove for some embodiments, Fig. 11B For along Fig.11A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0058] Fig. 12A Top view after forming the bit line layer for some embodiments, Fig. 12B For along Fig. 12A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0059] Fig.13A Top view after forming bit lines and a third insulating layer for some embodiments Fig. 13B For the direction along Fig.13A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0060] Fig.14A Top view after forming a second hole for some embodiments Fig. 14B For the direction along Fig.14A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0061] Fig.15A Top view after forming a third groove for some embodiments Fig. 15B For the direction along Fig.15A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0062] Fig.16A Top view after forming a first electrode layer and a fourth insulating layer for some embodiments Fig. 16B For the direction along Fig.16A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0063] Fig.17A Top view after forming a first electrode for some embodiments Fig. 17B For the direction along Fig.17A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0064] Fig.18A Top view after forming a first sub-electrode and a first dielectric layer for some embodiments Fig.18B For the direction along Fig.18A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0065] Fig.19A Top view after forming a word line and a gate insulating layer for some embodiments Fig.19B For the direction along Fig.19A Cross-sectional view perpendicular to the substrate in the AA' direction in

[0066] Fig. 20A Top view of a semiconductor device for some exemplary embodiments Fig. 20B For the direction along Fig. 20A Cross-sectional view perpendicular to the substrate in the A1A1' direction in Fig. 20C For the direction along Fig. 20A Cross-sectional view perpendicular to the substrate in the BB' direction, Fig.20D For the direction along Fig. 20C Cross-sectional view parallel to the substrate in the DD' direction;

[0067] Fig.21A Top view after forming a third hole and a fourth hole for some embodiments Fig. 21Bis a cross-sectional view perpendicular to the substrate along the Fig.21A direction A1A1’ in

[0068] Fig.22A is a top view after forming the second insulating layer provided for some embodiments, Fig. 22B is a cross-sectional view perpendicular to the substrate along the Fig.22A direction A1A1’ in

[0069] Fig.23A is a top view after exposing the third hole and the fourth hole provided for some embodiments, Fig. 23B is a cross-sectional view perpendicular to the substrate along the Fig.23A direction A1A1’ in

[0070] Fig.24A is a top view after forming the fourth groove provided for some embodiments, Fig. 24B is a cross-sectional view perpendicular to the substrate along the Fig.24A direction A1A1’ in

[0071] Fig.25A is a top view after forming the first semiconductor structure layer provided for some embodiments, Fig.25B is a cross-sectional view perpendicular to the substrate along the Fig.25A direction A1A1’ in

[0072] Fig.26A is a top view after forming the first word line, the first gate insulating layer, the second word line and the second gate insulating layer provided for some embodiments, Fig.26B is a cross-sectional view perpendicular to the substrate along the Fig.26A direction A1A1’ in

[0073] Fig.27A is a top view after forming the second trench provided for some embodiments, Fig.27B is a cross-sectional view perpendicular to the substrate along the Fig.27A direction A1A1’ in

[0074] Fig.28A is a top view after forming the second groove provided for some embodiments, Fig.28B is a cross-sectional view perpendicular to the substrate along the Fig.28A direction A1A1’ in

[0075] Fig.29A is a top view after forming the bit line layer provided for some embodiments, Fig.29B is a cross-sectional view perpendicular to the substrate along the Fig.29A direction A1A1’ in

[0076] Fig. 30A is a top view after forming the bit line and the third insulating layer provided for some embodiments, Fig. 30B is a cross-sectional view perpendicular to the substrate along the Fig. 30A Cross-sectional view perpendicular to the substrate in the A1A1' direction;

[0077] Fig.31A Top view after forming the second hole for some embodiments, Fig.31B Along Fig.31A Cross-sectional view perpendicular to the substrate in the A1A1' direction, Fig.31C Along Fig.31A Cross-sectional view perpendicular to the substrate in the BB' direction;

[0078] Fig.32A Top view after forming the third groove for some embodiments, Fig.32B Along Fig.32A Cross-sectional view perpendicular to the substrate in the A1A1' direction, Fig.32C Along Fig.32A Cross-sectional view perpendicular to the substrate in the BB' direction;

[0079] Fig.33A Top view after forming the first electrode layer and the fourth insulating layer for some embodiments, Fig.33B Along Fig.33A Cross-sectional view perpendicular to the substrate in the A1A1' direction, Fig.33C Along Fig.33A Cross-sectional view perpendicular to the substrate in the BB' direction;

[0080] Fig.34A Top view after forming the first electrode for some embodiments, Fig.34B Along Fig.34A Cross-sectional view perpendicular to the substrate in the A1A1' direction, Fig.34C Along Fig.34A Cross-sectional view perpendicular to the substrate in the BB' direction;

[0081] Fig.35A Top view after forming the first sub-electrode and the first dielectric layer for some embodiments, Fig.35B Along Fig.35A Cross-sectional view perpendicular to the substrate in the A1A1' direction, Fig.35C Along Fig.35A Cross-sectional view perpendicular to the substrate in the BB' direction;

[0082] Fig.36A Top view after forming the third trench for some embodiments, Fig.36B Along Fig.36A Cross-sectional view perpendicular to the substrate in the A1A1' direction, Fig.36C Along Fig.36A Cross-sectional view perpendicular to the substrate in the BB' direction, Fig.36D Along Fig.36B Cross-sectional view parallel to the substrate in the DD' direction. Detailed implementation manners

[0083] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Without conflict, the embodiments of the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0084] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should have the ordinary meanings understood by those of ordinary skill in the field to which the present disclosure belongs.

[0085] The embodiments of the present disclosure do not necessarily limit the sizes shown in the accompanying drawings, and the shapes and sizes of the components in the drawings do not reflect the actual proportions. In addition, the accompanying drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the accompanying drawings.

[0086] The ordinal numbers such as "first", "second", "third", etc. in the present disclosure are set to avoid confusion of the components and do not represent any order, quantity or importance.

[0087] In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle part", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of the components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the components is appropriately changed according to the directions describing the components. Therefore, it is not limited to the terms described in the disclosure and can be appropriately replaced according to the situation.

[0088] In the present disclosure, unless otherwise clearly defined and limited, the terms "mount", "connect", and "couple" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific situations.

[0089] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region or drain electrode) and the source electrode (source electrode terminal, source region or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to the region where current mainly flows.

[0090] In the present disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. In cases where transistors with opposite polarities are used or the direction of current flow changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" may sometimes be swapped. Therefore, in the present disclosure, the "source electrode" and "drain electrode" may be swapped with each other.

[0091] In the present disclosure, "connection" includes cases where components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0092] In the present disclosure, "parallel" means approximately parallel or almost parallel. For example, a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular. For example, a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0093] "A and B are of an integrated structure" in the embodiments of the present disclosure may mean that there is no obvious boundary interface such as a fault or gap in the microscopic structure. Generally, a connected film layer patterned on one film layer is of an integrated structure. For example, A and B are made of the same material to form one film layer and are simultaneously formed with a connected structure through the same patterning process.

[0094] In the embodiments of the present disclosure, "the positive projection of B is within the range of the positive projection of A" means that the boundary of the positive projection of B falls within the boundary of the positive projection of A, or the boundary of the positive projection of A overlaps with the boundary of the positive projection of B.

[0095] Figure 1A A top view of a semiconductor device provided for some embodiments, Figure 1B is a cross-sectional view perpendicular to the substrate 1 along the Figure 1A AA' direction; Figure 1C is a cross-sectional view parallel to the substrate 1 along the Figure 1B DD' direction. As shown in Figure 1A , Figure 1B and Figure 1C illustrate, the embodiments of the present disclosure provide a semiconductor device including a multi-layer memory cell array vertically stacked on the substrate 1, and the multi-layer memory cell array may be distributed along the third direction Z. The third direction Z may be perpendicular to the substrate 1.

[0096] The memory cell array may include a plurality of bit lines 30, a plurality of word lines 40, and a plurality of memory cells. Each of the memory cell arrays may include a plurality of memory cells arrayed in a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y may intersect. As Figure 1C shown, the bit lines 30 may be conductive lines extending along the second direction Y parallel to the substrate 1. The plurality of bit lines 30 in the same memory cell array may be spaced apart from each other, and the plurality of bit lines 30 in the same memory cell array may be spaced apart and distributed along the first direction X. The bit lines 30 of different memory cell arrays may be stacked on the substrate 1, and the bit lines 30 at the same position in different layers are spaced apart from each other.

[0097] The word lines 40 may extend along a third direction Z. A plurality of memory cells stacked vertically at the same position in different layers share one of the word lines 40; different memory cells in the same layer correspond to different word lines 40.

[0098] The memory cell may be a 1T or 2T memory cell or other multi-transistor memory cells.

[0099] Taking the 1T1C memory cell as an example, the memory cell may include a transistor and a capacitor connected to the transistor. The transistor and the capacitor of the same memory cell may be distributed along the first direction X. The transistor may include a gate electrode 26, a first electrode 51, and a second electrode 52. The gate electrode 26 may be a part of the word line 40, and the gate electrodes 26 of the transistors at the same position in different layers may be a part of the same word line 40.

[0100] The second electrode 52 may be connected to the bit line 30, or the second electrode 52 may be a part of the bit line 30. The second electrodes 52 of the transistors of the memory cells in the same column of the same memory cell array may be connected to the same bit line 30. That is, the second electrodes 52 of the transistors in the same column distributed along the second direction Y are connected to form a bit line 30 extending along the second direction Y. The second electrodes 52 of the transistors of the memory cells in adjacent columns of the same memory cell array may be connected to different bit lines 30.

[0101] The capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42. The first electrode 51 may be connected to the first capacitor electrode 41 of the capacitor. For example, the first electrode 51 and the first capacitor electrode 41 are multiplexed.

[0102] Hereinafter, a semiconductor device including a plurality of vertically stacked transistors at the same position will be taken as an example for description, and the memory cell is taken as an example of 1T1C for description.

[0103] As Figures 1A to 1CAs shown, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising:

[0104] A substrate 1, and at least one transistor disposed on the substrate 1;

[0105] The transistor may include a gate electrode 26 and a semiconductor layer 23, wherein the gate electrode 26 may extend in a direction perpendicular to the substrate 1; the semiconductor layer 23 may include a first semiconductor sublayer 231 at least partially surrounding the gate electrode 26 and a second semiconductor sublayer 232 disposed on a side of the first semiconductor sublayer 231 away from the gate electrode 26, wherein the doping concentration of the second semiconductor sublayer 232 is greater than the doping concentration of the first semiconductor sublayer 231, and the second semiconductor sublayer 232 may include a first portion 2321 and a second portion 2322 spaced apart from each other on a surface of the first semiconductor sublayer 231 away from the gate electrode;

[0106] In some embodiments, the semiconductor device may include a plurality of transistors, which are distributed in different layers and stacked in a direction perpendicular to the substrate 1. In the direction perpendicular to the substrate 1, a plurality of gate electrodes 26 of the plurality of transistors are interconnected to form a word line 40 perpendicular to the substrate 1, and a plurality of semiconductor layers 23 of the plurality of transistors are arranged at intervals. In the above scheme, the sublayer with high doping concentration is arranged on the outer side wall of the sublayer with low doping concentration, which facilitates the formation of the sublayer with low doping concentration and the sublayer with high doping concentration in advance, avoids additional and more complicated doping operations in the process of manufacturing the semiconductor device, and simplifies the process.

[0107] Among them, the second semiconductor sublayer 232 can be a heavily doped semiconductor film layer, and the first semiconductor sublayer 231 can be a lightly doped or undoped semiconductor film layer, so that the first semiconductor sublayer 231 can be used as the channel region of the transistor, and the two parts of the second semiconductor sublayer 232 can be used as the source contact region and drain contact region of the transistor, respectively contacting the source electrode and the drain electrode.

[0108] The gate electrodes 26 of multiple transistors in different layers can be connected to form an integrated structure extending in a direction perpendicular to the substrate 1, and the integrated structure is the word line 40. Before and after the word line 40 is formed, there is no need to separately make the gate electrode 26. After the word line 40 is made, a part of the word line 40 plays the role of the gate electrode 26.

[0109] In some embodiments, the size and shape of the cross section of the word line 40 at different positions parallel to the substrate 1 may be substantially the same. However, the present disclosure is not limited thereto, and the word line 40 may extend only in a direction perpendicular to the substrate 1 as a whole, but the morphology of the sidewall of the word line 40 is not specifically limited.

[0110] In some embodiments, the first semiconductor sub-layer 231 surrounding the gate electrode 26 may partially or entirely surround the gate electrode 26. That is, in a plane parallel to the substrate 1, the cross-section of the first semiconductor sub-layer 231 may be an open loop or a closed loop. Figure 1C The cross-section of the first semiconductor sub-layer 231 shown in Figure 1C is a closed loop, and at this time, the transistor is a double-channel transistor. However, the embodiments of the present disclosure are not limited thereto. The cross-section of the first semiconductor sub-layer 231 in a plane parallel to the substrate 1 may be an open loop, and at this time, the transistor is a single-channel transistor.

[0111] In some embodiments, the second semiconductor sub-layer 232 may extend along a second direction Y parallel to the substrate 1. This solution facilitates obtaining the second semiconductor sub-layer 232 by stacking semiconductor film layers with high doping concentrations and etching the semiconductor film layers, without doping different layers of semiconductor layers.

[0112] In some embodiments, the height of the first portion 2321 of the second semiconductor sub-layer 232 in a direction perpendicular to the substrate 1 may be the same as or substantially the same as the height of the second portion 2322 of the second semiconductor sub-layer 232 in a direction perpendicular to the substrate 1.

[0113] In some embodiments, the first portion 2321 and the second portion 2322 of the second semiconductor sub-layer 232 may be spaced apart along a first direction X parallel to the substrate 1. The first portion 2321 may extend along the second direction Y, the second portion 2322 may extend along the second direction Y, the first direction X and the second direction Y may intersect, and the second direction Y is parallel to the substrate. In some embodiments, the first direction X and the second direction Y may be perpendicular.

[0114] In some embodiments, as Figure 1C shown, the second portions 2322 of the second semiconductor sub-layers 232 of the transistors in the same column distributed along the second direction Y in the same layer may be connected to form an integral structure. This integral structure may extend along the second direction Y. However, the embodiments of the present disclosure are not limited thereto. The second portions 2322 of the second semiconductor sub-layers 232 of the transistors in the same column distributed along the second direction Y in the same layer may be separated from each other.

[0115] In some embodiments, as Figure 1C shown, the first portions 2321 of the second semiconductor sub-layers 232 of the transistors in the same column distributed along the second direction Y in the same layer may be separated from each other.

[0116] In some embodiments, the bit line 30 may be a strip-shaped electrode parallel to the substrate 1. A part of the strip-shaped electrode may be the second electrode 52 of the transistor. The side wall of the strip-shaped electrode is connected to the second part 2322 of the second semiconductor sub-layer 232. Alternatively, the bit line 30 may have an integrally designed branch, and the branch is connected to the second part 2322 of the second semiconductor sub-layer 232. Wherein, the extending direction of the branch intersects with the extending direction of the bit line 30, such as being approximately perpendicular, and the branch may be the second electrode 52 of the transistor.

[0117] The branch may be a plurality of branches on one side wall of the bit line 30, and each branch is correspondingly connected to the second part 2322 of the second semiconductor sub-layer 232 of one transistor.

[0118] In some embodiments, the transistor may further include a gate insulating layer 24 disposed between the semiconductor layer 23 and the gate electrode 26. The gate insulating layer 24 surrounds the gate electrode 26, and the first semiconductor sub-layer 231 surrounds the gate insulating layer 24. The gate insulating layer 24 isolates the semiconductor layer 23 and the gate electrode 26. The gate insulating layers 24 of multiple transistors at the same position in different layers may be connected to form an integral structure. The solution provided in this embodiment can form the gate insulating layers 24 of multiple transistors at one time, which can simplify the process. However, the embodiments of the present disclosure are not limited thereto. The gate insulating layers 24 of multiple transistors at the same position in different layers may be arranged at intervals, for example, physically disconnected.

[0119] In some embodiments, the first semiconductor sub-layer 231, the gate insulating layer 24, and the gate electrode 26 may be disposed in a hole. That is, the semiconductor device may further include: insulating layers and conductive layers alternately distributed along the direction perpendicular to the substrate 1; a first hole K1 penetrating through the insulating layers and the conductive layers; the conductive layer includes the first electrode 51 and the second electrode 52 of the transistor, the first electrode 51 is connected to the first part 2321, and the second electrode 52 is connected to the second part 2322;

[0120] In the first hole K1, the first semiconductor sub-layer 231, the gate insulating layer 24 surrounding the gate electrode 26, and the gate electrode 26 are distributed in sequence from the outside to the inside. The gate electrodes 26 of multiple transistors at the same position in different layers fill the first hole K1.

[0121] In some embodiments, the shape of the orthographic projection of the first hole K1 on the substrate 1 may be square, but the embodiments of the present disclosure are not limited thereto. The shape of the orthographic projection of the first hole K1 on the substrate 1 may be other shapes, such as circular, etc.

[0122] In some embodiments, the first hole K1 may include a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, and the orthographic projection of the first sub-hole on the substrate 1 falls within the orthographic projection of the second sub-hole on the substrate 1. In the solution provided in this embodiment, by setting the first hole and the second hole of different aperture sizes, etching can be performed in the hole to disconnect the first semiconductor layer 231 of transistors of different layers. However, the embodiments of the present disclosure are not limited thereto, and the orthographic projection of the second sub-hole on the substrate 1 may fall within the orthographic projection of the first sub-hole on the substrate 1, so that the first semiconductor layer 231 of transistors of different layers can be etched outside the hole to disconnect.

[0123] In some embodiments, when the orthographic projection of the first sub-hole on the substrate 1 falls within the orthographic projection of the second sub-hole on the substrate 1, the second sub-hole has a groove relative to the first sub-hole along a direction parallel to the substrate 1, and the first semiconductor sub-layer 231 may be disposed in the groove, and the first semiconductor sub-layer 231 may fill the groove. However, the embodiments of the present disclosure are not limited thereto, and the first semiconductor 231 may not completely fill the groove, for example, the first semiconductor sub-layer 231 may cover the inner wall of the groove, and the gate insulating layer 24 and the gate electrode 26 may extend into the groove.

[0124] In some embodiments, the first electrode 51 is connected to the first portion 2321 and is disposed on a side of the first portion 2321 away from the gate electrode 26. The first electrode 51 may have a variety of shapes. For example, the conductive layer may be formed with a groove with an opening away from the gate electrode 26, and the first electrode 51 may cover the inner wall of the groove.

[0125] For another example, the first electrode 51 and the first capacitor electrode 41 can be reused, that is, the two have the same structure. In order to increase the capacitance of the capacitor and increase the area of ​​the first capacitor electrode 41, a second hole K2 penetrating the conductive layer and the insulating layer can be provided, and the first capacitor electrode 41 can be provided on the inner wall of the second hole K2. Figure 1A , Figure 1B and Figure 1C As shown, the semiconductor device may further include:

[0126] a second hole K2 penetrating the insulating layer and the conductive layer; the second hole K2 comprises a third sub-hole located in the insulating layer and a fourth sub-hole located in the conductive layer, the fourth sub-hole having a groove extending in a horizontal direction relative to the third sub-hole;

[0127] In some embodiments, the semiconductor device may further include: a plurality of capacitors, the capacitors including a first capacitor electrode 41 and a second capacitor electrode 42 , and the first electrode 51 and the first capacitor electrode 41 are reused.

[0128] In some embodiments, the second capacitive electrode 42 may include a first sub - electrode 421;

[0129] In the second via K2, from the outside to the inside, there are distributed in sequence the first capacitive electrode 41 surrounding the first sub - electrode 421, a first dielectric layer 431 surrounding the first sub - electrode 421, and the first sub - electrode 421;

[0130] In some embodiments, the first capacitive electrode 41 is distributed on the inner wall of the groove and does not completely fill the groove, and the first sub - electrode 421 extends in a direction perpendicular to the substrate 1 and has an extending portion extending into the groove.

[0131] Among them, the first electrodes 51 of the transistors at the same position in different layers are arranged at intervals.

[0132] In some embodiments, the second capacitive electrode may further include a second sub - electrode 422. The second sub - electrode 422 may be distributed on the side of the first capacitive electrode 41 facing away from the substrate 1, on the side facing the substrate 1, and on the side facing away from the second semiconductor sub - layer 232. A second dielectric layer 432 is provided between the second sub - electrode 422 and the first capacitive electrode 41. The first dielectric layer 431 and the second dielectric layer 432 together form the dielectric layer 43 of the capacitor. The solution provided in this embodiment sets electrodes both inside and outside the first capacitive electrode 41 as the second capacitive electrode 42, which can increase the plate area of the capacitor as much as possible, increase the capacitance value, and the planar size occupied by the capacitor remains basically unchanged. The first sub - electrode 421 and the second sub - electrode 422 may be connected on the side of the plurality of memory arrays away from the substrate 1.

[0133] In some embodiments, the first sub - electrodes 421 of the capacitors connected to the transistors in different layers may be connected to form an integral structure.

[0134] In some embodiments, the second sub - electrodes 422 of the capacitors connected to the transistors in different layers may be connected to form an integral structure.

[0135] In some embodiments, every two columns of memory cells may be taken as a group, and the second sub - electrodes 422 of the capacitors connected to the transistors in the same group may be connected to form an integral structure. That is, the second sub - electrodes 422 of the capacitors connected to the transistors in adjacent columns (two columns in the same group) of the same layer are connected to form an integral structure.

[0136] The technical solution of this embodiment will be further described below through the manufacturing process of the semiconductor device in this embodiment. The "lithography process" mentioned in this embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist, which are mature manufacturing processes in the related art. The "lithography process" mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, coating can use known coating processes, and etching can use known methods, which will not be specifically limited here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a lithography process or a lithography process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" still requires a lithography process or a lithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the lithography process contains at least one "pattern".

[0137] In some embodiments, the manufacturing process of the semiconductor device may include:

[0138] 101) Forming a stacked structure;

[0139] The forming of the stacked structure may include: providing a substrate 1, and alternately depositing a first semiconductor thin film and a sacrificial layer thin film on the substrate 1 to form a stacked structure including a plurality of alternately arranged second semiconductor structure layers 232a and sacrificial layers 10;

[0140] Depositing a hard mask thin film to form a hard mask layer 9. At this time, the stacked structure includes a plurality of alternately arranged second semiconductor structure layers 232a and sacrificial layers 10, and a hard mask layer 9 disposed on the side of the topmost sacrificial layer 10 away from the substrate 1, and the hard mask layer 9 covers the sacrificial layer 10, as Figure 2A and Figure 2B shown. Figure 2A A top view of the stacked structure formed for some embodiments is provided, Figure 2B is along Figure 2A The cross-sectional view perpendicular to the substrate 1 in the AA' direction. The AA' direction may be parallel to the first direction X.

[0141] In some embodiments, the substrate 1 may be a conventional silicon substrate or other bulk substrates including semiconductor material layers.

[0142] In some embodiments, the first semiconductor thin film may be a heavily doped semiconductor film layer, and subsequently the second semiconductor structure layer 232a may form a second semiconductor sublayer 232.

[0143] In some embodiments, the sacrificial layer film may be a semiconductor material, such as SiGe, etc. Using a semiconductor material here facilitates the epitaxial growth of the first semiconductor film. Subsequently, the sacrificial layer film will be replaced with an insulating film.

[0144] In some embodiments, the hard mask layer 9 includes, but is not limited to, at least one of the following: carbon, polysilicon, silicon oxide, etc.

[0145] Figure 2B The stacked structure shown in includes three second semiconductor structure layers 232a and three sacrificial layers 10, only as an example. In other embodiments, the stacked structure may include more or fewer alternately arranged second semiconductor structure layers 232a and sacrificial layers 10.

[0146] 102) Form a first trench T1 and a first insulating layer 11;

[0147] Etch the plurality of stacked structures to form a plurality of first trenches T1 penetrating through the plurality of stacked structures; the first trenches T1 extend along a first direction X, and the plurality of first trenches T1 are spaced apart along the first direction X and a second direction Y. A storage unit region is defined between adjacent first trenches T1 along the second direction Y, and the storage unit region may include a transistor region and a capacitor region; the transistor region and the capacitor region may be arranged along the first direction X;

[0148] Deposit a first insulating film in each first trench T1 and planarize it to form a first insulating layer 11 filling the first trench T1; the first insulating layer 11 may be flush with the hard mask layer 9. As Figure 3A and Figure 3B shown, wherein, Figure 3A is a top view after forming the first trench T1 and the first insulating layer 11 provided for some embodiments, Figure 3B is a cross-sectional view perpendicular to the substrate 1 along the Figure 3A CC' direction in. The CC' direction may be parallel to the first direction X. The first insulating layer 11 may isolate a plurality of subsequent formed storage units.

[0149] In some embodiments, the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The same applies to the subsequent second insulating film to the fourth insulating film and will not be elaborated further.

[0150] 103) Form a first hole K1;

[0151] Etch the stacked structure from the top layer to the bottom layer (the etching stops on the substrate 1) by dry etching in the transistor region defined by the first trench T1 adjacent in the second direction Y, to form a first hole K1. At this time, the aperture of the second sub-hole K12 of the second semiconductor structure layer 232a and the first sub-hole K11 of the sacrificial layer 10 in the first hole K1 are the same. As Figure 4A and Figure 4B shown, wherein, Figure 4A FIG. is a top view after forming the first hole K1 provided for some embodiments, Figure 4B is along Figure 4A a cross-sectional view perpendicular to the substrate 1 in the AA' direction in FIG.. The sidewall of the first hole K1 does not expose the first insulating layer 11.

[0152] 104) Form a second insulating layer 12;

[0153] Etch and remove the sacrificial layer 10 through the first hole K1;

[0154] Deposit a second insulating thin film on the substrate 1 on which the foregoing structure is formed to form a second insulating layer 12 filling the first hole K1 and the region where the original sacrificial layer 10 was located. As Figure 5A and Figure 5B shown, wherein, Figure 5A FIG. is a top view after forming the second insulating layer 12 provided for some embodiments, Figure 5B is along Figure 5A a cross-sectional view perpendicular to the substrate 1 in the AA' direction in FIG.. The second insulating layer 12 can isolate the memory cells of different layers.

[0155] 105) Expose the first hole K1;

[0156] Etch and remove the second insulating layer 12 in the first hole K1 to expose the first hole K1. As Fig. 6A and Figure 6B shown, wherein, Fig. 6A FIG. is a top view after exposing the first hole K1 provided for some embodiments, Figure 6B is along Fig. 6A a cross-sectional view perpendicular to the substrate 1 in the AA' direction in FIG..

[0157] 106) Form a first groove V1;

[0158] Etch the second semiconductor structure layer 232a laterally based on the first hole K1 (i.e., along a direction parallel to the substrate 1), expand the aperture of the second sub-hole K12 of the first hole K1 located in the second semiconductor structure layer 232a, such that the orthographic projection of the first sub-hole K11 of the first hole K1 located in the second insulating layer 12 on the substrate 1 falls within the orthographic projection of the second sub-hole K12 on the substrate 1. At this time, the second sub-hole K12 has a first lateral groove V1 relative to the first sub-hole K11, as Fig. 7A and Figure 7B shown, where Fig. 7A is a top view after forming the first groove V1 provided for some embodiments, Figure 7B is a cross-sectional view perpendicular to the substrate 1 along the Fig. 7A AA' direction in

[0159] Referring to Fig. 7A the area shown by the dashed line surrounding the first hole K1 in

[0160] i.e., the area where the second sub-hole K12 is located. Among the four sidewalls of the second sub-hole K12, two of the sidewalls are the second semiconductor structure layer 232a, and the other two sidewalls are the first insulating layer 11. That is, when etching laterally along the second direction Y, all of the second semiconductor structure layer 232a in this direction is etched away, exposing the first insulating layer 11. When etching laterally along the first direction X, only a part of the second semiconductor structure layer 232a in this direction is etched away.

[0160] 107) Form the first semiconductor structure layer 231a;

[0161] Deposit a second semiconductor thin film on the substrate 1 on which the foregoing structure is formed to form the first semiconductor structure layer 231a filling the first hole K1, as Fig. 8A and Figure 8B shown, where Fig. 8A is a top view after forming the first semiconductor structure layer 231a provided for some embodiments, Figure 8B is a cross-sectional view perpendicular to the substrate 1 along the Fig. 8A AA' direction in

[0162] The first semiconductor structure layer 231a can be a lightly doped or undoped semiconductor material.

[0163] In some embodiments, the deposition of the second semiconductor thin film can be epitaxial growth of the second semiconductor thin film.

[0164] In the exemplary embodiments of the present disclosure, the material of the second semiconductor thin film can be silicon or polysilicon and other materials with a bandgap less than 1.65 eV, or can be a wide-bandgap material, such as a metal oxide material with a bandgap greater than 1.65 eV.

[0165] For example, the material of the metal oxide semiconductor layer or the channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, and other materials. Of course, compounds containing other elements are not excluded in the metal oxide, such as elements such as N and Si; nor are small amounts of other doping elements excluded.

[0166] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxide nitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and other materials, as long as the leakage current of the transistor can meet the requirements, and specific adjustments can be made according to the actual situation.

[0167] These materials have a wide bandgap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the operating performance of the dynamic memory.

[0168] The above materials of the metal oxide semiconductor layer or the channel only emphasize the element type of the material, not the atomic ratio in the material and the film quality of the material.

[0169] 108) Form the word line 40 and the gate insulating layer 24;

[0170] Etch and remove the first semiconductor structure layer 231a in the first hole K1 except for the area where the first groove V1 is located, that is, only the first semiconductor structure layer 231a located in the first groove V1 is retained, and the retained first semiconductor structure layer 231a is the first semiconductor sub-layer 231 of the plurality of transistors. The first semiconductor sub-layer 231 is only located in the first groove V1; the first semiconductor sub-layer 231 fills the first groove V1;

[0171] Deposit a gate insulating thin film and a gate electrode thin film in the first hole K1 in sequence to form a gate insulating layer 24 and a word line 40; the word line 40 fills the first hole K1, as Fig.9A and Fig. 9B shown, wherein, Fig.9A is a top view after forming the word line 40 and the gate insulating layer 24 provided in some embodiments, Fig. 9B is a cross-sectional view perpendicular to the substrate 1 along the Fig.9A AA' direction in. At this time, the first hole K1 refers to the first hole K1 formed with the first semiconductor sub-layer 231, that is, the gate insulating layer 24 and the word line 40 are formed in the first hole K1 except for the first groove V1.

[0172] The gate electrodes 26 of the transistors at the same position in different layers are part of the word line 40. The gate insulating layer 24 covers the bottom wall and side wall of the first hole K1.

[0173] In some embodiments, the material of the gate insulating layer 24 may include one or more layers of High-K dielectric materials. In some embodiments, it may include oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other High-K materials.

[0174] In some embodiments, the gate electrode thin film may be one or more of the following different types of materials:

[0175] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing these metals mentioned above;

[0176] Or, it may be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO) and other metal oxide materials with relatively high conductivity; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials;

[0177] Or, it may be polysilicon materials, conductive doped semiconductor materials, etc., such as silicon after conductive doping, germanium after conductive doping, silicon germanium after conductive doping, etc.; other materials showing conductivity, etc.

[0178] 109) Form a second trench T2;

[0179] Etch the stacked structure from the top layer to the bottom layer to form a second trench T2 penetrating the stacked structure. The second trench T2 extends along a second direction Y, and a group of memory cells is defined between adjacent second trenches T2. Each group of memory cells includes two columns of memory cells, as Fig. 10A and Fig. 10B shown. Among them, Fig. 10A is a top view of the structure after forming the second trench T2 provided in some embodiments, Fig. 10B is along Fig. 10A a cross-sectional view perpendicular to the substrate 1 in the AA' direction in

[0180] 110) Form a second groove V2;

[0181] Laterally etch the second semiconductor structure layer 232a in the second trench T2, and do not completely etch away the second semiconductor structure layer 232a to form a second groove V2. The second groove V2 extends along the second direction Y, as Fig.11A and Fig. 11B shown. Among them, Fig.11A is a top view of the structure after forming the second groove V2 provided in some embodiments, Fig. 11B is along Fig.11A a cross-sectional view perpendicular to the substrate 1 in the AA' direction in . At this time, the second semiconductor structure layer 232a located on the side of the first semiconductor sub-layer 231 facing the second groove V2 serves as the second part 2322 of the second semiconductor sub-layer 232.

[0182] 111) Form a bit line layer 30a;

[0183] Perform silicidation on the second semiconductor sub-layer 232 to form a metal silicide, so as to reduce the contact resistance between the second semiconductor sub-layer 232 and the to-be-formed bit line layer 30a;

[0184] Deposit a first conductive thin film to form a bit line layer 30a. The bit line layer 30a fills the second trench T2 and the second groove V2; as Fig. 12A and Fig. 12B shown. Among them, Fig. 12A is a top view of the structure after forming the bit line layer 30a provided in some embodiments, Fig. 12B is along Fig. 12A a cross-sectional view perpendicular to the substrate 1 in the AA' direction in .

[0185] In some embodiments, the first conductive thin film may be the following conductive materials:

[0186] For example, containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing these metals mentioned above;

[0187] Alternatively, it can be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), etc.; for example, metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.

[0188] Alternatively, it can be a polysilicon material, a conductive doped semiconductor material, etc., such as silicon after conductive doping, germanium after conductive doping, silicon germanium after conductive doping, etc.; other materials that exhibit conductivity, etc.

[0189] Subsequently, the materials of the second conductive film, the third conductive film, the fourth conductive film, and the first conductive film are similar and will not be elaborated here.

[0190] 112) Form the bit line 30 and the third insulating layer 13;

[0191] Etch and remove the bit line layer 30a in the second trench T2, and retain the bit line layer 30a in the second groove V2. At this time, the bit line layer 30a is divided into multiple bit lines 30 located in different layers, and these multiple bit lines 30 are disconnected from each other;

[0192] Deposit a third insulating film to form the third insulating layer 13 that fills the second trench T2. The third insulating layer 13 separates different groups of memory cells, as Fig.13A and Fig. 13B shown, where Fig.13A is a top view of the formed bit line 30 and the third insulating layer 13 provided in some embodiments, Fig. 13B is Fig.13A a cross-sectional view perpendicular to the substrate 1 along the AA' direction in

[0193] 113) Form the second hole K2;

[0194] In the capacitor region defined by the first trench T1 adjacent along the second direction Y, use dry etching to etch the stacked structure from the top layer to the bottom layer (the etching stops on the substrate 1) to form the second hole K2. At this time, the aperture of the fourth sub-hole K22 of the second hole K2 in the second semiconductor structure layer 232a is the same as that of the third sub-hole K21 in the second insulating layer 12, as Fig.14A and Fig. 14B shown, where Fig.14A is a top view of the formed second hole K2 provided in some embodiments, Fig. 14B is Fig.14A a cross-sectional view perpendicular to the substrate 1 along the AA' direction in

[0195] 114) Form a third groove V3;

[0196] Transversely etch the second semiconductor structure layer 232a based on the second hole K2 to enlarge the aperture of the fourth sub-hole K22 of the second hole K2 located in the second semiconductor structure layer 232a, such that the orthographic projection of the third sub-hole K21 of the second hole K2 located in the second insulating layer 12 on the substrate 1 falls within the orthographic projection of the fourth sub-hole K22 on the substrate 1. At this time, the fourth sub-hole K22 has a transverse third groove V3 relative to the third sub-hole K21, as Fig.15A and Fig. 15B shown, where Fig.15A is a top view after forming the third groove V3 provided for some embodiments, Fig. 15B is a cross-sectional view perpendicular to the substrate 1 along the Fig.15A AA' direction in

[0197] Referring to Fig.15A the region shown by the dashed line surrounding the second hole K2 in

[0198] 115) Form a first electrode layer 51a and a fourth insulating layer 14;

[0199] Deposit a second conductive thin film and a fourth insulating thin film in sequence in the second hole K2 to form a first electrode layer 51a and a fourth insulating layer 14; the fourth insulating layer 14 fills the second hole K2 (here the second hole K2 includes the third groove V3), as Fig.16A and Fig. 16B shown, where Fig.16A is a top view after forming the first electrode layer 51a and the fourth insulating layer 14 provided for some embodiments, Fig. 16B is a cross-sectional view perpendicular to the substrate 1 along the Fig.16A AA' direction in

[0200] 116) Form a first electrode 51;

[0201] Etch away the first electrode layer 51a and the fourth insulating layer 14 in the second hole K2 except for the area where the third groove V3 is located, that is, only the first electrode layer 51a and the fourth insulating layer 14 located in the third groove V3 are retained. The retained first electrode layer 51a is the plurality of first electrodes 51 that are disconnected from each other. The first electrode 51 is only located in the third groove V3; the first electrode 51 covers the inner wall of the third groove V3, including the top wall of the third groove V3 parallel to the substrate 1 (the inner wall on the side of the third groove V3 away from the substrate 1) and the bottom wall (the inner wall on the side of the third groove V3 close to the substrate 1), and the four side walls perpendicular to the substrate 1, as Fig.17A and Fig. 17B shown, where Fig.17A is a top view of some embodiments after forming the first electrode 51, Fig. 17B is a cross-sectional view perpendicular to the substrate 1 along the Fig.17A AA' direction in

[0202] 117) Form the first sub-electrode 421 and the first dielectric layer 431;

[0203] Etch away the fourth insulating layer 14 located in the third groove V3; at this time, all of the fourth insulating layer 14 is removed and the first electrode 51 is exposed;

[0204] Deposit a first dielectric thin film and a third conductive thin film in the second hole K2 in sequence to form the first dielectric layer 431 and the first sub-electrode 421; the first sub-electrode 421 fills the second hole K2, and the first sub-electrode 421 extends into the third groove V3, as Fig.18A and Fig.18B shown, where Fig.18A is a top view of some embodiments after forming the first sub-electrode 421 and the first dielectric layer 431, Fig.18B is a cross-sectional view perpendicular to the substrate 1 along the Fig.18A AA' direction in

[0205] In some embodiments, the first dielectric thin film may be a High-K dielectric material. In some embodiments, it may include one or more oxides such as hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other High-K materials. The subsequent second dielectric thin film is similar to the first dielectric thin film and will not be elaborated further.

[0206] 118) Form the third trench T3;

[0207] Etching the stack structure from the top layer to the bottom layer to form a third trench T3 penetrating the stack structure, wherein the third trench T3 extends along the second direction Y and is located between two adjacent columns of memory cells in the same group;

[0208] The second insulating layer 12 is laterally etched through the third trench T3, and the second insulating layer 12 is etched along the first direction x to expose the top wall (the surface facing the substrate 1) and the bottom wall (the surface facing away from the substrate 1) of the first capacitor electrode 41, and the second semiconductor structure layer 232a is etched to expose the side wall of the first capacitor electrode 41 facing the third trench T3, so that the second sub-electrode 422 formed subsequently can surround the top wall, bottom wall and side wall of the first capacitor electrode 41, thereby increasing the electrode area of ​​the capacitor as much as possible. When the second insulating layer 12 is laterally etched, part of the second insulating layer 12 is retained, and the gate insulating layer 24 is not exposed; Fig.19A and Fig.19B As shown, Fig.19A A top view after forming a word line 40 and a gate insulating layer 24 is provided for some embodiments. Fig.19B For along Fig.19A A cross-sectional view perpendicular to the substrate 1 along the AA′ direction.

[0209] 119) forming a second sub-electrode 422 and a second dielectric layer 432;

[0210] A second dielectric film and a fourth conductive film are sequentially deposited in the third trench T3 to form a second dielectric layer 432 and a second sub-electrode 422; the second sub-electrode 422 fills the third trench T3. Figure 1A , Figure 1B and Figure 1C As shown, it can be seen that the second sub-electrodes 422 of the two columns of memory cells in the same group are connected to form an integrated structure. The second sub-electrode 422 and the first sub-electrode 421 constitute the second capacitor electrode 42 of the capacitor.

[0211] In the above embodiments, the transistor includes one gate electrode. In some exemplary embodiments, the transistor may include two gate electrodes. Fig. 20A A top view of a semiconductor device provided for some other embodiments, Fig. 20B For along Fig. 20A Cross-sectional view along the A1A1' direction; Fig. 20C For along Fig. 20A A cross-sectional view perpendicular to the substrate 1 in the BB' direction, Fig.20D For along Fig. 20C A cross-sectional view parallel to the substrate 1 in the DD' direction. Fig. 20A , Fig. 20B , Fig. 20C and Fig.20DAs shown, embodiments of the present disclosure provide a semiconductor device. In this semiconductor device, a transistor includes a dual-gate electrode, that is, the transistor includes a first gate electrode 26a extending in a direction perpendicular to the substrate 1 and a first gate insulating layer 24a surrounding the first gate electrode 26a, and a second gate electrode 26b extending in a direction perpendicular to the substrate 1 and a second gate insulating layer 24b surrounding the second gate electrode 26b. The first gate electrode 26a and the second gate electrode 26b may be spaced apart along the second direction Y. The first gate electrodes 26a of multiple transistors at the same position in different layers are connected to form an integral structure extending along a direction perpendicular to the substrate 1, that is, a first word line 40a is formed. The second gate electrodes 26b of multiple transistors at the same position in different layers are connected to form an integral structure extending along a direction perpendicular to the substrate 1, that is, a second word line 40b is formed. The transistor further includes a first semiconductor sub-layer 231 and a second semiconductor sub-layer 232. The first semiconductor sub-layer 231 partially surrounds the first gate electrode 26a and the first semiconductor sub-layer 231 partially surrounds the second gate electrode 26b. The second semiconductor sub-layer 232 includes a first portion 2321 and a second portion 2322 that are spaced apart on sidewalls of the first semiconductor sub-layer 231 facing away from the first gate electrode 26a and the second gate electrode 26a. For a memory array composed of transistors with dual-gate electrodes, by activating a first word line and a second word line, a vertical column of memory cells (i.e., a group of memory cells at the same position in different layers) can be selected. Thus, a vertical column of memory cells can be selected without providing a select transistor for the word line. Compared with a solution that requires a select transistor for a memory array composed of transistors with only one gate electrode, the solution provided in this embodiment does not require adding process steps for manufacturing a select transistor, has a small number of word line drivers, and the number of word line drivers remains unchanged as the number of stacked layers increases. In addition, the control logic of the driving circuit is simple.

[0212] In some embodiments, in a plane parallel to the substrate 1, the cross-section of the first semiconductor sub-layer 231 may be an H shape. This H-shaped structure may include a first strip-shaped structure extending along the first direction X and two second strip-shaped structures located at both ends of the first strip-shaped structure and extending along the second direction Y. The first gate electrode 26a and the second gate electrode 26b are respectively located on both sides of the first strip-shaped structure. The first portion 2321 may be connected to a sidewall of one of the second strip-shaped structures facing away from the first gate electrode 26a, and the second portion 2322 may be connected to a sidewall of the other second strip-shaped structure facing away from the first gate electrode 26a.

[0213] In some embodiments, multiple first gate insulating layers 24a of multiple transistors at the same position in different layers are connected to form an integral structure extending along a direction perpendicular to the substrate 1, and multiple second gate insulating layers 24b of multiple transistors at the same position in different layers are connected to form an integral structure extending along a direction perpendicular to the substrate 1.

[0214] The first gate electrode 26a and the second gate electrode 26b may be respectively disposed in different holes. In some embodiments, the semiconductor device may further include: insulating layers and conductive layers alternately distributed along a direction perpendicular to the substrate 1; a third hole K3 and a fourth hole K4 penetrating through the insulating layers and the conductive layers; the conductive layers include a first electrode 51 and a second electrode 52 of the transistor, the first electrode 51 is connected to the first portion 2321, and the second electrode 52 is connected to the second portion 2322; the third hole K3 and the fourth hole K4 communicate with each other in the conductive layer;

[0215] In the third hole K3, the first semiconductor sub-layer 231, the first gate insulating layer 24a surrounding the first gate electrode 26a, and the first gate electrode 26a are sequentially distributed from the outside to the inside;

[0216] In the fourth hole, the first semiconductor sub-layer 231, the second gate insulating layer 24b surrounding the second gate electrode 26b, and the second gate electrode 26b are sequentially distributed from the outside to the inside.

[0217] In some embodiments, the third hole K3 may include a fifth sub-hole located in the insulating layer and a sixth sub-hole located in the conductive layer, and the orthographic projection of the fifth sub-hole on the substrate falls within the orthographic projection of the sixth sub-hole on the substrate;

[0218] The fourth hole K4 may include a seventh sub-hole located in the insulating layer and the sixth sub-hole located in the conductive layer, and the orthographic projection of the seventh sub-hole on the substrate falls within the orthographic projection of the sixth sub-hole on the substrate 1. That is, the third hole K3 and the fourth hole K4 share the sixth sub-hole.

[0219] For the first electrode 51, the second electrode 52 of the transistor with the double-gate structure, and the structure of the connected capacitor, reference may be made to the content described in the foregoing embodiments and the embodiments of the manufacturing process of the semiconductor device with the double-gate structure hereinafter, and details are not described herein again.

[0220] In some embodiments, the manufacturing process of the semiconductor device with the above double-gate structure may include:

[0221] 201) - 202), similar to 101) to 102), a stacked structure including the first trench T1 and the first insulating layer 11 is formed;

[0222] (203) Form a third hole K3 and a fourth hole K4;

[0223] In the transistor region defined by the adjacent first trench T1, the stacked structure is etched from the top layer to the bottom layer by dry etching (the etching stops on the substrate 1), forming a third hole K3 and a third hole K4. At this time, the aperture diameters of the third hole K3 in the sixth sub-hole K32 of the second semiconductor structure layer 232a and in the fifth sub-hole K31 of the sacrificial layer 10 are the same, and the aperture diameters of the fourth hole K4 in the eighth sub-hole of the second semiconductor structure layer 232a and in the seventh sub-hole of the sacrificial layer 10 are the same, as Fig.21A and Fig. 21B shown, where Fig.21A is a top view of the formed third hole K3 and fourth hole K4 provided for some embodiments, Fig. 21B is Fig.21A a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in

[0224] (204) Form a second insulating layer 12;

[0225] Etch away the sacrificial layer 10 through the third hole K3 and the fourth hole K4;

[0226] Deposit a second insulating thin film on the substrate 1 where the foregoing structure is formed, forming a second insulating layer 12 that fills the third hole K3, the fourth hole K4, and the region where the original sacrificial layer 10 is located, as Fig.22A and Fig. 22B shown, where Fig.22A is a top view of the formed second insulating layer 12 provided for some embodiments, Fig. 22B is Fig.22A a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in

[0227] (205) Expose the third hole K3 and the fourth hole K4;

[0228] Etch away the second insulating layer 12 in the third hole K3 and the fourth hole K4 to expose the third hole K3 and the fourth hole K4, as Fig.23A and Fig. 23B shown, where Fig.23A is a top view of the exposed third hole K3 and fourth hole K4 provided for some embodiments, Fig. 23B is Fig.23A a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in

[0229] (206) Form a fourth groove V4;

[0230] Transversely etch the second semiconductor structure layer 232a within the third hole K3 and the fourth hole K4 to enlarge the apertures of the sub-holes of the third hole K3 and the fourth hole K4 located in the second semiconductor structure layer 232a, such that the orthographic projection of the fifth sub-hole K31 of the third hole K3 located in the second insulating layer 12 onto the substrate 1 falls within the orthographic projection of the sixth sub-hole K32 onto the substrate 1, and such that the orthographic projection of the seventh sub-hole K41 of the fourth hole K4 located in the second insulating layer 12 onto the substrate 1 falls within the orthographic projection of the eighth sub-hole K42 onto the substrate 1. At this time, the sixth sub-hole K32 and the eighth sub-hole K42 overlap, and the sixth sub-hole K32 has an H-shaped fourth groove V4 relative to the fifth sub-hole K31 and the seventh sub-hole, as Fig.24A and Fig. 24B shown, where Fig.24A FIG. is a top view after forming the fourth groove V4 provided for some embodiments, Fig. 24B is a cross-sectional view perpendicular to the substrate 1 along the Fig.24A A1A1' direction in

[0231] Referring to the region indicated by the dashed line in Figure 24A , that is, the region where the sixth sub-hole K32 or the eighth sub-hole K42 is located, it can be seen that when transversely etching along the second direction Y, all of the second semiconductor structure layer 232a in this direction is etched away, exposing the first insulating layer 11. When transversely etching along the first direction X, part of the second semiconductor structure layer 232a in this direction is etched away, and part of the second semiconductor structure layer 232a is retained.

[0232] 207) Form the first semiconductor structure layer 231a;

[0233] Deposit a second semiconductor thin film on the substrate 1 on which the foregoing structure is formed to form the first semiconductor structure layer 231a filling the third hole K3 and the fourth hole K4, as Figure 25A and Figure 25B shown, where Figure 25A FIG. is a top view after forming the first semiconductor structure layer 231a provided for some embodiments, Figure 25B is a cross-sectional view perpendicular to the substrate 1 along the Figure 25A A1A1' direction in

[0234] 208) Form the first word line 40a and the first gate insulating layer 24a, the second word line 40b and the second gate insulating layer 24b;

[0235] Etch away the first semiconductor structure layer 231a in the third hole K3 and the fourth hole K4 except for the area where the fourth groove V4 is located, that is, only the first semiconductor structure layer 231a located in the fourth groove V4 is retained. The retained first semiconductor structure layer 231a is the first semiconductor sub-layer 231 of the plurality of transistors. The first semiconductor sub-layer 231 is only located in the fourth groove V4; the first semiconductor sub-layer 231 fills the fourth groove V4;

[0236] Deposit a gate insulating film and a gate electrode film in sequence in the third hole K3 to form a first gate insulating layer 24a and a first word line 40a. The first word line 40a fills the third hole K3; deposit a gate insulating film and a gate electrode film in sequence in the fourth hole K4 to form a second gate insulating layer 24b and a second word line 40b. The second word line 40b fills the fourth hole K4, as Figure 26A and Figure 26B shown, wherein, Figure 26A is a top view after forming the first word line 40a, the first gate insulating layer 24a, the second word line 40b and the second gate insulating layer 24b provided for some embodiments, Figure 26B is a cross-sectional view perpendicular to the substrate 1 along the Figure 26A A1A1' direction in

[0237] The first gate electrode 26a of the transistors at the same position in different layers is a part of the first word line 40a. The first gate insulating layer 24a covers the bottom wall and the side wall of the third hole K3. The second gate electrode 26b of the transistors at the same position in different layers is a part of the second word line 40b. The second gate insulating layer 24a covers the bottom wall and the side wall of the fourth hole K4.

[0238] 209) Form a second trench T2;

[0239] Etch the stacked structure from the top layer to the bottom layer to form a second trench T2 that penetrates the stacked structure. The second trench T2 extends along the second direction Y. A set of memory cells is defined between adjacent second trenches T2. Each set of memory cells includes two columns of memory cells, as Figure 27A and Figure 27B shown, wherein, Figure 27A is a top view after forming the second trench T2 provided for some embodiments, Figure 27B is a cross-sectional view perpendicular to the substrate 1 along the Figure 27A A1A1' direction in

[0240] 210) Form a second groove V2;

[0241] Etch the second semiconductor structure layer 232a laterally within the second trench T2, without completely etching away the second semiconductor structure layer 232a, to form a second groove V2. The second groove V2 extends along the second direction Y and penetrates the stacked structure along the second direction Y, as Figure 28A and Figure 28B shown, where Figure 28A is a top view of the formation of the second groove V2 provided in some embodiments, Figure 28B is along Figure 28A a cross-sectional view perpendicular to the substrate 1 in the direction of A1A1' in . At this time, the second semiconductor structure layer 232a on the side of the first semiconductor sub-layer 231 facing the second groove V2 serves as the second part 2322 of the second semiconductor sub-layer 232.

[0242] 211) Form the bit line layer 30a;

[0243] Perform silicidation on the second semiconductor sub-layer 232 to form a metal silicide, so as to reduce the contact resistance between the second semiconductor sub-layer 232 and the bit line layer 30a to be formed;

[0244] Deposit a first conductive thin film to form the bit line layer 30a. The bit line layer 30a fills the second trench T2 and the second groove V2; as Figure 29A and Figure 29B shown, where Figure 29A is a top view of the formation of the bit line layer 30a provided in some embodiments, Figure 29B is along Figure 29A a cross-sectional view perpendicular to the substrate 1 in the direction of A1A1' in .

[0245] 212) Form the bit line 30 and the third insulating layer 13;

[0246] Etch away the bit line layer 30 in the second trench T2, and retain the bit line layer 30a in the second groove V2. At this time, the bit line layer 30a is divided into multiple bit lines 30 located in different layers, and the multiple bit lines 30 are disconnected from each other;

[0247] Deposit a third insulating thin film to form the third insulating layer 13 that fills the second trench T2. The third insulating layer 13 separates different groups of memory cells, as Figure 30A and Figure 30B shown, where Figure 30A is a top view of the formation of the bit line 30 and the third insulating layer 13 provided in some embodiments, Figure 30B is along Figure 30A a cross-sectional view perpendicular to the substrate 1 in the direction of A1A1' in .

[0248] 213) Form the second hole K2;

[0249] Etch the stacked structure from the top layer to the bottom layer (the etching stops on the substrate 1) by dry etching in the capacitor region defined by the first trench T1 adjacent along the second direction Y, to form a second hole K2. At this time, the aperture diameters of the fourth sub-hole of the second semiconductor structure layer 232a and the third sub-hole of the second insulating layer 12 in the second hole K2 are the same, as Figure 31A , Figure 31B and Figure 31C shown, wherein, Figure 31A is a top view of some embodiments after forming the second hole K2, Figure 31B is a cross-sectional view perpendicular to the substrate 1 along the Figure 31A A1A1' direction in Figure 31C is a cross-sectional view perpendicular to the substrate 1 along the Figure 31A BB' direction in

[0250] 214) Form a third groove V3;

[0251] Etch the second semiconductor structure layer 232a laterally in the second hole K2 to enlarge the aperture diameter of the fourth sub-hole K22 of the second hole K2 located in the second semiconductor structure layer 232a, such that the orthographic projection of the third sub-hole K21 of the second hole K2 on the substrate 1 falls within the orthographic projection of the fourth sub-hole K22 on the substrate 1. At this time, the fourth sub-hole K22 has a lateral third groove V3 relative to the third sub-hole K21, as Figure 32A , Figure 32B and Figure 32C shown, wherein, Figure 32A is a top view of some embodiments after forming the third groove V3, Figure 32B is a cross-sectional view perpendicular to the substrate 1 along the Figure 32A A1A1' direction in Figure 32C is a cross-sectional view perpendicular to the substrate 1 along the Figure 32A BB' direction in

[0252] 215) Form a first electrode layer 51a and a fourth insulating layer 14;

[0253] Deposit a second conductive thin film and a fourth insulating thin film in sequence in the second hole K2 to form a first electrode layer 51a and a fourth insulating layer 14; the fourth insulating layer 14 fills the second hole K2, as Figure 33A , Figure 33B and Figure 33C shown, wherein, Figure 33A is a top view of some embodiments after forming the first electrode layer 51a and the fourth insulating layer 14, Figure 33B is a cross-sectional view perpendicular to the substrate 1 along the Figure 33ACross-sectional view perpendicular to the substrate 1 in the direction of A1A1', Figure 33C is the cross-sectional view perpendicular to the substrate 1 in the direction of BB' along Figure 33A in.

[0254] 216) Form the first electrode 51;

[0255] Etch away the first electrode layer 51a and the fourth insulating layer 14 in the second hole K2 except for the area where the third groove V3 is located, that is, only the first electrode layer 51a and the fourth insulating layer 14 located in the third groove V3 are retained. The retained first electrode layer 51a is the plurality of mutually disconnected first electrodes 51, and the first electrode 51 is only located in the third groove V3; the first electrode 51 covers the inner wall of the third groove V3, including the top wall (the inner wall of the third groove V3 far from the substrate 1) and the bottom wall (the inner wall of the third groove V3 close to the substrate 1) of the third groove V3 parallel to the substrate 1, and the four side walls perpendicular to the substrate 1, as Figure 34A , Figure 34B and Figure 34C shown, where Figure 34A is the top view after forming the first electrode 51 provided in some embodiments, Figure 34B is the cross-sectional view perpendicular to the substrate 1 in the direction of A1A1' along Figure 34A in, Figure 34C is the cross-sectional view perpendicular to the substrate 1 in the direction of BB' along Figure 34A in. This first electrode 51 also serves as the first capacitive electrode 41 of the capacitor.

[0256] 217) Form the first sub-electrode 421 and the first dielectric layer 431;

[0257] Etch away the fourth insulating layer 14 located in the third groove V3; at this time, all of the fourth insulating layer 14 is removed, and the first electrode 51 is exposed;

[0258] Deposit a first dielectric thin film and a third conductive thin film in sequence in the second hole K2 to form the first dielectric layer 431 and the first sub-electrode 421; the first sub-electrode 421 fills the second hole K2, and the first sub-electrode 421 extends into the third groove V3, as Figure 35A , Figure 35B and Figure 35C shown, where Figure 35A is the top view after forming the first sub-electrode 421 and the first dielectric layer 431 provided in some embodiments, Figure 35B is the cross-sectional view perpendicular to the substrate 1 in the direction of A1A1' along Figure 35A in, Figure 35C is the cross-sectional view perpendicular to the substrate 1 in the direction of BB' along Figure 35A in.

[0259] 218) forming a third trench T3;

[0260] Etching the stack structure from the top layer to the bottom layer to form a third trench T3 penetrating the stack structure, wherein the third trench T3 extends along the second direction Y and is located between two adjacent columns of memory cells in the same group;

[0261] The second insulating layer 12 is laterally etched through the third trench T3, and the second insulating layer 12 is etched along the first direction x to expose the top wall (the surface facing the substrate 1) and the bottom wall (the surface facing away from the substrate 1) of the first capacitor electrode 41, and the second semiconductor structure layer 232a is etched to expose the side wall of the first capacitor electrode 41 facing the third trench T3, so that the second sub-electrode 422 formed subsequently can surround the top wall, bottom wall and side wall of the first capacitor electrode 41, thereby increasing the electrode area of ​​the capacitor as much as possible. When the second insulating layer 12 is laterally etched, part of the second insulating layer 12 is retained, and the gate insulating layer 24 is not exposed; Figure 36A , Figure 36B , Figure 36C and Figure 36D As shown, Figure 36A A top view of the third trench T3 provided for some embodiments, Figure 36B For along Figure 36A A cross-sectional view perpendicular to the substrate 1 in the A1A1' direction, Figure 36C For along Figure 36A A cross-sectional view perpendicular to the substrate 1 in the BB' direction, Figure 36D For along Figure 36C Cross-sectional view parallel to the substrate in the DD' direction.

[0262] 219) forming a second sub-electrode 422 and a second dielectric layer 432;

[0263] A second dielectric film and a fourth conductive film are sequentially deposited in the third trench T3 to form a second dielectric layer 432 and a second sub-electrode 422; the second sub-electrode 422 fills the third trench T3. Figure 20A , Figure 20B Figure 20C and Figure 20D It can be seen that the second sub-electrodes 422 of two columns of memory cells in the same group are connected to form an integrated structure.

[0264] The present disclosure also provides an electronic device, including the semiconductor device of the aforementioned embodiment, or a semiconductor device formed by the method for manufacturing the semiconductor device of the aforementioned embodiment. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0265] Although the embodiments disclosed in the present invention are as above, the content described is only the embodiments adopted for facilitating the understanding of the present invention and is not intended to limit the present invention. Any person skilled in the art within the scope of the present invention may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: a substrate, and at least one transistor disposed on the substrate; The transistor comprises a gate electrode and a semiconductor layer; The semiconductor layer includes a first semiconductor sublayer that at least partially surrounds the gate electrode and a second semiconductor sublayer that is arranged on a side of the first semiconductor sublayer away from the gate electrode, the doping concentration of the second semiconductor sublayer is greater than the doping concentration of the first semiconductor sublayer, and the second semiconductor sublayer includes a first part and a second part that are spaced apart on a surface of the first semiconductor sublayer away from the gate electrode.

2. The semiconductor device according to claim 1, wherein Along a direction perpendicular to the substrate, the gate electrodes of the plurality of transistors are connected to each other to form a word line perpendicular to the substrate, and the semiconductor layers of the plurality of transistors are arranged at intervals.

3. The semiconductor device according to claim 1, wherein, The second semiconductor sublayer extends in a direction parallel to the substrate.

4. The semiconductor device according to claim 3, characterized in that, The first portion and the second portion are spaced apart along a first direction, the first portion extends along a second direction, the second portion extends along the second direction, and the first direction and the second direction intersect and are both parallel to the substrate.

5. The semiconductor device according to claim 4, characterized in that, The transistor includes only one gate electrode; along a plane parallel to the substrate, a cross section of the first semiconductor sublayer is a closed loop.

6. The semiconductor device according to claim 4, characterized in that, The transistor includes a first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode are spaced apart along the second direction, a plurality of first gate electrodes of the transistors are interconnected to form an integrated structure extending along a direction perpendicular to the substrate, a plurality of second gate electrodes of the transistors are interconnected to form an integrated structure extending along a direction perpendicular to the substrate, the first semiconductor sublayer partially surrounds the first gate electrode, and the first semiconductor sublayer partially surrounds the second gate electrode.

7. The semiconductor device according to claim 5, wherein The semiconductor device further comprises: An insulating layer and a conductive layer are alternately distributed along a direction perpendicular to the substrate; a first hole penetrates the insulating layer and the conductive layer; the conductive layer comprises a first electrode and a second electrode of the transistor, the first electrode is connected to the first part, and the second electrode is connected to the second part.

8. The semiconductor device according to claim 7, wherein, The first hole includes a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, and an orthographic projection of the first sub-hole on the substrate falls within an orthographic projection of the second sub-hole on the substrate.

9. The semiconductor device according to claim 6, wherein The semiconductor device further comprises: Insulating layers and conductive layers are alternately distributed along a direction perpendicular to the substrate; a third hole and a fourth hole penetrate the insulating layer and the conductive layer; and the third hole and the fourth hole are connected in the conductive layer.

10. The semiconductor device according to claim 9, characterized in that The first semiconductor sublayer, the first gate insulating layer, and the first gate electrode are sequentially distributed in the third hole from outside to inside; The first semiconductor sublayer, the second gate insulating layer, and the second gate electrode are sequentially distributed in the fourth hole from outside to inside.

11. The semiconductor device according to claim 9, wherein, The third hole includes a fifth sub-hole located in the insulating layer and a sixth sub-hole located in the conductive layer, and the orthographic projection of the fifth sub-hole on the substrate falls within the orthographic projection of the sixth sub-hole on the substrate; The fourth hole includes a seventh sub-hole located in the insulating layer and a sixth sub-hole located in the conductive layer, and a positive projection of the seventh sub-hole on the substrate falls within a positive projection of the sixth sub-hole on the substrate.

12. The semiconductor device according to claim 7 or 8, characterized in that, The semiconductor device further includes: a multi-layer memory cell array distributed in a direction perpendicular to the substrate, each layer of the memory cell array including a plurality of rows and columns of memory cells distributed in a first direction and a second direction respectively, the memory cell including the transistor, and second electrodes of the transistors in the same column distributed in the second direction in the same layer are interconnected to form a bit line extending in the second direction.

13. The semiconductor device according to claim 12, wherein, The second portions of the transistors in the same column distributed in the second direction in the same layer are interconnected to form an integral structure, and the first portions of the transistors in the same column distributed in the second direction in the same layer are separated from each other.

14. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes: a second hole penetrating the insulating layer and the conductive layer; the second hole includes a third sub-hole located in the insulating layer and a fourth sub-hole located in the conductive layer, and the fourth sub-hole has a groove extending in a horizontal direction with respect to the third sub-hole.

15. The semiconductor device according to claim 14, wherein, The semiconductor device further includes: a plurality of capacitors, the capacitor including a first capacitor electrode and a second capacitor electrode, and the first electrode is multiplexed with the first capacitor electrode.

16. The semiconductor device according to claim 15, wherein, The second capacitor electrode includes a first sub-electrode; in the second hole, the first capacitor electrode surrounding the first sub-electrode, a first dielectric layer surrounding the first sub-electrode, and the first sub-electrode are sequentially distributed from the outside to the inside.

17. The semiconductor device according to claim 16, wherein, The first capacitor electrode is distributed on an inner wall of the groove, the first sub-electrode extends in a direction perpendicular to the substrate and has an extension extending into the groove.

18. The semiconductor device according to claim 16, wherein The second capacitor electrode further includes a second sub-electrode; The second sub-electrode is distributed on a side of the first capacitor electrode facing away from the substrate, a side facing the substrate, and a side facing away from the second semiconductor sub-layer, and a second dielectric layer is disposed between the second sub-electrode and the first capacitor electrode.

19. A manufacturing method of a semiconductor device, characterized in that, Including: providing a substrate, and forming a stacked structure including alternately arranged semiconductor structure layers and sacrificial layers on the substrate; patterning the stacked structure to form a first trench penetrating through each layer, the first trench extending in a first direction; a transistor region is included between adjacent first trenches spaced apart in a second direction; the first direction and the second direction intersect and are both parallel to the substrate; forming a hole in the transistor region that penetrates the stacked structure in a direction perpendicular to the substrate, removing the sacrificial layer through the hole, and replacing the sacrificial layer with an insulating layer; etching the semiconductor structure layer in a direction parallel to the substrate based on the hole to form a second semiconductor sub-layer, the second semiconductor sub-layer including a first portion and a second portion that are disconnected from each other; forming a plurality of gate electrodes arranged in a direction perpendicular to the substrate and a plurality of first semiconductor sub-layers surrounding the gate electrodes in the hole, the plurality of gate electrodes being connected to form an integral structure, and the plurality of first semiconductor sub-layers being separated from each other.

20. The manufacturing method of the semiconductor device according to claim 19, wherein, Forming holes that penetrate the stacked structure in a direction perpendicular to the substrate in the transistor region includes: forming a third hole and a fourth hole that penetrate the stacked structure in a direction perpendicular to the substrate in the same transistor region; Etching the semiconductor structure layer along a direction parallel to the substrate based on the holes includes: Etching the semiconductor structure layer in the third hole along a direction parallel to the substrate such that the orthographic projection of the sub-hole of the insulating layer on the substrate falls within the orthographic projection of the sub-hole of the semiconductor structure layer on the substrate; laterally etching the semiconductor structure layer in the fourth hole such that the orthographic projection of the sub-hole of the insulating layer on the substrate falls within the orthographic projection of the sub-hole of the semiconductor structure layer on the substrate, and the sub-holes of the semiconductor structure layer of the third hole and the fourth hole communicate; Forming a plurality of gate electrodes arranged in a direction perpendicular to the substrate and a plurality of first semiconductor sub-layers surrounding the gate electrodes in the holes includes: Forming a plurality of first gate electrodes extending in a direction perpendicular to the substrate in the third hole, forming a plurality of second gate electrodes extending in a direction perpendicular to the substrate in the fourth hole, and forming the first semiconductor sub-layers in the sub-holes of the semiconductor structure layer of the third hole and the fourth hole.

21. The manufacturing method of the semiconductor device according to claim 19, wherein, Forming a plurality of first semiconductor sub-layers surrounding the gate electrodes in the holes includes: forming a plurality of first semiconductor sub-layers surrounding the gate electrodes by epitaxial growth in the holes.

22. An electronic device, characterized in that, Including the semiconductor device according to any one of claims 1 to 18.

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