Formation method of semiconductor structure, semiconductor structure and electronic device

Abstract

The invention discloses a semiconductor structure forming method, a semiconductor structure and an electronic device, and the method comprises the steps: providing a substrate which comprises a semiconductor substrate and a fin structure which is formed on the semiconductor substrate and is provided with a channel region, and carrying out the wet processing technology and the drying technology in sequence, feeding the substrate subjected to the wet treatment process and the drying process into a treatment chamber, sequentially performing a chemical oxide removal process and a heat treatment process on the substrate in the treatment chamber, and forming a channel protection layer on the channel region of the fin structure, therefore, the in-situ formation of the channel protection layer in the channel region of the fin structure is realized without contacting with an external new environment, the technological process of the semiconductor structure is simplified, and the production efficiency and the yield and performance of the semiconductor structure are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. Background Art

[0002] With the continuous reduction of the size of semiconductor devices, in order to reduce the short-channel effect and improve the performance of semiconductor devices, three-dimensional field-effect transistor devices with fin structures have emerged, such as fin field-effect transistor (FinFET) devices and gate-all-around field-effect transistor (GAAFET) devices.

[0003] In the manufacturing process of three-dimensional field-effect transistor devices with fin structures, a Wet process including cleaning and etching is commonly used to process the fin structures, and an interface layer is formed in the channel region of the fin structures after this process. This interface layer can provide an interface for the subsequent formation of the gate. However, in the related art, the process flow of the above manufacturing process is relatively complex, the production efficiency is low, and the yield of the devices also needs to be further improved. Summary of the Invention

[0004] To solve the problems of the prior art, embodiments of this application provide a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. The technical solutions are as follows:

[0005] On the one hand, a method for forming a semiconductor structure is provided, including:

[0006] Providing a substrate, the substrate includes a semiconductor substrate and fin structures formed on the semiconductor substrate, and the fin structures have channel regions;

[0007] Performing a wet treatment process and a drying process on the substrate in sequence;

[0008] Feeding the substrate after the wet treatment process and the drying process into a processing chamber, and performing a chemical oxide removal process and a heat treatment process on the substrate in sequence in the processing chamber, and forming a channel protection layer on the channel regions of the fin structures.

[0009] In an exemplary embodiment, the wet treatment process includes wet cleaning and / or wet etching.

[0010] In an exemplary embodiment, the fin structures include alternately stacked channel nanomaterial layers and sacrificial nanomaterial layers; the performing a wet treatment process and a drying process on the substrate in sequence includes:

[0011] Perform selective wet etching on the substrate to remove the sacrificial nanomaterial layer between adjacent channel nanomaterial layers;

[0012] Perform a drying process on the substrate after the selective wet etching.

[0013] In an exemplary embodiment, the material for forming the channel nanomaterial layer is different from the material for forming the sacrificial nanomaterial layer, and the material for forming the sacrificial nanomaterial layer is silicon germanium.

[0014] In an exemplary embodiment, the substrate further includes a dummy gate structure spanning the fin structure; the performing selective wet etching on the substrate to remove the sacrificial nanomaterial layer between adjacent channel nanomaterial layers includes:

[0015] Remove the dummy gate structure on the fin structure to expose a part of the fin structure covered by the dummy gate structure;

[0016] Perform selective wet etching on the exposed part of the fin structure to remove the sacrificial nanomaterial layer between adjacent channel nanomaterial layers.

[0017] In an exemplary embodiment, the forming a channel protection layer on the channel region of the fin structure includes:

[0018] Introduce a silicon source precursor gas into the processing chamber, and form an epitaxial silicon layer on the surface of the channel nanomaterial layer based on the silicon source precursor gas;

[0019] Introduce oxygen into the processing chamber to perform thermal oxidation treatment on the epitaxial silicon layer to generate a silicon oxide layer; the silicon oxide layer serves as the channel protection layer for the corresponding channel region.

[0020] In an exemplary embodiment, the forming method further includes:

[0021] Form a gate structure on the channel protection layer; the gate structure includes a dielectric layer and a gate electrode, the dielectric layer is formed on the channel protection layer, and the gate electrode is formed on the dielectric layer.

[0022] In an exemplary embodiment, the sequentially performing a chemical oxide removal process and a heat treatment process on the substrate in the processing chamber and forming a channel protection layer on the channel region of the fin structure includes:

[0023] Under the condition that the pressure in the processing chamber is maintained at no more than 10 mTorr, sequentially perform a chemical oxide removal process and a heat treatment process on the substrate in the processing chamber, and form a channel protection layer on the channel region of the fin structure;

[0024] Among them, the chemical oxide removal process forms reaction by-products on the surface of the substrate, and the heat treatment process removes the reaction by-products from the surface of the substrate at a temperature of not less than 380°C.

[0025] In an exemplary embodiment, performing the chemical oxide removal process includes:

[0026] Using ammonia gas and hydrogen fluoride gas as reaction gases to etch the silicon oxide layer on the exposed surface of the fin structure to form the reaction by-products.

[0027] On the other hand, a semiconductor structure is provided, which is formed by using the formation method of any of the foregoing semiconductor structures, and includes:

[0028] A semiconductor substrate;

[0029] A fin structure located on the semiconductor substrate, and the fin structure has a channel region;

[0030] A channel protection layer located on the channel region of the fin structure.

[0031] In an exemplary embodiment, the fin structure includes a plurality of stacked and spaced channel nanomaterial layers, and a silicon oxide layer obtained by oxidizing an epitaxial silicon layer is formed on the surface of each channel nanomaterial layer, and the silicon oxide layer serves as the channel protection layer of the corresponding channel region.

[0032] In an exemplary embodiment, it further includes:

[0033] A gate structure located on the channel protection layer; the gate structure includes a dielectric layer and a gate electrode, the dielectric layer is formed on the channel protection layer, and the gate electrode is formed on the dielectric layer.

[0034] On the other hand, an electronic device is provided, and the electronic device includes a semiconductor structure formed by using the formation method of any of the foregoing semiconductor structures.

[0035] Embodiments of the present application provide a substrate, which includes a semiconductor substrate and a fin structure with a channel region formed on the semiconductor substrate. Then, a wet treatment process and a drying process are sequentially performed on the substrate. Next, the substrate after the wet treatment process and the drying process is sent into a processing chamber, where a chemical oxide removal process and a heat treatment process are sequentially performed on the substrate, and a channel protection layer is formed on the channel region of the fin structure. Thus, the channel protection layer is formed in situ on the channel region of the fin structure without contacting the external new environment, which not only avoids the elastic deformation of the fin structure caused by the above drying process, improves the process window of film deposition, but also avoids the deionized water cleaning process after heat treatment compared with the prior art, that is, simplifies the process flow of the semiconductor structure, improves the production efficiency, and also avoids the adverse effects of the deionized water cleaning process, improving the yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0037] Figure 1 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the present application;

[0038] Figure 2 is a cross-sectional view of a fin structure formed along the extending direction of the fin in the substrate provided by an embodiment of the present application;

[0039] Figure 3a is a cross-sectional view of the fin structure after sequential selective wet etching and drying provided by an embodiment of the present application;

[0040] Figure 3b is Figure 3a an image of the corresponding physical object;

[0041] Figure 4 is the Figure 3b image of the physical object after the physical object of the foregoing is processed by the processes (1) and (2) in step S105 provided by an embodiment of the present application;

[0042] Figure 5 is a cross-sectional view of the fin structure after epitaxial growth of a channel protection layer in the channel region provided by an embodiment of the present application;

[0043] Figure 6 is an application example of a conventional COR process in the preparation of a three-dimensional field effect transistor device with a fin structure in the related art;

[0044] Figure 7 It is another cross-sectional schematic diagram of the fin structure formed along the extending direction of the fin in the substrate provided by the embodiment of the present application;

[0045] Figure 8 It is another cross-sectional schematic diagram of the fin structure formed along the extending direction of the fin in the substrate provided by the embodiment of the present application;

[0046] Figure 9 It is a cross-sectional schematic diagram formed along the extending direction of the fin in the semiconductor structure provided by the embodiment of the present application. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0048] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe specific objects or the order of precedence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or server including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0049] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not imply that there must be a first element, component, region, layer, or part in the present application.

[0050] An embodiment of the present application provides a method for forming a semiconductor structure. The method includes providing a substrate, which includes a semiconductor substrate and a fin structure having a channel region formed on the semiconductor substrate, then sequentially performing a wet treatment process and a drying process on the substrate, then sending the substrate after the wet treatment process and the drying process into a processing chamber, and sequentially performing a chemical oxide removal process and a heat treatment process on the substrate in the processing chamber, and forming a channel protection layer on the channel region of the fin structure, thereby realizing in-situ formation of the channel protection layer on the channel region of the fin structure without contacting a new external environment. This not only avoids the elastic deformation of the fin structure caused by the above drying process, improves the process window of film deposition, but also can omit the deionized water cleaning process after the heat treatment compared with the prior art, that is, simplifies the process flow of the semiconductor structure, improves the production efficiency, and also avoids the adverse effects of the deionized water cleaning process, improving the yield of the semiconductor structure.

[0051] It should be noted that the semiconductor structure of the embodiment of the present application can be used to form three-dimensional field-effect transistor devices having fin structures, such as fin field-effect transistor (FinFET) devices, gate-all-around field-effect transistor (GAAFET) devices, etc. In the subsequent introduction of the embodiment of the present application, the semiconductor structure for forming a gate-all-around field-effect transistor GAAFET will be taken as an example for detailed introduction.

[0052] Please refer to Figure 1, which shows a schematic flow chart of a method for forming a semiconductor structure provided by an embodiment of the present application. The following will be combined with Figures 2 to 9 , and the method for forming the semiconductor structure provided by the embodiment of the present application will be described in detail.

[0053] Referring to Figure 1 , in step S101: Provide a substrate, which includes a semiconductor substrate and a fin structure formed on the semiconductor substrate. The fin structure has a channel region.

[0054] Among them, the semiconductor substrate can be a bulk semiconductor or a silicon-on-insulator (SOI) substrate, etc. It can be doped (for example, doped with a p-type dopant or an n-type dopant), or it can be undoped. Among them, the SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer or a silicon oxide layer, etc. The insulator layer is provided on a silicon substrate or a glass substrate. In a specific implementation, the semiconductor material of the semiconductor substrate can include: one or a combination of silicon, germanium, compound semiconductors, and alloy semiconductors. Among them, the compound semiconductor can be one or more of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and the alloy semiconductor can be one or more of silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide.

[0055] The semiconductor substrate can include a region for forming a P-type field effect transistor. Of course, it can also include a region for forming an N-type field effect transistor.

[0056] A fin structure is formed on the semiconductor substrate. The fin structure has a channel region. The channel region can be a silicon-based nanostructure, such as a nanosheet or a nanowire, which can be used as the semiconductor channel of the transistor of the semiconductor structure. The aspect ratio of the semiconductor channel can be greater than 17.

[0057] In some examples, the fin structure can further include source / drain regions formed on both sides of the channel region. The source / drain regions can include silicon or doped silicon, such as silicon doped with a p-type material (such as boron or gallium), or silicon doped with an n-type material (such as phosphorus or arsenic).

[0058] Continuing to refer to Figure 1 , in step S103: Perform a wet treatment process and a drying process on the substrate in sequence.

[0059] Among them, the wet treatment process can include wet cleaning and / or wet etching, and the fin structure in the substrate is wet etched and / or wet cleaned by using the wet treatment process. Specifically, an oxide layer (SiO2) is usually formed on the surface of the channel region of the fin structure after the wet treatment process.

[0060] Among them, the drying process is used to remove liquids such as moisture remaining on the surface of the semiconductor structure in the wet treatment process. In specific implementations, the semiconductor structure can be treated with hot isopropyl alcohol to remove the liquid on its surface to achieve the purpose of drying.

[0061] In some exemplary embodiments, the fin structure of the substrate includes alternately stacked channel nanomaterial layers and sacrificial nanomaterial layers, such as Figure 2 As shown in the cross-sectional schematic diagram of the fin structure formed along the extension direction of the fin in the substrate. Specifically, the fin structure 20 is formed on a semiconductor substrate (not shown in the figure). An active source region 21 and a drain region 22 are formed on the fin structure 20, and an adjacent initial channel region is formed between the source region 21 and the drain region 22. The initial channel region includes alternately stacked channel nanomaterial layers 231 and sacrificial nanomaterial layers 232.

[0062] Among them, the formation materials of the channel nanomaterial layer 231 and the sacrificial nanomaterial layer 232 are different, and the formation material of the channel nanomaterial layer 231 is the same as the formation material of the semiconductor substrate. Exemplarily, the formation materials of the channel nanomaterial layer 231 and the sacrificial nanomaterial layer 232 have different oxidation rates and / or etching selectivities.

[0063] In one example, the formation material of the channel nanomaterial layer 231 can be silicon (Si), and the formation material of the sacrificial nanomaterial layer 232 can be silicon germanium (SiGe). In another example, the formation material of the channel nanomaterial layer 231 can be silicon germanium (SiGe), and the formation material of the sacrificial nanomaterial layer 232 can be silicon (Si).

[0064] In specific implementations, the thickness of the channel nanomaterial layer 231 and the thickness of the sacrificial nanomaterial layer 232 can be the same or different. The sacrificial nanomaterial layer 232 is used to define the vertical distance between adjacent channel nanomaterial layers 231.

[0065] Among them, the source region 21 can include a silicon germanium (SiGe) material, and the drain region 22 can include a silicon phosphorus (SiP) material.

[0066] Such as Figure 2 As shown, an inner spacer layer 24 is formed between the source region 21 and the initial channel region and between the drain region 22 and the initial channel region. The inner spacer layer 24 can reduce the parasitic capacitance and protect the source region 21 and the drain region 22 from etching during the subsequent removal of the sacrificial nanomaterial layer 232. The formation material of the inner spacer layer 24 can include one or a combination of silicon nitride, silicon oxide, silicon oxynitride, carbon silicon oxide, carbon silicon nitride, carbon oxynitride.

[0067] In practical applications, in order not to affect the source region 21 and the drain region 22 during the subsequent processing of the initial channel region, an isolation layer 25 can be further formed on the source region 21 and the drain region 22. The forming material of the isolation layer 25 can include silicon oxide (such as silicon dioxide).

[0068] Furthermore, the wet treatment process and the drying process performed on the substrate in step S103 can include: performing selective wet etching on the substrate to remove the sacrificial nanomaterial layer between adjacent channel nanomaterial layers; performing a drying treatment process on the substrate after the selective wet etching.

[0069] Specifically, in the case where the forming material of the sacrificial nanomaterial layer 232 is silicon germanium (SiGe), an ammonia solution of ammonium hydroxide (NH4OH) or other suitable liquid etchant can be used to selectively etch away the sacrificial nanomaterial layer 232 while retaining the silicon (Si) channel nanomaterial layer 231 as the channel region. In the case where the forming material of the sacrificial nanomaterial layer 232 is silicon (Si), a hydrochloric acid solution (HCL) or other liquid etchant can be used to selectively etch away the sacrificial nanomaterial layer 232 while retaining the silicon germanium (SiGe) channel nanomaterial layer 231 as the channel region.

[0070] Taking the forming material of the channel nanomaterial layer 231 as silicon (Si) and the forming material of the sacrificial nanomaterial layer 232 as silicon germanium (SiGe) as an example. Refer to Figure 3a and Figure 3b , where Figure 3a shows a cross-sectional schematic diagram of the fin structure after sequential selective wet etching and drying, Figure 3b shows Figure 3a the image of the corresponding physical object. From Figure 3a and Figure 3b it can be seen that for the fin structure 30 after selective wet etching, in the channel region of the fin structure after the drying process, such as Figure 3a the channel nanomaterial layer 231 in undergoes elastic bending deformation, thereby causing defects in the substrate. The existence of such defects will narrow the process window of subsequent gap-filling.

[0071] The reason for the above-mentioned elastic bending deformation is that during the drying process, the liquid surface tension will act, and the magnitude of the liquid surface tension is strongly related to the liquid surface contact angle and the aspect ratio of the channel layer, as shown in the following formula (1):

[0072]

[0073] where F represents the liquid surface tension; d represents the gap distance between adjacent channel layers; θ represents the liquid surface contact angle; Denotes the aspect ratio of the channel layer. For GAAFET, it refers to the ratio of the length to the thickness of the nanosheet; σ denotes the Young's modulus of the material, which is a parameter of the material's inherent properties.

[0074] Furthermore, when the aspect ratio of the channel region in the fin structure is relatively large, such as exceeding 17, a large liquid surface tension will be generated during the drying process, causing the channel layer to undergo elastic bending deformation, resulting in the adjacent channel layers approaching each other, as Figure 3b indicated by the dashed box in. If the film filling in the subsequent process is directly based on the substrate with this defect, the electrical properties and yield of the semiconductor device will be reduced.

[0075] Based on this, after step S103 in the method for forming a semiconductor structure provided by the embodiments of the present application, the multiple processes in step S105 are sequentially performed, and these multiple processes are carried out in the same processing chamber. Specifically, continue to refer to Figure 1 In step S105: The substrate after the wet process and the drying process is sent into the processing chamber, and in the processing chamber, the substrate is sequentially subjected to a chemical oxide removal process and a heat treatment process, and a channel protection layer is formed on the channel region of the fin structure.

[0076] Specifically, in a relatively low negative pressure environment in the processing chamber, the substrate sent in is sequentially subjected to a chemical oxide removal process, a heat treatment process, and the process of forming the above-mentioned channel protection layer. That is to say, when the channel protection layer is formed, the substrate is always located in the processing chamber and does not contact the external new environment. Therefore, the process of forming the channel protection layer can be considered an in-situ formation process.

[0077] In some specific embodiments, step S105 can be implemented by sequentially performing the following processes (1) to (3) on the substrate. During the process of performing the following processes (1) to (3), the pressure in the processing chamber is maintained within a pressure range not exceeding 10 mTorr. Specifically, the process steps sequentially performed in the processing chamber include:

[0078] (1) Perform a chemical oxide removal process, which forms reaction by-products on the surface of the substrate;

[0079] (2) Perform a heat treatment process at a temperature not less than 380 °C to remove the reaction by-products from the surface of the substrate;

[0080] (3) Form a channel protection layer on the channel region of the fin structure.

[0081] Among them, in the above (1), the chemical oxide removal process may use ammonia gas and hydrogen fluoride gas as reaction gases to etch the silicon oxide layer on the exposed surface of the fin structure to form reaction by-products, and the reaction by-products are specifically ammonium fluorosilicate. The chemical reactions in this chemical oxide removal process include:

[0082] SiO2++4HF+4NH3→SiF4+2H2O+4NH3

[0083] SiF4+2HF+2NH3→(NH4)2SiF6

[0084] Among them, the silicon oxide in the silicon oxide layer first reacts with hydrogen fluoride gas under the catalysis of ammonia gas to generate SiF4, and then this SiF4 continues to react with hydrogen fluoride gas and ammonia gas to generate a volatile solid substance (NH4)2SiF6.

[0085] In specific implementation, the above chemical oxide removal process can be implemented within the temperature range of room temperature to 600 °C.

[0086] Among them, in the above (2), the heat treatment process can specifically be carried out within the temperature range of 380 °C to 600 °C, so that the reaction by-product ammonium fluorosilicate generated in the above (1) can be completely decomposed into gaseous substances for volatilization and removal. Specifically, the reaction by-product ammonium fluorosilicate decomposes according to the following chemical reaction within the temperature range of 380 °C to 600 °C:

[0087] (NH4)2SiF6→SiF4+2NH3+2HF

[0088] The gases SiF4, NH3, and HF decomposed in the above (2) are further pumped out of the processing chamber under a lower negative pressure of less than 10 mTorr in the processing chamber. It can be understood that the gases pumped out of the processing chamber may also include water vapor and carrier gas, so as to completely remove the reaction by-products, and there is no need to perform a process of deionized water cleaning after heat treatment.

[0089] See Figure 4 , which shows the physical image of the aforementioned Figure 3b after being processed by the processes (1) and (2) in the above step S105. It can be seen that after being processed by the processes (1) and (2) in the above step S105, the elastic bending deformation of the channel nanomaterial layer 231 is restored, thereby eliminating the defect that the adjacent channel layers in the substrate approach each other.

[0090] After the above (2) in the embodiment of the present application, the formation process of (3) is then carried out in situ in the processing chamber, that is, the channel protection layer is formed in situ in the channel region of the fin structure without breaking the vacuum and without contacting the external new environment. In this way, not only the adhesion between the channel protection layer and the channel material can be improved, but also the process flow of the semiconductor structure is simplified. Among them, the above (3) can be implemented in the temperature range of 380°C to 600°C. The channel protection layer can be a silicon-containing oxide layer, and this channel protection layer can provide an interaction interface for the subsequent formation of the gate structure.

[0091] In some exemplary embodiments, the above (3) implemented in the processing chamber can be epitaxially growing a channel protection layer on the channel region of the fin structure, which specifically may include: introducing a silicon source precursor gas into the processing chamber, and forming an epitaxial silicon layer on the surface of the channel nanomaterial layer based on this silicon source precursor gas; introducing oxygen into the processing chamber to perform a thermal oxidation treatment on the epitaxial silicon layer to generate a silicon oxide layer, and this silicon oxide layer serves as the channel protection layer for the corresponding channel region. In specific implementation, the silicon source precursor gas can be introduced into the processing chamber in the temperature range of 380°C to 600°C, so as to form an epitaxial silicon layer on the surface of the channel nanomaterial layer based on this silicon source precursor gas; then oxygen is introduced into the processing chamber in the temperature range of 380°C to 600°C to perform a thermal oxidation treatment on the epitaxial silicon layer to generate a silicon oxide layer.

[0092] See Figure 5 , which shows a cross-sectional schematic diagram after epitaxially growing a channel protection layer in the channel region of the fin structure, where the silicon oxide layer 51, that is, the channel protection layer, surrounds the outer surface of the channel nanomaterial layer 231 that has eliminated the elastic bending deformation. In specific implementation, the silicon source precursor gas can be silane, dichlorosilane (DCS) or similar silicon-containing gases, such as Si2H6, Si3H8, Si4H 10 , SiH3Cl, etc.

[0093] See Figure 6 , the conventional COR (Chemical Oxide Removal) process can be used to remove a large amount of oxides to form the shape of the fin and to remove a small amount of oxides to modify the corner regions in the preparation of three-dimensional field effect transistor devices with fin structures. Among them, the pressure for removing a large amount of oxides is a high chamber pressure exceeding 200 mTorr, and the temperature of the subsequent heat treatment (Post Heat Treatment, PHT) is 60°C to 80°C; the pressure for removing a small amount of oxides is a low chamber pressure of 50 mTorr - 200 mTorr, and the temperature of the subsequent heat treatment PHT is room temperature to 40°C. Under the process conditions of the conventional COR, such as Figure 6As shown, whether it is a large amount of oxide removal or a small amount of oxide removal, after PHT, it is necessary to break the vacuum and add an additional deionized water cleaning process to completely remove the reaction by-products. This not only makes the manufacturing process of the semiconductor structure complex and the production efficiency low, but also reduces the yield of the device.

[0094] The technical solution of the embodiment of the present application removes a small amount of oxide on the fin structure under the low process chamber pressure of not more than 10 mTorr and the high temperature process condition of not less than 380 °C, realizing the complete removal of the reaction by-products. Thus, the growth of the low temperature (not less than 380 °C) epitaxial channel protection layer can continue under the low process chamber pressure of not more than 10 mTorr, and then the process of breaking the vacuum and using deionized water for cleaning can be avoided. This not only simplifies the manufacturing process of the semiconductor structure and improves the production efficiency, but also, since the growth of the epitaxial channel protection layer is carried out without breaking the vacuum and without contacting the external new environment, the adhesion of the channel protection layer can be improved, and then the quality of the interaction interface for forming the gate structure can be improved, and the performance of the device can be improved.

[0095] In practical applications, the substrate in the foregoing step S101 may further include a dummy gate structure spanning the fin structure, as Figure 7 shown, the dummy gate structure 71 covers the initial channel region of the fin structure, and this dummy gate structure 71 is used to define the position and size of the subsequently formed gate structure. Specifically, the dummy gate structure 71 may include a dummy dielectric layer 711 (schematically shown in Figure 8 ) and a dummy electrode 712 formed on the dummy dielectric layer 711. The material for forming the dummy dielectric layer 711 may include silicon oxide (SiO2), and the material for forming the dummy electrode 712 may include amorphous silicon, polysilicon, or doped polysilicon.

[0096] Based on this, when the foregoing step S103 performs the wet treatment process and the drying process on the substrate in sequence, it may include: removing the dummy gate structure on the fin structure to expose the part of the fin structure covered by the dummy gate structure; performing selective wet etching on the exposed part of the fin structure to remove the sacrificial nanomaterial layer between adjacent channel nanomaterial layers; and performing a drying process on the substrate after the selective wet etching.

[0097] Among them, removing the dummy gate structure 71 may include removing the dummy electrode 712 to expose the underlying dummy dielectric layer 711, as Figure 8 shown, and then removing the dummy dielectric layer 711 shown in Figure 8 to expose the part of the fin structure covered by the dummy gate structure 71. This part of the fin structure will subsequently serve as the channel region of the fin structure, and then the fin structure 20 as shown in the foregoing Figure 2 can be obtained.

[0098] Among them, removing the dummy gate structure 71 may include one or more etching processes, such as wet etching, dry etching, or other etching techniques.

[0099] In some exemplary embodiments, after forming the channel protection layer on the channel region of the fin structure based on the foregoing step S105, a gate structure may further be formed on the channel protection layer, and the gate structure surrounds the outer surface of the nanochannel.

[0100] In some examples, Figure 7 The formation of the shown substrate may be as follows: forming a nano-stack structure above a semiconductor substrate, the nano-stack structure including alternating silicon layers and germanium silicide layers; then patterning the nano-stack structure to form fins separated by a shallow trench isolation (STI) layer; conformally forming an oxide layer above the portions of the fins protruding from the shallow trench isolation layer and above the top surface of the shallow trench isolation layer, and after forming the oxide layer, orthogonally forming a dummy gate structure across the fins by a patterning operation; removing the oxide layer not covered by the dummy gate structure, etching the regions of the fins on both sides of the dummy gate structure to form source / drain grooves; depositing an insulating material along the sidewalls and bottom of the source / drain grooves to form an inner spacer layer, depositing one or more epitaxial growth materials on the inner spacer layer to form source / drain regions, and forming an isolation layer on the source / drain regions.

[0101] As Figure 9 shown, a plurality of channel nanomaterial layers 231 extend through the gate structure 91, and the gate structure 91 covers all sides of each nanochannel to increase the control of the nanochannel and reduce the short-channel effect of the device.

[0102] Specifically, the gate structure 91 includes a dielectric layer (not shown in the figure) and a gate electrode (not shown in the figure). Among them, the dielectric layer is formed on the channel protection layer, and the gate electrode is formed on the dielectric layer. Further, the dielectric layer may include a high-k dielectric layer, and the high-k dielectric layer may include a high-k dielectric material (for example, a dielectric material with a k value greater than about 7.0), such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and their combinations, and the formation method thereof may adopt one method or a combination of multiple methods such as molecular beam deposition (MBD), ALD, and PECVD, etc. The gate electrode is deposited on the high-k dielectric layer and may include a liner layer, a work function adjustment layer, and a conductive material. The liner layer may include TiN, TiO, TaN, TaC, their combinations, or their multilayers, etc., and may be formed by PVD, CVD, ALD, or their combinations, etc. The work function layer may include TiN, WN, TaN, Ru, Co, their combinations, or their multilayers, etc., and may be formed using PVD, CVD, ALD, or their combinations, etc. The conductive filling material may include Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, their alloys, their combinations, or their multilayers, etc., and may be formed by PVD, CVD, ALD, electroplating, or their combinations, etc.

[0103] In the embodiment of the present application, by sequentially performing a chemical oxide removal process, a heat treatment process, and a channel protection layer formation process on the dried substrate in a processing chamber with a pressure less than 10 mTorr and a temperature between 380 °C and 600 °C, not only can the defect of the elastic bending deformation of the channel layer caused by the liquid surface tension during the drying process be repaired, the process window of the subsequent film filling be improved, and the yield of the device be increased, but also in the above process conditions of the processing chamber in the embodiment of the present application, the reaction by-products can be completely removed, realizing the epitaxial growth of the channel protection layer without breaking the vacuum and without contacting the external new environment, that is, improving the interface quality of the channel region, thereby improving the performance of the device, and also being able to avoid the process of cleaning the reaction by-products with deionized water after the heat treatment, greatly simplifying the process flow and improving the preparation efficiency of the semiconductor structure.

[0104] The embodiment of the present application also provides a semiconductor structure formed based on the foregoing formation method, and the semiconductor structure includes:

[0105] A semiconductor substrate;

[0106] A fin structure located on the semiconductor substrate, and the fin structure has a channel region;

[0107] A channel protection layer located on the channel region of the fin structure.

[0108] Among them, the semiconductor substrate can be a bulk semiconductor or a silicon-on-insulator semiconductor. The semiconductor substrate can include regions for forming P-type field-effect transistors, and can of course also include regions for forming N-type field-effect transistors.

[0109] In some exemplary embodiments, the fin structure includes a plurality of stacked and spaced channel nanomaterial layers. An oxide layer obtained by oxidizing the epitaxial silicon layer is formed on the surface of each channel nanomaterial layer, and this oxide layer serves as the channel protection layer for the corresponding channel region.

[0110] In some exemplary embodiments, the semiconductor structure further includes a gate structure formed on the channel protection layer. The gate structure includes a dielectric layer and a gate electrode. Among them, the dielectric layer is formed on the channel protection layer, and the dielectric layer can include a high-k dielectric layer. The gate electrode is formed on the dielectric layer.

[0111] Specifically, the channel protection layer covers all sides of each nanoscale channel. The plurality of channel nanomaterial layers extend through the gate structure, and the gate structure covers all sides of each nanoscale channel to increase the control of the nanoscale channel and reduce the short-channel effect of the device.

[0112] Among them, the material for forming the plurality of channel nanomaterial layers is the same as the material for forming the semiconductor substrate, such as silicon (Si). The thicknesses of the plurality of channel nanomaterial layers can be the same or different.

[0113] In some examples, the semiconductor structure may further include source / drain regions formed on the fin structure and adjacent to the gate structure. Exemplarily, an inner spacer layer may also be formed between the source / drain regions and the gate structure.

[0114] In the semiconductor structure of the embodiment of the present application, the channel protection layer improves the interface quality of the channel region, thereby improving the performance of the device.

[0115] Correspondingly, the embodiment of the present application further provides an electronic device, and the electronic device includes any one of the semiconductor structures described above in the embodiment of the present application.

[0116] Since the working performance of the semiconductor device is better, and the electronic device uses the semiconductor device, this correspondingly improves the performance of the electronic device. Among them, the electronic device can be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc., or can also be an intermediate product having the semiconductor device, for example: a device main board having the semiconductor device, etc.

[0117] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate includes a semiconductor substrate and fin structures formed on the semiconductor substrate, and the fin structures have channel regions; Successively performing a wet treatment process and a drying process on the substrate; Feeding the substrate after the wet treatment process and the drying process into a processing chamber, and successively performing a chemical oxide removal process and a heat treatment process on the substrate in the processing chamber, and forming a channel protection layer on the channel regions of the fin structures.

2. The forming method according to claim 1, characterized in that, The wet treatment process includes wet cleaning and / or wet etching.

3. The forming method according to claim 2, wherein The fin structures include alternately stacked channel nanomaterial layers and sacrificial nanomaterial layers; the successively performing a wet treatment process and a drying process on the substrate includes: Performing selective wet etching on the substrate to remove the sacrificial nanomaterial layers between adjacent channel nanomaterial layers; Performing a drying process on the substrate after the selective wet etching.

4. The forming method according to claim 3, wherein The materials for forming the channel nanomaterial layers are different from the materials for forming the sacrificial nanomaterial layers, and the material for forming the sacrificial nanomaterial layers is germanium silicon.

5. The forming method according to claim 3, wherein The substrate further includes dummy gate structures spanning the fin structures; the performing selective wet etching on the substrate to remove the sacrificial nanomaterial layers between adjacent channel nanomaterial layers includes: Removing the dummy gate structures on the fin structures to expose the part of the fin structures covered by the dummy gate structures; Performing selective wet etching on the exposed part of the fin structures to remove the sacrificial nanomaterial layers between adjacent channel nanomaterial layers.

6. The forming method according to any one of claims 3-5, characterized in that, The forming a channel protection layer on the channel regions of the fin structures includes: Introducing a silicon source precursor gas into the processing chamber, and forming an epitaxial silicon layer on the surface of the channel nanomaterial layers based on the silicon source precursor gas; Introducing oxygen into the processing chamber to perform thermal oxidation treatment on the epitaxial silicon layer to generate a silicon oxide layer; the silicon oxide layer serves as the channel protection layer for the corresponding channel regions.

7. The forming method according to claim 1, wherein The forming method further includes: Forming a gate structure on the channel protection layer; the gate structure includes a dielectric layer and a gate electrode, the dielectric layer is formed on the channel protection layer, and the gate electrode is formed on the dielectric layer.

8. The forming method according to claim 1, wherein The successively performing a chemical oxide removal process and a heat treatment process on the substrate in the processing chamber, and forming a channel protection layer on the channel regions of the fin structures includes: When the pressure in the processing chamber is maintained at no more than 10 mTorr, successively performing a chemical oxide removal process and a heat treatment process on the substrate in the processing chamber, and forming a channel protection layer on the channel regions of the fin structures; Wherein, the chemical oxide removal process forms reaction by-products on the surface of the substrate, and the heat treatment process removes the reaction by-products from the surface of the substrate at a temperature condition of not less than 380 °C.

9. The forming method according to claim 8, wherein The performing the chemical oxide removal process includes: Etching the silicon oxide layer on the exposed surface of the fin structures with ammonia gas and hydrogen fluoride gas as reaction gases to form the reaction by-products.

10. A semiconductor structure, characterized in that, Formed by using any one of the forming methods in claims 1-9, including: A semiconductor substrate; Fin structures located on the semiconductor substrate, and the fin structures have channel regions; A channel protection layer located on the channel region of the fin structure.

11. The semiconductor structure according to claim 10, wherein The fin structure includes a plurality of stacked and spaced channel nanomaterial layers, and a silicon oxide layer obtained by oxidizing an epitaxial silicon layer is formed on the surface of each channel nanomaterial layer, and the silicon oxide layer serves as the channel protection layer for the corresponding channel region.

12. The semiconductor structure according to claim 10, wherein, It further includes: A gate structure located on the channel protection layer; the gate structure includes a dielectric layer and a gate electrode, the dielectric layer is formed on the channel protection layer, and the gate electrode is formed on the dielectric layer.

13. An electronic device, characterized in that, The electronic device includes a semiconductor structure formed by using the formation method according to any one of claims 1 to 9.

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