Planar complementary metal-oxide-semiconductor field effect transistor structure for reducing leakage and planar area

Abstract

The invention discloses a planar complementary metal-oxide-semiconductor field effect transistor structure, which is used in a peripheral circuit of a dynamic random access memory chip and a sensing amplifier of an array core circuit of the dynamic random access memory chip, and comprises a planar P-type metal-oxide-semiconductor field effect transistor, the substrate has a first conductive region; the planar N-type metal-oxide-semiconductor field effect transistor is provided with a second conductive region; the cross-shaped local isolation region is positioned between the planar P-type metal-oxide-semiconductor field effect transistor and the planar N-type metal-oxide-semiconductor field effect transistor; wherein the cross-shaped local isolation region comprises a horizontally extending isolation region, and the horizontally extending isolation region is in contact with the bottom side of the first conductive region and the bottom side of the second conductive region. The invention also can be similarly applied to a transistor of a complementary metal-oxide-semiconductor logic circuit.

Description

Technical Field

[0001] The present invention relates to new planar transistors and planar complementary metal-oxide-semiconductor field-effect transistor (MOSFET) structures, and particularly to planar transistors and / or planar complementary MOSFET structures used in the peripheral circuits or sense amplifiers of dynamic random access memories (DRAMs), which can reduce leakage current, reduce short-channel effects, and prevent latch-up effects. Background Art

[0002] Although advanced technology nodes (such as 3 nm to 7 nm) are frequently used in high-performance computing applications (such as artificial intelligence (AI), central processing units (CPUs), graphics processing units (GPUs), etc.), mature technology nodes (such as 20 nm to 30 nm) are still popular in many integrated circuit (IC) applications such as power management ICs, microcontroller units (MCUs), or DRAM chips. Taking DRAM as an example, currently most customized DRAMs are still manufactured using mature technology nodes (such as 12 nm to 30 nm), and all the transistors in the DRAM chip 17 (as Figure 1A shown), including the transistors in the peripheral circuit 171 (at least including data / address input / output circuits, address decoders, command logics, and update circuits, etc.) and the transistors in the array core circuit 172 (including storage memory arrays, sense amplifiers, etc.), are still planar transistors.

[0003] Figure 1BThe cross-sectional view of the most advanced Complementary Metal-Oxide-Semiconductor Field-Effect Transistor (CMOSFET) 10 most widely used in the peripheral circuit of the DRAM chip and the sense amplifier of the array core circuit of the DRAM chip is marked. The CMOSFET 10 includes a planar N-type metal-oxide-semiconductor (NMOS) transistor 11 and a planar P-type metal-oxide-semiconductor (PMOS) transistor 12. Among them, a Shallow Trench Isolation (STI) region 13 is located between the NMOS transistor 11 and the PMOS transistor 12. The gate structure 14 of the NMOS transistor 11 or the PMOS transistor 12 uses some conductive materials (such as metal, polysilicon, or polysilicide, etc.) above an insulator (such as oxide, oxide / nitride, or some high-k dielectrics, etc.), formed on the top of the Complementary Metal-Oxide-Semiconductor (CMOS), and its sidewalls are isolated from the sidewalls of other transistors by using insulating materials (such as oxide, or oxide / nitride, or other dielectrics). For the planar NMOS transistor 11, it has a source region and a drain region, which are formed by implanting N-type dopants into a P-type substrate (or P-type well) through ion implantation and thermal annealing techniques to form two separate N+ / P junction regions. For the planar PMOS transistor 12, the source region and the drain region are formed by implanting P-type dopants into an N-type well through ion implantation to form two separate P+ / N junction regions. Moreover, in order to reduce impact ionization and hot carrier injection before the highly doped N+ / P or P+ / N junction, a lightly doped-drain (LDD) region 15 is usually formed under the gate structure.

[0004] On the one hand, during the aforementioned thermal annealing process, the implanted N-type or P-type dopants in the CMOSFET 10 will inevitably diffuse in different directions and expand the areas of the source region and the drain region. And when forming a capacitor above the access transistor of the array core circuit of the DRAM chip, another thermal annealing process will be carried out to reduce the connection resistance between the capacitor and the access transistor. This second thermal annealing process will again cause the diffusion of N-type or P-type dopants and increase the areas of the source region and the drain region. The larger the areas of the source region and the drain region caused by the thermal annealing process, the effective channel length between the source region and the drain region ( Figure 1BThe shorter the effective channel length (Leff) shown, this reduced effective channel length Leff will lead to the short channel effect (SCE). Therefore, in order to reduce the impact of the short channel effect, a longer gate length is usually retained to accommodate the diffusion of N-type or P-type dopants caused by thermal annealing. Taking the 25nm technology node (λ) as an example, the retained gate length will be approximately 100nm, almost 4 times the technology node λ.

[0005] On the other hand, since the NMOS transistor 11 and the PMOS transistor 12 are respectively located in some adjacent regions of the P-type substrate and the N-type well formed adjacent to each other, a parasitic junction structure of a parasitic bipolar device called N+ / P / N / P+ ( Figure 1B The path marked by the dashed line in is called the N+ / P / N / P+ latching path) is formed. Its profile starts from the N+ region of the NMOS transistor 11, goes to the P-type well, to the adjacent N-type well, and further up to the P+ region of the PMOS transistor 12.

[0006] Once significant noise occurs at the N+ / P junction or the P+ / N junction, an abnormally large current may flow through this N+ / P / N / P+ junction, which may stop some operations of the CMOS circuit and cause the failure of the entire chip. This abnormal phenomenon called the latching effect is harmful to the operation of the CMOS and must be avoided. One way to increase the resistance to the latching effect, which is indeed a weakness of the CMOS, is to increase the distance between the N+ region and the P+ region ( Figure 1B marked as the latching distance in ), and both the N+ region and the P+ region must be designed to be isolated by some vertical oxides (or other suitable insulating materials) used as isolation regions, which are usually the shallow trench isolation region 13. Taking the 25nm technology node (λ) as an example, the retained latching distance will be approximately 500nm, almost 20 times the technology node λ. A more serious effort to avoid the latching effect must design a protection spacer structure to further increase the distance between the N+ region and the P+ region, and / or additional N+ regions or P+ regions must be added to collect abnormal charges from the noise source. These multiple isolation schemes will always increase the additional planar area, sacrificing the chip size of the CMOS circuit.

[0007] Current DRAM designs using planar transistors or complementary MOSFETs also introduce or exacerbate other problems:

[0008] (1) All junction leakage caused by junction formation processes such as forming a lightly doped drain (LDD) structure into the substrate / well region, forming an N+ source / drain structure into a P-type substrate, and forming a P+ source / drain structure into an N-type well is becoming increasingly difficult to control because leakage current occurs in the peripheral and bottom regions, and ion implantation causes lattice defects that create additional damage in these regions that is difficult to repair, such as hole and electron traps.

[0009] (2) In addition, since the ion implantation used to form the LDD structure (or N+ / P or P+ / N junction) works like an impact to directly insert ions from the top of the silicon surface straight down into the substrate, it is difficult to create a uniform material interface with few defects from the source and drain regions to the channel and the substrate bulk region because the doping concentration is non-uniformly distributed vertically from the upper surface with a higher doping concentration down to the junction region with a lower doping concentration.

[0010] (3) It is becoming increasingly difficult to align the LDD junction edge perfectly with the edge of the transistor gate structure using only the conventional self-alignment method formed using a gate, spacers, and ion implantation. In addition, the thermal annealing process used to remove ion implantation damage must rely on high-temperature processing techniques such as rapid thermal annealing methods using various energy sources or other thermal processes, so a problem that results is gate-induced drain leakage (GIDL). As Figure 1C shown (cited from: A. Sen and J. Das, “MOSFET GIDL Current Variation with Impurity Doping Concentration – A Novel Theoretical Approach” IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO. 5, MAY 2017), in a metal-oxide-semiconductor field-effect transistor structure with a thin oxide near the gate and drain / source regions, there is a parasitic metal-gated diode, and the formation of the parasitic metal-gated diode from the gate to the source / drain region causes the initiation of drain leakage current GIDL, and although the drain leakage current GIDL should be minimized to reduce leakage current, the drain leakage current GIDL is difficult to control; other problems that arise are difficulty in controlling the effective channel length, and thus difficulty in minimizing the short-channel effect.

[0011] (4) Since it is difficult to make the vertical length of the shallow trench isolation structure deeper while the planar width of the device isolation region must be reduced (otherwise it will cause a poor depth and aspect ratio of the opening for the integration processes of etching, filling, and planarization), the ratio of the planar isolation distance reserved between the N+ region and the P+ region of adjacent transistors to prevent latch-up in the reduced λ cannot be reduced, but will instead increase. Therefore, it is harmful to the reduction of the chip area when shrinking the CMOS device. Summary of the Invention

[0012] The present invention discloses several new concepts for understanding new planar transistors and planar complementary MOSFET structures, especially used in the peripheral circuits of DRAM chips and sense amplifiers in the array core circuits of DRAM chips, which greatly improve or even solve most of the above problems, such as minimizing leakage current, increasing channel conduction performance and control, optimizing the functions of the source region and the drain region, such as enhancing the conductivity of the source region and the drain region for metal interconnect components and the closest physical integrity to the channel region with a seamless and orderly crystal lattice match, increasing the immunity of the CMOS circuit to latch-up, and minimizing the planar area of the layout isolation region between NMOS and PMOS to avoid latch-up.

[0013] According to one objective of the present invention, a DRAM chip or circuit includes: a semiconductor substrate having a semiconductor surface; an array core circuit having a sense amplifier circuit and a plurality of dynamic random access memory cells electrically coupled to the sense amplifier circuit; and a peripheral circuit electrically coupled to the array core circuit. Wherein, the sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure, and the complementary MOSFET structure includes: a planar P-type MOSFET having a first conductive region; a planar N-type MOSFET having a second conductive region; and a cross-shaped local isolation region located between the planar P-type MOSFET and the planar N-type MOSFET. Wherein, the cross-shaped local isolation region includes a horizontally extending isolation region located below the semiconductor surface, and the horizontally extending isolation region contacts the bottom sides of the first conductive region and the second conductive region.

[0014] According to one aspect of the present invention, the complementary MOSFET structure further includes a first recess formed below the semiconductor surface, and the first recess accommodates the first conductive region.

[0015] According to one aspect of the present invention, the first conductive region includes an undoped semiconductor region and / or a lightly doped semiconductor region, which is independent of the semiconductor substrate.

[0016] According to one aspect of the present invention, the undoped semiconductor region or the lightly doped semiconductor region is adjacent to a channel region of the planar P-type MOSFET.

[0017] According to one aspect of the present invention, the first conductive region further includes a heavily doped semiconductor region located in the first recess, wherein the lightly doped semiconductor region and the heavily doped semiconductor region are formed to have the same lattice structure.

[0018] According to one aspect of the present invention, the first conductive region further includes a metal region located in the first recess and adjacent to the heavily doped semiconductor region.

[0019] According to one aspect of the present invention, the complementary MOSFET structure further includes a first recess formed below the semiconductor surface, and the first recess accommodates a first portion of the horizontally extending isolation region.

[0020] According to one aspect of the present invention, the planar P-type MOSFET further includes a gate region located above the semiconductor surface, and an edge of the gate region is aligned or substantially aligned with an edge of the first conductive region.

[0021] According to one aspect of the present invention, the planar P-type MOSFET further includes a gate region, and the entire first portion of the horizontally extending isolation region is not directly located below the gate structure.

[0022] According to one aspect of the present invention, the planar P-type MOSFET further includes a gate region, and less than 5% of the first portion of the horizontally extending isolation region is directly located below the gate structure.

[0023] According to one aspect of the present invention, the horizontally extending isolation region is a composite isolation region.

[0024] According to one aspect of the present invention, the composite isolation region includes an oxide layer and a nitride layer, and the nitride layer is located above the oxide layer.

[0025] According to one aspect of the present invention, a vertical depth of the oxide layer is less than a vertical depth of the nitride layer.

[0026] According to one aspect of the present invention, the horizontally extending isolation region includes a first horizontally extending isolation region and a second horizontally extending isolation region. The first horizontally extending isolation region shields the bottom side of the first conductive region from the semiconductor substrate, and the second horizontally extending isolation region shields the bottom side of the second conductive region from the semiconductor substrate.

[0027] According to one aspect of the present invention, the cross-shaped local isolation region includes a vertically extending isolation region located between the first horizontally extending isolation region and the second horizontally extending isolation region. Wherein, a vertical depth of the vertically extending isolation region is greater than a sum of a vertical depth of the first horizontally extending isolation region and a vertical depth of the first conductive region.

[0028] According to another object of the present invention, a DRAM circuit formed at a technology node λ according to the present invention includes: a semiconductor substrate having a semiconductor surface; an array core circuit having a sense amplifier circuit and a plurality of dynamic random access memory cells, the plurality of dynamic random access memory cells being coupled to the sense amplifier circuit; and a peripheral circuit electrically coupled to the array core circuit. Among them, the sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure, and the complementary MOSFET structure includes: a planar P-type MOSFET including a first source region, a first drain region, and a first gate region, the first gate region being located above the semiconductor surface; and a planar N-type MOSFET including a second source region, a second drain region, and a second gate region, the second gate region being located above the semiconductor surface. Among them, the first source region or the first drain region includes a lightly doped semiconductor region and a heavily doped semiconductor region, and the heavily doped semiconductor region is laterally adjacent to the lightly doped semiconductor region; wherein a dynamic random access memory cell includes an access transistor and a storage capacitor, and the access transistor includes a third source region, a third drain region, and a third gate region, and the third source region or the third drain region includes a lightly doped semiconductor region and a heavily doped semiconductor region, and the heavily doped semiconductor region is vertically adjacent to the lightly doped semiconductor region.

[0029] According to an aspect of the present invention, one edge of the first gate region is aligned or substantially aligned with one edge of the first source region, and the other edge of the first gate region is aligned or substantially aligned with one edge of the first drain region.

[0030] According to an object of the present invention, the complementary MOSFET structure further includes a local isolation region located between the planar P-type MOSFET and the planar N-type MOSFET, and the local isolation region shields a highly doped P+ region in the first source region or the first drain region from the semiconductor substrate.

[0031] According to an aspect of the present invention, the local isolation region includes a vertically extending isolation region and a horizontally extending isolation region, and the latching path between the planar P-type MOSFET and the planar N-type MOSFET depends at least on a bottom length of the horizontally extending isolation region.

[0032] According to another object of the present invention, a DRAM circuit according to the present invention includes: a semiconductor substrate having a semiconductor surface; an array core circuit having a sense amplifier circuit and a plurality of dynamic random access memory cells, the plurality of dynamic random access memory cells being coupled to the sense amplifier circuit; and a peripheral circuit electrically coupled to the array core circuit. Each dynamic random access memory cell includes an access transistor and a storage capacitor. The sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure, and the complementary MOSFET structure includes: a planar P-type MOSFET including a first source region, a first drain region, and a first gate region, the first gate region being located above the semiconductor surface; and a planar N-type MOSFET including a second source region, a second drain region, and a second gate region, the second gate region being located above the semiconductor surface. Wherein, the access transistor includes a third source region, a third drain region, and a third gate region, and at least a portion of the third gate region is located below the semiconductor surface; and the first source region and the first drain region have a first lattice structure, the third source region and the third drain region have a second lattice structure, and the first lattice structure is different from the second lattice structure. Moreover, the first source region or the first drain region includes a lower surface that is lower than a lower surface of the first gate region, and the third source region or the third drain region includes a lower surface that is higher than a lower surface of the third gate region.

[0033] According to an aspect of the present invention, the lower surface included in the third source region or the third drain region is aligned or substantially aligned with an upper surface of the third gate region.

[0034] According to an aspect of the present invention, the first source region and the first drain region are independent of the semiconductor substrate, and the third source region and the third drain are independent of the semiconductor substrate.

[0035] According to an aspect of the present invention, wherein the semiconductor substrate is a silicon substrate, the first source region and the first drain region are selectively grown and laterally extended from the (110) crystal plane of the silicon substrate, and the third source region and the third drain region are selectively grown and vertically extended from the (100) crystal plane of the silicon substrate.

[0036] After reading the following detailed description of the preferred embodiments shown in the various figures, the above and other objects of the present invention will undoubtedly be apparent to those of ordinary skill in the art to which the present invention pertains. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given in conjunction with the accompanying drawings, wherein:

[0038] Figure 1A is a drawing illustrating a circuit diagram of a DRAM chip.

[0039] Figure 1B is a drawing showing a cross-sectional view of a conventional CMOS structure.

[0040] Figure 1C is a drawing showing a parasitic metal gate diode formed in the gate-to-source / drain region of a MOSFET and the GIDL problem in the MOSFET.

[0041] Figure 2A and Figure 2B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) after depositing a pad nitride layer and forming a shallow trench isolation component.

[0042] Figure 3A and Figure 3B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) after defining the gate length.

[0043] Figure 3C and Figure 3D is a drawing showing a top view and a cross-sectional view along the section line (X-axis) of another embodiment after forming a shallow trench for the channel region.

[0044] Figure 3E and Figure 3F is a drawing showing a top view and a cross-sectional view along the section line (X-axis) of another embodiment after selectively forming the channel region.

[0045] Figure 3G and Figure 3H is a drawing showing a top view and a cross-sectional view along the section line (X-axis) of another embodiment after forming a shallow trench with an arc shape for the channel region.

[0046] Figure 3I and Figure 3J is a drawing showing a top view and a cross-sectional view along the section line (X-axis) of another embodiment after selectively forming the channel region in a shallow trench with an arc shape.

[0047] Figure 4A and Figure 4B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) after forming the gate conductive region.

[0048] Figure 5A and Figure 5B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) after forming the gate covering region.

[0049] Figure 6A and Figure 6B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) after removing the pad nitride and pad oxide outside the gate region.

[0050] Figure 7A and Figure 7B is a drawing showing a top view and a cross-sectional view along a sectional line (X-axis) after forming spacers on sidewalls of a gate region.

[0051] Figure 8A and Figure 8B is a drawing showing a top view and a cross-sectional view along a sectional line (X-axis) after forming a recess outside a gate region.

[0052] Figure 9A and Figure 9B is a drawing showing a top view and a cross-sectional view along a sectional line (X-axis) after forming a local isolation layer in a recess.

[0053] Figure 10A and Figure 10B is a drawing showing a top view and a cross-sectional view along a sectional line (X-axis) after laterally growing a semiconductor region from a sidewall exposed in a recess.

[0054] Figure 10C is a drawing showing a cross-sectional view along a sectional line (X-axis) of another embodiment after laterally growing a semiconductor region from a sidewall exposed in a recess.

[0055] Figure 10D and Figure 10E is a drawing showing a cross-sectional view along a sectional line (X-axis) after laterally growing a semiconductor region from a sidewall exposed in a recess according to another embodiment.

[0056] Figure 11A and Figure 11B is a drawing showing a top view and a cross-sectional view along a sectional line along a vertical dotted line of an embodiment of a planar CMOS structure in a peripheral circuit / sense amplifier of a DRAM chip according to the present invention.

[0057] Figure 12 is a drawing showing a conventional CMOS structure having N+ regions and P+ regions not completely isolated by an insulator.

[0058] Figure 13A and Figure 13B is a drawing showing a top view and a cross-sectional view along a sectional line along a horizontal dotted line of another embodiment of a planar CMOS structure in a peripheral circuit / sense amplifier of a DRAM chip according to the present invention.

[0059] Figure 14 is a drawing showing a potential latch path of a conventional CMOS structure from an N+ / P junction through a P-well / N-well junction to an N / P+ junction structure.

[0060] Figure 15Ais a cross-sectional view of an access transistor in an array core circuit of a DRAM chip according to the present invention.

[0061] Figure 15B is a cross-sectional view of an access transistor in an array core circuit of a DRAM chip according to the present invention after forming a recess for accommodating a source region / drain region.

[0062] Figures 16 to 18 is a cross-sectional view of the formation steps of a semiconductor gate of a proposed NMOS transistor.

[0063] Figures 19 to 21 is a cross-sectional view of the formation steps of a semiconductor gate of a proposed PMOS transistor.

[0064] Figure 22A is a cross-sectional view of a conventional polysilicon gate transistor.

[0065] Figure 22B is a cross-sectional view of a proposed semiconductor gate transistor according to the present invention.

[0066] Figure 23A Marks the electron backscatter diffraction (EBSD) results of the amorphous silicon layer after annealing in a real sample structure, Figure 23B Shows the transmission electron microscopy (TEM) results of the amorphous silicon layer after annealing, Figure 23C Shows the X-ray diffraction (XRD) results of two specified regions in the amorphous silicon layer after annealing.

[0067] Reference numerals:

[0068] 10: CMOSFET

[0069] 11: NMOS transistor

[0070] 12: PMOS transistor

[0071] 13: Shallow trench isolation region

[0072] 14: Gate structure

[0073] 15: LDD region

[0074] 17: DRAM chip

[0075] 21: Shallow trench isolation component

[0076] 22: Pad oxide layer

[0077] 23: Contact nitride layer

[0078] 24: Channel region

[0079] 31: Patterning photoresist

[0080] 32: Gate receiving trench

[0081] 36: Vertical side surface

[0082] 41: Oxide layer

[0083] 42: Nitride layer

[0084] 70: Cross-shaped LISS

[0085] 71: Vertically extending isolation region

[0086] 72: First horizontally extending isolation region

[0087] 73: Second horizontally extending isolation region

[0088] 171: Peripheral circuit

[0089] 172: Array core circuit

[0090] 201: Substrate

[0091] 202: Shallow trench isolation region

[0092] 204: Well region

[0093] 208A: U-shaped channel region

[0094] 208B: U-shaped channel region

[0095] 209: Gate dielectric layer

[0096] 210A: Gate conductive region

[0097] 210B: Gate conductive region

[0098] 213A: Source region

[0099] 213B: Drain region

[0100] 213C: Source region

[0101] 214A: Dielectric gate covering component

[0102] 214B: Dielectric gate covering component

[0103] 216A: First recess

[0104] 216B: Second recess

[0105] 216C: Third recess

[0106] 217A: LDD region

[0107] 217B: LDD region

[0108] 217C: LDD region

[0109] 218A: Heavily doped region

[0110] 218B: Heavily doped region

[0111] 218C: Heavily doped region

[0112] 331: Gate dielectric layer

[0113] 332: Heavily doped polysilicon

[0114] 333: Titanium / titanium nitride layer

[0115] 334: Tungsten layer

[0116] 335: Nitride capping layer

[0117] 336: Oxide capping layer

[0118] 341: Thin nitride sublayer

[0119] 342: Thin oxide sublayer

[0120] 343: Thin oxide sublayer

[0121] 411: Oxide layer

[0122] 412: Oxide layer

[0123] 430: First semiconductor region

[0124] 431: N+ doped region

[0125] 432: N+ doped region

[0126] 441: P+ doped region

[0127] 442: P+ doped region

[0128] 501: Vertical semiconductor sidewall

[0129] 502: Vertical semiconductor sidewall

[0130] 4301: Vertical P-type layer

[0131] 3321: Thin layer of undoped or doped amorphous silicon (or polysilicon)

[0132] 3322: Larger silicon layer of the die

[0133] 3323: In-situ N+ doped silicon

[0134] 4302: LDD region

[0135] BL: Bit line

[0136] C1: Storage capacitor

[0137] C2: Storage capacitor

[0138] Leff: Effective channel length

[0139] Lgate: Gate length

[0140] OSS: Original silicon surface

[0141] Xn, Xp: Distance Detailed implementation manners

[0142] The present invention discloses a planar transistor and a planar complementary MOSFET structure, especially for use in the peripheral circuit of a DRAM chip and the sense amplifier in the array core circuit of a DRAM chip. The manufacturing methods of the proposed planar NMOS transistor and planar PMOS transistor are exemplarily described as follows:

[0143] Step 10: Start.

[0144] Step 20: Based on a semiconductor substrate, define the active regions of the NMOS transistor and the PMOS transistor, and form a deep shallow trench isolation structure.

[0145] Step 30: Form a gate structure above the original semiconductor surface of the semiconductor substrate.

[0146] Step 40: Form spacers to cover the gate structure, and form recesses in the semiconductor substrate.

[0147] Step 50: Form a local isolation layer in the recesses.

[0148] Step 60: Expose the sidewalls of the silicon in the recesses, and laterally grow semiconductor regions from the exposed silicon sidewalls in the recesses to form the source regions and drain regions of the planar NMOS transistor and the planar PMOS transistor.

[0149] Please refer to Figure 2A and Figure 2B , step 20 may include:

[0150] Step 202: Form a pad oxide layer 22, and deposit a pad nitride layer 23.

[0151] Step 204: Define the active regions of the planar NMOS transistors and planar PMOS transistors using patterned photo-resistance (PR), and remove the portion of the silicon material in the semiconductor substrate outside the patterns of the plurality of active regions to create temporary trenches.

[0152] Step 206: Deposit an oxide layer in the created temporary trenches, and then etch back and planarize the oxide layer to form the shallow trench isolation component 21, wherein the upper surface of the shallow trench isolation component 21 is aligned with the upper surface of the pad nitride layer 23, as Figure 2B shown, which is a cross-sectional view along the Figure 2A X-axis profile line in

[0153] Please refer to Figures 3A to 3B to Figures 5A to 5B , the step 30 of forming the gate structure may include:

[0154] Step 302: Use another patterned photo-resistance 31 to define the gate length Lgate of the gate regions of the planar NMOS transistors and planar PMOS transistors, and then remove the portions of the pad oxide layer 22 and the pad nitride layer 23 not covered by the photo-resistance to form the gate receiving trench 32, as Figure 3A and Figure 3B shown, wherein, Figure 3B is a cross-sectional view along the Figure 3A X-axis profile line in

[0155] Step 304: Then, form a gate dielectric layer 331 (such as a thermal oxide or a high-k material), highly doped polysilicon 332 (N+ polysilicon for MOS and P+ polysilicon for MOS), a titanium / titanium nitride (Ti / TiN) layer 333, and a tungsten (W) layer 334 in the gate receiving trench 32, as Figure 4A and Figure 4B shown, wherein, Figure 4B is a cross-sectional view along the Figure 4A X-axis profile line in

[0156] Step 306: Form a nitride capping layer 335 and an oxide capping layer 336 above the tungsten layer 334 to complete the gate regions of the NMOS transistors and PMOS transistors, as Figure 5A and Figure 5B shown, wherein, Figure 5B is a cross-sectional view along the Figure 5A X-axis profile line in

[0157] Next, please refer to Figures 6A to 6B to Figures 8A to 8B , the step 40 may include:

[0158] Step 402: Remove the pad oxide layer 22 and the pad nitride layer 23 between the layer of the shallow trench isolation component 21 and the aforementioned gate region to expose the original silicon surface OSS of the substrate, as Figure 6A and Figure 6B shown, where Figure 6B is a cross-sectional view along the Figure 6A X-axis profile line in

[0159] Step 404: Form a spacer layer on the side surfaces of the aforementioned gate region, where the spacer layer may include a thin oxide sub-layer 343 thermally grown on the original silicon surface OSS of the substrate, and a thin nitride sub-layer 341 and a thin oxide sub-layer 342 above the thin oxide sub-layer 343, as Figure 7A and Figure 7B shown, where Figure 7B is a cross-sectional view along the Figure 7A X-axis profile line in

[0160] Step 406: Etch a part of the semiconductor substrate to form recesses in the semiconductor substrate, as Figure 8A and Figure 8B shown, where Figure 8B is a cross-sectional view along the Figure 8A X-axis profile line in. When the semiconductor substrate is a silicon substrate, each recess includes an exposed vertical side surface 36 having a (100) crystal plane, and the vertical side surface 36 is directly below the spacer layer in Step 404.

[0161] Please refer to Figure 9A and Figure 9B , Step 50 may include: Thermally grow an oxide layer 41, which includes a vertical oxide layer 411 and a horizontal oxide layer 412. The vertical oxide layer 411 covers the side walls of the recesses in the aforementioned Step 406, and the horizontal oxide layer 412 covers the bottoms of the aforementioned recesses. Then, deposit a nitride material with a sufficient thickness to completely fill the aforementioned recesses, and then use an etch-back process to remove the unnecessary part of the nitride material, so that only a suitable nitride layer 42 remains in the aforementioned recesses, as Figure 9A and Figure 9B shown, where Figure 9B is a cross-sectional view along the Figure 9A X-axis profile line in. It should be noted that the nitride layer 42 can be replaced by any suitable insulating material.

[0162] It should be noted that Figure 9BThe thicknesses of oxide layer 411 and oxide layer 412 shown in the following figures are for illustrative purposes only. However, it is very important to design this thermally grown oxide layer 41 such that the thickness of oxide layer 411 is very precisely controlled under precisely controlled thermal oxidation temperature, timing, and growth rate. For thermal oxidation on a well-defined silicon surface, 40% of the thickness of oxide layer 411 should be subtracted from the silicon substrate portion of the previously exposed (110) vertical side surface 36, and the remaining 60% thickness of oxide layer 411 is considered an addition outside the previously exposed (110) vertical side surface 36 ( Figure 9B The 40% and 60% distribution on oxide layer 411 is shown particularly clearly in

[0163] Please refer to Figure 10A and Figure 10B , step 60 may include:

[0164] Step 602: Remove the portion of oxide layer 411 located above nitride 42 to expose additional vertical semiconductor sidewalls 501 and 502. Again, when the semiconductor substrate is a silicon substrate, the plurality of vertical semiconductor sidewalls 501 and 502 have (110) crystal planes. The remaining oxide layer 41 and nitride layer 42 can be referred to as Localized Isolation into Silicon Substrate (LISS) in the silicon substrate.

[0165] Step 604: Horizontally grow first semiconductor regions 430 from the exposed vertical semiconductor sidewalls 501 and 502 respectively. Each first semiconductor region 430 may include a lightly doped region (or lightly doped drain (LDD)), or include an undoped region plus a lightly doped region. The first semiconductor regions 430 can be formed by selective growth methods such as Selective Epitaxial Growth (SEG) technology or Atomic Layer Deposition (ALD) technology.

[0166] Step 606: Horizontally grow a second semiconductor region from the plurality of first semiconductor regions 430; each second semiconductor region includes a highly doped region, and the highly doped region can also be formed by a selective growth method. Thus, the drain region of the planar NMOS transistor includes an N-LDD region and an N+ doped region 431, and the source region of the planar NMOS transistor includes another N-LDD region and an N+ doped region 432. Similarly, the drain region of the planar PMOS transistor includes a P-LDD region and a P+ doped region 441, and the source region of the planar PMOS transistor includes another P-LDD region and a P+ doped region 442.

[0167] Note that each of the exposed vertical semiconductor sidewalls 501 and 502 has a vertical boundary that is aligned (or substantially aligned) with the edge of the gate region, as Figure 10B shown. That is, the edge of the source or drain region in the planar transistor is aligned (or substantially aligned) with the edge of the gate region. The present invention provides a deep SAPC technology (alignment from the gate to the source / drain and precisely creating a crystalline structure to form the source / drain). Thus, the alignment from the edge of the source / drain to the edge of the gate region can be precisely defined or controlled by using thermal oxidation and the crystalline structure, and, compared with the conventional method of using LDD implantation for alignment from the gate edge to the LDD, the GIDL effect should be reduced.

[0168] Moreover, the new source / drain regions are formed of all (110) crystalline silicon; as explained, improving the conventional method of growing source / drain regions from two different seed regions results in a mixed lattice of (100) and (110) crystal planes in the silicon substrate. Therefore, the present invention can create a better source / drain to channel conduction mechanism and can also reduce sub-threshold leakage. And, during the formation of the planar transistor, the effective channel length between the source region and the drain region can be almost equal to the gate length ( Figure 10B Leff shown), because ion implantation and thermal annealing are not required. Since ion implantation is not required to form the LDD region or the source / drain regions, a thermal annealing process is not required to reduce defects. Therefore, any accidental leakage current sources should be significantly minimized because no additional defects are generated that are difficult to completely eliminate even by an annealing process once induced.

[0169] In addition, even if there is another thermal annealing process to reduce the connection resistance between the capacitor and the access transistor, since the first semiconductor region 430 of the present invention may include an undoped region plus a lightly doped region, the dopant redistribution caused by another thermal annealing process will not significantly reduce the effective channel length (Leff). Therefore, compared with the conventional CMOS structure, the design rule for the gate length (Lgate) reserved for the gate region according to the present invention will be reduced. Taking the technology node (λ) of 20nm to 30nm used in planar transistors as an example, the gate length reserved in the present invention will be between 1.5λ and 3λ, such as 2λ or 2.5λ.

[0170] Meanwhile, the source and drain regions of each planar transistor of the present invention are isolated by the insulating materials (nitride layer 42 and remaining oxide layer 41) located on the bottom structure and are isolated along three sidewalls by the layer of the shallow trench isolation component 21. The possibility of junction leakage can only occur in a very small region from the first semiconductor region 430 to the channel region (directly below the planar transistor gate region). Therefore, the possibility of junction leakage is significantly reduced.

[0171] In the foregoing embodiment, before forming the gate structure, a channel region may be formed by ion implantation (not shown) near the original silicon surface OSS below the original silicon surface OSS. Then, in addition to the channel region formed by ion implantation, a channel region according to the present invention may be selectively grown. For example, before forming the gate dielectric layer 331 in Figure 4B , the exposed silicon surface may be etched to form a shallow trench with a depth of 1.5nm to 3nm, as shown in Figure 3C and Figure 3D . Then, a channel region 24 is selectively grown in the shallow trench, as shown in Figure 3E and Figure 3F . After that, the processes for forming the gate region, source region, and drain region mentioned in Figure 4A / Figures 4B to 10A / Figure 10B can be similarly applied to form another planar transistor structure as shown in Figure 10C .

[0172] In yet another embodiment, before forming the gate dielectric layer 331 in Figure 4B , the exposed silicon surface may be etched to form a shallow trench with an arc shape or a curved shape, as shown in Figure 3G and Figure 3H . Then, a channel region 24 is selectively grown along the sidewalls of the shallow trench, as shown in Figure 3I and Figure 3JAs shown. Since the semiconductor channel region 24 grows along the sidewalls of the shallow trench having a curved or arc shape, the channel length in this embodiment can be relatively long. Thereafter, the processes of forming the gate region, source region, and drain region mentioned can be similarly applied Figure 4A / Figures 4B to 10A / Figure 10B to form another planar transistor.

[0173] Figure 10D and Figure 10E is a cross-sectional view along the section line (X-axis) after laterally growing a semiconductor region from the sidewalls exposed in the recess according to another embodiment. Figure 10D / Figure 10E The difference from Figure 10C is that before growing the LDD region 4302 of the NMOS, a vertical P-type layer 4301 is formed by selective growth, and then the LDD region 4302 and the heavily doped N+ doped regions 431 / 432 are sequentially formed by selective growth. Such a vertical P-type layer 4301 can reduce the leakage current of the NMOS transistor in the off state.

[0174] In another embodiment, the source region (or drain region) may further include some tungsten or other suitable metal materials (not shown), which are located in the recess and contact the heavily doped region of the selectively grown source region (or drain region). Thus, the source region (or drain region) is a composite source region (or drain region). Thus, the external contact will be connected to the metal region of the source region (or drain region), and such a metal-to-metal contact has a lower resistance compared to the conventional silicon-to-metal contact.

[0175] Moreover, as Figures 11A to 11B shown, Figure 11A is a top view of a new planar CMOS structure according to the present invention, Figure 11B is a cross-sectional view showing the new planar CMOS structure along the 11A section line (Y-axis). Figures 11A to 11B The planar PMOS transistor and the planar NMOS transistor in Figure 11A are vertically arranged side by side. In Figures 11A to 11BAs shown, there is a composite local isolation component (including oxide layer 412 and nitride layer 42) between the P+ doped region 442 (or the P+ doped region 441 as the drain region) of the PMOS serving as the source region and the N-type well. Therefore, there is also another composite local isolation component (including oxide layer 412 and nitride layer 42) between the N+ doped region 432 (or the N+ doped region 431 as the drain region) of the NMOS serving as the source region and the P-type well or the substrate. That is to say, each drain region and source region of the new planar CMOS structure is surrounded by the shallow trench isolation component 21 on three sidewalls and by the composite local isolation component on the lower sidewall. Thus, the potential latch-up path from the bottom of the P+ region of the PMOS to the bottom of the N+ region of the NMOS is completely blocked by the local isolation component. Therefore, the latch-up distance Xp + Xn (measured on the plane) can be shortened as much as possible without causing serious latch-up problems. On the other hand, in the traditional CMOS structure, the N+ region and the P+ region are not completely isolated by the insulator, as Figure 1B or Figure 12 shown, there is a potential latch-up path from the N+ / P junction through the P-type well / N-type well junction to the N / P+ junction, including the length Length and the length

[0176] Moreover, please refer to Figures 13A to 13B . Figure 13A is a top view of the new planar CMOS structure having a planar NMOS transistor and a planar PMOS transistor, Figure 13B is a drawing showing a cross-sectional view of the new planar CMOS structure along the Figure 13A horizontal dotted line. Figures 13A to 13B The planar PMOS transistor and the planar NMOS transistor in Figure 13B are arranged side by side horizontally. As Figure 13B shown, it can be simplified to have an intersecting LISS 70 between the PMOS transistor and the NMOS transistor. The intersecting LISS 70 includes a vertically extending isolation region 71 (such as the shallow trench isolation component 21, and the vertical depth below the OSS is as Figure 13BThe dimensions shown will be approximately 150 nm to 300 nm, such as 200 nm), a first horizontally extending isolation region 72 (vertical depth will be approximately 50 nm to 120 nm, such as 100 nm) located on the right - hand side of the vertically extending isolation region 71, and a second horizontally extending isolation region 73 (vertical depth will be approximately 50 nm to 120 nm, such as 100 nm) located on the left - hand side of the vertically extending isolation region 71. Each horizontally extending isolation region may include an oxide layer 41 and a nitride layer 42. The vertical depth of the source / drain regions of the PMOS transistor / NMOS transistor will be approximately 30 nm to 150 nm, such as 40 nm. The vertical depth of the gate region of the PMOS transistor / NMOS transistor will be approximately 40 nm to 60 nm, such as Figure 13B 50 nm as shown.

[0177] In this embodiment, the first horizontally extending isolation region 72 and the second horizontally extending isolation region 73 are not directly located under the gate structure or channel of the transistor. The first horizontally extending isolation region 72 (on the right - hand side of the vertically extending isolation region 71) contacts the bottom side of the source / drain region of the PMOS transistor, and the second horizontally extending isolation region 732 (on the left - hand side of the vertically extending isolation region 71) contacts the bottom side of the source / drain region of the NMOS transistor. Thus, the bottom sides of the source / drain regions in the PMOS transistor and the NMOS transistor are shielded from the semiconductor substrate. Also, the first horizontally extending isolation region 72 or the second horizontally extending isolation region 73 may be a composite isolation component, which may include two or more different isolation materials (such as the oxide layer 41 and the nitride layer 42), or two or more of the same isolation materials but each isolation material is formed by a different process.

[0178] As described above and Figure 1B As described, compared to pure NMOS technology, one disadvantage of traditional CMOS types / technologies is that once there are parasitic bipolar structures such as N+ / P - type substrates / N - wells / P+ junctions, and unfortunately some poor designs cannot resist the large current surges caused by the noise that triggers the latch - up effect, it can cause the entire chip operation to shut down or permanent damage to the chip function. The layout and process rules of traditional CMOS always require a very large space to separate the N+ source / drain regions of NMOS from the P+ source / drain regions of PMOS, which is called the latch - up distance ( Figure 1B ), which consumes a large amount of planar surface space to suppress any possible latch - up effect. Also, if the source / drain N+ / P and P+ / N semiconductor junction areas are too large, once a forward - bias accident occurs, it will trigger a large current surge, resulting in the latch - up effect.

[0179] Figure 13BThe new planar CMOS structure in [ ] makes the path from the N+ / P junction through the P-well (or P-substrate) / N-well junction to the N / P+ junction longer. As Figure 13B shown, according to the present invention, the potential latch-up path from the LDD-N / P junction through the P-well / N-well junction to the N / LDD-P junction includes Figure 13B the lengths ①, ② (the length of the lower sidewall of a horizontally extending isolation region), ③, ④, ⑤, ⑥, ⑦ (the length of the lower sidewall of another horizontally extending isolation region), and ⑧ marked in [ ].

[0180] On the other hand, in the conventional CMOS structure, the potential latch-up path from the N+ / P junction through the P-well junction to the N / P+ junction only includes the lengths Length Length and length (as Figure 14 shown). Figure 13B The such potential latch-up path in [ ] is longer than the potential latch-up path in Figure 14 [ ]. Therefore, from the perspective of device layout, the edge distance (Xn + Xp) reserved between the NMOS and PMOS in Figure 13B [ ] according to the present invention can be less than the edge distance (Xn + Xp) reserved in Figure 14 [ ]. And, compared with the N+ / P junction to the N / P+ junction in Figure 14 [ ], in Figure 13B [ ], the latch-up path starts from the LDD-N / P junction to the N / LDD-P junction. Since Figure 13B the doping concentration in the LDD-N region or LDD-P region of [ ] is lower than the doping concentration in the N+ region or P+ region of Figure 14 [ ], the amount of electrons or holes emitted from the LDD-N region or LDD-P region of Figure 13B [ ] will be much lower than the amount emitted from the N+ region or P+ region of Figure 14 [ ]. This lower carrier emission not only effectively reduces the possibility of triggering the latch-up phenomenon, but also significantly reduces the current even if the latch-up phenomenon is triggered. Since the areas of both the N+ / P junction and the P+ / N junction are significantly reduced, even if there is some sudden forward bias on these junctions, the abnormal current amplitude can be reduced, thereby reducing the chance of forming the Figure 13B latch-up effect in [ ].

[0181] Please refer to Figure 13B, according to the present invention, the source region or drain region of the planar PMOS is surrounded by the first horizontally extending isolation region 72 and the vertically extending isolation region 71. Only the LDD region (the vertical length will be approximately 10 nm to 50 nm) of the source region or drain region of the planar PMOS contacts the semiconductor substrate to form an LDD-P / N junction, rather than a P+ / N junction. Similarly, the source region or drain region of the planar NMOS is surrounded by the second horizontally extending isolation region 73 and the vertically extending isolation region 71. Only the LDD region (the vertical length will be approximately 40 nm) of the source region or drain region of the planar NMOS contacts the semiconductor substrate to form an LDD-N / P junction, rather than a P+ / N junction. Therefore, the N+ region of the planar NMOS and the P+ region of the planar PMOS are shielded from the substrate or well region. And, since the first horizontally extending isolation region 72 or the second horizontally extending isolation region 73 is a composite isolation component and thick enough, it can minimize the parasitic metal gate diode induced between the source region (or drain region) and the silicon substrate. In addition, the gate-induced drain leakage (GIDL) effect can also be improved. It is expected that the planar latch-up distance reserved for adjacent NMOS transistors and PMOS transistors is significantly shortened, enabling the planar area of the new planar CMOS to be significantly reduced.

[0182] In addition, the source / drain regions directly grown from a specific crystal plane of the semiconductor substrate can be applied to the access transistors of the dynamic random access memory cells in the array core circuit of the DRAM chip. Each dynamic random access memory cell includes an access transistor and a storage capacitor. As Figure 15A shown, an access transistor Q1 includes a source region 213A connected to a storage capacitor C1, a drain region 213B connected to a bit line BL of the DRAM chip, a gate dielectric layer 209 (such as an oxide), a gate conductive region 210A (including metal or polysilicon), a dielectric gate covering component 214A (such as an oxide / nitride), and a U-shaped channel region 208A surrounding the gate conductive region 210A. Another access transistor Q2 includes a source region 213C connected to a storage capacitor C, a drain region 213B connected to a bit line BL of the DRAM chip, a gate dielectric layer 209 (such as an oxide), a gate conductive region 210B (including metal or polysilicon), a dielectric gate covering component 214B (such as an oxide / nitride), and a U-shaped channel region 208B surrounding the gate conductive region 210B. The access transistor Q1 and the access transistor Q2 are U-groove transistors or buried gate transistors, and can be formed in the well region 204 of the substrate 201 and surrounded by the shallow trench isolation region 202.

[0183] It should be noted that the source region 213A, the drain region 213B, and the source region 213C can be selectively grown and from Figure 15BThe silicon (100) crystal planes exposed in the shown first recess 216A, second recess 216B, and third recess 216C grow vertically. The source region 213A may include an LDD region 217A and a heavily doped region 218A, the drain region 213B may include an LDD region 217B and a heavily doped region 218B, and the source region 213C may include an LDD region 217C and a heavily doped region 218C, as Figure 15A shown. In the dynamic random access memory cell of the present invention, the source / drain regions of the access transistor grow directly vertically from the (100) crystal plane (e.g., by selective epitaxial growth technology or atomic layer deposition technology), and their interfaces form seamless junctions with the channel region. Moreover, no ion implantation process is performed during the formation of the source / drain regions, nor is there a thermal annealing process that makes it difficult to define and control the junction boundary.

[0184] In summary, since the source / drain regions of the CMOS structure planar transistors in the peripheral circuit / sense amplifier of the DRAM chip grow directly laterally from the (110) crystal plane, their interfaces form seamless junctions with the channel region, so the gate length (Lgate) can be precisely controlled. Moreover, the surface of the lightly doped drain LDD grows horizontally from the transistor channel and the substrate body by in-situ doping technology during selective growth, without performing an ion implantation process that can only go from the top of the silicon to the source / drain regions, nor is there a thermal annealing process that makes it difficult to define and control the junction boundary. Unlike the conventional doped regions formed by ion implantation processes, this selectively grown semiconductor region (such as the undoped region, LDD region, and heavily doped region) is independent of the semiconductor substrate.

[0185] The present invention can more precisely define the boundaries of the source / drain to the edges of the gate region and can control the effective channel length (Leff) to minimize short-channel effects, GIDL, and junction leakage current.

[0186] Moreover, in this newly invented planar CMOS structure, the N+ region and the P+ region are completely isolated by isolation components, and the proposed LISS will increase the isolation distance to the silicon substrate to separate the junctions in the NMOS transistor and the PMOS transistor, so that the surface distance between the junctions can be reduced.

[0187] And, in the present invention, selective epitaxial growth forms LDD to the heavily doped region and even includes various non-silicon dopants such as germanium or carbon atoms, increasing the stress to improve the channel mobility. In the selective epitaxial growth / atomic layer deposition formation of the source / drain regions according to the present invention, the doping concentration distribution is controllable or adjustable.

[0188] Moreover, in the well-known CMOS process, the conductive material for the gate of a transistor can be polysilicon or metal. Among them, polysilicon is used because its work function is compatible with the silicon substrate and is often used in the gate-first process. Polysilicon is a material composed of tiny silicon crystals. However, the conductivity of polysilicon is very low, and due to this low conductivity, the accumulation of charges is also low, resulting in a delay in channel formation, thus causing unnecessary delays in the circuit. Therefore, polysilicon is usually doped with impurities to make it behave like a perfect conductor and reduce the delay.

[0189] However, in the polysilicon gate CMOS process, the polysilicon gate is doped by ion implantation, and problems will occur when the doping of the polysilicon gate is not heavy enough or not uniform. Therefore, the dopant activation concentration is limited. For example, in PMOS transistors, this dopant activation concentration is usually less than 1x10 20 / cm 3 (for example, it is 7x10 19 / cm 3 ), and in NMOS transistors, this dopant activation concentration is usually less than 4x10 20 / cm 3 (for example, it is 2.5x10 20 / cm 3 ). In addition, it usually causes the polysilicon depletion effect, which is a phenomenon of unnecessary changes in the critical voltage of the MOSFET device when using polysilicon as the gate material, resulting in unpredictable behavior in the electronic circuit. Therefore, in advanced semiconductor processes for polysilicon gate processes, a key issue is to have appropriate doping activation in the polysilicon (poly-Si) gate to minimize this polysilicon depletion effect.

[0190] On the other hand, when a high-k dielectric (such as hafnium oxide) replaces the SiO2 dielectric as the gate oxide in the mainstream CMOS technology (especially the gate-last process), metal is introduced as the gate conductive material. Since polysilicon is not used in the gate structure, a high-k dielectric metal gate (HKMG) is used to solve the polysilicon depletion effect. Nevertheless, compared with the polysilicon gate CMOS process, this HKMG process is complex and expensive.

[0191] The present invention further solves the problem of doping activation in traditional polysilicon gate transistors, and increases the doping activation concentration in the semiconductor / silicon gate of NMOS transistors to not less than 3×10 20 / cm 3 (N+), for example, 4×10 20 / cm 3 (N+) or higher. Moreover, the doping activation concentration in the semiconductor / silicon gate of PMOS transistors of the present invention can be increased to not less than 8×10 19 / cm 3 (P+), for example, 1×10 20 / cm 3 (P+) or higher. This high doping activation concentration can reduce the polysilicon depletion effect, reduce the thickness of the gate dielectric layer, and improve the on-current (Ion) and gate control ability.

[0192] In traditional transistors with a polysilicon gate structure, for traditional NMOS transistors, the doping activation concentration in this polysilicon gate is only about 2.5×10 20 / cm 3 , while for traditional PMOS transistors, it is about 7×10 19 / cm 3 . In the manufacturing process of traditional polysilicon gates, usually an undoped polysilicon layer is deposited above the gate oxide layer. Then, taking NMOS transistors as an example, arsenic (As) or phosphorus (P) ions are implanted into the undoped polysilicon, and then rapid thermal annealing is used to activate the doping concentration.

[0193] On the other hand, in the proposed transistors with a highly doped silicon gate structure, for NMOS transistors, the doping activation concentration in this highly doped silicon gate can be greater than 4×10 20 / cm 3 , while for PMOS transistors, it can be greater than 1×10 20 / cm 3 . According to the exemplary manufacturing process of NMOS transistors as shown in Figures 16 to 18 of the present invention, in order to increase the doping activation concentration in the gate structure, after forming the gate dielectric layer 331 (such as thermal oxide or high-k material), a thin layer 3321 of undoped or doped amorphous silicon (or polysilicon) is first deposited above the gate dielectric layer 331 at a temperature of 500°C to 650°C, as shown in Figure 16As shown. Subsequently, such an amorphous silicon layer is annealed at a temperature of about 1000 °C or higher (e.g., laser annealing, about 1200 °C, plus thermal annealing, about 600 °C) for recrystallization to become a silicon layer with larger die, and the grain size can be greater than 1 micrometer (μm) to 2 micrometers. For example, see T.I. KAMINS AND T.R. CASS, “STRUCTURE OF CHEMICALLY DEPOSITED POLYCRYSTALLINE-SILICON FILMS”, Thin Solid Films, 16(1973)147-165; see also Yasuo Wada and Shigeru Nishimatsu, “Grain Growth Mechanism of Heavily Phosphorus-implanted Polycrystalline Silicon”, J. Electrochem. Soc.: SOLID-STATE SCIENCE AND TECHNOLOGY, Vol. 125, No. 9, 1499-1504, September 1978).

[0194] After that, as Figure 17 shown, a silicon layer 3322 with larger die is used as a seed layer to selectively grow (e.g., selective epitaxial growth (SEG)) a layer of in-situ N+-doped silicon 3323. Subsequently, annealing is performed at a temperature of about 1000 °C or higher by a rapid thermal anneal (RTA) process, so that the doping activation concentration in the selectively grown silicon layer can be about 4x10 20 / cm 3 (Please see Z.N. Weinrich, et al., “Dopant-defect interactions in highly doped epitaxial Si:P thin films”, Thin Solid Films 685(2019)1–7). Moreover, since the originally undoped amorphous silicon layer is extremely thin, through the above-mentioned rapid thermal annealing, the dopants in the in-situ N+-doped silicon layer will diffuse outward into the recrystallized silicon layer with larger die, making the doping concentration of the recrystallized silicon layer with larger die almost equal to that of the in-situ N+-doped silicon layer. Thus, after rapid thermal annealing, it is almost difficult to distinguish the in-situ N+-doped silicon 3323 and the silicon layer 3322 with larger die.

[0195] After that, to complete the NMOS transistor structure, as Figure 18As shown, a standard gate patterning process can be applied to form the gate shape. A titanium nitride (TiN) layer 333 and a tungsten layer 334 can be deposited over the in-situ N+ doped silicon 3323. Then, the LDD regions and nitride spacers can be formed, and the N+ source / drain regions can be formed by ion implantation and annealing processes, as Figure 18 shown. It should be noted that the grain size of the larger silicon layer of the recrystallized die can be greater than 1 um to 2 um, and the same is true for the in-situ N+ doped silicon layer formed by selective epitaxial growth. After forming the standard gate patterning process based on technology nodes below 28 nm, the gate length is generally not greater than 150 nm. Therefore, in the gate length of the in-situ N+ doped silicon layer, the in-situ N+ doped silicon layer is almost a single crystal layer; alternatively, along the tangent of the gate length, the in-situ N+ doped silicon layer will contain no more than three silicon die.

[0196] Similarly, in the process of forming a conventional PMOS transistor, an undoped polysilicon layer is first deposited over the gate oxide layer. Then, boron (B) ions are implanted into the undoped polysilicon, and then rapid thermal annealing is used to activate the doping concentration. In such a polysilicon gate of a conventional PMOS transistor, the activated doping concentration will not be greater than 1x10 20 / cm 3 . On the other hand, Figures 19 to 21 shows an exemplary process of a PMOS transistor according to the present invention. Similar details are omitted here, however, the dopant type in the epitaxial polysilicon gate of the PMOS transistor is different from the dopant type in the epitaxial polysilicon gate of the NMOS transistor. In such an epitaxial polysilicon gate of a PMOS transistor according to the present invention, the activated doping concentration will not be greater than 1x10 Figures 16 to 18 20 / cm 3 20 .

[0197] Figure 22A and Figure 22B show a comparison between a polysilicon gate transistor according to a conventional process ( Figure 22A ) and a polysilicon gate transistor according to the process of the present invention ( Figure 22B ). The high activated doping concentration of the in-situ N+ / P+ doped silicon 3323 can reduce the polysilicon depletion effect, reduce the thickness of the gate dielectric layer 331, and improve the on-current and gate control ability. In summary, the present invention solves the problem of activated doping in conventional polysilicon gate transistors, and raises the activated doping concentration in the silicon gates of NMOS transistors and PMOS transistors to not less than 4×10 20 / cm 3 (N+) and 1x10 20 / cm 3(P+). This high doping activation concentration can reduce the polysilicon depletion effect, decrease the thickness of the gate dielectric layer, and improve the on-current and gate control ability. The present invention can be applied to all transistors with silicon gates, such as planar transistors, fin-structured transistors, gate-all-around (GAA) transistors, and so on. Moreover, this epitaxial silicon gate transistor can be applied not only to the logic circuits of semiconductor memories such as DRAM, but also to the peripheral circuits. And, the present invention can be applied to other semiconductor materials used for the gate structures of MOS transistors, such as silicon germanium (SiGe), silicon carbide (SiC), or gallium nitride (GaN), and so on.

[0198] Figure 23A Mark the electron backscatter diffraction (EBSD) results of the annealed amorphous silicon layer in the real sample structure. In this sample structure, the amorphous silicon layer was initially formed on the oxide layer deposited on the silicon substrate, and then, the amorphous silicon layer was annealed, as Figure 23A shown in the upper left figure. The EBSD results show that many die exist in the annealed amorphous silicon layer, and the die size can be about 1.35 microns. Moreover, from Figure 23B the transmission electron microscopy (TEM) results shown, the polycrystalline crystal planes of the annealed amorphous silicon layer can be observed. From the X-ray diffraction (XRD) results, Figure 23B two designated regions of the annealed amorphous silicon layer in Figure 23C show two {110} die, as shown in the right figure and the left figure of

[0199] Those of ordinary skill in the art to which the present invention pertains will readily observe that various modifications and changes can be made to the apparatus and method while retaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the scope and bounds of the claims.

Claims

1. A semiconductor structure, comprising: a semiconductor substrate; a first dielectric layer directly located on a first portion of the semiconductor substrate, wherein a length of the first dielectric layer is equal to a length of the first portion of the semiconductor substrate; and an undoped semiconductor layer located on the first dielectric layer.

2. The semiconductor structure according to claim 1, wherein A first sidewall of the undoped semiconductor layer is covered by a second dielectric layer, and a second sidewall of the undoped semiconductor layer opposite to the first sidewall is covered by a third dielectric layer.

3. The semiconductor structure according to claim 2, wherein The undoped semiconductor layer comprises a silicon-containing material.

4. The semiconductor structure according to claim 3, wherein, A die size in the silicon-containing material is greater than 1 micron.

5. The semiconductor structure according to claim 2, wherein The first dielectric layer comprises an oxide.

6. The semiconductor structure according to claim 3, wherein Both the second dielectric layer and the third dielectric layer comprise an oxide.

7. The semiconductor structure according to claim 2, wherein, Further comprising a dielectric cover layer located above the undoped semiconductor layer.

8. The semiconductor structure according to claim 7, wherein Further comprising a doped semiconductor layer located between the dielectric cover layer and the undoped semiconductor layer; wherein the doped semiconductor layer comprises a silicon-containing material, and a die size in the silicon-containing material is greater than 1 micron.

9. A semiconductor structure, comprising: a semiconductor substrate; a first dielectric layer directly located on a first portion of the semiconductor substrate, wherein a length of the first dielectric layer is equal to a length of the first portion of the semiconductor substrate; a first semiconductor layer located on the first dielectric layer, wherein the first semiconductor layer comprises a first silicon-containing material, and a die size in the first silicon-containing material is greater than 1 micron; and a dielectric cover layer located above the first semiconductor layer.

10. The semiconductor structure according to claim 9, wherein, A first sidewall of the first semiconductor layer is covered by a second dielectric layer, and a second sidewall of the first semiconductor layer opposite to the first sidewall is covered by a third dielectric layer.

11. The semiconductor structure according to claim 10, wherein, The first dielectric layer comprises an oxide, and both the second dielectric layer and the third dielectric layer comprise an oxide.

12. The semiconductor structure according to claim 9, wherein Further comprising a second semiconductor layer located between the dielectric cover layer and the first semiconductor layer; wherein the second semiconductor layer comprises a second silicon-containing material, and a die size in the second silicon-containing material is greater than 1 micron.

13. A method for manufacturing a semiconductor structure, comprising: preparing a semiconductor substrate; defining a first portion of the semiconductor substrate; directly forming a first dielectric layer on the first portion of the semiconductor substrate, wherein a length of the first dielectric layer is equal to a length of the first portion of the semiconductor substrate; forming an undoped semiconductor layer on the first dielectric layer; and annealing the undoped semiconductor layer.

14. The manufacturing method of the semiconductor structure according to claim 13, characterized in that, The annealing step is performed at a temperature not lower than 1000 °C.

15. The manufacturing method of the semiconductor structure according to claim 13, characterized in that, The undoped semiconductor layer comprises a first silicon-containing material, and after the annealing step, a die size in the first silicon-containing material is greater than 1 micron.

16. The manufacturing method of the semiconductor structure according to claim 13, characterized in that, Further comprising: after the annealing step, forming a dielectric cover layer above the undoped semiconductor layer.

17. The manufacturing method of the semiconductor structure according to claim 16, wherein, Further comprising: after the annealing step and before forming the dielectric cover layer, forming a doped semiconductor layer on the undoped semiconductor layer, wherein the doped semiconductor layer comprises a second silicon-containing material, and a die size in the second silicon-containing material is greater than 1 micron.

18. A method for manufacturing a semiconductor structure, comprising: preparing a semiconductor substrate; defining a first portion of the semiconductor substrate; Directly form a first dielectric layer on the first portion of the semiconductor substrate, wherein a length of the first dielectric layer is equal to a length of the first portion of the semiconductor substrate; Form a first semiconductor layer on the first dielectric layer, wherein the first semiconductor layer comprises a first silicon-containing material; Anneal the first semiconductor layer, wherein after annealing, a size of a die in the first silicon-containing material is greater than 1 micron; and Form a dielectric covering layer above the first semiconductor layer.

19. The method for manufacturing a semiconductor structure according to claim 18, wherein, The step of annealing is performed at a temperature not lower than 1000 °C.

20. The manufacturing method of the semiconductor structure as described in claim 18, characterized in that, Further comprising: Before forming the dielectric covering layer, form a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer comprises a second silicon-containing material, and a size of a die in the second silicon-containing material is greater than 1 micron.

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