Method for improving IDSS discretization of deep-trench super-junction device

Abstract

The invention provides a method for improving IDSS discretization of a deep trench super junction device, which comprises the following steps of: transferring a substrate into a reaction chamber, forming an oxide layer on the surface of a deep trench due to natural oxidation, forming a silicon layer of which the N-type impurity concentration is greater than that of an epitaxial layer on the interface of the deep trench and the oxide layer, raising the temperature in the reaction chamber to a first set temperature, increasing the pressure in the reaction chamber to a first set pressure, and introducing a reducing gas into the cavity to remove the oxide layer on the surface of the deep trench; reducing the pressure in the reaction chamber to a second set pressure, continuously reducing the temperature in the reaction chamber until the bottom temperature of the deep trench is higher than the top temperature of the deep trench, introducing etching gas into the reaction chamber, removing the silicon layer on the surface of the deep trench by using the etching gas, and stopping introducing the etching gas when the temperature in the reaction chamber is reduced to the second set temperature; and increasing the pressure in the reaction chamber to a third set pressure, and removing the residual etching gas in the deep trench. According to the invention, the IDSS discretization of the deep trench super junction device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for improving the IDSS discreteness of a deep trench superjunction device. Background Art

[0002] In deep trench filled superjunction products, IDSS refers to the drain-source leakage current under a specific drain-source voltage when the gate-source voltage is zero, and is an important indicator for measuring the leakage power consumption of the device.

[0003] In the deep trench filled superjunction device structure, the P-pillar (P column structure) is formed by "deep trench etching + one-time filling of P column epitaxy" on the N-EPI. When the gate-source is shorted, the leakage current between the P column structure and the N-drift (N-type drift region) is an important influencing factor of IDSS.

[0004] For some products, due to differences in design, process nodes, and manufacturing, the IDSS discreteness is relatively high, and the higher the drain-source voltage, the more serious the leakage.

[0005] To solve the above problems, a new method for improving the IDSS discreteness of deep trench superjunction devices needs to be proposed. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for improving the IDSS discreteness of a deep trench superjunction device, which is used to solve the problem that the IDSS discreteness of some products in the prior art is relatively high, and the higher the drain-source voltage, the more serious the leakage.

[0007] To achieve the above purpose and other related purposes, the present invention provides a method for improving the IDSS discreteness of a deep trench superjunction device, including:

[0008] Step 1: Provide a substrate, form an N-type epitaxial layer on the substrate, form a hard mask layer on the epitaxial layer, and form deep trenches on the hard mask layer and the epitaxial layer below it by means of photolithography and etching;

[0009] Step 2: Transfer the substrate to a reaction chamber. An oxide layer is formed on the surface of the deep trench due to natural oxidation, and a silicon layer with an N-type impurity concentration greater than that of the epitaxial layer is formed at the interface between the deep trench and the oxide layer. Raise the temperature in the reaction chamber to a first set temperature, raise the pressure in the reaction chamber to a first set pressure, and introduce a reducing gas into the chamber to remove the oxide layer on the surface of the deep trench;

[0010] Step 3: Reduce the pressure in the reaction chamber to a second set pressure, continuously reduce the temperature in the reaction chamber, control the temperature at the bottom of the deep trench to be higher than that at the top, and introduce an etching gas into the reaction chamber. Use the etching gas to remove the silicon layer on the surface of the deep trench. When the temperature in the reaction chamber drops to the second set temperature, stop introducing the etching gas.

[0011] Step 4: Increase the pressure in the reaction chamber to a third set pressure to remove the residual etching gas in the deep trench.

[0012] Step 5: Form a P pillar structure to fill the deep trench.

[0013] Preferably, the first set temperature in Step 2 is 1050 to 1180 °C.

[0014] Preferably, the first set pressure in Step 2 is 300 to 700 Torr.

[0015] Preferably, the reducing gas in Step 2 is H2.

[0016] Preferably, the H2 in Step 2 continues to be introduced in Step 3 as the carrier gas of the etching gas.

[0017] Preferably, in Step 2, the heating lamp in the reaction chamber is used to increase the temperature.

[0018] Preferably, the second set pressure in Step 3 is 80 to 300 Torr.

[0019] Preferably, the second set temperature in Step 3 is 900 to 1180 °C.

[0020] Preferably, the etching gas in Step 3 is HCl.

[0021] Preferably, in Step 3, the method of adjusting the power of the heating lamps on the back and front of the substrate is used to make the temperature at the bottom of the deep trench higher than that at the top.

[0022] Preferably, the ratio of the power of the heating lamps on the back and front of the substrate in Step 3 is 4:6 to 7:3.

[0023] Preferably, the power of the heating lamp is 40 - 90 KW.

[0024] Preferably, the gas flow rate of the etching gas in Step 3 is 300 to 5000 slm.

[0025] Preferably, the third set pressure in Step 4 is 300 to 700 Torr.

[0026] Preferably, the H2 in step two is continuously introduced in step four to discharge the etching gas.

[0027] Preferably, the gas flow rate of the H2 is 20 to 75 liters per minute.

[0028] Preferably, the P pillar structure in step five is a P-type doped epitaxial layer.

[0029] As described above, the method for improving the IDSS dispersion of the deep trench superjunction device of the present invention has the following beneficial effects:

[0030] The present invention improves the IDSS dispersion of the deep trench superjunction device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of the deep trench morphology shown as the prior art;

[0032] Figure 2 Schematic diagram of the process flow of the present invention;

[0033] Figure 3 Schematic diagram of the baking process added in the present invention between heating up and depositing the P pillar structure;

[0034] Figure 4 Schematic diagram of the deep trench morphology of the present invention;

[0035] Figure 5 Schematic diagram of the comparison of the IDSS dispersion of the device of the present invention with respect to the prior art. DETAILED DESCRIPTION OF THE INVENTION

[0036] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] The inventor conjectures that during the growth of the sacrificial oxide layer, N-type impurities in the substrate and the epitaxial layer diffuse towards the interface, resulting in a relatively high N-type impurity concentration at the interface after filling growth, and diffusion into the P region causes relatively high leakage current; based on this conjecture, it is considered to improve the high IDSS leakage current by adjusting the epitaxial layer process conditions.

[0038] However, there are the following technical difficulties:

[0039] By performing a small amount of etching before depositing the P pillar structure, the silicon layer with a relatively high N-type impurity concentration on the surface layer of the trench interface is removed, reducing the influence of diffusion into the P region.

[0040] When continuously heating at a fixed temperature, the bottom to the top of the trench is uniformly heated. The diffusion distance of the etching gas to the top of the deep trench is shorter, and the top of the deep trench is more easily etched, resulting in a great change in the topography of the top of the deep trench.

[0041] To solve the above problems, please refer to Figure 2 , the present invention provides a method for improving the IDSS dispersion of a deep trench superjunction device, including:

[0042] Step 1: Provide a substrate. Usually, the substrate is a silicon substrate. Form an N-type epitaxial layer on the substrate, and form a hard mask layer on the epitaxial layer. Use photolithography and etching methods to form deep trenches on the hard mask layer and the epitaxial layer below it;

[0043] The deep trench of the superjunction has the morphological characteristics of small critical dimensions and deep depth, and has the physical property that the heat radiation at the bottom of the trench is slower than that at the top. Based on this property, the present invention develops a baking process (the method in Steps 2 to 4) as shown in Figure 3 between the steps of heating up and depositing the P pillar structure.

[0044] Step 2: Transfer the substrate to the reaction chamber. An oxide layer is formed on the surface of the deep trench due to natural oxidation, and a silicon layer with an N-type impurity concentration greater than that of the epitaxial layer is formed at the interface between the deep trench and the oxide layer. Raise the temperature in the reaction chamber to the first set temperature, raise the pressure in the reaction chamber to the first set pressure, and introduce a reducing gas into the cavity to remove the oxide layer on the surface of the deep trench;

[0045] In the embodiment of the present invention, the first set temperature in Step 2 is 1050 to 1180 °C, and the temperature can be raised at a fixed rate.

[0046] In the embodiment of the present invention, the first set pressure in Step 2 is 300 to 700 Torr.

[0047] In the embodiment of the present invention, the reducing gas in Step 2 is H2.

[0048] In the embodiment of the present invention, the H2 in Step 2 is continuously introduced in Step 3 as the carrier gas of the etching gas.

[0049] In the embodiment of the present invention, the heating lamp in the reaction chamber is used to raise the temperature in Step 2.

[0050] Step 3: Reduce the pressure in the reaction chamber to the second set pressure, continuously reduce the temperature in the reaction chamber, control the temperature at the bottom of the deep trench to be higher than that at the top, and introduce an etching gas into the reaction chamber to remove the silicon layer on the surface of the deep trench. When the temperature in the reaction chamber drops to the second set temperature, stop introducing the etching gas; since the temperature at the bottom of the deep trench is higher than that at the top, the etching gas is more likely to diffuse to the bottom of the deep trench, and the top of the deep trench is not easily etched, avoiding a large change in the topography at the top of the deep trench.

[0051] In an embodiment of the present invention, the second set pressure in Step 3 is 80 to 300 Torr.

[0052] In an embodiment of the present invention, the second set temperature in Step 3 is 900 to 1180 °C.

[0053] In an embodiment of the present invention, the etching gas in Step 3 is HCl. The etching rate of HCl can be jointly controlled by the HCl flow rate, and the etching time can be set by controlling the power during the temperature reduction process.

[0054] In an embodiment of the present invention, in Step 3, the method of adjusting the power of the heating lamps on the back and front of the substrate is used to make the temperature at the bottom of the deep trench higher than that at the top.

[0055] In an embodiment of the present invention, the ratio of the power of the heating lamps on the back and front of the substrate in Step 3 is 4:6 to 7:3.

[0056] In an embodiment of the present invention, the power of the heating lamp is 40 - 90 KW.

[0057] In an embodiment of the present invention, the gas flow rate of the etching gas in Step 3 is 300 to 5000 slm.

[0058] Step 4: Increase the pressure in the reaction chamber to the third set pressure to remove the residual etching gas in the deep trench. The present invention avoids over-etching the silicon at the top of the deep trench and a large change in the topography at the top, and a deep trench as shown in Figure 4 can be formed;

[0059] In an embodiment of the present invention, the third set pressure in Step 4 is 300 to 700 Torr.

[0060] In an embodiment of the present invention, the H2 in Step 2 continues to be introduced in Step 4 to discharge the etching gas.

[0061] In an embodiment of the present invention, the gas flow rate of H2 is 20 to 75 liters per minute.

[0062] Step 5: Form a P pillar structure filling the deep trench.

[0063] In an embodiment of the present invention, the P pillar structure in step five is a P-type doped epitaxial layer.

[0064] Please refer to Figure 5 , it can be seen that the IDSS discreteness of the device of the present invention is improved compared with the prior art.

[0065] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0066] In summary, the present invention improves the IDSS discreteness of the deep trench superjunction device. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0067] The above embodiments are only used to illustrate the principle and efficacy of the present invention by way of example, rather than to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the discreteness of IDSS in a deep trench super junction device, characterized in that, At least including: Step 1: Provide a substrate, form an N-type epitaxial layer on the substrate, form a hard mask layer on the epitaxial layer, and form deep trenches on the hard mask layer and the epitaxial layer thereunder by means of photolithography and etching; Step 2: Transfer the substrate to a reaction chamber. An oxide layer is formed on the surface of the deep trenches due to natural oxidation, and a silicon layer with an N-type impurity concentration greater than that of the epitaxial layer is formed at the interface between the deep trenches and the oxide layer. Raise the temperature in the reaction chamber to a first set temperature, raise the pressure in the reaction chamber to a first set pressure, and introduce a reducing gas into the chamber to remove the oxide layer on the surface of the deep trenches; Step 3: Lower the pressure in the reaction chamber to a second set pressure, continuously lower the temperature in the reaction chamber, and control the bottom temperature of the deep trenches to be higher than the top temperature thereof. Introduce an etching gas into the reaction chamber, and use the etching gas to remove the silicon layer on the surface of the deep trenches. Stop introducing the etching gas when the temperature in the reaction chamber is lowered to a second set temperature; Step 4: Raise the pressure in the reaction chamber to a third set pressure to remove the residual etching gas in the deep trenches; Step 5: Form a P-column structure filling the deep trenches.

2. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 1, wherein: The first set temperature in Step 2 is 1050 to 1180 °C.

3. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 1, characterized in that: The first set pressure in Step 2 is 300 to 700 Torr.

4. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 1, wherein: The reducing gas in Step 2 is H2.

5. The method for improving the IDSS discreteness of a deep trench superjunction device according to claim 4, wherein: The H2 in Step 2 continues to be introduced in Step 3 as the carrier gas of the etching gas.

6. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 1, characterized in that: In Step 2, the heating lamp in the reaction chamber is used to raise the temperature.

7. The method for improving the IDSS discreteness of a deep trench superjunction device according to claim 1, characterized in that: The second set pressure in Step 3 is 80 to 300 Torr.

8. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 1, characterized in that: The second set temperature in Step 3 is 900 to 1180 °C.

9. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 1, wherein: The etching gas in Step 3 is HCl.

10. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 1, characterized in that: In Step 3, the method of adjusting the power of the heating lamps on the back and front of the substrate is used to make the bottom temperature of the deep trenches higher than the top temperature thereof.

11. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 10, characterized in that: The ratio of the power of the heating lamps on the back and front of the substrate in Step 3 is 4:6 to 7:

3.

12. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 7 or 10 or 11, characterized in that: The power of the heating lamp is 40 to 90 KW.

13. The method for improving the IDSS discreteness of a deep trench superjunction device according to claim 1, characterized in that: The gas flow rate of the etching gas in Step 3 is 300 to 5000 slm.

14. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 1, characterized in that: The third set pressure in Step 4 is 300 to 700 Torr.

15. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 4, characterized in that: The H2 in Step 2 continues to be introduced in Step 4 to discharge the etching gas.

16. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 4 or 5 or 15, characterized in that: The gas flow rate of the H2 is 20 to 75 liters per minute.

17. The method for improving the IDSS discreteness of a deep trench super junction device according to claim 1, wherein: The P-column structure in Step 5 is a P-type doped epitaxial layer.

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