Planar complementary metal-oxide-semiconductor field effect transistor structure for reducing leakage and planar area

Abstract

The invention discloses a planar complementary metal-oxide-semiconductor field effect transistor structure, which is used in a peripheral circuit of a dynamic random access memory chip and a sensing amplifier of an array core circuit of the dynamic random access memory chip, and comprises a planar P-type metal-oxide-semiconductor field effect transistor, the substrate has a first conductive region; the planar N-type metal-oxide-semiconductor field effect transistor is provided with a second conductive region; the cross-shaped local isolation region is positioned between the planar P-type metal-oxide-semiconductor field effect transistor and the planar N-type metal-oxide-semiconductor field effect transistor; wherein the cross-shaped local isolation region comprises a horizontally extending isolation region, and the horizontally extending isolation region is in contact with the bottom side of the first conductive region and the bottom side of the second conductive region. The invention also can be similarly applied to a transistor of a complementary metal-oxide-semiconductor logic circuit.

Description

Technical Field

[0001] The present invention relates to new planar transistors and planar complementary metal-oxide-semiconductor field-effect transistor (MOSFET) structures, and more particularly to planar transistors and / or planar complementary MOSFET structures used in the peripheral circuits or sense amplifiers of dynamic random access memories (DRAMs), which can reduce leakage current, reduce short-channel effects, and prevent latch-up effects. Background Art

[0002] Although advanced technology nodes (such as 3nm to 7nm) are frequently used in high-performance computing applications (such as artificial intelligence (AI), central processing units (CPUs), graphics processing units (GPUs), etc.), mature technology nodes (such as 20nm to 30nm) are still popular in many integrated circuit (IC) applications such as power management ICs, microcontroller units (MCUs), or DRAM chips. Take DRAM as an example. Currently, most customized DRAMs are still manufactured using mature technology nodes (such as 12nm to 30nm), and all the transistors in the DRAM chip 17 (as Figure 1A shown), including the transistors in the peripheral circuit 171 (at least including data / address input / output circuits, address decoders, command logics, and update circuits, etc.) and the transistors in the array core circuit 172 (including storage memory arrays, sense amplifiers, etc.), are still planar transistors.

[0003] Figure 1BMark a cross-sectional view of the state-of-the-art Complementary Metal-Oxide-Semiconductor Field-Effect Transistor (CMOSFET) 10 that is most widely used in the peripheral circuit of the DRAM chip and in the sense amplifier of the array core circuit of the DRAM chip. The CMOSFET 10 includes a planar N-type Metal-Oxide-Semiconductor (NMOS) transistor 11 and a planar P-type Metal-Oxide-Semiconductor (PMOS) transistor 12. Among them, a Shallow Trench Isolation (STI) region 13 is located between the NMOS transistor 11 and the PMOS transistor 12. The gate structure 14 of the NMOS transistor 11 or the PMOS transistor 12 uses some conductive materials (such as metal, polysilicon, or polysilicide, etc.) above an insulator (such as oxide, oxide / nitride, or some high-k dielectrics, etc.), formed on the top of the Complementary Metal-Oxide-Semiconductor (CMOS), and its sidewalls are isolated from the sidewalls of other transistors by using insulating materials (such as oxide, or oxide / nitride, or other dielectrics). For the planar NMOS transistor 11, there are source and drain regions, which are formed by implanting N-type dopants into a P-type substrate (or P-type well) through ion implantation and thermal annealing techniques to form two separate N+ / P junction regions. For the planar PMOS transistor 12, the source and drain regions are formed by implanting P-type dopants into an N-type well through ion implantation to form two separate P+ / N junction regions. Moreover, in order to reduce impact ionization and hot carrier injection before the highly doped N+ / P or P+ / N junction, a lightly doped-drain (LDD) region 15 is usually formed under the gate structure.

[0004] On the one hand, during the aforementioned thermal annealing process, the implanted N-type or P-type dopants in the CMOSFET 10 will inevitably diffuse in different directions and increase the area of the source and drain regions. And when forming a capacitor above the access transistor in the array core circuit of the DRAM chip, another thermal annealing process will be carried out to reduce the connection resistance between the capacitor and the access transistor. This second thermal annealing process will again cause the diffusion of N-type or P-type dopants and increase the area of the source and drain regions. The larger the area of the source and drain regions caused by the thermal annealing process, the effective channel length between the source and drain regions ( Figure 1BThe shorter the effective channel length (Leff) shown, this reduced effective channel length Leff will lead to the short channel effect (SCE). Therefore, to reduce the impact of the short channel effect, a longer gate length is usually retained to accommodate the diffusion of N-type or P-type dopants caused by thermal annealing. Taking the 25 nm technology node (λ) as an example, the retained gate length will be approximately 100 nm, almost 4 times the technology node λ.

[0005] On the other hand, since the NMOS transistor 11 and the PMOS transistor 12 are respectively located in some adjacent regions of the P-type substrate and the N-type well formed adjacent to each other, a parasitic junction structure of a parasitic bipolar device called N+ / P / N / P+ ( Figure 1B The path marked by the dotted line in is called the N+ / P / N / P+ latching path) is formed. Its contour starts from the N+ region of the NMOS transistor 11, goes to the P-type well, to the adjacent N-type well, and further up to the P+ region of the PMOS transistor 12.

[0006] Once significant noise occurs at the N+ / P junction or the P+ / N junction, an abnormally large current may flow through this N+ / P / N / P+ junction, which may stop certain operations of the CMOS circuit and cause a failure of the entire chip. This abnormal phenomenon called the latching effect is harmful to the operation of the CMOS and must be avoided. One way to increase the resistance to the latching effect, which is indeed a weakness of the CMOS, is to increase the distance between the N+ region and the P+ region ( Figure 1B marked as the latching distance in ). And both the N+ region and the P+ region must be designed to be isolated by some vertical oxides (or other suitable insulating materials) used as isolation regions, which are usually the shallow trench isolation region 13. Taking the 25 nm technology node (λ) as an example, the retained latching distance will be approximately 500 nm, almost 20 times the technology node λ. A more serious effort to avoid the latching effect must design a protection spacer structure that further increases the distance between the N+ region and the P+ region, and / or additional N+ regions or P+ regions must be added to collect abnormal charges from the noise source. These isolation schemes always increase the additional planar area, sacrificing the chip size of the CMOS circuit.

[0007] Current DRAM designs using planar transistors or complementary MOSFETs also introduce or exacerbate other problems:

[0008] (1) All junction leakage caused by junction formation processes such as forming a lightly doped drain (LDD) structure into the substrate / well region, forming an N+ source / drain structure into a P-type substrate, and forming a P+ source / drain structure into an N-type well is becoming increasingly difficult to control because leakage current occurs in the peripheral region and the bottom region, and ion implantation causes lattice defects that create additional damage in these regions that is difficult to repair, such as hole and electron traps.

[0009] (2) In addition, since the ion implantation used to form the LDD structure (or N+ / P junction or P+ / N junction) works like an impact to directly insert ions from the top of the silicon surface straight down into the substrate, it is difficult to create a uniform material interface with few defects from the source and drain regions to the channel and the substrate bulk region because the doping concentration is non-uniformly distributed vertically from the upper surface with a higher doping concentration down to the junction region with a lower doping concentration.

[0010] (3) It is becoming increasingly difficult to align the LDD junction edge perfectly with the edge of the transistor gate structure using only traditional self-alignment methods formed using gates, spacers, and ion implantation. In addition, the thermal annealing process used to remove ion implantation damage must rely on high-temperature processing techniques such as rapid thermal annealing methods using various energy sources or other thermal processes, so a problem that results is gate-induced drain leakage (GIDL). As Figure 1C shown (cited from: A. Sen and J. Das, “MOSFET GIDL Current Variation with Impurity Doping Concentration – A Novel Theoretical Approach” IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO. 5, MAY 2017), in a metal-oxide-semiconductor field-effect transistor structure with thin oxide near the gate and drain / source regions, there is a parasitic metal-gated diode, and the formation of the parasitic metal-gated diode from the gate to the source / drain region causes the initiation of drain leakage current GIDL, and although the drain leakage current GIDL should be minimized to reduce leakage current, the drain leakage current GIDL is difficult to control; other problems that arise are that it is difficult to control the effective channel length, and thus difficult to minimize the short-channel effect.

[0011] (4) Since it is difficult to make the vertical length of the shallow trench isolation structure deeper while the planar width of the device isolation region must be reduced (otherwise it will cause a poor depth and aspect ratio of the opening for the integrated processes of etching, filling, and planarization), the proportion of the planar isolation distance reserved between the N+ region and the P+ region of adjacent transistors to prevent latch-up from occurring in the reduced λ cannot be reduced, but instead will increase. Therefore, it is harmful to the reduction of the chip area when shrinking the CMOS device. Summary of the Invention

[0012] The present invention discloses several new concepts for understanding new planar transistors and planar complementary MOSFET structures, especially used in the peripheral circuits of DRAM chips and sense amplifiers in the array core circuits of DRAM chips, which greatly improve or even solve most of the above problems, such as minimizing leakage current, increasing channel conduction performance and control, optimizing the functions of the source region and the drain region, such as improving the conductivity of the source region and the drain region for metal interconnect components and the closest physical integrity to the channel region with seamless and orderly crystal lattice matching, increasing the immunity of CMOS circuits to latch-up, and minimizing the planar area of the layout isolation region between NMOS and PMOS to avoid latch-up.

[0013] According to one object of the present invention, a DRAM chip or circuit includes: a semiconductor substrate having a semiconductor surface; an array core circuit having a sense amplifier circuit and a plurality of dynamic random access memory cells, the plurality of dynamic random access memory cells being electrically coupled to the sense amplifier circuit; and a peripheral circuit electrically coupled to the array core circuit. Among them, the sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure, and the complementary MOSFET structure includes: a planar P-type MOSFET having a first conductive region; a planar N-type MOSFET having a second conductive region; and a cross-shaped local isolation region located between the planar P-type MOSFET and the planar N-type MOSFET. Among them, the cross-shaped local isolation region includes a horizontally extending isolation region located below the semiconductor surface, and the horizontally extending isolation region contacts the bottom sides of the first conductive region and the second conductive region.

[0014] According to one aspect of the present invention, the complementary MOSFET structure further includes a first recess formed below the semiconductor surface, and the first recess accommodates the first conductive region.

[0015] According to one aspect of the present invention, the first conductive region includes an undoped semiconductor region and / or a lightly doped semiconductor region, which is independent of the semiconductor substrate.

[0016] According to one aspect of the present invention, the undoped semiconductor region or the lightly doped semiconductor region is adjacent to a channel region of the planar P-type MOSFET.

[0017] According to an aspect of the present invention, the first conductive region further includes a heavily doped semiconductor region located in the first recess, wherein the lightly doped semiconductor region and the heavily doped semiconductor region are formed to have the same lattice structure.

[0018] According to an aspect of the present invention, the first conductive region further includes a metal region located in the first recess and adjacent to the heavily doped semiconductor region.

[0019] According to an aspect of the present invention, the complementary MOSFET structure further includes a first recess formed under the semiconductor surface, and the first recess accommodates a first portion of the horizontally extending isolation region.

[0020] According to an aspect of the present invention, the planar P-type MOSFET further includes a gate region located above the semiconductor surface, and an edge of the gate region is aligned or substantially aligned with an edge of the first conductive region.

[0021] According to an aspect of the present invention, the planar P-type MOSFET further includes a gate region, and the entire first portion of the horizontally extending isolation region is not directly located under the gate structure.

[0022] According to an aspect of the present invention, the planar P-type MOSFET further includes a gate region, and less than 5% of the first portion of the horizontally extending isolation region is directly located under the gate structure.

[0023] According to an aspect of the present invention, the horizontally extending isolation region is a composite isolation region.

[0024] According to an aspect of the present invention, the composite isolation region includes an oxide layer and a nitride layer, and the nitride layer is located above the oxide layer.

[0025] According to an aspect of the present invention, a vertical depth of the oxide layer is less than a vertical depth of the nitride layer.

[0026] According to an aspect of the present invention, the horizontally extending isolation region includes a first horizontally extending isolation region and a second horizontally extending isolation region. The first horizontally extending isolation region shields the bottom side of the first conductive region from the semiconductor substrate, and the second horizontally extending isolation region shields the bottom side of the second conductive region from the semiconductor substrate.

[0027] According to an aspect of the present invention, the cross-shaped local isolation region includes a vertically extending isolation region located between the first horizontally extending isolation region and the second horizontally extending isolation region. Wherein, a vertical depth of the vertically extending isolation region is greater than the sum of a vertical depth of the first horizontally extending isolation region and a vertical depth of the first conductive region.

[0028] According to another object of the present invention, a DRAM circuit formed at a technology node λ according to the present invention includes: a semiconductor substrate having a semiconductor surface; an array core circuit having a sense amplifier circuit and a plurality of dynamic random access memory cells, the plurality of dynamic random access memory cells being coupled to the sense amplifier circuit; and a peripheral circuit electrically coupled to the array core circuit. Among them, the sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure, and the complementary MOSFET structure includes: a planar P-type MOSFET including a first source region, a first drain region, and a first gate region, the first gate region being located above the semiconductor surface; and a planar N-type MOSFET including a second source region, a second drain region, and a second gate region, the second gate region being located above the semiconductor surface. Among them, the first source region or the first drain region includes a lightly doped semiconductor region and a heavily doped semiconductor region, and the heavily doped semiconductor region is laterally adjacent to the lightly doped semiconductor region; wherein a dynamic random access memory cell includes an access transistor and a storage capacitor, and the access transistor includes a third source region, a third drain region, and a third gate region, and the third source region or the third drain region includes a lightly doped semiconductor region and a heavily doped semiconductor region, and the heavily doped semiconductor region is vertically adjacent to the lightly doped semiconductor region.

[0029] According to an aspect of the present invention, one edge of the first gate region is aligned or substantially aligned with one edge of the first source region, and the other edge of the first gate region is aligned or substantially aligned with one edge of the first drain region.

[0030] According to an object of the present invention, the complementary MOSFET structure further includes a local isolation region located between the planar P-type MOSFET and the planar N-type MOSFET, and the local isolation region shields a highly doped P+ region in the first source region or the first drain region from the semiconductor substrate.

[0031] According to an aspect of the present invention, the local isolation region includes a vertically extending isolation region and a horizontally extending isolation region, and the latching path between the planar P-type MOSFET and the planar N-type MOSFET depends at least on a bottom length of the horizontally extending isolation region.

[0032] According to another object of the present invention, a DRAM circuit according to the present invention includes: a semiconductor substrate having a semiconductor surface; an array core circuit having a sense amplifier circuit and a plurality of dynamic random access memory cells, the plurality of dynamic random access memory cells being coupled to the sense amplifier circuit; and a peripheral circuit electrically coupled to the array core circuit. Each dynamic random access memory cell includes an access transistor and a storage capacitor. The sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure, and the complementary MOSFET structure includes: a planar P-type MOSFET including a first source region, a first drain region, and a first gate region, the first gate region being located above the semiconductor surface; and a planar N-type MOSFET including a second source region, a second drain region, and a second gate region, the second gate region being located above the semiconductor surface. Wherein, the access transistor includes a third source region, a third drain region, and a third gate region, and at least a part of the third gate region is located below the semiconductor surface; and the first source region and the first drain region have a first lattice structure, the third source region and the third drain region have a second lattice structure, and the first lattice structure is different from the second lattice structure. Moreover, the first source region or the first drain region includes a lower surface that is lower than a lower surface of the first gate region, and the third source region or the third drain region includes a lower surface that is higher than a lower surface of the third gate region.

[0033] According to an aspect of the present invention, the lower surface included in the third source region or the third drain region is aligned or substantially aligned with an upper surface of the third gate region.

[0034] According to an aspect of the present invention, the first source region and the first drain region are independent of the semiconductor substrate, and the third source region and the third drain are independent of the semiconductor substrate.

[0035] According to an aspect of the present invention, wherein the semiconductor substrate is a silicon substrate, the first source region and the first drain region are selectively grown and laterally extended from the (110) crystal plane of the silicon substrate, and the third source region and the third drain region are selectively grown and vertically extended from the (100) crystal plane of the silicon substrate.

[0036] After reading the following detailed description of the preferred embodiments shown in the various drawings, the above and other objects of the present invention will be undoubtedly apparent to those of ordinary skill in the art to which the present invention pertains. Description of the Drawings

[0037] In order to make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given in conjunction with the drawings, wherein:

[0038] Figure 1A is a drawing illustrating a circuit diagram of a DRAM chip.

[0039] Figure 1B is a drawing showing a cross-sectional view of a conventional CMOS structure.

[0040] Figure 1C is a drawing showing a parasitic metal gate diode formed in the gate-to-source / drain region of a MOSFET and the GIDL problem in the MOSFET.

[0041] Figure 2A and Figure 2B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) after depositing a pad nitride layer and forming a shallow trench isolation component.

[0042] Figure 3A and Figure 3B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) after defining the gate length.

[0043] Figure 3-1A and Figure 3-1B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) of another embodiment after forming a shallow trench for the channel region.

[0044] Figure 3-2A and Figure 3-2B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) of another embodiment after selectively forming the channel region.

[0045] Figure 3-3A and Figure 3-3B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) of another embodiment after forming a shallow trench with an arc shape for the channel region.

[0046] Figure 3-4A and Figure 3-4B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) of another embodiment after selectively forming the channel region in a shallow trench with an arc shape.

[0047] Figure 4A and Figure 4B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) after forming the gate conductive region.

[0048] Figure 5A and Figure 5B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) after forming the gate covering region.

[0049] Figure 6A and Figure 6B is a drawing showing a top view and a cross-sectional view along the section line (X-axis) after removing the pad nitride and pad oxide outside the gate region.

[0050] Figure 7A And Figure 7B is a drawing showing a top view and a cross-sectional view along a sectional line (X-axis) after a spacer is formed on the sidewall of the gate region.

[0051] Figure 8A And Figure 8B is a drawing showing a top view and a cross-sectional view along a sectional line (X-axis) after a recess is formed outside the gate region.

[0052] Figure 9A And Figure 9B is a drawing showing a top view and a cross-sectional view along a sectional line (X-axis) after a local isolation layer is formed in the recess.

[0053] Figure 10A And Figure 10B is a drawing showing a top view and a cross-sectional view along a sectional line (X-axis) after a semiconductor region grows laterally from the sidewall exposed in the recess.

[0054] Figure 10C is a drawing showing a cross-sectional view along a sectional line (X-axis) of another embodiment after a semiconductor region grows laterally from the sidewall exposed in the recess.

[0055] Figure 10-1A And Figure 10-1B is a drawing showing a cross-sectional view along a sectional line (X-axis) according to another embodiment after a semiconductor region grows laterally from the sidewall exposed in the recess.

[0056] Figure 11A And Figure 11B is a drawing showing a top view and a cross-sectional view along a sectional line of a vertical dotted line of an embodiment of a planar CMOS structure in a peripheral circuit / sense amplifier of a DRAM chip according to the present invention.

[0057] Figure 12 is a drawing showing a conventional CMOS structure having N+ regions and P+ regions not completely isolated by an insulator.

[0058] Figure 13A And Figure 13B is a drawing showing a top view and a cross-sectional view along a sectional line of a horizontal dotted line of another embodiment of a planar CMOS structure in a peripheral circuit / sense amplifier of a DRAM chip according to the present invention.

[0059] Figure 14 is a drawing showing a potential latch path of a conventional CMOS structure from an N+ / P junction through a P-well / N-well junction to an N / P+ junction structure.

[0060] Figure 15AIt is a cross-sectional view of an access transistor in the array core circuit of a DRAM chip according to the present invention.

[0061] Figure 15B It is a cross-sectional view of an access transistor in the array core circuit of a DRAM chip according to the present invention after forming a recess for accommodating a source region / drain region.

[0062] Figures 16 to 18 It is a cross-sectional view of the formation steps of a semiconductor gate of a proposed NMOS transistor.

[0063] Figures 19 to 21 It is a cross-sectional view of the formation steps of a semiconductor gate of a proposed PMOS transistor.

[0064] Figure 22A It is a cross-sectional view of a conventional polysilicon gate transistor.

[0065] Figure 22B It is a cross-sectional view of a proposed semiconductor gate transistor according to the present invention.

[0066] Reference numerals:

[0067] 10: CMOSFET

[0068] 11: NMOS transistor

[0069] 12: PMOS transistor

[0070] 13: Shallow trench isolation region

[0071] 14: Gate structure

[0072] 15: LDD region

[0073] 17: DRAM chip

[0074] 21: Shallow trench isolation component

[0075] 22: Pad oxide layer

[0076] 23: Pad nitride layer

[0077] 24: Channel region

[0078] 31: Patterning photoresist

[0079] 32: Gate accommodating trench

[0080] 36: Vertical side surface

[0081] 41: Oxide layer

[0082] 42: Nitride layer

[0083] 70: Cross-shaped LISS

[0084] 71: Vertically extending isolation region

[0085] 72: First horizontally extending isolation region

[0086] 73: Second horizontally extending isolation region

[0087] 171: Peripheral circuit

[0088] 172: Array core circuit

[0089] 201: Substrate

[0090] 202: Shallow trench isolation region

[0091] 204: Well region

[0092] 208A: U-shaped channel region

[0093] 208B: U-shaped channel region

[0094] 209: Gate dielectric layer

[0095] 210A: Gate conductive region

[0096] 210B: Gate conductive region

[0097] 213A: Source region

[0098] 213B: Drain region

[0099] 213C: Source region

[0100] 214A: Dielectric gate covering component

[0101] 214B: Dielectric gate covering component

[0102] 216A: First recess

[0103] 216B: Second recess

[0104] 216C: Third recess

[0105] 217A: LDD region

[0106] 217B: LDD region

[0107] 217C: LDD region

[0108] 218A: Heavily doped region

[0109] 218B: Heavily doped region

[0110] 218C: Heavily doped region

[0111] 331: Gate dielectric layer

[0112] 332: Heavily doped polysilicon

[0113] 333: Titanium / Titanium nitride layer

[0114] 334: Tungsten layer

[0115] 335: Nitride capping layer

[0116] 336: Oxide capping layer

[0117] 341: Thin nitride sub-layer

[0118] 342: Thin oxide sub-layer

[0119] 343: Thin oxide sub-layer

[0120] 411: Oxide layer

[0121] 412: Oxide layer

[0122] 430: First semiconductor region

[0123] 431: N+ doped region

[0124] 432: N+ doped region

[0125] 441: P+ doped region

[0126] 442: P+ doped region

[0127] 501: Vertical semiconductor sidewall

[0128] 502: Vertical semiconductor sidewall

[0129] 4301: Vertical P-type layer

[0130] 3321: Thin layer of undoped or doped amorphous silicon (or polysilicon)

[0131] 3322: Larger silicon layer of the die

[0132] 3323: In-situ N+ doped silicon

[0133] 4302: LDD region

[0134] BL: Bit line

[0135] C1: Storage capacitor

[0136] C2: Storage capacitor

[0137] Leff: Effective channel length

[0138] Lgate: Gate length

[0139] OSS: Original silicon surface

[0140] Xn, Xp: Distance Detailed implementation manners

[0141] The present invention discloses a planar transistor and a planar complementary MOSFET structure, especially used in the peripheral circuit of a DRAM chip and the sense amplifier in the array core circuit of a DRAM chip. The manufacturing methods of the proposed planar NMOS transistor and planar PMOS transistor are exemplarily described as follows:

[0142] Step 10: Start.

[0143] Step 20: Based on a semiconductor substrate, define the active regions of the NMOS transistor and the PMOS transistor, and form a deep shallow trench isolation structure.

[0144] Step 30: Form a gate structure above the original semiconductor surface of the semiconductor substrate.

[0145] Step 40: Form spacers to cover the gate structure, and form recesses in the semiconductor substrate.

[0146] Step 50: Form a local isolation layer in the recesses.

[0147] Step 60: Expose the sidewalls of the silicon in the recesses, and laterally grow semiconductor regions from the exposed silicon sidewalls in the recesses to form the source regions and drain regions of the planar NMOS transistor and the planar PMOS transistor.

[0148] Please refer to Figure 2A and Figure 2B , step 20 may include:

[0149] Step 202: Form a pad oxide layer 22, and deposit a pad nitride layer 23.

[0150] Step 204: Use patterned photo-resistance (PR) to define the active regions of the planar NMOS transistor and the planar PMOS transistor, and remove the part of the silicon material outside the active region patterns in the semiconductor substrate to create temporary trenches.

[0151] Step 206: Deposit an oxide layer in the created temporary trenches, and then etch back and planarize the oxide layer to form the shallow trench isolation component 21, wherein the upper surface of the shallow trench isolation component 21 is aligned with the upper surface of the pad nitride layer 23, as Figure 2B shown, which is a cross-sectional view along the Figure 2A X-axis profile line in

[0152] Please refer to Figures 3A to 3B toFigures 5A to 5B The step 30 of forming the gate structure may include:

[0153] Step 302: Use another patterned photoresist 31 to define the gate length Lgate of the gate regions of the planar NMOS transistor and the planar PMOS transistor, and then remove the portions of the pad oxide layer 22 and the pad nitride layer 23 that are not covered by the photoresist to form a gate receiving trench 32, as Figure 3A and Figure 3B shown, wherein, Figure 3B is a cross-sectional view along the Figure 3A X-axis section line in

[0154] Step 304: Then, form a gate dielectric layer 331 (such as a thermal oxide or a high-k material), a highly doped polysilicon 332 (N+ polysilicon for MOS and P+ polysilicon for MOS), a titanium / titanium nitride (Ti / TiN) layer 333, and a tungsten (W) layer 334 in the gate receiving trench 32, as Figure 4A and Figure 4B shown, wherein, Figure 4B is a cross-sectional view along the Figure 4A X-axis section line in

[0155] Step 306: Form a nitride capping layer 335 and an oxide capping layer 336 over the tungsten layer 334 to complete the gate regions of the NMOS transistor and the PMOS transistor, as Figure 5A and Figure 5B shown, wherein, Figure 5B is a cross-sectional view along the Figure 5A X-axis section line in

[0156] Next, please refer to Figures 6A to 6B to Figures 8A to 8B The step 40 may include:

[0157] Step 402: Remove the pad oxide layer 22 and the pad nitride layer 23 between the layers of the shallow trench isolation component 21 and the aforementioned gate regions to expose the original silicon surface OSS of the substrate, as Figure 6A and Figure 6B shown, wherein, Figure 6B is a cross-sectional view along the Figure 6A X-axis section line in

[0158] Step 404: Form a spacer layer on the sides of the aforementioned gate regions, wherein the spacer layer may include a thin oxide sub-layer 343 thermally grown on the original silicon surface OSS of the substrate, and a thin nitride sub-layer 341 and a thin oxide sub-layer 342 over the thin oxide sub-layer 343, as Figure 7A and Figure 7B shown, wherein, Figure 7B is a cross-sectional view along theFigure 7A Cross-sectional view of the X-axis profile line in

[0159] Step 406: Etch a portion of the semiconductor substrate to form recesses in the semiconductor substrate, as Figure 8A and Figure 8B shown, wherein, Figure 8B is a cross-sectional view along the Figure 8A X-axis profile line in

[0160] Please refer to Figure 9A and Figure 9B , step 50 may include: thermally growing an oxide layer 41, which includes a vertical oxide layer 411 and a horizontal oxide layer 412, the vertical oxide layer 411 covering the sidewalls of the recesses in the aforementioned step 406, and the horizontal oxide layer 412 covering the bottoms of the aforementioned recesses. Thereafter, deposit a nitride material with a sufficient thickness to completely fill the aforementioned recesses, and then use an etch-back process to remove the unnecessary portions of the nitride material, leaving only a suitable nitride layer 42 in the aforementioned recesses, as Figure 9A and Figure 9B shown, wherein, Figure 9B is a cross-sectional view along the Figure 9A X-axis profile line in

[0161] It should be noted that, Figure 9B the thicknesses of the oxide layer 411 and the oxide layer 412 shown in Figure 9B and subsequent figures are for illustrative purposes only, but it is very important to design this thermally grown oxide layer 41 such that the thickness of the oxide layer 411 is very precisely controlled under precisely controlled thermal oxidation temperature, timing, and growth rate. Thermal oxidation on a well-defined silicon surface should result in 40% of the thickness of the oxide layer 411 being subtracted from the aforementioned exposed (110) vertical side surface 36 of the silicon substrate, and the remaining 60% thickness of the oxide layer 411 being considered as an addition outside the aforementioned exposed (110) vertical side surface 36 (

[0162] Please refer to Figure 10A and Figure 10B , step 60 may include:

[0163] Step 602: Remove the portion of the oxide layer 411 located above the nitride 42 to expose additional vertical semiconductor sidewalls 501 and 502. Again, when the semiconductor substrate is a silicon substrate, the plurality of vertical semiconductor sidewalls 501 and 502 have (110) crystal planes. The remaining oxide layer 41 and nitride layer 42 can be referred to as Localized Isolation into Silicon Substrate (LISS) in the silicon substrate.

[0164] Step 604: Horizontally grow first semiconductor regions 430 from the exposed vertical semiconductor sidewalls 501 and 502 respectively. Each first semiconductor region 430 can include a lightly doped region (or lightly doped drain (LDD)), or include an undoped region plus a lightly doped region. The first semiconductor regions 430 can be formed by a selective growth method such as Selective Epitaxial Growth (SEG) technology or Atomic Layer Deposition (ALD) technology.

[0165] Step 606: Horizontally grow second semiconductor regions from the plurality of first semiconductor regions 430; each second semiconductor region includes a highly doped region, and the highly doped region can also be formed by a selective growth method. Thus, the drain region of the planar NMOS transistor includes an N-LDD region and an N+ doped region 431, and the source region of the planar NMOS transistor includes another N-LDD region and an N+ doped region 432. Similarly, the drain region of the planar PMOS transistor includes a P-LDD region and a P+ doped region 441, and the source region of the planar PMOS transistor includes another P-LDD region and a P+ doped region 442.

[0166] Note that each of the exposed vertical semiconductor sidewalls 501 and 502 has a vertical boundary that is aligned (or substantially aligned) with the edge of the gate region, as Figure 10B shown. That is, the edges of the source or drain regions in the planar transistor are aligned (or substantially aligned) with the edge of the gate region. The present invention provides a deep SAPC technology (alignment from the gate to the source / drain and precisely creating a crystal structure to form the source / drain). Thus, the alignment from the edge of the source / drain to the edge of the gate region can be precisely defined or controlled by using thermal oxidation and crystal structure, and compared with the conventional method of using LDD implantation for the alignment from the gate edge to the LDD, the GIDL effect should be reduced.

[0167] Moreover, the new source / drain regions are formed by all of the (110) crystalline silicon; as explained, improving the conventional method of growing source / drain regions from two different seed regions results in a mixed lattice of (100) and (110) crystal planes in the silicon substrate. Thus, the present invention can create a better source / drain-to-channel conduction mechanism and can also reduce subthreshold leakage. Also, during planar transistor formation, the effective channel length between the source and drain regions can be almost equal to the gate length ( Figure 10B shown as Leff), because ion implantation and thermal annealing are not required. Since ion implantation is not required to form the LDD regions or the source / drain regions, a thermal annealing process is not required to reduce defects. Thus, any accidental leakage current sources should be significantly minimized because no additional defects are created that are difficult to completely eliminate even by an annealing process once induced.

[0168] In addition, even if there is another thermal annealing process to reduce the connection resistance between the capacitor and the access transistor, since the first semiconductor region 430 of the present invention can include an undoped region plus a lightly doped region, the dopant redistribution caused by another thermal annealing process will not significantly reduce the effective channel length (Leff). Thus, the design rules for the gate length (Lgate) retained for the gate region according to the present invention will be reduced compared to a conventional CMOS structure. Taking the 20nm to 30nm technology node (λ) used in planar transistors as an example, the gate length retained in the present invention will be between 1.5λ and 3λ, such as 2λ or 2.5λ.

[0169] Meanwhile, the source and drain regions of each planar transistor of the present invention are isolated by the insulating materials (nitride layer 42 and remaining oxide layer 41) located on the bottom structure and are isolated along three sidewalls by the layer of the shallow trench isolation component 21. The possibility of junction leakage can only occur in a very small region from the first semiconductor region 430 to the channel region (directly below the planar transistor gate region), thus significantly reducing the possibility of junction leakage.

[0170] In the foregoing embodiment, before forming the gate structure, a channel region can be formed by ion implantation (not shown) near the original silicon surface OSS below the original silicon surface OSS. Then, in addition to the channel region formed by ion implantation, a channel region according to the present invention can be selectively grown. For example, before forming Figure 4B the gate dielectric layer 331 in, the exposed silicon surface can be etched to form a shallow trench with a depth of 1.5nm to 3nm, as Figure 3-1A and Figure 3-1B shown. Then, a channel region 24 is selectively grown in the shallow trench, as Figure 3-2A and Figure 3-2BAs shown. Thereafter, the processes of forming the gate region, source region, and drain region mentioned above can be similarly applied Figure 4A / Figures 4B to 10A / Figure 10B to form another planar transistor structure as shown Figure 10C .

[0171] In yet another embodiment, before forming the gate dielectric layer 331 in Figure 4B , the exposed silicon surface can be etched to form a shallow trench having a circular arc shape or a curved shape, as shown in Figure 3-3A and Figure 3-3B . Then, a channel region 24 is selectively grown along the sidewalls of the shallow trench, as shown in Figure 3-4A and Figure 3-4B . Since the semiconductor channel region 24 is grown along the sidewalls of the curved or circular arc-shaped shallow trench, the channel length in this embodiment can be longer. Thereafter, the processes of forming the gate region, source region, and drain region mentioned above can be similarly applied Figure 4A / Figures 4B to 10A / Figure 10B to form another planar transistor.

[0172] Figure 10-1A and Figure 10-1B are diagrams showing cross-sectional views along the section line (X-axis) after laterally growing a semiconductor region from the sidewalls exposed in the recess according to another embodiment. Figure 10-1A / Figure 10-1B The difference from Figure 10C is that before growing the LDD region 4302 of the NMOS, a vertical P-type layer 4301 is first formed by selective growth, and then the LDD region 4302 and the heavily doped N+ doped regions 431 / 432 are sequentially formed by selective growth. Such a vertical P-type layer 4301 can reduce the leakage current of the NMOS transistor in the off state.

[0173] In another embodiment, the source region (or drain region) can further include some tungsten or other suitable metal materials (not shown), which are located in the recess and contact the heavily doped region of the selectively grown source region (or drain region). Thus, the source region (or drain region) is a composite source region (or drain region). Thus, the external contact will be connected to the metal region of the source region (or drain region), and such a metal-to-metal contact has a lower resistance compared to the conventional silicon-to-metal contact.

[0174] Moreover, as shown in Figures 11A to 11B , Figure 11A is a top view of a new planar CMOS structure according to the present invention, Figure 11B is a diagram showing a cross-sectional view of the new planar CMOS structure along the section line 11A (Y-axis).Figures 11A to 11B The planar PMOS transistor and the planar NMOS transistor in [reference] are arranged vertically side by side. In Figure 11A , the four sides of the new planar CMOS structure are surrounded by the shallow trench isolation component 21. And, as Figures 11A to 11B shown, there is a composite local isolation component (including the oxide layer 412 and the nitride layer 42) between the P+ doped region 442 (or the P+ doped region 441 as the drain region) of the PMOS serving as the source region and the N-type well. Therefore, there is also another composite local isolation component (including the oxide layer 412 and the nitride layer 42) between the N+ doped region 432 (or the N+ doped region 431 as the drain region) of the NMOS serving as the source region and the P-type well or the substrate. That is to say, each drain region and source region of the new planar CMOS structure is surrounded by the shallow trench isolation component 21 on three sidewalls and by the composite local isolation component on the lower sidewall. Thus, the potential latch-up path from the bottom of the P+ region of the PMOS to the bottom of the N+ region of the NMOS is completely blocked by the local isolation component. Therefore, the latch-up distance Xp+Xn (measured on the plane) can be shortened as much as possible without causing serious latch-up problems. On the other hand, in the traditional CMOS structure, the N+ region and the P+ region are not completely isolated by the insulator. As Figure 1B or Figure 12 shown, there is a potential latch-up path from the N+ / P junction through the P-type well / N-type well junction to the N / P+ junction, including the length Length and the length

[0175] Moreover, please refer to Figures 13A to 13B according to another embodiment of the present invention. Figure 13A is a top view of a new planar CMOS structure having a planar NMOS transistor and a planar PMOS transistor, Figure 13B is an attached drawing of a cross-sectional view showing the cross-sectional line of the new planar CMOS structure along the Figure 13A horizontal dotted line. Figures 13A to 13B The planar PMOS transistor and the planar NMOS transistor in [reference] are arranged horizontally side by side. As Figure 13B shown, it can be simplified that there is a cross-shaped LISS 70 between the PMOS transistor and the NMOS transistor. The cross-shaped LISS 70 includes a vertically extending isolation region 71 (such as the shallow trench isolation component 21, and the vertical depth below the OSS is as Figure 13BThe dimensions shown will be approximately 150 nm to 300 nm, such as 200 nm), a first horizontally extending isolation region 72 (vertical depth will be approximately 50 nm to 120 nm, such as 100 nm) located on the right hand side of the vertically extending isolation region 71, and a second horizontally extending isolation region 73 (vertical depth will be approximately 50 nm to 120 nm, such as 100 nm) located on the left hand side of the vertically extending isolation region 71. Each horizontally extending isolation region may comprise an oxide layer 41 and a nitride layer 42. The vertical depth of the source / drain regions of the PMOS transistor / NMOS transistor will be approximately 30 nm to 150 nm, such as 40 nm. The vertical depth of the gate region of the PMOS transistor / NMOS transistor will be approximately 40 nm to 60 nm, such as Figure 13B the 50 nm shown.

[0176] In this embodiment, the first horizontally extending isolation region 72 and the second horizontally extending isolation region 73 are not directly located under the gate structure or channel of the transistor. The first horizontally extending isolation region 72 (right hand side of the vertically extending isolation region 71) contacts the bottom side of the source / drain region of the PMOS transistor, and the second horizontally extending isolation region 732 (left hand side of the vertically extending isolation region 71) contacts the bottom side of the source / drain region of the NMOS transistor. Thus, the bottom sides of the source / drain regions in the PMOS transistor and the NMOS transistor are shielded from the semiconductor substrate. Also, the first horizontally extending isolation region 72 or the second horizontally extending isolation region 73 may be a composite isolation component, which may comprise two or more different isolation materials (such as the oxide layer 41 and the nitride layer 42), or two or more identical isolation materials but each isolation material is formed by a different process.

[0177] As described above and Figure 1B as described, compared to pure NMOS technology, one disadvantage of traditional CMOS type / technology is that once there are parasitic bipolar structures such as N+ / P type substrates / N wells / P+ junctions, and unfortunately some poor designs cannot resist the large current surges caused by the noise that triggers the latch-up effect, which can cause the entire chip operation to shut down or permanent damage to the chip function. The layout and process rules of traditional CMOS always require a very large space to separate the N+ source / drain regions of NMOS from the P+ source / drain regions of PMOS, which is called the latch-up distance ( Figure 1B ), and it will consume a large amount of planar surface space to suppress any possible latch-up effect. Also, if the source / drain N+ / P and P+ / N semiconductor junction areas are too large, once a forward bias accident occurs, it will trigger a large current surge, resulting in the latch-up effect.

[0178] Figure 13BThe new planar CMOS structure in Figure 13B results in a longer path from the N+ / P junction through the P-well (or P-substrate) / N-well junction to the N / P+ junction. As Figure 13B shown, according to the present invention, the potential latch-up path from the LDD-N / P junction through the P-well / N-well junction to the N / LDD-P junction includes

[0179] length ①, length ② (the length of the lower sidewall of a horizontally extending isolation region), length ③, length ④, length ⑤, length ⑥, length ⑦ (the length of the lower sidewall of another horizontally extending isolation region), and length ⑧ marked in length length and length (as Figure 14 shown). Figure 13B Such potential latch-up paths in Figure 14 are longer than the potential latch-up paths in Figure 13B . Therefore, from the perspective of device layout, the edge distance (Xn + Xp) reserved between the NMOS and PMOS in Figure 14 according to the present invention can be smaller than the edge distance (Xn + Xp) reserved in Figure 14 . And, compared with the N+ / P junction to the N / P+ junction in Figure 13B , in Figure 13B , the latch-up path starts from the LDD-N / P junction to the N / LDD-P junction. Since Figure 14 the doping concentration in the LDD-N region or LDD-P region of Figure 13B is lower than the doping concentration in the N+ region or P+ region of Figure 14 , the amount of electrons or holes emitted from the LDD-N region or LDD-P region of Figure 13B will be much lower than the amount emitted from the N+ region or P+ region of

[0180] Please refer to Figure 13B, according to the present invention, the source region or drain region of the planar PMOS is surrounded by a first horizontally extending isolation region 72 and a vertically extending isolation region 71. Only the LDD region (the vertical length will be approximately 10 nm to 50 nm) of the source region or drain region of the planar PMOS contacts the semiconductor substrate to form an LDD-P / N junction, rather than a P+ / N junction. Similarly, the source region or drain region of the planar NMOS is surrounded by a second horizontally extending isolation region 73 and a vertically extending isolation region 71. Only the LDD region (the vertical length will be approximately 40 nm) of the source region or drain region of the planar NMOS contacts the semiconductor substrate to form an LDD-N / P junction, rather than a P+ / N junction. Therefore, the N+ region of the planar NMOS and the P+ region of the planar PMOS are shielded from the substrate or well region. And, since the first horizontally extending isolation region 72 or the second horizontally extending isolation region 73 is a composite isolation component and thick enough, the parasitic metal gate diode induced between the source region (or drain region) and the silicon substrate can be minimized. In addition, the gate-induced drain leakage (GIDL) effect can also be improved. It is expected that the planar latch-up distance reserved for adjacent NMOS transistors and PMOS transistors is significantly shortened, enabling the planar area of the new planar CMOS to be significantly reduced.

[0181] In addition, the source region / drain region directly grown from a specific crystal plane of the semiconductor substrate can be applied to the access transistor of the dynamic random access memory cell in the array core circuit of the DRAM chip. Each dynamic random access memory cell includes an access transistor and a storage capacitor. As Figure 15A shown, an access transistor Q1 includes a source region 213A connected to a storage capacitor C1, a drain region 213B connected to a bit line BL of the DRAM chip, a gate dielectric layer 209 (such as oxide), a gate conductive region 210A (including metal or polysilicon), a dielectric gate covering component 214A (such as oxide / nitride), and a U-shaped channel region 208A surrounding the gate conductive region 210A. Another access transistor Q2 includes a source region 213C connected to a storage capacitor C, a drain region 213B connected to a bit line BL of the DRAM chip, a gate dielectric layer 209 (such as oxide), a gate conductive region 210B (including metal or polysilicon), a dielectric gate covering component 214B (such as oxide / nitride), and a U-shaped channel region 208B surrounding the gate conductive region 210B. The access transistor Q1 and the access transistor Q2 are U-groove transistors or buried gate transistors, and can be formed in the well region 204 of the substrate 201 and surrounded by a shallow trench isolation region 202.

[0182] It should be noted that the source region 213A, the drain region 213B, and the source region 213C can be selectively grown and from Figure 15BThe silicon (100) crystal planes exposed in the shown first recess 216A, second recess 216B, and third recess 216C grow vertically. The source region 213A may include an LDD region 217A and a heavily doped region 218A, the drain region 213B may include an LDD region 217B and a heavily doped region 218B, and the source region 213C may include an LDD region 217C and a heavily doped region 218C, as Figure 15A shown. In the dynamic random access memory cell of the present invention, the source / drain regions of the access transistors grow directly vertically from the (100) crystal plane (e.g., by selective epitaxial growth technology or atomic layer deposition technology), and their interfaces form a seamless junction with the channel region_R. Moreover, no ion implantation process is performed during the formation of the source / drain regions, nor is a thermal annealing process performed that makes it difficult to define and control the junction boundary.

[0183] In summary, since the source / drain regions of the CMOS structure planar transistors in the peripheral circuit / sense amplifier of the DRAM chip grow directly horizontally from the (110) crystal plane, their interfaces form a seamless junction with the channel region, so the gate length (Lgate) can be precisely controlled. Moreover, the surface of the lightly doped drain LDD grows horizontally from the transistor channel and the substrate body by in-situ doping technology during selective growth, without performing an ion implantation process that can only go from the top of the silicon to the source / drain regions, nor is a thermal annealing process performed that makes it difficult to define and control the junction boundary. Unlike the conventional doped regions formed by ion implantation processes, this selectively grown semiconductor region (such as the undoped region, LDD region, and heavily doped region) is independent of the semiconductor substrate.

[0184] The present invention can more precisely define the boundaries of the source / drain to the edges of the gate region and can control the effective channel length (Leff) to minimize short-channel effects, GIDL, and junction leakage current.

[0185] Moreover, in this newly invented planar CMOS structure, the N+ region and the P+ region are completely isolated by isolation components, and the proposed LISS will increase the isolation distance to the silicon substrate to separate the junctions in the NMOS transistor and the PMOS transistor, so that the surface distance between the junctions can be reduced.

[0186] And, in the present invention, selective epitaxial growth forms the LDD to the heavily doped region and even includes various non-silicon dopants such as germanium or carbon atoms, increasing the stress to improve the channel mobility. In the selective epitaxial growth / atomic layer deposition formation of the source / drain regions according to the present invention, the doping concentration profile is controllable or adjustable.

[0187] Moreover, in the well-known CMOS process, the conductive material for the gate of a transistor can be polysilicon or metal. Among them, polysilicon is used because its work function is compatible with the silicon substrate and is often used in the gate-first process. Polysilicon is a material composed of tiny silicon crystals. However, the conductivity of polysilicon is very low, and due to this low conductivity, the accumulation of charges is also low, resulting in a delay in channel formation and thus unnecessary delays in the circuit. Therefore, polysilicon is usually doped with impurities to make it behave like a perfect conductor and reduce the delay.

[0188] However, in the polysilicon gate CMOS process, the polysilicon gate is doped by ion implantation, and problems will occur when the doping of the polysilicon gate is not heavy enough or not uniform. Therefore, the dopant activation concentration is limited. For example, in PMOS transistors, this dopant activation concentration is usually less than 1x10 20 / cm 3 (for example, 7x10 19 / cm 3 ), and in NMOS transistors, this dopant activation concentration is usually less than 4x10 20 / cm 3 (for example, 2.5x10 20 / cm 3 ). In addition, it usually causes the polysilicon depletion effect, which is a phenomenon of unnecessary changes in the critical voltage of the MOSFET device when using polysilicon as the gate material, resulting in unpredictable behavior in electronic circuits. Therefore, in advanced semiconductor processes for polysilicon gate processes, a key issue is to have appropriate dopant activation in the polysilicon (poly-Si) gate to minimize this polysilicon depletion effect.

[0189] On the other hand, when a high-k dielectric (such as hafnium oxide) replaces the SiO2 dielectric as the gate oxide in the mainstream CMOS technology (especially the gate-last process), metal is introduced as the gate conductive material. Since polysilicon is not used in the gate structure, a high-k dielectric metal gate (HKMG) is used to solve the polysilicon depletion effect. Nevertheless, compared with the polysilicon gate CMOS process, this HKMG process is complex and expensive.

[0190] The present invention further solves the problem of doping activation in traditional polysilicon gate transistors, and increases the doping activation concentration in the semiconductor / silicon gate of NMOS transistors to not less than 3×10 20 / cm 3 (N+), for example, 4×10 20 / cm 3 (N+) or higher. Moreover, the doping activation concentration in the semiconductor / silicon gate of PMOS transistors of the present invention can be increased to not less than 8x10 19 / cm 3 (P+), for example, 1x10 20 / cm 3 (P+) or higher. This high doping activation concentration can reduce the polysilicon depletion effect, reduce the thickness of the gate dielectric layer, and improve the on-current (Ion) and gate control ability.

[0191] In traditional transistors with a polysilicon gate structure, for traditional NMOS transistors, the doping activation concentration in this polysilicon gate is only about 2.5×10 20 / cm 3 , while for traditional PMOS transistors, it is about 7×10 19 / cm 3 . In the manufacturing process of traditional polysilicon gates, an undoped polysilicon layer is usually deposited above the gate oxide layer. Then, taking the NMOS transistor as an example, arsenic (As) or phosphorus (P) ions are implanted into the undoped polysilicon, and then rapid thermal annealing is used to activate the doping concentration.

[0192] On the other hand, in the proposed transistors with a highly doped silicon gate structure, for NMOS transistors, the doping activation concentration in this highly doped silicon gate can be greater than 4x10 20 / cm 3 , while for PMOS transistors, it can be greater than 1x10 20 / cm 3 . According to the exemplary manufacturing process of the NMOS transistor as Figures 16 to 18 shown in the present invention, in order to increase the doping activation concentration in the gate structure, after forming the gate dielectric layer 331 (such as thermal oxide or high-k material), a thin layer 3321 of undoped or doped amorphous silicon (or polysilicon) is first deposited above the gate dielectric layer 331 at a temperature of 500°C to 650°C, as Figure 16As shown. Next, anneal such an amorphous silicon layer at a temperature of about 1000 °C or higher (e.g., laser annealing, about 1200 °C, plus thermal annealing, about 600 °C) for recrystallization to become a silicon layer with larger die, and the grain size can be greater than 1 micrometer (μm) to 2 micrometers. For example, see T.I. KAMINS AND T.R. CASS, “STRUCTURE OF CHEMICALLY DEPOSITED POLYCRYSTALLINE-SILICON FILMS”, Thin Solid Films, 16(1973)147 - 165; see also Yasuo Wada and Shigeru Nishimatsu, “Grain Growth Mechanism of Heavily Phosphorus-implanted Polycrystalline Silicon”, J.Electrochem.Soc.: SOLID-STATE SCIENCE AND TECHNOLOGY, Vol.125, No.9, 1499 - 1504, September 1978).

[0193] After that, as Figure 17 shown, use the silicon layer 3322 with larger die as a seed layer to selectively grow (e.g., selective epitaxial growth (SEG)) a layer of in-situ N+-doped silicon 3323. Then, anneal at a temperature of about 1000 °C or higher by a rapid thermal anneal (RTA) process, so that the doping activation concentration in the selectively grown silicon layer can be about 4x10 20 / cm 3 (Please see Z.N. Weinrich, et al, “Dopant-defect interactions in highly doped epitaxial Si:P thin films”, Thin Solid Films 685(2019)1–7). Moreover, since the originally undoped amorphous silicon layer is extremely thin, through the above rapid thermal annealing, the dopants in the in-situ N+-doped silicon layer will diffuse outward into the recrystallized silicon layer with larger die, making the doping concentration of the recrystallized silicon layer with larger die almost equal to that of the in-situ N+-doped silicon layer. Thus, after rapid thermal annealing, it is almost difficult to distinguish the in-situ N+-doped silicon 3323 and the silicon layer 3322 with larger die.

[0194] After that, to complete the NMOS transistor structure, as Figure 18As shown, a standard gate patterning process can be applied to form a gate shape, a titanium nitride (TiN) layer 333 and a tungsten layer 334 can be deposited on top of the in-situ N+ doped silicon 3323, an LDD region and a nitride spacer can then be formed, and an N+ source / drain region can be formed by ion implantation and annealing processes, as shown in FIG. Figure 18 As shown. It should be noted that the grain size of the larger silicon layer of the recrystallized tube core can be larger than 1um to 2um, and the same is true for the in-situ N+ doped silicon layer formed by selective epitaxial growth. After the standard gate patterning process is formed based on the technology node below 28nm, the gate length is usually not more than 150nm. Therefore, in the gate length of the in-situ N+ doped silicon layer, the in-situ N+ doped silicon layer is almost a single crystal layer; or, along the tangent of the gate length, the in-situ N+ doped silicon layer will contain no more than three silicon tube cores.

[0195] Similarly, in the process of forming a conventional PMOS transistor, a layer of undoped polysilicon is first deposited over the gate oxide layer. Boron (B) ions are then implanted into the undoped polysilicon, followed by rapid thermal annealing to activate the doping concentration. In this polysilicon gate of a conventional PMOS transistor, the doping activation concentration will not be greater than 1x10 20 / cm 3 .on the other hand, Figures 19 to 21 An exemplary process of manufacturing a PMOS transistor according to the present invention is shown. Figures 16 to 18 Similar details are omitted here, however, the dopant type in the epitaxial silicon gate of the PMOS transistor is different from the dopant type in the epitaxial silicon gate of the NMOS transistor. In such an epitaxial silicon gate of the PMOS transistor according to the present invention, the doping activation concentration will not be greater than 1×10 20 / cm 3 .

[0196] Figure 22A and Figure 22B A polysilicon gate transistor ( Figure 22A ) and the polysilicon gate transistor ( Figure 22B ). The high doping activation concentration of the in-situ N+ / P+ doped silicon 3323 can reduce the polysilicon depletion effect, reduce the thickness of the gate dielectric layer 331, and improve the on-current and gate control capability. In summary, the present invention solves the doping activation problem in the traditional polysilicon gate transistor, and increases the doping activation concentration in the silicon gate of the NMOS transistor and the PMOS transistor to not less than 4×10 20 / cm 3 (N+) and 1x10 20 / cm 3(P+). This high doping activation concentration can reduce the polysilicon depletion effect, reduce the thickness of the gate dielectric layer, and improve the on-current and gate control ability. The present invention can be applied to all transistors with silicon gates, such as planar transistors, fin-structured transistors, gate-all-around (GAA) transistors, and so on. Moreover, such a polycrystalline silicon gate transistor can be applied not only to the logic circuits of semiconductor memories such as DRAM, but also to peripheral circuits. And the present invention can be applied to other semiconductor materials used for the gate structure of MOS transistors, such as silicon germanium (SiGe), silicon carbide (SiC), or gallium nitride (GaN), and so on.

[0197] Those of ordinary skill in the art to which the present invention pertains will readily observe that various modifications and changes can be made to the apparatus and method while retaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the scope and bounds of the claims.

Claims

1. A semiconductor transistor, comprising: a source region, a drain region, and a channel region located between the source region and the drain region; and a gate region located above the channel region, wherein the gate region includes a gate dielectric layer and an epitaxially doped semiconductor layer, the gate dielectric layer is located on the channel region, and the epitaxially doped semiconductor layer is located above the gate dielectric layer.

2. The semiconductor transistor according to claim 1, characterized in that, The semiconductor transistor is an N-type metal-oxide-semiconductor transistor. The epitaxially doped semiconductor layer is an epitaxially doped silicon layer, and the doping activation concentration of the epitaxially doped silicon layer is not less than 3x10 20 / cm 3 .

3. The semiconductor transistor according to claim 1, wherein, The semiconductor transistor is a P-type metal-oxide-semiconductor transistor. The epitaxially doped semiconductor layer is an epitaxially doped silicon layer, and the doping activation concentration of the epitaxially doped silicon layer is not less than 8x10 19 / cm 3 .

4. The semiconductor transistor according to claim 1, characterized in that, The gate region further includes a titanium nitride layer and a tungsten layer located above the epitaxially doped semiconductor layer.

5. The semiconductor transistor according to claim 4, wherein, The semiconductor transistor is a transistor in a peripheral circuit of a dynamic random access memory.

6. A method for manufacturing a semiconductor transistor, comprising: preparing a semiconductor substrate; forming a gate region in the semiconductor substrate, wherein the gate region includes an epitaxially doped semiconductor layer; and forming a source region and a drain region, wherein the gate region is between the source region and the drain region.

7. The method for manufacturing a semiconductor transistor according to claim 6, wherein, The step of forming the gate region includes: forming a gate dielectric layer above the semiconductor substrate; depositing an amorphous semiconductor layer above the gate dielectric layer; annealing the amorphous semiconductor layer for recrystallization; selectively growing the epitaxially doped semiconductor layer based on the recrystallized semiconductor layer; and thermally annealing the epitaxially doped semiconductor layer.

8. The method for manufacturing a semiconductor transistor according to claim 7, wherein, The grain size of the recrystallized semiconductor layer is from 1 um to 2 um.

9. The method for manufacturing a semiconductor transistor according to claim 7, wherein, The step of forming the gate region further includes: forming a titanium nitride layer above the epitaxially doped semiconductor layer; and forming a tungsten layer on the titanium nitride layer.

10. The method for manufacturing a semiconductor transistor according to claim 6, characterized in that, The semiconductor transistor is an N-type metal-oxide-semiconductor transistor. The epitaxially doped semiconductor layer is an epitaxially doped silicon layer, and the doping activation concentration of the epitaxially doped silicon layer is not less than 3x10 20 / cm 3 .

11. The method for manufacturing a semiconductor transistor according to claim 6, wherein, The semiconductor transistor is a P-type metal-oxide-semiconductor transistor. The epitaxially doped semiconductor layer is an epitaxially doped silicon layer, and the doping activation concentration of the epitaxially doped silicon layer is not less than 8x10 19 / cm 3 .

12. A semiconductor transistor, comprising: a source region, a drain region, and a channel region located between the source region and the drain region; and a gate region located above the channel region, wherein the gate region includes a gate dielectric layer and a highly doped semiconductor layer, the gate dielectric layer is located on the channel region, and the highly doped semiconductor layer is located above the gate dielectric layer. Wherein, the gate length of the gate region is not greater than 150 nm, and wherein, within the gate length, the highly doped semiconductor layer is a single crystal layer, or, along the gate length, the highly doped semiconductor layer includes no more than three semiconductor die.

13. The semiconductor transistor according to claim 12, wherein, The semiconductor transistor is an N-type metal-oxide-semiconductor transistor. The highly doped semiconductor layer is a highly doped silicon layer, and the doping activation concentration of the highly doped silicon layer is not less than 3x10 20 / cm 3 .

14. The semiconductor transistor according to claim 12, wherein The semiconductor transistor is a P-type metal-oxide-semiconductor transistor. The highly doped semiconductor layer is a highly doped silicon layer, and the doping activation concentration of the highly doped silicon layer is not less than 8x10 19 / cm 3 .

15. A semiconductor transistor, comprising: a source region, a drain region, and a channel region located between the source region and the drain region; and a gate region located above the channel region, characterized in that the gate region includes a gate dielectric layer and a doped semiconductor layer, the gate dielectric layer is located on the channel region, and the doped semiconductor layer is located above the gate dielectric layer. Wherein, when the semiconductor transistor is an N-type metal-oxide-semiconductor transistor, the doping activation concentration of the doped semiconductor layer is not less than 3x10 20 / cm 3 , or, when the semiconductor transistor is a P-type metal-oxide-semiconductor transistor, the doping activation concentration of the doped semiconductor layer is not less than 8x10 19 / cm 3 .

16. The semiconductor transistor according to claim 15, characterized in that, The doped semiconductor layer is a doped silicon layer or a doped silicon germanium layer.

17. The semiconductor transistor according to claim 15, characterized in that, The semiconductor transistor is a transistor in a peripheral circuit of a dynamic random access memory chip.

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