Nanowire double-gate quantum well infrared detection transistor and preparation method thereof
Nanowire detectors designed with nanowire double gate structure and quantum well layer solve the shortcomings of traditional transistor detectors in high sensitivity, fast response and low power consumption, and achieve efficient three-dimensional integration and high sensitivity infrared detection.
Patent Information
- Application Number
- CN202510225970.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-07-11
AI Technical Summary
Traditional transistor detectors have shortcomings in high sensitivity, fast response and low power consumption, and are difficult to achieve efficient three-dimensional integration. The single-gate structure gate control capability of nanowire detectors is limited.
Using nanowire double gate structure and quantum well layer design, electrons and holes are confined to two-dimensional space through the quantum well layer, combined with dual gate regulation, optimize carrier concentration and photoresponse performance, and achieve high precision and small feature size applications.
It significantly improves the light-dark current ratio, response speed and gate control capability, realizes high sensitivity and efficient three-dimensional integration, and is suitable for high-precision infrared detection.
Smart Images
Figure CN120302731A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an infrared detection transistor, in particular to a nanowire double-gate quantum well infrared detection transistor and a preparation method thereof. Background Art
[0002] With the rapid development of semiconductor technology, traditional transistor detectors face many challenges in terms of performance improvement. Traditional transistor detectors are mainly designed based on planar structures, with limited gate control ability, making it difficult to meet the requirements of modern high-performance detectors for high sensitivity, fast response, and low power consumption. In addition, traditional detectors also have deficiencies in terms of the light-to-dark current ratio, response speed, and three-dimensional integration ability, restricting their applications in fields such as high-precision infrared detection.
[0003] To overcome the limitations of traditional transistor detectors, researchers have proposed various improvement schemes, such as new gate structures like SOI (silicon-on-insulator) and FinFET (fin field-effect transistor). However, although these structures have improved the gate control ability to a certain extent, there are still deficiencies in terms of light response performance and three-dimensional integration. For example, although the FinFET structure can enhance the gate control ability, due to the complexity of its three-dimensional structure, it is difficult to achieve efficient light absorption and fast light response.
[0004] In recent years, nanowire structures have received extensive attention due to their unique physical properties. Nanowires have the advantages of a high surface area ratio and being easy to fabricate a surrounding gate structure, which can significantly improve the gate control ability and device performance. In addition, the nanowire structure can be further optimized through the design of quantum wells, and quantum wells can effectively improve the carrier mobility and light response ability of the material, showing great potential in the field of weak light detection.
[0005] At present, many research groups and companies at home and abroad have the ability to grow III-V nanowires on silicon substrates: Mamidala Saketh Ram of Lund University in Sweden demonstrated the preparation of an InAs nanowire 1T1R array in the article "High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon" published in Nature Electronics, 2021, 4(12): 914-920. Kensuke Kusao of Hokkaido University in Japan demonstrated the growth and preparation of vertical nanowire transistors of various III-V materials in his doctoral thesis "Growth of III-V Compound Semiconductor Nanowire Heterostructures and Their Electron Device Applications".
[0006] The existence of quantum wells can greatly improve the surface characteristics of materials and increase the mobility of semiconductor materials, thus improving the switching speed of devices; and because of their extremely sensitive properties to light, they can achieve extremely high sensitivity to light in a certain wavelength range. For example, Zhongrui Wang et al. of Southern University of Science and Technology demonstrated the improvement of the light response performance of quantum dot devices in the article "Ultralow-power optoelectronic synaptic transistors based on polyzwitterion dielectrics for in-sensor reservoir computing" published in Advanced Science, 2021, 8(16): 2100513. Also, because nanowires have an extremely high surface area ratio, using quantum wells in vertical nanowires can produce devices with more sensitive light responses.
[0007] However, most current nanowire detectors use a single-gate structure, with limited gate control ability, and it is difficult to achieve efficient three-dimensional integration. It is difficult to ensure both high sensitivity and response speed. Summary of the Invention
[0008] This application provides a nanowire double-gate quantum well infrared detection transistor and its preparation method to solve the problems in the background technology.
[0009] The present invention optimizes the structure of a detector with a nanowire structure. The nanowire is divided by a quantum well layer into a second part inside and a first part outside. With the setting of the cooperative gate, dual-gate regulation is achieved to meet the increasing demand for gate control ability due to the decreasing feature size of current devices. The carrier concentration inside the quantum well can be regulated more precisely, making it applicable to application scenarios with higher precision and smaller feature sizes. It has high sensitivity while ensuring the response speed.
[0010] In this application, the presence of the quantum well can significantly improve the photocurrent-to-dark-current ratio. Through the quantum confinement effect, the quantum well layer confines electrons and holes in a two-dimensional space, discretizes the energy levels, thereby enhancing the accumulation of photo-generated carriers and the generation efficiency of photocurrent. At the same time, the recombination and separation of carriers in the quantum well layer are more efficient, reducing the generation of dark current. In addition, the quantum well layer structure can reduce the dark current by adjusting the energy band and interface characteristics, and optimize the absorption ability for light of a specific wavelength, further improving the generation of photo-generated carriers. The quantum well layer also changes the density-of-states distribution of electrons, making it easier for carriers to occupy low-energy states, thereby improving the mobility and lifetime, and further enhancing the optoelectronic performance. In summary, through the combined action of multiple mechanisms, the quantum well layer significantly improves the photocurrent-to-dark-current ratio of the phototransistor.
[0011] When voltages are applied to the first gate and the second gate, electric fields are respectively formed in the first part and the second part, confining the carriers in the quantum well layer. And because there are fewer defects in the quantum well layer, the carrier transport rate becomes faster, so that the device reaches a faster light response rate.
[0012] Due to the presence of the second gate, it can play multiple roles such as adjusting the threshold voltage, enhancing the electric field control, reducing the leakage current, increasing the transconductance, and optimizing the device performance, significantly improving the gate control ability of the dual-gate transistor.
[0013] Without the presence of the second gate, only when a voltage is applied to the first gate, the current in this application will pass through the second part, and the current cannot be confined in the quantum well layer, resulting in a small photocurrent-to-dark-current ratio and low light response sensitivity.
[0014] The present invention provides the following technical solution: a nanowire dual-gate quantum well infrared detection transistor, including a first part and a second part. The first part is sleeved outside the second part and combined to form a nanowire structure. The first part is an intrinsic core layer, the second part is a low-doped shell layer, and there is a quantum well layer between the first part and the second part. A source electrode and a drain electrode are provided outside the first part, and a first gate located between the source electrode and the drain electrode is also provided outside the first part. The first gate is isolated from the first part by a gate dielectric layer. The second part is connected to the second gate. The bandgap width of the material of the quantum well layer is lower than the bandgap widths of the materials of the first part and the second part.
[0015] The first part and the second part are isolated by a quantum well layer, which has fewer lattice defects. Therefore, the carriers inside it have a faster mobility. And because the quantum well layer is more sensitive to light response, it has a faster response rate and a larger light-to-dark current ratio compared to traditional transistors.
[0016] In this application, the positions of the source electrode and the drain electrode can be interchanged, as long as it is ensured that the first gate is located between the source electrode and the drain electrode.
[0017] Further, the second part is connected to the second gate through a substrate layer.
[0018] Further, the first gate, or the source electrode, or the drain electrode is made of a transparent material.
[0019] Further, the materials of the first part, the second part, and the quantum well layer are respectively selected from one of III-V materials, binary compounds of III-V materials, ternary compounds of III-V materials, and quaternary compounds of III-V materials.
[0020] Further, the material of the first gate is ITO or FTO; the material of the source electrode or the drain electrode is ITO or FTO; the gate dielectric layer uses a transparent high-k material, and its relative permittivity value in vacuum is greater than 10. The transparent high-k material is HfO2 or Al2O3.
[0021] Further, the source electrode, the drain electrode, and the first gate are isolated by an isolation layer.
[0022] Further, the isolation layer uses a low-k material with a relative permittivity value less than 4.
[0023] Further, the second gate is a metal gate.
[0024] A method for fabricating the above-mentioned nanowire double-gate quantum well infrared detection transistor includes the following steps: 1) Prepare an oxide layer on the substrate layer by the method of dry oxidation, and then perform photolithography and etching to pattern the oxide layer to determine the diameter and array of nanowire growth; 2) Prepare nanowires by autocatalysis or Au catalysis; 3) Spin-coat photoresist, perform photolithography, and after exposing and developing to determine the position of the source electrode, define the position of the source electrode, and then prepare the source electrode by thermal evaporation, electron beam evaporation, or magnetron sputtering; 4) Prepare an isolation layer between the source electrode and the first gate; 5) Spin-coat photoresist, perform photolithography and etching on the isolation layer prepared in step 4 to determine the position of the first gate, and then prepare the gate dielectric layer and the first gate by thermal evaporation, electron beam evaporation, or magnetron sputtering; 6) Prepare the gate dielectric layer and the isolation layer between the first gate and the drain; 7) Spin coat, lithograph, and etch on the isolation layer prepared in step 7 to define the drain region and fabricate the drain; 8) Fabricate the second gate by thermal evaporation, electron beam evaporation, or magnetron sputtering under the oxide layer; 9) Perform low-temperature annealing on the device to eliminate the Schottky barrier.
[0025] The beneficial effects of the present invention are as follows: The infrared detection transistor of the present application has a larger light-to-dark current ratio, faster response speed, and stronger gate control ability through the dual-gate structure and quantum well layer design, and has high sensitivity while ensuring the response speed. Description of the Drawings
[0026] Figure 1 It is a schematic structural diagram of Embodiment 1 of a nanowire dual-gate quantum well infrared detection transistor of the present invention; Figure 2 It is a schematic diagram showing that the source and drain of Embodiment 1 of a nanowire dual-gate quantum well infrared detection transistor of the present invention are conducted through the first gate; Figure 3 It is a schematic diagram showing that the source and drain of Embodiment 1 of a nanowire dual-gate quantum well infrared detection transistor of the present invention are conducted through the second gate; Figure 4 It is a schematic structural diagram of Embodiment 2 of a nanowire dual-gate quantum well infrared detection transistor of the present invention; Figure 5 It is a schematic structural diagram of Embodiment 3 of a nanowire dual-gate quantum well infrared detection transistor of the present invention; Figure 6 It is a schematic diagram showing that the source and drain of Embodiment 3 of a nanowire dual-gate quantum well infrared detection transistor of the present invention are conducted through the first gate; Figure 7 It is a schematic diagram showing that the source and drain of Embodiment 3 of a nanowire dual-gate quantum well infrared detection transistor of the present invention are conducted through the second gate; Wherein, the first part 1, the second part 2, the quantum well layer 3, the source 4, the drain 5, the first gate 6, the gate dielectric layer 7, the second gate 8, the substrate layer 9, the oxide layer 10, the isolation layer 11. Detailed Embodiments
[0027] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following describes in detail the specific embodiments, structures, features, and their effects of the present invention in combination with the accompanying drawings and preferred embodiments.
[0028] The present invention provides a nanowire double-gate quantum well infrared detection transistor and a preparation method thereof. Through a unique double-gate structure and quantum well layer design, the photodark current ratio, response speed, and gate control ability of the detector are significantly improved. At the same time, efficient three-dimensional integration is achieved, and high sensitivity is obtained while ensuring the response speed.
[0029] The embodiments of the present invention will be further described in multiple embodiments below.
[0030] Embodiment 1 As Figure 1 , a nanowire double-gate quantum well infrared detection transistor includes a first part 1 and a second part 2. The first part 1 is sleeved outside the second part 2 and combined to form a nanowire structure. The first part 1 is an intrinsic core layer, and the second part 2 is a low-doped shell layer. There is a quantum well layer 3 between the first part 1 and the second part 2. A source electrode 4 and a drain electrode 5 are provided outside the first part 1. A first gate 6 is also provided outside the first part 1 between the source electrode 4 and the drain electrode 5. The first gate 6 is isolated from the first part 1 by a gate dielectric layer 7. The second part 2 is connected to a second gate 8. The bandgap width of the material of the quantum well layer 3 is lower than that of the materials of the first part 1 and the second part 2.
[0031] The first gate 6 and the source electrode 4 are made of transparent materials.
[0032] The material of the first part 1 is InP (1.344 ev); The material of the second part 2 is InP (1.344 ev); The material of the quantum well layer 3 is In 0.53 Ga 0.47 As (0.74 ev); The gate dielectric layer 7 is made of a transparent high-k material with a relative vacuum permittivity value greater than 10, and the transparent high-k material is HfO2.
[0033] The source electrode 4, the drain electrode 5, and the first gate 6 are isolated by an isolation layer 11.
[0034] The isolation layer 11 is made of a low-k material with a relative permittivity value less than 4, specifically BCB.
[0035] The second gate 8 is a metal gate, specifically made of titanium gold, and can also be made of nickel gold or aluminum gold.
[0036] In the absence of light: Case 1: A voltage is applied to the source electrode 4 and the drain electrode 5 of the device, and no voltage is applied to the first gate 6 and the second gate 8 of the device. The conduction current of the device is as Figure 2As shown, in this case, due to the lack of control of the gate electric field, carriers will flow in the first part 1 under the control of the source 4 and the drain 5; Case 2: A voltage is applied to the source 4 and the drain 5 of the device, and a voltage is applied to the first gate 6 and the second gate 8 of the device. The on-current of the device is as Figure 3 shown. In this case, due to the application of voltage to the first gate 6 and the second gate 8, the distribution of the electron gas will be concentrated in the quantum well layer 3, making the quantum well layer 3 rich in carriers. And because there are fewer defects in the quantum well layer 3, the carrier transport rate will be faster; Under light conditions (select the following materials): The material of the first part 1 is InP (1.344 eV); The material of the second part 2 is InP (1.344 eV); The material of the quantum well layer 3 is In0.53Ga0.47As (0.74 eV); When light with wavelengths of 1310 and 1550 nm irradiates in: For Case 2, photo-generated carriers will be generated in the quantum well layer 3 part of the device. Due to the increase in the number of photo-generated carriers in the quantum well layer 3, the current between the source and the drain will increase. And because the conductive layer is mainly the quantum well layer 3 and there are fewer lattice defects inside, it will respond to the light source faster; For Case 1, since the main conductive layer is the first part 1 and InP is selected, its turn-on band is about 922 nm. Therefore, it has basically no response to the infrared band, and thus the current in Case 1 remains basically unchanged.
[0037] Therefore, due to the two working modes of the device, it can detect the infrared band between 922 - 1675 nm.
[0038] Embodiment 2 As Figure 4 , a nanowire double-gate quantum well infrared detection transistor includes a first part 1 and a second part 2. The first part 1 is sleeved outside the second part 2 and combined to form a nanowire structure; the first part 1 is an intrinsic core layer, the second part 2 is a low-doped shell layer, and there is a quantum well layer 3 between the first part 1 and the second part 2; a source 4 and a drain 5 are provided outside the first part 1, and a first gate 6 located between the source 4 and the drain 5 is also provided outside the first part 1. The first gate 6 is isolated from the first part 1 by a gate dielectric layer 7; the second part 2 is connected to the second gate 8; the bandgap of the material of the quantum well layer 3 is lower than the bandgaps of the materials of the first part 1 and the second part 2.
[0039] The first gate 6 and the drain 5 are made of transparent materials.
[0040] The material of the first part 1 is GaAs (1.42 eV); The material of the second part 2 is GaAs (1.42 eV); The material of the quantum well layer 3 is In0.53Ga0.47As0.47P0.53 (1.02 eV); The gate dielectric layer 7 is made of a transparent high-k material with a relative permittivity greater than 10, and the transparent high-k material is Al2O3.
[0041] The source 4, drain 5, and the first gate 6 are isolated by an isolation layer 11.
[0042] The isolation layer 11 is made of a low-k material with a relative permittivity less than 4, specifically SOG.
[0043] The second gate 8 is a metal gate, specifically nickel-gold, and it can also be titanium-gold or aluminum-gold.
[0044] In this embodiment, the schematic diagram of the conduction between the source 4 and the drain 5 is the same as that of Figure 2 and Figure 3 Example 1.
[0045] Example 3 Such as Figure 5 , a nanowire double-gate quantum well infrared detection transistor, including a first part 1 and a second part 2. The first part 1 is sleeved outside the second part 2 and combined to form a nanowire structure; the first part 1 is an intrinsic core layer, the second part 2 is a low-doped shell layer, and there is a quantum well layer 3 between the first part 1 and the second part 2; a source 4 and a drain 5 are provided outside the first part 1, and a first gate 6 located between the source 4 and the drain 5 is also provided outside the first part 1. The first gate 6 is isolated from the first part 1 by a gate dielectric layer 7; the second part 2 is connected to the second gate 8; the bandgap of the material of the quantum well layer 3 is lower than the bandgaps of the materials of the first part 1 and the second part 2.
[0046] The second part 2 is connected to the second gate 8 through a substrate layer 9, and the substrate layer 9 is isolated from the first part 1 and the quantum well layer 2 by an oxide layer 10.
[0047] The first gate 6 and the drain 5 are made of transparent materials.
[0048] The material of the first part 1 is AlGaAs; The material of the second part 2 is AlGaAs; The material of the quantum well layer 3 is In0.53Ga0.47As (0.74 eV); The gate dielectric layer 7 is made of a transparent high-k material with a relative permittivity greater than 10, and the transparent high-k material is HfO2.
[0049] The source electrode 4, the drain electrode 5, and the first gate electrode 6 are isolated by an isolation layer 11.
[0050] The isolation layer 11 is made of a low dielectric constant material with a relative dielectric constant value less than 4, specifically BCB.
[0051] The second gate 8 is a metal gate, specifically made of aluminum alloy, and can also be made of titanium alloy or nickel alloy.
[0052] Such as Figure 6 is a schematic diagram showing that the source electrode 4 and the drain electrode 5 are not conducted through the first gate electrode 6 and the second gate electrode 8; such as Figure 7 is a schematic diagram showing that the source electrode 4 and the drain electrode 5 are conducted through the first gate electrode 6 and the second gate electrode 8.
[0053] Under the condition of no light: Case 1: A voltage is applied to the source electrode 4 and the drain electrode 5 of the device, and no voltage is applied to the first gate electrode 6 and the second gate electrode 8 of the device. The conduction current of the device is as Figure 6 shown. In this case, due to the lack of control of the gate electric field, the carriers will flow in the first part 1 under the control of the source electrode 4 and the drain electrode 5; Case 2: A voltage is applied to the source electrode 4 and the drain electrode 5 of the device, and a voltage is applied to the first gate electrode 6 and the second gate electrode 8 of the device. The conduction current of the device is as Figure 7 shown. In this case, due to the application of voltage to the first gate electrode 6 and the second gate electrode 8, the distribution of the electron gas will be concentrated in the quantum well layer 3, and the quantum well layer 3 will be rich in carriers. And because there are fewer defects in the quantum well layer 3, the carrier transport rate will become faster; For Case 2, photo-generated carriers will be generated in the quantum well layer 3 part of the device. Due to the increase in the number of photo-generated carriers in the quantum well layer 3, the current between the source and the drain will increase. And because the conductive layer is mainly the quantum well layer 3 and there are fewer internal lattice defects, it will react to the light source faster.
[0054] Example 4 A method for preparing the nanowire double-gate quantum well infrared detection transistor of Example 3 includes the following steps: 1) Prepare an oxide layer 10 on the substrate layer 9 by the method of dry oxygen, and then perform photolithography and etching to pattern the oxide layer to determine the diameter and array of the nanowire growth; 2) Prepare nanowires by self-catalysis or Au catalysis. The nanowires include a first part 1 and a second part 2. The first part 1 is sleeved outside the second part 2, and there is a quantum well layer 3 between the two; 3) Spin-coat the photoresist, perform photolithography, develop after exposing to determine the position of the source electrode 4, define the position of the source electrode 4, and then prepare the source electrode 4 by thermal evaporation, electron beam evaporation or magnetron sputtering. 4) Prepare the isolation layer 11 between the source electrode 4 and the first gate electrode 6; 5) Spin coat, lithograph, and etch on the isolation layer 11 prepared in step 4 to determine the position of the first gate electrode 6, and then prepare the gate dielectric layer 7 and the first gate electrode 6 by thermal evaporation, electron beam evaporation, or magnetron sputtering; 6) Prepare the isolation layer 11 between the gate dielectric layer 7 and the first gate electrode 6 and the drain electrode 5; 7) Spin coat, lithograph, and etch on the isolation layer 11 prepared in step 7 to determine the drain electrode 5 region, and prepare the drain electrode 5; 8) Prepare the second gate electrode 10 by thermal evaporation, electron beam evaporation, or magnetron sputtering under the oxide layer 11; 9) Perform low-temperature annealing on the device to eliminate the Schottky barrier.
[0055] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed as above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any brief modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.
Claims
1. A nanowire double-gate quantum well infrared detection transistor, characterized in that, It includes a first part and a second part. The first part is sleeved outside the second part and they are combined to form a nanowire structure. The first part is an intrinsic core layer, the second part is a low-doped shell layer, and there is a quantum well layer between the first part and the second part. A source electrode and a drain electrode are provided outside the first part, and a first gate electrode is also provided between the source electrode and the drain electrode outside the first part. The first gate electrode is isolated from the first part by a gate dielectric layer. The second part is connected to a second gate electrode. The bandgap width of the material of the quantum well layer is lower than that of the materials of the first part and the second part.
2. The transistor according to claim 1, wherein, The second part is connected to the second gate electrode through a substrate layer. The substrate layer is isolated from the first part and the quantum well layer by an oxide layer.
3. The transistor according to claim 1, wherein The first gate electrode, or the source electrode, or the drain electrode is made of a transparent material.
4. The transistor according to claim 3, characterized in that, The materials of the first part, the second part, and the quantum well layer are respectively selected from one of III-V group materials, binary compounds of III-V group materials, ternary compounds of III-V group materials, and quaternary compounds of III-V group materials.
5. The transistor according to claim 4, wherein The electrode material of the first gate electrode is ITO or FTO; the electrode materials of the source electrode or the drain electrode are ITO or FTO; the gate dielectric layer is made of a transparent high-k material with a relative permittivity value greater than 10, and the transparent high-k material is HfO2 or Al2O3.
6. The transistor according to claim 1, wherein The source electrode, the drain electrode, and the first gate electrode are isolated by an isolation layer.
7. The transistor according to claim 1, characterized in that, The isolation layer is made of a low-k material with a relative permittivity value less than 4.
8. The transistor according to claim 1, wherein The second gate electrode is a metal gate electrode.
9. A method for fabricating a nanowire double-gate quantum well infrared detection transistor as claimed in claim 2, characterized in that, It includes the following steps: 1) Prepare an oxide layer on the substrate layer by the method of dry oxygen, then perform photolithography and etching to pattern the oxide layer to determine the diameter and array of nanowire growth. 2) Prepare nanowires by autocatalysis or Au catalysis. 3) Spin-coat photoresist, perform photolithography. After exposing and developing to determine the position of the source electrode, define the position of the source electrode, and then prepare the source electrode by thermal evaporation, electron beam evaporation, or magnetron sputtering. 4) Prepare an isolation layer between the source electrode and the first gate electrode. 5) Spin-coat photoresist, perform photolithography and etching on the isolation layer prepared in step 4 to determine the position of the first gate electrode, and then prepare the gate dielectric layer and the first gate electrode by thermal evaporation, electron beam evaporation, or magnetron sputtering. 6) Prepare an isolation layer between the gate dielectric layer and the first gate electrode and the drain electrode. 7) Spin-coat photoresist, perform photolithography and etching on the isolation layer prepared in step 7 to determine the drain region and prepare the drain electrode. 8) Prepare the second gate electrode by thermal evaporation, electron beam evaporation, or magnetron sputtering under the oxide layer. 9) Perform low-temperature annealing on the device to eliminate the Schottky barrier.