Back contact battery, manufacturing method thereof and photovoltaic module

Abstract

The invention discloses a back contact battery and a manufacturing method thereof, and a photovoltaic module, and relates to the field of photovoltaic technology. The back contact battery comprises a semiconductor substrate, a first semiconductor layer, a first grid line, a second semiconductor layer and a second grid line. The first area of the semiconductor substrate comprises an electrode area and a non-electrode area, at least part of the electrode area is a textured surface, and the non-electrode area is a polished surface; the second semiconductor layer comprises at least one extension part extending to the third region, and the extension part at least extends to the interface of the first region and the third region, so that the first semiconductor layer and the second semiconductor layer are in lap joint. The textured surface is at least partially formed in the electrode region, and the polished surface is formed in the non-electrode region, so that the lower resistivity between the first semiconductor layer and the first grid line and the higher carrier collection efficiency of the first semiconductor layer covering the non-electrode region are considered, and the power generation efficiency is improved. And when shielded, the current can be transmitted through the first semiconductor layer, the extension part and the second semiconductor layer, so that the hot spot risk is reduced.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and particularly to a back-contact battery, a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] A back-contact battery refers to a solar cell in which the light-facing surface of the cell has no electrodes, and the positive and negative electrodes are both arranged on the backlight side of the cell, thereby reducing the shielding of the electrodes on the cell, increasing the short-circuit current of the cell, and improving the energy conversion efficiency of the cell.

[0003] During the actual use of the back-contact battery, blocking objects such as bird droppings, leaves, and dust may fall on the back-contact battery, and the temperature of the cell will increase after being blocked by the blocking object, generating a hot spot effect. If the temperature generated by the hot spot exceeds a certain temperature value, problems such as delamination of the photovoltaic module, burning of the backplane, and bursting of the glass will occur, resulting in the scrapping of the entire back-contact battery and possibly causing a fire risk in severe cases. Summary of the Invention

[0004] The purpose of the present application is to provide a back-contact battery, a manufacturing method thereof, and a photovoltaic module to prevent the hot spot problem caused by severe heating of the back-contact battery, and reduce the manufacturing cost while ensuring the current transmission efficiency.

[0005] To achieve the above purpose, the present application provides the following technical solutions:

[0006] A back-contact battery includes:

[0007] A semiconductor substrate having opposite first and second surfaces, the first surface including first and second regions arranged alternately in a first direction, and having a third region between the first and second regions; the first region includes an electrode region and a non-electrode region, at least a part of the electrode region is a matte surface, and the non-electrode region is a polished surface;

[0008] A first semiconductor layer and a first grid line, the first semiconductor layer is at least formed on the first region, the first grid line is formed on a side of the first semiconductor layer away from the first surface, and is electrically connected to the first semiconductor layer covering the electrode region;

[0009] A second semiconductor layer and a second grid line, the second semiconductor layer is at least formed on the second region and has a conductivity type opposite to that of the first semiconductor layer; the second grid line is formed on a side of the second semiconductor layer away from the first surface, and is electrically connected to the second semiconductor layer;

[0010] The second semiconductor layer includes at least one extension extending onto the third region, and the extension extends at least to the interface between the first region and the third region, so that the first semiconductor layer and the second semiconductor layer overlap.

[0011] In the case of adopting the above technical solution, at least a part of the electrode region is a matte surface, the matte surface has a large roughness and uneven features, so that the specific surface area of the electrode region is increased compared with the polished surface. The first semiconductor layer covering the electrode region will also undulate along with the undulation of the electrode region. Therefore, when at least a part of the electrode region is a matte surface, the side of the part of the first semiconductor layer formed in the electrode region facing away from the semiconductor substrate also has corresponding uneven features, which is conducive to increasing the surface area of the side of the part of the first semiconductor layer formed in the electrode region facing away from the semiconductor substrate, and further conducive to increasing the contact area between the first semiconductor layer and the first gate line, reducing the contact resistance and transmission loss between the first semiconductor layer and the first gate line, and further improving the working performance of the back contact battery. At the same time, it is possible to avoid increasing the contact area between the first semiconductor layer and the first gate line by increasing the width of the first gate line. That is, when at least a part of the electrode region is a matte surface, the width of the first gate line can be appropriately reduced, thereby reducing the raw materials of the first gate line, such as reducing the use of silver paste and lowering the manufacturing cost.

[0012] The matte surface has a large roughness and uneven features, and there are many defects in the first semiconductor layer formed on the matte surface, the formation quality is low, and the passivation effect is poor. Therefore, in this application, the non-electrode region is a polished surface to facilitate improving the formation quality of the first semiconductor layer in the non-electrode region, and further enabling the first semiconductor layer covering the non-electrode region to have a good passivation effect, ensuring that the part of the first semiconductor layer covering the non-electrode region still has a high carrier collection ability.

[0013] As can be seen from the above, in the back contact battery provided by this application, a matte surface is formed at least partially in the electrode region, and a polished surface is formed in the non-electrode region at the same time, taking into account both the lower resistivity between the first semiconductor layer and the first gate line and the higher carrier collection efficiency of the first semiconductor layer covering the non-electrode region, thereby improving the power generation efficiency of the back contact battery.

[0014] Moreover, in the back contact battery provided by this application, the first semiconductor layer and the second semiconductor layer with opposite conductivity types are distributed on the backlight side of the semiconductor substrate to effectively shunt carriers when the back contact battery is in a working state, which is conducive to forming a photocurrent. The second semiconductor layer of the back contact battery provided by the embodiment of the present invention includes an extension portion, and the extension portion can be used to electrically connect the first semiconductor layer and the second semiconductor layer. Based on this, when the back contact battery is blocked and a certain reverse voltage is provided to the blocked back contact battery, the current can be transmitted through the first semiconductor layer, the extension portion, and the second semiconductor layer, avoiding the blocked battery cell from becoming a load and consuming the energy generated by other illuminated battery cells, and thus reducing the hot spot risk. As Figure 8 shown, the extension portion is equivalent to Figure 8 a reverse diode within the elliptical region. When the back contact battery is blocked, the extension portion can provide a reverse bias voltage to prevent the hot spot risk.

[0015] A manufacturing method of a back-contact battery, comprising:

[0016] Providing a semiconductor substrate having opposite first and second surfaces, wherein the first surface includes first regions and second regions arranged alternately along a first direction, and there is a third region between the first regions and the second regions; the first regions include electrode regions and non-electrode regions;

[0017] Forming a textured surface at least partially in the electrode regions, and forming a polished surface in the non-electrode regions and the second regions;

[0018] Forming a first semiconductor layer at least in the first regions;

[0019] Forming a second semiconductor layer at least in the second regions, and the second semiconductor layer has a conductivity type opposite to that of the first semiconductor layer. The second semiconductor layer includes at least one extension extending onto the third region, and the extension extends at least to the interface between the first region and the third region so that the first semiconductor layer and the second semiconductor layer overlap.

[0020] A photovoltaic module, comprising a plurality of back-contact batteries as described in any one of the above and at least one interconnecting member, and the interconnecting member connects two adjacent back-contact batteries in series or in parallel.

[0021] Compared with the prior art, the beneficial effects of the photovoltaic module and the manufacturing method of the back-contact battery provided by the embodiments of the present application are the same as the beneficial effects of the above back-contact battery, and will not be elaborated here. Description of the Drawings

[0022] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0023] Figure 1 It is a cross-sectional view of the back-contact battery provided by the embodiment of the present application at a position where no extension is provided in the third region;

[0024] Figure 2 It is a cross-sectional view of the back-contact battery provided by the embodiment of the present application at a position where an extension is provided in the third region;

[0025] Figure 3 It is a cross-sectional view of the back-contact battery provided by another embodiment of the present application at a position where an extension is provided in the third region;

[0026] Figure 4 It is a schematic diagram of the resistivity comparison of the first grid line in contact with the first semiconductor layer covering the polished surface and the textured surface provided by the embodiment of the present application;

[0027] Figure 5Schematic diagram of the comparison between the PL brightness of the polished surface and the PL brightness of the matte surface provided by the embodiments of the present application;

[0028] Figure 6 Schematic diagram of the comparison between the minimum contact resistivity between the first semiconductor layer and the first gate line in three cases where the entire first region is a polished surface or a matte surface provided by the embodiments of the present application, and the structure in the present application;

[0029] Figure 7 Schematic diagram of the comparison between the PL brightness of the first semiconductor layer in three cases where the entire first region is a polished surface or a matte surface provided by the embodiments of the present application, and the structure in the present application;

[0030] Figure 8 Equivalent circuit of the back-contact battery provided by the embodiments of the present application;

[0031] Figure 9 Partial schematic diagram of the depression in the non-electrode region provided by the embodiments of the present application;

[0032] Figure 10 Another partial schematic diagram of the depression in the non-electrode region provided by the embodiments of the present application;

[0033] Figure 11 Top view of the back-contact battery provided by the embodiments of the present application;

[0034] Figure 12 Schematic diagram of the first region of the back-contact battery provided by the embodiments of the present application;

[0035] Figure 13 Schematic diagram of the first region of the back-contact battery provided by another embodiment of the present application;

[0036] Figure 14 Schematic diagram of the first region of the back-contact battery provided by another embodiment of the present application;

[0037] Figure 16 - Figure 23 Schematic diagram of the first region of the back-contact battery provided by another embodiment of the present application;

[0038] Figure 16 - Figure 23 Flow schematic diagram of the manufacturing method of the back-contact battery provided by the embodiments of the present application;

[0039] Figure 24 - Figure 31 Flow schematic diagram of the manufacturing method of the back-contact battery provided by another embodiment of the present application.

[0040] Reference numerals:

[0041] 1 - Semiconductor substrate, 1a - First region, 1a1 - Non - electrode region, 1a2 - Electrode region, 1b - Second region, 1c - Third region, 2 - Passivation layer, 3 - First semiconductor layer, 4 - Second semiconductor layer, 4a - Extension, 5 - Second interface layer, 6 - Second gate line, 7 - First gate line, 8 - First mask layer, 9 - Second mask layer, 10 - Third mask layer, 11 - Fourth mask layer, 12 - Fifth mask layer, 13 - Sixth mask layer. Detailed implementation mode

[0042] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application clearer and more understandable, the following further details this application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0043] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0044] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0045] In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to this application.

[0046] In the description of this application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0047] Please refer to Figure 1 - 3 The back-contact battery provided by the embodiment of the present application includes a semiconductor substrate 1, a first semiconductor layer 3, a first gate line 7, a second semiconductor layer 4, and a second gate line 6. Among them, the semiconductor substrate 1 has opposite first and second surfaces, that is, the two surfaces opposite along the thickness direction of the semiconductor substrate 1 are the first surface and the second surface respectively. The first surface may correspond to the backlight surface of the back-contact battery, and the second surface may correspond to the light-facing surface of the back-contact battery. The first surface includes a first region 1a and a second region 1b that are alternately distributed in a first direction, and there is a third region 1c between the first region 1a and the second region 1b. For example: the first region 1a and the second region 1b may be alternately distributed at intervals in a strip shape, or may be alternately distributed at intervals in an interdigitated shape. Among them, the first region 1a includes an electrode region 1a2 and a non-electrode region 1a1, and the electrode region 1a2 is used for electrical connection with the first gate line 7. Among them, at least a part of the electrode region 1a2 is a matte surface, and the non-electrode region 1a1 is a polished surface.

[0048] The first semiconductor layer 3 is at least formed on the first region 1a. The first semiconductor layer 3 can be additionally formed on the semiconductor substrate 1 through a deposition technique, or can be formed in the semiconductor substrate 1 through diffusion, ion implantation, etc. The first gate line 7 is formed on the side of the first semiconductor layer 3 away from the first surface and is electrically connected to the first semiconductor layer 3 covering the electrode region 1a2. Specifically, the first gate line 7 can extend in a second direction. The first gate line 7 can be in direct contact or indirect contact with the side of the first semiconductor layer 3 covering the electrode region 1a2 away from the semiconductor substrate 1. The first direction and the second direction intersect, that is, the first direction is different from the second direction, and the included angle between the first direction and the second direction can be an acute angle or a right angle. The first direction can be one of the length and width directions of the back-contact battery, and the second direction can be the other of the length and width directions of the back-contact battery.

[0049] The second semiconductor layer 4 is at least formed on the second region 1b. The second semiconductor layer 4 can be additionally formed on the semiconductor substrate 1 through a deposition technique, or can be formed in the semiconductor substrate 1 through diffusion, ion implantation, etc. The second semiconductor layer 4 has a conductivity type opposite to that of the first semiconductor layer 3 to respectively collect and export electrons and holes, which is conducive to forming a photocurrent. The second gate line 6 is formed on the side of the second semiconductor layer 4 away from the first surface and is electrically connected to the second semiconductor layer 4. The second gate line 6 also extends in the second direction, and the first gate line 7 and the second gate line 6 are spaced apart in the first direction.

[0050] As Figure 2 and Figure 3As shown, the second semiconductor layer 4 includes at least one extension 4a extending onto the third region 1c, and the extension 4a extends at least to the interface between the first region 1a and the third region 1c, so that the first semiconductor layer 3 and the second semiconductor layer 4 overlap. Specifically, a part of the second semiconductor layer 4 extends onto the third region 1c to form the extension 4a, and the extension 4a overlaps with the first semiconductor layer 3 at the interface between the first region 1a and the third region 1c. In this way, the first semiconductor layer 3 and the second semiconductor layer 4 are electrically connected by using the extension 4a (forming a PN reverse diode). According to the actual situation, two, three or more extensions 4a can be provided. At the overlapping position, a second interface layer 5 can also be provided between the first semiconductor layer and the second semiconductor layer. For example, the second interface layer 5 can be a tunneling oxide layer.

[0051] In the case of adopting the above technical solution, at least a part of the electrode region 1a2 is a matte surface, and the matte surface has a large roughness and uneven features, so that the specific surface area of the electrode region 1a2 is increased compared with the polished surface. The first semiconductor layer 3 covering the electrode region 1a2 will also fluctuate with the undulation of the electrode region 1a2. Therefore, when at least a part of the electrode region 1a2 is a matte surface, a part of the first semiconductor layer 3 formed on the electrode region 1a2 also has corresponding uneven features on the side facing away from the semiconductor substrate 1, which is beneficial to increasing the surface area of the part of the first semiconductor layer 3 formed on the electrode region 1a2 on the side facing away from the semiconductor substrate 1, and further beneficial to increasing the contact area between the first semiconductor layer 3 and the first gate line 7, reducing the contact resistance and transmission loss between the first semiconductor layer 3 and the first gate line 7, and further improving the working performance of the back contact battery; as Figure 4 shown, the resistivity between the first gate line 7 and the first semiconductor layer 3 covering the matte surface is significantly lower than the resistivity between the first gate line 7 and the first semiconductor layer 3 covering the polished surface. At the same time, it is possible to avoid increasing the contact area between the first semiconductor layer 3 and the first gate line 7 by increasing the width of the first gate line 7. That is, when at least a part of the electrode region 1a2 is a matte surface, the width of the first gate line 7 can be appropriately reduced, thereby reducing the raw materials of the first gate line 7, such as reducing the use of silver paste and reducing the manufacturing cost.

[0052] The matte surface has a large roughness and uneven features, and there are more defects in the first semiconductor layer 3 formed on the matte surface, the formation quality is lower, and the passivation effect is poorer. Therefore, in this application, the non-electrode region 1a1 is a polished surface, which is beneficial to improving the formation quality of the first semiconductor layer 3 in the non-electrode region 1a1, and further enabling the first semiconductor layer 3 covering the non-electrode region 1a1 to have a better passivation effect, ensuring that the part of the first semiconductor layer 3 covering the non-electrode region 1a1 still has a high carrier collection ability. As Figure 5As shown, the PL (Photoluminescence Intensity) brightness of the polished surface is significantly higher than that of the textured surface. The higher the PL brightness, the fewer surface defects and the better the passivation effect. Thus, it can be seen that the passivation effect of the polished surface is significantly better than that of the textured surface.

[0053] Furthermore, as Figure 6 shown, Figure 6 compares the minimum contact resistivity between the first semiconductor layer 3 and the first gate line 7 in three cases: when the entire first region 1a is a polished surface or a textured surface, and the structure in this application. By comparison, it can be seen that the minimum resistivity between the first semiconductor layer 3 and the first gate line 7 in the structure of this application is between the minimum resistivity between the first semiconductor layer 3 and the first gate line 7 when the entire first region 1a is a polished surface and a textured surface, and is very close to the minimum resistivity between the first semiconductor layer 3 and the first gate line 7 when the entire first region 1a is a textured surface. Thus, it can be known that the purpose of reducing the resistivity between the first semiconductor layer 3 and the first gate line 7 can be achieved in the structure of this application to reduce transmission loss. As Figure 7 shown, Figure 7 compares the PL brightness of the first semiconductor layer 3 in three cases: when the entire first region 1a is a polished surface or a textured surface, and the structure in this application. The higher the PL brightness, the better the passivation effect. By comparison, it can be seen that the PL brightness of the first semiconductor layer 3 in the structure of this application is between the PL brightness of the first semiconductor layer 3 when the entire first region 1a is a polished surface and a textured surface, and is very close to the PL brightness of the first semiconductor layer 3 when the entire first region 1a is a polished surface. Thus, it can be known that the passivation effect of the first semiconductor layer 3 can be ensured in the structure of this application to improve the carrier collection efficiency of the first semiconductor layer 3.

[0054] As can be seen from the above, in the back contact battery provided by this application, a textured surface is formed at least partially in the electrode region 1a2, while a polished surface is formed in the non - electrode region 1a1. This takes into account both the lower resistivity between the first semiconductor layer 3 and the first gate line 7 and the higher carrier collection efficiency of the first semiconductor layer 3 covering the non - electrode region 1a1, thereby improving the power generation efficiency of the back contact battery. Moreover, forming a polished surface in the non - electrode region 1a1 is conducive to the second semiconductor layer 4 forming a lap joint at the adjacent side position of the first semiconductor layer 3; the lap - joint area directly affects the leakage and anti - hot - spot effects. Therefore, a relatively flat polished surface can more easily control the lap - joint area between the extension 4a of the second semiconductor layer 4 and the first semiconductor layer 3, and further precisely control the reverse breakdown voltage to effectively control the hot - spot problem.

[0055] Moreover, in the back-contact battery provided by the present application, the first semiconductor layer 3 and the second semiconductor layer 4 with opposite conduction types are distributed on one side of the backlight surface of the semiconductor substrate 1 to effectively shunt carriers when the back-contact battery is in a working state, facilitating the formation of photocurrent. The second semiconductor layer 4 of the back-contact battery provided by the embodiment of the present invention includes an extension portion 4a, and the first semiconductor layer 3 and the second semiconductor layer 4 can be electrically connected by using the extension portion 4a. Based on this, when the back-contact battery is blocked and a certain reverse voltage is provided to the blocked back-contact battery, current can be transmitted through the first semiconductor layer 3, the extension portion 4a, and the second semiconductor layer 4, avoiding the blocked cell becoming a load and consuming the energy generated by other illuminated cells, thereby reducing the hot spot risk. As Figure 8 shown, the extension portion 4a is equivalent to Figure 8 a reverse diode within the elliptical region. When the back-contact battery is blocked, the extension portion 4a can provide a reverse bias voltage, thereby preventing the hot spot risk.

[0056] In some embodiments, a part of the electrode region 1a2 can be a matte surface, or the entire electrode region 1a2 can be a matte surface. The matte surface of the electrode region 1a2 includes a plurality of pyramid-like structures. In terms of the arrangement of the pyramid-like structures, the present invention's embodiments do not specifically limit the morphology, size, and distribution of the pyramid-like structures formed on the matte surface, as long as they can be applied to the back-contact battery provided by the embodiments of the present invention.

[0057] Exemplarily, the above-mentioned pyramid-like structures can be pyramids with sharp apex angles; alternatively, the pyramid-like structures can also be pyramid-like structures with rounded chamfers; or, the pyramid-like structures can also be pyramid-like structures with flattened apex angles. In this case, the pyramid-like structures can have at least the above three examples, which is beneficial to improving the applicability of the back-contact battery provided by the embodiments of the present invention in different application scenarios. Additionally, there is no need to strictly control the manufacturing precision to obtain a single-morphology pyramid-like structure, reducing the process difficulty and facilitating the improvement of the yield of the back-contact battery.

[0058] In some embodiments, as Figure 2 and Figure 3 shown, the electrode region 1a2 protrudes in a direction away from the first surface relative to the non-electrode region 1a1. That is, along the thickness direction of the semiconductor substrate 1, the electrode region 1a2 is higher than the non-electrode region 1a1, and the electrode region 1a2 is farther from the second surface relative to the non-electrode region 1a1. Such a setting is more conducive to making the first gate line 7 correspond to the electrode region 1a2 during the formation of the first gate line 7, reducing the precision requirements for the position of the first gate line 7, and thus facilitating the improvement of the processing efficiency of the first gate line 7.

[0059] In some embodiments, as Figure 2As shown, the distance between the non-electrode region 1a1 and the top of the pyramid-like structure is h1, where h1 ≤ 10 μm. Such a setting can prevent the pyramid-like structure from being too tall, blocking the light irradiating the non-electrode region 1a1 and affecting the light absorption efficiency. At the same time, it can avoid the situation where the formed first grid line 7 protrudes too high from the first surface, resulting in stress concentration during the lamination process and affecting the product yield. For example, h1 can be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm, etc.

[0060] In some embodiments, as Figure 2 shown, the distance between the non-electrode region 1a1 and the bottom of the pyramid-like structure is h2, where 0.5 μm ≤ h2 ≤ 2.5 μm. It can be understood that the non-electrode region 1a1 can be located on one side of the bottom of the pyramid-like structure close to the second surface or on the side away from the second surface. Such a setting can adjust the height of the pyramid-like structure protruding relative to the non-electrode region 1a1 by setting the range of h2, so that the protruding height of the pyramid-like structure is within a reasonable range. For example, h2 can be 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, or 2.5 μm, etc.

[0061] Alternatively, in some other embodiments, as Figure 9 and Figure 10 shown, the electrode region 1a2 is recessed relative to the non-electrode region 1a1 in the direction closer to the first surface, that is, along the thickness direction of the semiconductor substrate 1, the electrode region 1a2 is set lower than the non-electrode region 1a1, and the electrode region 1a2 is closer to the second surface relative to the non-electrode region 1a1. Such a setting makes the first grid line 7 located in the recessed electrode region 1a2 after the first grid line 7 is formed in the electrode region 1a2, and the height of the first grid line 7 protruding from the first surface is lower or does not protrude from the first surface, which is beneficial to increasing the flatness of the first surface of the back-contact battery and thus avoiding stress concentration during the lamination process.

[0062] In some embodiments, as Figure 9 shown, the distance between the non-electrode region 1a1 and the top of the pyramid-like structure is h3, where 0 μm ≤ h3 ≤ 2.5 μm. Such a setting makes the distance h3 between the non-electrode region 1a1 and the top of the pyramid-like structure within a reasonable range, so as to prevent the depth of the recess of the electrode region 1a2 from being too deep, increasing the processing difficulty, and at the same time avoiding the situation where the mechanical strength of the semiconductor substrate 1 is reduced due to the too-deep recess of the electrode region 1a2. Exemplarily, h3 can be 0, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, or 2.5 μm, etc.

[0063] In some embodiments, as Figure 9As shown, the distance between the non-electrode region 1a1 and the bottom of the quasi-pyramid is h4, where h4 ≤ 10 μm. With this setting, it is also possible to prevent the electrode region 1a2 from sagging too deeply, thus avoiding the situation where the mechanical strength of the semiconductor substrate 1 is reduced due to the excessive sagging of the electrode region 1a2. For example, h4 can be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm, etc.

[0064] In some embodiments, the first semiconductor layer 3 has an adjacent side surface close to the second semiconductor layer 4, that is, the adjacent side surface extends along the thickness direction of the first semiconductor layer 3. As Figure 2 shown in region A therein, the extension portion 4a extends to overlap only with the adjacent side surface. In other words, at the position of the extension portion 4a, the extension portion 4a overlaps with the adjacent side surface of the first semiconductor layer 3 along the thickness direction of the semiconductor substrate 1. With this setting, the processing technology is simple, and the overlapping area between the extension portion 4a of the second semiconductor layer 4 and the first semiconductor layer 3 is small, and when the back contact battery is not blocked, the leakage is less.

[0065] Or, as Figure 3 shown in region B therein, the extension portion 4a extends to the side of the first semiconductor layer 3 facing away from the semiconductor substrate 1 near the third region 1c, that is, the extension portion 4a not only overlaps with the adjacent side surface of the first semiconductor layer 3 along the thickness direction of the semiconductor substrate 1, but also overlaps with the side of the first semiconductor layer 3 facing away from the semiconductor substrate 1 within the non-electrode region 1a1. With this setting, the overlapping area between the extension portion 4a of the second semiconductor layer 4 and the first semiconductor layer 3 is large, and when the back contact battery is blocked, the transmission of lateral and longitudinal leakage current can be realized, avoiding the situation where the blocked cell becomes a load and consumes the energy generated by other illuminated cells, and further reducing the hot spot risk.

[0066] In some embodiments, as Figure 2 and Figure 10 shown, the third region 1c is recessed in the direction close to the first surface relative to the first region 1a; that is, the third region 1c is arranged closer to the second surface than the first region 1a. The third region 1c has a side wall surface close to the first region 1a, and the extension portion 4a extends from the side wall surface to overlap with the adjacent side surface. With this setting, there is a certain height difference between the third region 1c and the second region 1b and the first region 1a in the thickness direction of the semiconductor substrate 1, which is beneficial to suppressing the leakage between the part of the second semiconductor layer 4 without the extension portion 4a and the first semiconductor layer 3. The extension portion 4a is integral with the second semiconductor layer 4.

[0067] In other embodiments, as Figure 11As shown, except for the region where at least one extension portion 4a is located, the first semiconductor layer 3 or the second semiconductor layer 4 is not provided on other parts of the third region 1c. That is, the third region 1c completely separates the first semiconductor layer 3 and the second semiconductor layer 4. Or rather, at least part of the region of the second semiconductor layer 4 and at least part of the region of the first semiconductor layer 3 are separated by the third region 1c, preventing a large leakage current between the first semiconductor layer 3 and the second semiconductor layer 4 when the back-contact battery operates normally, which may lead to a low working efficiency of the back-contact battery, and ensuring that the photovoltaic module including the back-contact battery provided in the embodiment of the present invention has a high photoelectric conversion efficiency in the forward voltage region.

[0068] In some embodiments, as Figure 2 and Figure 3 shown, the third region 1c covered by the extension portion 4a is a polished surface, that is, the extension portion 4a is formed in the polished surface region. In this way, the extension portion 4a has fewer defects and better formation quality, so that the passivation effect of the extension portion 4a is better, which is beneficial to the collection and transmission of carriers. After the extension portion 4a overlaps with the first semiconductor layer 3, it can increase the transmission of leakage current when the back-contact battery is shaded, and further reduce the risk of hot spots.

[0069] In some embodiments, as Figure 1 shown, except for the region where at least one extension portion 4a is located, other parts of the third region 1c are a matte surface, and the matte surface includes a plurality of pseudo-pyramids. The structure of the pseudo-pyramids can refer to the foregoing, and will not be elaborated here. With this technical solution, except for the region where the extension portion 4a is located in the third region 1c, the remaining regions are matte surfaces, which is beneficial to better isolate the first semiconductor layer 3 and the second semiconductor layer 4, and further prevent a large leakage current between the first semiconductor layer 3 and the second semiconductor layer 4 when the back-contact battery operates normally.

[0070] In some embodiments, if the overlapping area between the extending portion 4a and the first semiconductor layer 3 is too large, the leakage current between the first semiconductor layer 3 and the second semiconductor layer 4 is relatively large, resulting in a relatively low working efficiency of the back-contact battery; if the overlapping area between the extending portion 4a and the first semiconductor layer 3 is too small, when the back-contact battery is shaded, the risk of hot spots cannot be effectively reduced. Therefore, the ratio of the orthographic projection area of at least one extending portion 4a on the first surface to the orthographic projection area of the third region 1c on the first surface is 0.05 to 0.75, that is, the ratio of the sum of the orthographic projection areas of all the extending portions 4a on the first surface to the orthographic projection area of the third region 1c on the first surface is 0.05 to 0.75. In this case, it is possible to prevent the leakage current passing through the extending portion 4a from being small due to the small orthographic projection area of the extending portion 4a on the first surface, prevent the back-contact battery from being burned due to local heat concentration, and effectively reduce the hot spot risk of the photovoltaic module including the back-contact battery provided in the embodiment of the present invention. It is also possible to prevent the leakage current of the back-contact battery from being large under normal working conditions due to the large orthographic projection area of the extending portion 4a on the first surface, and further ensure that the photovoltaic module including the back-contact battery provided in the embodiment of the present invention has a high photoelectric conversion efficiency in the forward voltage region. Exemplarily, the ratio of the orthographic projection area of at least one extending portion 4a on the first surface to the orthographic projection area of the third region 1c on the first surface is 0.05, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7 or 0.75, etc.

[0071] In some embodiments, as Figure 11 shown, along the extending direction of the third region 1c, a plurality of extending portions 4a are spaced apart. With this technical solution, the distribution of the extending portions 4a is more uniform. When a part of the back-contact battery is shaded, the current can be transmitted more uniformly through the plurality of extending portions 4a, preventing local current concentration on the first surface of the semiconductor substrate 1 and serious heating, resulting in problems such as backplane burning and glass bursting.

[0072] In some embodiments, along the extension direction of the third region 1c, the length of the extension portion 4a is 5 μm - 50 μm. Or, within the third region 1c, the extension distance of the extension portion 4a in the second direction is 5 μm - 50 μm. It can be understood that the larger the length of the extension portion 4a, the larger the overlapping area between the extension portion 4a and the first semiconductor layer 3; the smaller the length of the extension portion 4a, the smaller the overlapping area between the extension portion 4a and the first semiconductor layer 3. Therefore, by controlling the length of the extension portion 4a to be within a reasonable range of 5 μm - 50 μm, the overlapping area between the extension portion 4a and the first semiconductor layer 3 can be kept within a reasonable range, so that the leakage current of the back contact battery under normal working conditions is relatively large, further ensuring that the photovoltaic module including the back contact battery provided by the embodiment of the present invention has a high photoelectric conversion efficiency in the forward voltage region. For example, the length of the extension portion 4a is 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm, 20 μm, 22 μm, 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, 38 μm, 40 μm, 42 μm, 45 μm, 48 μm or 50 μm, etc.

[0073] In some embodiments, along the first direction, the width of the electrode region 1a2 of the first region 1a is 10 μm - 150 μm. With this technical solution, on the one hand, it can ensure that the contact area between the first semiconductor layer 3 covering the electrode region 1a2 and the first gate line 7 is large enough, thereby reducing the transfer resistance and transfer loss between the first semiconductor layer 3 covering the electrode region 1a2 and the first gate line 7; on the other hand, it is beneficial for the first gate line 7 to correspond to the electrode region 1a2 during the formation of the first gate line 7, reducing the processing difficulty of the first gate line 7 and improving the processing efficiency and product yield of the first gate line 7. For example, the width of the electrode region 1a2 of the first region 1a is 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm or 150 μm, etc.

[0074] In some embodiments, along the first direction, the width of the non - electrode region 1a1 on one side of the electrode region 1a2 is 10um - 200um. By adopting this technical solution, the width of the non - electrode region 1a1 of the first region 1a is maintained within a reasonable range of 10um - 200um, thereby ensuring that the first semiconductor layer 3 as a whole has a high carrier collection ability and further improving the power generation efficiency of the back - contact battery. For example, the width of the non - electrode region 1a1 on one side of the electrode region 1a2 is 10um, 20um, 30um, 40um, 50um, 60um, 70um, 80um, 90um, 100um, 110um, 120um, 130um, 140um, 150um, 160um, 170um, 180um, 190um or 200um, etc.

[0075] In some embodiments, along the first direction, the ratio of the width of the electrode region 1a2 to the width of the first region 1a is 5% - 50%, so as to ensure that the width of the electrode region 1a2 is maintained within a reasonable range, which is beneficial for the first gate line 7 to correspond to the electrode region 1a2 during the formation of the first gate line 7, reducing the processing difficulty of the first gate line 7 and improving the processing efficiency and product yield. For example, along the first direction, the ratio of the width of the electrode region 1a2 to the width of the first region 1a is 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45% or 50%, etc.

[0076] In some embodiments, along the first direction, the ratio of the width of the non - electrode region 1a1 on one side of the electrode region 1a2 to the width of the first region 1a is 25% - 98%, so as to ensure that the first semiconductor layer 3 as a whole has a high carrier collection ability and further improving the power generation efficiency of the back - contact battery. For example, the ratio of the width of the non - electrode region 1a1 on one side of the electrode region 1a2 to the width of the first region 1a is 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95% or 98%, etc.

[0077] In some embodiments, along the first direction, the width of the first region 1a is 100um - 500um, so as to control the width of the first region 1a to make the overall area of the first semiconductor layer 3 covering the first region 1a within a reasonable range, ensuring that the first semiconductor layer 3 as a whole has a high carrier collection ability. For example, the width of the first region 1a is 100um, 120um, 150um, 180um, 200um, 220um, 250um, 280um, 300um, 320um, 350um, 380um, 400um, 420um, 450um, 480um or 500um, etc.

[0078] On the one hand, since the area of the third region 1c other than the extension portion 4a does not cover the first semiconductor layer 3 and the second semiconductor layer 4, if the width of the third region 1c is too wide, the power generation efficiency of the back contact battery will be reduced; on the other hand, if the width of the third region 1c is too narrow, the isolation effect between the first semiconductor layer 3 and the second semiconductor layer 4 may be poor, and it is easy to leak electricity when the back contact battery is working normally. Therefore, in this technical solution, along the first direction, the width of the third region 1c is 20um - 1000um, so as to ensure the power generation efficiency of the back contact battery while improving the isolation effect between the first semiconductor layer 3 and the second semiconductor layer 4 and reducing leakage. For example, the width of the third region 1c is 20um, 100um, 200um, 300um, 400um, 500um, 600um, 700um, 800um, 900um or 1000um.

[0079] In some embodiments, along the first direction, the width of the second region 1b is 100um - 400um. By controlling the width of the second region 1b, the overall area of the second semiconductor layer 4 covering the second region 1b is within a reasonable range, so as to ensure that the second semiconductor layer 4 as a whole has a high carrier collection ability. For example, the width of the second region 1b is 100um, 120um, 150um, 180um, 200um, 220um, 250um, 280um, 300um, 320um, 350um, 380um or 400um, etc.

[0080] In some embodiments, on the first surface, the reflectivity of the electrode region 1a2 is 10% - 20%. The reflectivity of the non-electrode region 1a1 is 30% - 50%. For example, the reflectivity of the electrode region 1a2 is 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19% or 20%. For another example, the reflectivity of the non-electrode region 1a1 is 30%, 32%, 35%, 38%, 40%, 42%, 45%, 48% or 50%, etc.

[0081] In some embodiments, as Figure 12 and Figure 13 shown, the texture in the electrode region 1a2 can be continuously arranged along the second direction. Or, as Figure 14 and Figure 15 shown, the texture in the electrode region 1a2 can be intermittently arranged along the second direction.

[0082] In some other embodiments, the back-contact battery further includes a passivation layer 2 disposed on the first surface, and the passivation layer 2 is at least formed on one side of the first semiconductor layer 3 and the second semiconductor layer 4 facing away from the semiconductor substrate 1. Specifically, the passivation layer 2 can be formed as a whole layer on the first surface. At the position where the extension portion 4a is not provided in the third region 1c, the passivation layer 2 directly covers the semiconductor substrate 1. The passivation layer 2 can be a single-layer structure or a multi-layer structure. The material of the passivation layer 2 can include one or more of silicon nitride, silicon oxynitride, silicon oxide, and aluminum oxide, which can passivate the surface of the first semiconductor layer 3, reduce its carrier recombination rate, and further improve the photoelectric conversion efficiency of the back-contact battery.

[0083] When the back-contact battery further includes the passivation layer 2, the first grid line 7 passes through the passivation layer 2 and is electrically connected to the first semiconductor layer 3, and the second grid line 6 passes through the passivation layer 2 and is electrically connected to the second semiconductor layer 4. Among them, the passivation layer 2 can be provided with openings corresponding to the first semiconductor layer 3 and the second semiconductor layer 4, and the first grid line 7 and the second grid line 6 respectively pass through the openings and are electrically connected to the first semiconductor layer 3 and the second semiconductor layer 4. Alternatively, the first grid line 7 and the second grid line 6 pass through the passivation layer 2 by burning through and are respectively electrically connected to the first semiconductor layer 3 and the second semiconductor layer 4.

[0084] The reflectivity of the part of the passivation layer 2 covering the electrode region 1a2 is 2% - 8%. The reflectivity of the part of the passivation layer 2 covering the non-electrode region 1a1 is 3% - 15%. In this technical solution, through the setting of the passivation layer 2, the reflectivity of the first surface of the back-contact battery is reduced, thereby improving the light absorption utilization rate and further improving the power generation efficiency.

[0085] Exemplarily, the reflectivity of the part of the passivation layer 2 covering the electrode region 1a2 is 2%, 3%, 4%, 5%, 6%, 7% or 8%, etc. The reflectivity of the part of the passivation layer 2 covering the non-electrode region 1a1 is 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14% or 15%, etc.

[0086] In some embodiments, the sheet resistance of the electrode region 1a2 is less than the sheet resistance of the non-electrode region 1a1. With such a setting, the contact resistance between the part of the first semiconductor layer 3 covering the electrode region 1a2 and the first grid line 7 is small, which is beneficial to further reducing the transmission loss between the part of the first semiconductor layer 3 covering the electrode region 1a2 and the first grid line 7 and improving the power generation efficiency.

[0087] The sheet resistance of the electrode region 1a2 can be 150Ω - 500Ω, which is beneficial to reducing the transmission loss, while reducing the processing difficulty and improving the product yield. For example, the sheet resistance of the electrode region 1a2 can be 150Ω, 180Ω, 200Ω, 250Ω, 300Ω, 350Ω, 400Ω, 450Ω or 500Ω, etc.

[0088] In the actual application process, the material of the semiconductor substrate 1 can be selected from materials such as silicon (Si), germanium (Ge), or gallium arsenide (GaAs), etc. Obviously, in terms of the conduction type, the semiconductor substrate 1 can be an intrinsic conductive substrate, an n-type conductive substrate, or a p-type conductive substrate. Optionally, the semiconductor substrate 1 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsic conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the finally manufactured back-contact battery has a lower bulk resistivity, thereby improving the efficiency of the back-contact battery.

[0089] Exemplarily, the semiconductor substrate 1 can be a p-type substrate or an n-type substrate. The n-type substrate has the advantages of high minority carrier lifetime, no optical degradation, and good low-light performance.

[0090] The second semiconductor layer 4 can include doped polysilicon. The doped polysilicon layer has higher carrier transport characteristics. Therefore, when the first semiconductor layer 3 is a doped polysilicon layer, the carrier transport efficiency is higher, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery. In addition, the polysilicon layer has a strong ability to laterally transport current. When the back-contact battery is blocked, it is more conducive to the current to laterally transport along the polysilicon layer to the first semiconductor layer 3, which is beneficial to the formation of leakage current, thereby preventing the risk of hot spots.

[0091] In some embodiments, the above-mentioned back-contact battery may further include a second interface layer 5, and the second interface layer 5 is at least located between the second semiconductor layer 4 and the semiconductor substrate 1. The projection of the second interface layer 5 on the semiconductor substrate 1 may overlap with the projection of the second semiconductor layer 4 on the semiconductor substrate 1. In this case, the passivation contact structure composed of the second interface layer 5 and the second semiconductor layer 4 can achieve selective collection of carriers and reduce the carrier recombination rate in the region of the first surface of the semiconductor substrate 1 where the second semiconductor layer 4 is formed. The material and thickness of the second interface layer 5 can be set according to the material of the second semiconductor layer 4 and actual requirements, and no specific limitation is made here. For example: when the material of the second semiconductor layer 4 includes doped polysilicon, the second interface layer 5 includes a tunneling oxide layer. Another example is that when the material of the second semiconductor layer 4 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second interface layer 5 includes one or more of intrinsic amorphous silicon layer, intrinsic microcrystalline silicon layer, and intrinsic nanocrystalline silicon.

[0092] It can be understood that when the back-contact battery further includes the second interface layer 5, there is also a second interface layer 5 between the extension portion 4a and the first semiconductor layer 3.

[0093] The first semiconductor layer 3 may include doped polysilicon. The doped polysilicon layer has higher carrier transport characteristics. Therefore, when the first semiconductor layer 3 is a doped polysilicon layer, the carrier transport efficiency is higher, which is beneficial to improving the photoelectric conversion efficiency of the back contact battery. Of course, the first semiconductor layer 3 may also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0094] Optionally, when the first semiconductor layer 3 is one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, and the second semiconductor layer 4 is doped polysilicon, since the ability of doped polysilicon to laterally transport current is significantly better than that of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, after the second semiconductor layer 4 forms the extension portion 4a, the resistance of the current flowing from the second semiconductor layer 4 to the first semiconductor layer 3 is small, while the resistance of the current flowing from the first semiconductor layer 3 to the second semiconductor layer 4 is large. Thus, the extension portion 4a has the function of unidirectional conduction, and its function is similar to that of a unidirectional diode.

[0095] When the first semiconductor layer 3 is additionally formed on the semiconductor substrate 1 by a deposition technique, the back contact battery may further include a first interface layer, which is at least located between the first semiconductor layer 3 and the semiconductor substrate 1. In this case, the passivation contact structure composed of the first interface layer and the first semiconductor layer 3 has excellent interface passivation effect, and can achieve selective collection of carriers, reducing the carrier recombination rate in the region of the first surface of the semiconductor substrate 1 where the first semiconductor layer 3 is formed, and further improving the photoelectric conversion efficiency of the back contact battery. The material and thickness of the first interface layer can be set according to the material of the first semiconductor layer 3 and actual requirements, and no specific limitation is made here. For example: when the first semiconductor layer 3 includes a doped polysilicon layer, the first interface layer is a tunneling oxide layer; for another example: when the first semiconductor layer 3 includes a doped amorphous silicon layer, the first interface layer includes an intrinsic amorphous silicon layer.

[0096] In terms of doping type, the doping type of the first semiconductor layer 3 may also be P-type, and at this time, the doping type of the second semiconductor layer 4 is N-type; or, the doping type of the first semiconductor layer 3 may be N-type, and at this time, the doping type of the second semiconductor layer 4 is P-type. The embodiments of the present invention do not make specific limitations on the doping types of the first semiconductor layer 3 and the second semiconductor layer 4, as long as the doping types of the two are opposite. When the doping type is P-type, generally group III elements are doped. When the doping type is N-type, generally group V elements or group VI elements are doped.

[0097] In some embodiments, the first gate line 7 and the second gate line 6 may be formed by processes such as screen printing, electroplating, sputtering, or evaporation. The first gate line 7 and the second gate line 6 may be silver, copper, aluminum, and their alloys. The first gate line 7 and the second gate line 6 may be the same or different.

[0098] An embodiment of the present invention further provides a manufacturing method of a back-contact battery. This manufacturing method can fabricate the back-contact battery described in any of the above embodiments. The manufacturing method of the back-contact battery includes the following steps:

[0099] S100: Provide a semiconductor substrate 1. The semiconductor substrate 1 has opposite first and second surfaces. The first surface includes first regions 1a and second regions 1b arranged alternately along a first direction, and there is a third region 1c between the first region 1a and the second region 1b; the first region 1a includes an electrode region 1a2 and a non-electrode region 1a1.

[0100] Before this step, in some embodiments, the semiconductor substrate 1 can also be put into a polishing and cleaning machine, and the polishing liquid is used to remove the cutting damage layer of the semiconductor substrate 1.

[0101] S200: Form a textured surface on at least a part of the electrode region 1a2, and form a polished surface on the non-electrode region 1a1 and the second region 1b.

[0102] Among them, the textured surface of the electrode region 1a2 can include a plurality of pyramid-like shapes. The polished surface formed on the non-electrode region 1a1 and the second region 1b has a lower surface roughness and is smoother to facilitate subsequent processing and doping control, thereby helping to improve the yield rate of production and the overall reliability of the back-contact battery.

[0103] S300: Form a first semiconductor layer 3 at least in the first region 1a;

[0104] The first semiconductor layer 3 can be distributed in a plurality of strip shapes or in a plurality of shapes similar to the Chinese character "feng". The first semiconductor layer 3 can be formed in the semiconductor substrate 1 by means of diffusion, ion implantation, etc., or can be additionally formed on the first surface of the semiconductor substrate 1 through a deposition technique.

[0105] S400: Form a second semiconductor layer 4 at least in the second region 1b, and the second semiconductor layer 4 has a conductivity type opposite to that of the first semiconductor layer 3. The second semiconductor layer 4 includes at least one extension 4a extending onto the third region 1c, and the extension 4a extends at least to the interface between the first region 1a and the third region 1c so that the first semiconductor layer 3 and the second semiconductor layer 4 overlap.

[0106] The second semiconductor layer 4 can be additionally formed on the semiconductor substrate 1 through a deposition technique, or can be formed in the semiconductor substrate 1 by means of diffusion, ion implantation, etc. A part of the second semiconductor layer 4 extends onto the third region 1c to form the extension 4a, and the extension 4a overlaps with the first semiconductor layer 3 at the interface between the first region 1a and the third region 1c. In this way, the first semiconductor layer 3 and the second semiconductor layer 4 are electrically connected by using the extension 4a.

[0107] In the battery structure formed by the manufacturing method of the back-contact battery provided in this application, a matte surface is formed at least partially in the electrode region 1a2, while a polished surface is formed in the non-electrode region 1a1. At the same time, the lower resistivity between the first semiconductor layer 3 and the first gate line 7 and the higher carrier collection efficiency of the first semiconductor layer 3 covering the non-electrode region 1a1 are taken into account, thereby improving the power generation efficiency of the back-contact battery. Moreover, the second semiconductor layer 4 of the battery structure formed by the manufacturing method of the back-contact battery provided in this application includes an extension portion 4a, and the first semiconductor layer 3 and the second semiconductor layer 4 can be electrically connected by using the extension portion 4a. Based on this, when the back-contact battery is blocked and a certain reverse voltage is provided to the blocked back-contact battery, the current can be transmitted through the first semiconductor layer 3, the extension portion 4a, and the second semiconductor layer 4, avoiding the blocked cell from becoming a load and consuming the energy generated by other illuminated cells, thereby reducing the hot spot risk.

[0108] In some embodiments, a matte surface is formed at least partially in the electrode region 1a2, and a polished surface is formed in the non-electrode region 1a1 and the second region 1b; the method includes: forming a mask layer on the first surface and the second surface of the semiconductor substrate 1; removing the mask layer at least partially in the electrode region 1a2; and performing texturing on the semiconductor substrate 1 to form a matte surface at least partially in the electrode region 1a2. By adopting the above technical solution, a matte surface is formed at least partially in the electrode region 1a2 on the first surface by setting the mask layer, without reducing the overall thickness of the semiconductor substrate 1 and ensuring the mechanical strength of the semiconductor substrate 1.

[0109] Alternatively, a matte surface is formed at least partially in the electrode region 1a2, and a polished surface is formed in the non-electrode region 1a1 and the second region 1b; the method includes: performing texturing on the first surface and the second surface of the semiconductor substrate 1 to form a matte surface on the first surface and the second surface; forming a mask layer on the first surface and the second surface; removing the mask layer in the non-electrode region 1a1, the second region 1b, and the third region 1c; and forming a polished surface in the non-electrode region 1a1, the second region 1b, and the third region 1c. By adopting the manufacturing method of the back-contact battery described above, the matte surfaces on the first surface and the second surface in the electrode region 1a2 can be formed in the same step, simplifying the processing steps and facilitating the improvement of production efficiency.

[0110] In some embodiments, after at least forming the second semiconductor layer 4 in the second region 1b, the manufacturing method of the back contact battery further includes: forming a mask layer on the first surface and the second surface; removing the mask layer in the area except the extension portion 4a in the third region 1c; and performing texturing on the area except the extension portion 4a in the third region 1c to form a velvet surface. This is conducive to better isolating the first semiconductor layer 3 and the second semiconductor layer 4, and further preventing a large leakage current between the first semiconductor layer 3 and the second semiconductor layer 4 when the back contact battery is working normally.

[0111] The manufacturing method of the above-mentioned back contact battery is described in detail below through two specific embodiments.

[0112] Embodiment 1, as Figure 16 - Figure 23 As shown, the manufacturing method of the back contact battery specifically includes: Figure 16 As shown, a first mask layer 8 is formed on the first surface and the second surface of the semiconductor substrate 1. Next, as shown in Figure 17 As shown, the first mask layer 8 of at least a part of the electrode region 1a2 is removed to expose at least a part of the first surface of the electrode region 1a2 ( Figure 17 The first mask layer 8 in the vertical line area is removed). Next, Figure 18 As shown, the semiconductor substrate 1 is textured so that at least part of the electrode region 1a2 forms a texture surface. That is, the first surface not covered by the first mask layer 8 is textured so that the exposed first surface forms a texture surface. After the texture is completed, the first mask layer 8 is removed. Next, as shown in FIG. Figure 19 As shown, a first semiconductor layer 3 and a second mask layer 9 are formed on the first surface and the second surface, and the second mask layer 9 is located on the side of the first semiconductor layer 3 away from the semiconductor substrate 1. Next, as shown in FIG. Figure 20 As shown, the second mask layer 9 and the first semiconductor layer 3 of the second region 1b, the third region 1c and the second surface are removed, and the first semiconductor layer 3 of the first region 1a is retained. After this step, the second region 1b and the third region 1c can be processed to remove a portion of the semiconductor substrate 1 of the second region 1b and the third region 1c, so that the second region 1b and the third region 1c are recessed relative to the first region 1a toward the second surface. Next, as Figure 21As shown, a second semiconductor layer 4 is formed at least partially in the second region 1b and the third region 1c; when the back contact battery further includes a second interface layer 5, the second interface layer 5 is first formed at least partially in the second region 1b and the third region 1c, and then the second semiconductor layer 4 is formed. In this step, a third mask layer 10 may also be formed on the first surface, that is, the third mask layer 10 is formed on the side of the first semiconductor layer 3 and the second semiconductor layer 4 away from the semiconductor substrate 1 and the third region 1c. Next, the third mask layer 10 covering the position in the third region 1c where the extension 4a is not provided is removed, and then the region in the third region 1c not covered by the third mask layer 10 is textured to form a textured surface, and then the third mask layer 10 is removed. The position in the third region 1c having the extension 4a forms a structure as Figure 22 and the region in the third region 1c not covered by the third mask layer 10 forms a structure as Figure 23 after texturing.

[0113] Embodiment 2, as Figure 24 - Figure 31 shown, the manufacturing method of the back contact battery specifically includes: as Figure 24 shown, the first surface and the second surface of the semiconductor substrate 1 are textured so that the first surface and the second surface form a textured surface. Next, as Figure 25 shown, a fourth mask layer 11 is formed on the first surface and the second surface. Next, as Figure 26 shown, the fourth mask layer 11 on the non-electrode region 1a1 on the first surface, the second region 1b, and the third region 1c is removed so that the non-electrode region 1a1 on the first surface, the second region 1b, and the third region 1c are exposed. Next, as Figure 27 shown, the non-electrode region 1a1, the second region 1b, and the third region 1c are made to form a polished surface. Next, as Figure 28 shown, a first semiconductor layer 3 and a fifth mask layer 12 are formed on the first surface, the fifth mask layer 12 is located on the side of the first semiconductor layer 3 away from the semiconductor substrate 1, and the fifth mask layer 12 also covers the second surface of the semiconductor substrate 1. Next, as Figure 29As shown, the first semiconductor layer 3 and the fifth mask layer 12 in the second region 1b and the third region 1c are removed, and a second semiconductor layer 4 is formed at least partially in the second region 1b and the third region 1c; when the back-contact battery also includes a second interface layer 5, the second interface layer 5 is first formed at least partially in the second region 1b and the third region 1c, and then the second semiconductor layer 4 is formed. In this step, a sixth mask layer 13 can also be formed on the first surface, that is, the first semiconductor layer 3, the second semiconductor layer 4 on the side facing away from the semiconductor substrate 1, and the third region 1c all form the sixth mask layer 13. Next, the sixth mask layer 13 covering the position in the third region 1c where the extension portion 4a is not provided is removed, and then the area in the third region 1c not covered by the sixth mask layer 13 is textured to form a velvet surface, and then the sixth mask layer 13 is removed. The position in the third region 1c with the extension portion 4a is formed as shown in the figure. Figure 30 The structure of the third region 1c not covered by the third mask layer 10 is formed after texturing. Figure 31 structure.

[0114] In addition, the present application also provides a photovoltaic module, which includes a plurality of back-contact cells provided in any of the above embodiments and at least one interconnection member, wherein the interconnection member connects two adjacent back-contact cells in series or in parallel. In addition, when the first grid line 7 and the second grid line 6 are both fine grids, a main grid may be provided at the corresponding position of the interconnection member, and the current is transmitted through the semiconductor layer, the fine grid, the main grid and the interconnection member.

[0115] Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned back-contact cell and the method for manufacturing the back-contact cell, which will not be elaborated here.

[0116] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0117] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A back-contact battery, characterized in that, Comprising: A semiconductor substrate having opposite first and second surfaces, wherein the first surface includes first regions and second regions arranged alternately in a first direction, and there is a third region between the first regions and the second regions; the first regions include electrode regions and non-electrode regions, at least a part of the electrode regions is a matte surface, and the non-electrode regions are polished surfaces; A first semiconductor layer and a first gate line, the first semiconductor layer being formed at least in the first regions, the first gate line being formed on a side of the first semiconductor layer away from the first surface and being electrically connected to the first semiconductor layer covering the electrode regions; A second semiconductor layer and a second gate line, the second semiconductor layer being formed at least in the second regions and having a conductivity type opposite to that of the first semiconductor layer; the second gate line being formed on a side of the second semiconductor layer away from the first surface and being electrically connected to the second semiconductor layer; The second semiconductor layer includes at least one extension extending onto the third region, and the extension extends at least to an interface between the first region and the third region so that the first semiconductor layer and the second semiconductor layer overlap.

2. The back-contact battery according to claim 1, wherein, The matte surface of the electrode regions includes a plurality of pyramid-like structures, and the electrode regions protrude in a direction away from the first surface relative to the non-electrode regions; The distance between the non-electrode regions and the tops of the pyramid-like structures is h1, h1 ≤ 10 μm; and / or, the distance between the non-electrode regions and the bottoms of the pyramid-like structures is h2, 0.5 μm ≤ h2 ≤ 2.5 μm.

3. The back contact battery according to claim 1, characterized in that, The matte surface of the electrode regions includes a plurality of pyramid-like structures, and the electrode regions are recessed in a direction close to the first surface relative to the non-electrode regions; The distance between the non-electrode regions and the tops of the pyramid-like structures is h3, 0 μm ≤ h3 ≤ 2.5 μm; and / or, the distance between the non-electrode regions and the bottoms of the pyramid-like structures is h4, h4 ≤ 10 μm.

4. The back-contact battery according to claim 1, wherein, The first semiconductor layer has an adjacent side surface close to the second semiconductor layer; The extension extends to overlap only with the adjacent side surface; or, the extension extends to a side of the first semiconductor layer away from the semiconductor substrate near the third region.

5. The back-contact battery according to claim 4, characterized in that, The third region is recessed in a direction close to the first surface relative to the first region; the third region has a side wall surface close to the first region, and the extension extends from the side wall surface to overlap with the adjacent side surface.

6. The back-contact battery according to any one of claims 1-5, characterized in that, Except for the region where at least one of the extensions is located, the first semiconductor layer or the second semiconductor layer is not provided on other parts of the third region; and / or, at the overlapping position of the first semiconductor layer and the second semiconductor layer, there is also a second interface layer between the first semiconductor layer and the second semiconductor layer.

7. The back contact battery according to claim 6, characterized in that, The third region covered by the extension part is a polished surface; and / or, except for the regions where at least one of the extension parts is located, the other parts of the third region are suede surfaces, and the suede surfaces include a plurality of pyramid-like shapes; and / or, the ratio of the orthographic projection area of at least one of the extension parts on the first surface to the orthographic projection area of the third region on the first surface is 0.05 to 0.75; and / or, along the extension direction of the third region, the length of the extension part is 5 μm - 50 μm; and / or, along the extension direction of the third region, a plurality of the extension parts are spaced apart.

8. The back-contact battery according to claim 1, characterized in that, Along the first direction, the width of the electrode region in the first region is 10 μm to 150 μm; and / or, along the first direction, the width of the non-electrode region located on one side of the electrode region is 10 μm to 200 μm; and / or, along the first direction, the width of the first region is 100 μm to 500 μm; and / or, along the first direction, the width of the third region is 20 μm - 1000 μm; and / or, along the first direction, the width of the second region is 100 μm - 400 μm; and / or, along the first direction, the ratio of the width of the electrode region to the width of the first region is 5% - 50%; and / or, along the first direction, the ratio of the width of the non-electrode region located on one side of the electrode region to the width of the first region is 25% - 98%.

9. The back-contact battery according to claim 1, characterized in that, The reflectivity of the electrode region is 10% to 20%, and the reflectivity of the non-electrode region is 30% to 50%; or, the back-contact battery further includes a passivation layer provided on the first surface, the passivation layer is at least formed on the sides of the first semiconductor layer and the second semiconductor layer facing away from the semiconductor substrate, and the reflectivity of the part of the passivation layer covering the electrode region is 2% to 8%, and the reflectivity of the part of the passivation layer covering the non-electrode region is 3% to 15%.

10. The back-contact battery according to claim 1, wherein, The sheet resistance of the electrode region is less than the sheet resistance of the non-electrode region; and / or, the sheet resistance of the electrode region is 150 Ω to 500 Ω.

11. A manufacturing method of a back contact battery, characterized in that, Comprising: Providing a semiconductor substrate having opposite first and second surfaces, the first surface including a first region and a second region arranged alternately along a first direction, and there is a third region between the first region and the second region; the first region includes an electrode region and a non-electrode region; Forming a suede surface at least locally in the electrode region, and forming a polished surface in the non-electrode region and the second region; Forming a first semiconductor layer at least in the first region; Forming a second semiconductor layer at least in the second region, and the second semiconductor layer has a conductivity type opposite to that of the first semiconductor layer, and the second semiconductor layer includes at least one extension part extending onto the third region, and the extension part at least extends to the interface between the first region and the third region so that the first semiconductor layer and the second semiconductor layer overlap.

12. The manufacturing method of the back contact battery according to claim 11, characterized in that, Forming a suede surface at least locally in the electrode region, and forming a polished surface in the non-electrode region and the second region; Comprising: Forming a mask layer on the first surface and the second surface of the semiconductor substrate; Removing the mask layer at least locally in the electrode region; Texturize the semiconductor substrate such that at least a portion of the electrode region forms a textured surface; Alternatively, form a textured surface on at least a portion of the electrode region, and form a polished surface on the non-electrode region and the second region; including: Texturize the first surface and the second surface of the semiconductor substrate so that the first surface and the second surface form a textured surface; Form a mask layer on the first surface and the second surface; Remove the mask layer in the non-electrode region, the second region, and the third region; Make the non-electrode region, the second region, and the third region form a polished surface.

13. The manufacturing method of the back-contact battery according to claim 11, characterized in that, After forming at least the second semiconductor layer in the second region, the manufacturing method of the back-contact battery further includes: Form a mask layer on the first surface and the second surface; Remove the mask layer in the region of the third region except for the extension portion; Texturize the region of the third region except for the extension portion to form a textured surface.

14. The manufacturing method of the back contact battery according to claim 11, characterized in that, The first semiconductor layer has an adjacent side surface close to the second semiconductor layer; The extension portion extends to only overlap with the adjacent side surface; or, the extension portion extends to the side of the first semiconductor layer in the third region away from the semiconductor substrate.

15. A photovoltaic module, characterized in that, Including a plurality of back-contact batteries according to any one of claims 1 to 10 and at least one interconnect, the interconnect connecting two adjacent back-contact batteries in series or in parallel.

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