Back contact battery and preparation method thereof

Abstract

The invention belongs to the field of solar cells, relates to a back contact cell and a preparation method thereof, and can improve the conversion efficiency, and the back contact cell comprises a semiconductor substrate which comprises a front surface and a back surface; the first semiconductor layers and the second semiconductor layers are alternately arranged on the back face in the X-axis direction, the edges of the first semiconductor layers and the edges of the second semiconductor layers form an overlapping area in the Z-axis direction, first grooves are formed between the adjacent second semiconductor layers, second grooves are formed in the outer surfaces of the second semiconductor layers, and the first grooves are communicated with the second grooves. The conduction type of the second semiconductor layer is opposite to that of the first semiconductor layer; the conductive film layer is arranged on the outer surfaces of the first groove, the second groove and the overlapping area, two first isolation areas are arranged on the conductive film layer at intervals and correspond to the groove bottom of the second groove, and each first isolation area comprises at least one first isolation groove formed in the X-axis direction at intervals.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a back contact cell and a preparation method thereof. Background Art

[0002] Conventional hybrid back contact cells have a first region semiconductor layer mainly composed of a tunneling oxide layer / doped polysilicon layer and a second region semiconductor layer mainly composed of intrinsic amorphous silicon / doped amorphous silicon alternately arranged on the back of the cell, and the semiconductor layer in each region is connected to a transparent electrode.

[0003] Related Art A back contact battery mentioned in Chinese patent CN117577709B has an isolation area of ​​a transparent conductive layer such as Figure 8 As shown in Wa, the isolation region spans part of the p region ( Figure 8 The edge of the W2 region in the Figure 8 However, this method causes a large loss of transparent conductive layer area. In addition, in the process of removing the transparent conductive layer, it is easy to cause etching of the underlying thin film, reducing the battery efficiency. Summary of the invention

[0004] Based on this, it is necessary to provide a back contact battery that can improve the conversion efficiency of the battery. In addition, a preparation method of the back contact battery is also proposed.

[0005] In a first aspect of the present application, a back-contact battery comprises: a semiconductor substrate, comprising a front side and a back side; a first semiconductor layer and a second semiconductor layer, which are alternately arranged on the back side along the X-axis direction, wherein the edge of the first semiconductor layer and the edge of the second semiconductor layer form an overlapping area in the Z-axis direction, a first groove is formed between adjacent second semiconductor layers, the outer surface of the second semiconductor layer has a second groove, and the conductivity type of the second semiconductor layer is opposite to the conductivity type of the first semiconductor layer; and a conductive film layer, which is arranged on the outer surface of the first groove, the second groove and the overlapping area, wherein two first isolation areas are spaced apart on the conductive film layer corresponding to the bottom of the second groove, and each of the first isolation areas comprises at least one first isolation groove spaced apart along the X-axis direction.

[0006] In some embodiments, along the X-axis direction, in the same first isolation region, a distance between two adjacent first isolation trenches is 5-15 μm.

[0007] In some embodiments, in the same second groove, the second semiconductor layer between two first isolation regions includes a crystallized microcrystalline silicon region, and along the X-axis direction, a distance between the crystallized microcrystalline silicon region and any of the first isolation regions is less than 5 μm.

[0008] In some embodiments, the opposite sidewalls of the second groove are slopes that are biased towards the top of the overlapping region. Along the X-axis direction, the width of the overlapping region is 10 - 160 μm, the width of the slope is 5 - 20 μm, the width of the first isolation groove is 35 - 80 μm, and the width of the crystallized microcrystalline silicon region is 300 - 600 μm.

[0009] In some embodiments, in the same second groove, the second semiconductor layer between the two first isolation regions is an amorphous silicon region.

[0010] In some embodiments, the opposite sidewalls of the second groove are slopes that are biased towards the top of the overlapping region. In the X-axis direction, in the same second groove, the two first isolation regions are respectively close to one of the slopes. The starting points of the two first isolation regions are relatively far from each other, and the ending points of the two first isolation regions are relatively close to each other. The distance between the starting point of any one of the first isolation regions and the bottom of the adjacent slope is 0 - 3 μm.

[0011] In some embodiments, a second isolation region is provided at the position of the conductive film layer corresponding to the top of the overlapping region. The second isolation region includes at least one second isolation groove that is spaced along the X-axis direction.

[0012] In some embodiments, along the X-axis direction, the width of the second isolation groove is 0 - 80 μm.

[0013] In some embodiments, within the same second isolation region, the distance between two adjacent second isolation grooves is 10 - 30 μm.

[0014] In some embodiments, a third isolation region is provided at the position of the conductive film layer corresponding to the sidewall of the second groove.

[0015] In a second aspect of the present application, a method for manufacturing a back-contact battery is provided, including the steps of: Step S10: sequentially forming a first semiconductor layer and a mask layer on the back surface of a semiconductor substrate; Step S20: removing the first semiconductor layer and its corresponding mask layer within a first preset area on the back surface obtained in Step S10 to form a recessed area; Step S30: forming a textured surface at the bottom of the recessed area; Step S40: forming a second semiconductor layer on the back surface obtained in Step S30, and forming a second groove on the outer surface of the second semiconductor layer corresponding to the recessed area; Step S50: removing the second semiconductor layer and the mask layer corresponding to the second semiconductor layer within a second preset area on the back surface obtained in Step S40 to form a first groove arranged at intervals with the second groove, and an overlapping area is formed at the edges of the first semiconductor layer and the second semiconductor layer; Step S60: forming a conductive film layer on the back surface obtained in Step S50; Step S70: etching an opening in a third preset area on the back surface obtained in Step S60, and forming two spaced-apart first isolation areas on the conductive film layer at the bottom of the second groove, and each first isolation area includes at least one first isolation groove spaced apart in the X-axis direction.

[0016] In some embodiments, Step S40 includes: forming a passivation layer on the back surface obtained in Step S30; forming an amorphous silicon layer on the passivation layer.

[0017] In some embodiments, Step S50 includes: removing the passivation layer and the amorphous silicon layer at the first groove; performing laser scanning on a predetermined area of the amorphous silicon layer at the second groove to form a crystallized microcrystalline silicon area.

[0018] In some embodiments, it further includes: etching an opening in a fourth preset area on the back surface obtained in Step S60 to form a second isolation area on the conductive film layer at the top of the overlapping area.

[0019] In some embodiments, it further includes: etching an opening in a fifth preset area on the back surface obtained in Step S60 to form a third isolation area at the position of the side wall of the conductive film layer corresponding to the second groove.

[0020] In the present application, the first isolation area is arranged in the second groove on the outer surface of the second semiconductor layer, avoiding excessive etching of the conductive film layer and causing a decrease in the bifaciality of the battery, and improving the conversion efficiency; the first isolation area enables the conductive film layer to form one or more conductive film layer islands, causing local leakage of the conductive film layer at the first isolation area, which is beneficial to reducing the hot spot effect of the back-contact battery. Therefore, the back-contact battery of the present application can improve the conversion efficiency and reduce the hot spot effect. Description of the Drawings

[0021] Figure 1 It is a partial cross-sectional structural schematic diagram of a back-contact battery according to an embodiment of the present application.

[0022] Figure 2 is Figure 1 An enlarged view of part A in

[0023] Figure 3 is Figure 1 An enlarged view of part B in

[0024] Figure 4 A schematic flow chart of the preparation method of a back-contact battery according to an embodiment of the present application.

[0025] Figure 5 A schematic structural diagram after step S10 of the preparation method of the present application.

[0026] Figure 6 A schematic structural diagram after step S20 of the preparation method of the present application.

[0027] Figure 7 A schematic structural diagram after step S30 of the preparation method of the present application.

[0028] Figure 8 A schematic structural diagram after step S40 of the preparation method of the present application.

[0029] Figure 9 A schematic structural diagram after step S50 of the preparation method of the present application.

[0030] Figure 10 A schematic structural diagram after step S60 of the preparation method of the present application.

[0031] Figure 11 A schematic structural diagram after step S70 of the preparation method of the present application.

[0032] Figure 12 is Figure 11 An enlarged view of part C in

[0033] Figure 13 A schematic flow chart of the implementation manner of step S40 of the embodiment of the present application.

[0034] Figure 14 A schematic flow chart of the implementation manner of step S50 of the embodiment of the present application.

[0035] Figure 15 A schematic flow chart of the implementation manner of step S80 and step S90 of the embodiment of the present application.

[0036] Reference numerals:

[0037] 100, Back-contact battery; 10, Semiconductor substrate; 101, Front side; 102, Back side; 110, Concave region; 111, Textured surface; 20, First semiconductor layer; 210, Tunnel oxide layer; 220, Intrinsic polysilicon layer; 30, Second semiconductor layer; 301, Crystallized microcrystalline silicon region; 310, Passivation layer; 320, Amorphous silicon layer; 40, Overlap region; 401, Top; 50, First groove; 60, Second groove; 601, Sidewall; 70, Conductive film layer; 701, Bottom of slope; 710, First isolation region; 711, First isolation groove; 720, Second isolation region; 721, Second isolation groove; 730, Third isolation region; 80, Mask layer; 910, First electrode; 920, Second electrode. Detailed implementation manners

[0038] Unless otherwise indicated in the context, the materials described herein can be formed by any suitable techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the techniques for depositing or growing the material can be selected by those of ordinary skill in the art.

[0039] In addition, unless otherwise indicated in the context, the material removal described herein can be achieved by any suitable techniques, including but not limited to etching (e.g., dry etching, wet etching, vapor etching), ion milling, polishing planarization (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0040] The term "semiconductor" used herein can refer to, for example, a material layer, a substrate, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon on sapphire (SOS) technology, silicon on insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by substrate semiconductor structures, and other semiconductor structures well known to those skilled in the art.

[0041] In a first aspect of the present application, with reference to Figures 1 to 3 , an embodiment of the present application provides a back-contact battery 100, which includes a semiconductor substrate 10, a first semiconductor layer 20, a second semiconductor layer 30, and a conductive film layer 70.

[0042] The semiconductor substrate 10 includes a front surface 101 and a back surface 102. Here, the back surface 102 is the backlight surface, which refers to the side of the back-contact battery 100 that faces away from the sun when it is working. The front surface 101 is the side of the back-contact battery 100 that faces the sun when it is working. The semiconductor substrate 10 is used to receive incident light and generate photo-generated carriers. The semiconductor substrate 10 can be, for example, silicon, germanium, silicon-germanium, or silicon-on-insulator, and various doped silicon, including but not limited to boron-doped, phosphorus-doped, gallium-doped, antimony-doped, etc., or mixed-doped silicon.

[0043] The first semiconductor layer 20 and the second semiconductor layer 30 are alternately arranged on the back surface 102 along the X-axis direction. The edges of the first semiconductor layer 20 and the edges of the second semiconductor layer 30 form an overlapping region 40 in the Z-axis direction, and a first groove 50 is formed between adjacent second semiconductor layers 30, and the outer surface of the second semiconductor layer 30 has a second groove 60.

[0044] The X-axis direction is parallel to the back surface 102. The Z-axis direction is perpendicular to the back surface 102. In this application, the two end edges of the second semiconductor layer 30 respectively extend outward to cover the edges of the adjacent first semiconductor layer 20, thereby forming an overlapping region 40. The first groove 50 exposes the first semiconductor layer 20, so that it can be in ohmic contact with the first electrode 910.

[0045] The conductivity type of the second semiconductor layer 30 is opposite to that of the first semiconductor layer 20. Specifically, the second semiconductor layer 30 is a P-type doped semiconductor layer, and the doping element is a P-type doping element such as boron. The first semiconductor layer 20 is an N-type doped semiconductor layer, and the doping element is an N-type doping element such as antimony.

[0046] The material of the conductive film layer 70 can refer to the corresponding types in the prior art. Exemplarily, the material of the conductive film layer 70 can be an indium oxide-based thin film doped with at least one of tin, zinc, tungsten, titanium, etc. The conductive film layer 70 is disposed on the outer surfaces of the first groove 50, the second groove 60, and the overlapping region 40. Wherein, corresponding to the bottom of the second groove 60, two first isolation regions 710 are spaced on the conductive film layer 70, and each first isolation region 710 includes at least one first isolation groove 711 spaced along the X-axis direction.

[0047] Specifically, the outer surface of the first groove 50 (including the bottom wall and side walls of the first groove 50), the surface of the second groove 60 (including the bottom of the second groove 60 and the side wall 601), and the outer surface of the overlapping region 40 are all covered with the conductive film layer 70. When the two ends of the second semiconductor layer 30 respectively extend outward to cover the ends of the adjacent first semiconductor layer 20 to form an overlapping region 40, the second side wall 601 of the second groove 60 is also the side wall 601 of the overlapping region 40.

[0048] Reference Figure 1and Figure 2 In this application, two first isolation regions 710 are provided at intervals on the conductive film layer 70 at the bottom of the second groove 60. The first isolation region 710 includes at least one first isolation groove 711. The first isolation groove 711 interrupts the conductive film layer 70 to form a partition. When multiple first isolation grooves 711 are provided in the first isolation region 710, the range of the first isolation region 710 refers to the range between the edges of the head and tail first isolation grooves 711 in the same first isolation region 710 that are far away from each other in the X-axis direction.

[0049] Compared with the prior art where the isolation region straddles the P region and the N region, in this application, the first isolation region 710 on the conductive film layer 70 is provided in the second groove 60 on the outer surface of the second semiconductor layer 30, avoiding the decrease in the double-sided rate of the battery caused by excessive etching of the conductive film layer 70. Specifically, when the second semiconductor layer 30 is a P-type semiconductor layer, the region corresponding to the second groove 60 is the P region, and the region corresponding to the first groove 50 is the N region. The first isolation region 710 is provided in the P region with poor lateral transmission, which can avoid etching the conductive film layer 70 in the N region.

[0050] In addition, in the X-axis direction, the first isolation groove 711 makes the conductive film layer 70 form one or more conductive film layer islands, causing local leakage of the conductive film layer 70 at the first isolation region 710, which is beneficial to reducing the hot spot effect of the back contact battery 100. Thus, the back contact battery 100 of this application can improve the conversion efficiency and reduce the hot spot effect.

[0051] In some embodiments, referring to Figure 1 and Figure 2 in the X-axis direction, in the same first isolation region 710, the distance d1 between two adjacent first isolation grooves 711 is 5 - 15 μm. The distance d1 between two adjacent first isolation grooves 711 refers to the distance between the edges of two adjacent first isolation grooves 711 that are close to each other. The distance d1 between two adjacent first isolation grooves 711 is, for example, 5 μm, 10 μm, 15 μm. The above distance can avoid etching off too much of the conductive film layer 70, and at the same time form conductive film layer islands, resulting in local leakage, which is beneficial to reducing the hot spot effect of the back contact battery 100.

[0052] In some embodiments, referring to Figure 1 and Figure 2, in the same first groove 50, the second semiconductor layer 30 between the two first isolation regions 710 includes a crystallized microcrystalline silicon region 301. Along the X-axis direction, the distance d2 between the crystallized microcrystalline silicon region 301 and any one of the first isolation regions 710 is less than 5 μm. The distance d2 between the crystallized microcrystalline silicon region 301 and the first isolation region 710 refers to the distance between the two edges of the crystallized microcrystalline silicon region 301 and the first isolation region 710 that are close to each other. This distance can specifically be 0 μm, 1 μm, 3 μm, 5 μm; this can ensure that the crystallized microcrystalline silicon region 301 has a relatively large area.

[0053] The second semiconductor layer 30 between the two first isolation regions 710 is crystallized into a crystallized microcrystalline silicon region 301. The crystallized microcrystalline silicon region 301 can improve the contact with the conductive film layer 70, reduce the contact resistance, and thus improve the battery efficiency.

[0054] Furthermore, referring to Figure 1 and Figure 2 , the conductive film layers 70 on the opposite sidewalls 601 of the second groove 60 are slopes that are biased towards the top 401 of the overlapping region 40. Along the X-axis direction, the width D1 of the overlapping region 40 is 10 - 160 μm, the width W1 of the slope is 5 - 20 μm, the width Wa of the first isolation groove 711 is 35 - 80 μm, and the width W2 of the crystallized microcrystalline silicon region 301 is 300 - 600 μm.

[0055] In actual preparation, the opposite sidewalls 601 of the second groove 60 and the conductive film layers 70 thereon are a slope. The width D1 of the overlapping region 40 is 10 - 160 μm, such as 10 μm; 40 μm; 60 μm, 90 μm, 130 μm, 160 μm. The width W1 of the slope is, for example, 5 μm, 8 μm, 0 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm. The width Wa of the first isolation groove 711 is, for example, 35 μm, 40 μm, 45 μm, 50 μm, 60 μm, 70 μm, 80 μm. The width W2 of the crystallized microcrystalline silicon region 301 is, for example, 300 μm, 350 μm, 380 μm, 400 μm, 450 μm, 500 μm, 580 μm, 600 μm. Within the above dimensional ranges, it has been verified that a relatively high battery efficiency can be ensured, and at the same time, it can be achieved by patterning using an etching process.

[0056] In some other embodiments, in the same first groove 50, the second semiconductor layer 30 between the two first isolation regions 710 can also be an amorphous silicon region. When the second semiconductor layer 30 between the two first isolation regions 710 is an amorphous silicon region, during the preparation process, for example, the amorphous silicon region can be formed by a conventional deposition process, without additional processing steps, and the manufacturing process is relatively simple.

[0057] In some embodiments, referring to Figure 1 and Figure 2, the conductive film layers 70 on the opposite side walls 601 of the second groove 60 are slopes that are biased towards the top 401 of the overlapping region 40; in the X-axis direction, in the same second groove 60, the two first isolation regions 710 are respectively close to one slope. The starting points of the two first isolation regions 710 are relatively far from each other, and the ending points of the two first isolation regions 710 are relatively close to each other. The distance between the starting point of any first isolation region 710 and the bottom 701 of the adjacent slope is 0 - 3 μm.

[0058] For the two first isolation regions 710, their ending points are closer to the other first isolation region 710 than their starting points. Refer to Figure 1 and Figure 2 , where Figure 2 only magnifies and shows schematically Figure 1 the structure of the first isolation region 710 located on the left side of the second groove 60 in

[0059] The distance between the starting point of the first isolation region 710 on the left side and the bottom 701 of the slope on the left side is D2. The starting point of the first isolation region 710 on the left side is the edge of the first isolation groove 711 that is closest to the bottom 701 of the slope on the left side among the first isolation regions 710 on the left side. The situation of the distance between the first isolation region 710 on the right side and the bottom 701 of the slope on the right side is similar. Taking the first isolation region 710 on the left side as an example, the above distance is, for example, 0 μm, 1 μm, 3 μm. When the distance is 0 μm, it means that the starting point of the first isolation region 710 on the left side coincides with the first end point of the second groove 60.

[0060] Through the above design, the distance between the starting point of each first isolation region 710 and the bottom 701 of the adjacent slope is 0 - 3 μm, reducing the risk of leakage and keeping the local leakage within the expected range.

[0061] Refer to Figures 1 to 3 As shown, a second isolation region 720 is provided at the position of the conductive film layer 70 corresponding to the top 401 of the overlapping region 40. The second isolation region 720 includes at least one second isolation groove 721 spaced along the X-axis direction.

[0062] At least one second isolation region 720 is provided on the conductive film layer 70 at the top 401 of the overlapping region 40. Each second isolation region 720 includes one or more second isolation grooves 721. Along the X-axis direction, the width Wb of the second isolation groove 721 is 0 - 50 μm. The width Wb of the second isolation groove 721 is, for example, 0 μm; 35 μm, 40 μm, 45 μm, 50 μm, 60 μm, 70 μm, 80 μm. When the width of the second isolation groove 721 is 0 μm, it means that no second isolation groove 721 is provided.

[0063] The second isolation region 720 forms islands of the conductive film layer on the top 401 of the overlapping region 40 to achieve local leakage, thereby facilitating the reduction of the hot spot effect of the back contact battery 100. The width Wb of the second isolation groove 721 is 0 - 80 μm, which can reduce the etching degree of the conductive film layer 70 and avoid the reduction of the bifaciality of the battery caused by excessive etching of the transparent conductive film.

[0064] Specifically, the distance d3 between two adjacent second isolation grooves 721 is 10 - 30 μm. The distance d3 between two adjacent second isolation grooves 721 refers to the distance between the edges of two adjacent second isolation grooves 721 that are close to each other. The distance d3 between two adjacent second isolation grooves 721 is, for example, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm. The above distance can avoid etching away too much of the conductive film layer 70, while forming multiple islands of the conductive film layer to form local leakage, which is beneficial to reducing the hot spot effect of the back contact battery 100.

[0065] In some embodiments, referring to Figure 2 , a third isolation region 730 is provided at the position of the sidewall 601 of the first groove 50 corresponding to the conductive film layer 70. The formation method of the third isolation region 730 can be completely similar to the formation methods of the first isolation region 710 and the second isolation region 720. The third isolation region 730 forms multiple islands of the conductive film layer at the sidewall 601 of the first groove 50 to form local leakage, which is beneficial to reducing the hot spot effect of the back contact battery 100 and improving the conversion efficiency of the back contact battery 100.

[0066] In a second aspect, the present application proposes a method for manufacturing a back contact battery 100 for manufacturing the above-mentioned back contact battery 100.

[0067] Referring to Figure 4 , the method for manufacturing the back contact battery 100 of the present application includes the following steps.

[0068] Step S10, as Figure 5 shown, a first semiconductor layer 20 and a mask layer 80 are sequentially formed on the back surface 102 of the semiconductor substrate 10.

[0069] Step S20, as Figure 6 shown, the first semiconductor layer 20 and the corresponding mask layer 80 in the first preset area on the back surface obtained in step S10 are removed to form a recessed area 110.

[0070] After removing the first semiconductor layer 20 and the corresponding mask layer 80, a recessed area 110 exposing the semiconductor substrate 10 is formed.

[0071] Step S30, referring to Figure 7, a matte surface 111 is formed at the bottom of the concave area 110. For texturing and cleaning, a matte surface 111 is formed on the semiconductor substrate 10 at the concave area 110.

[0072] Step S40, refer to Figure 8 , a second semiconductor layer 30 is formed on the back surface obtained in step S30, and a second groove 60 is formed on the outer surface of the second semiconductor layer 30 corresponding to the concave area 110.

[0073] In this step, the formed second semiconductor layer 30 covers the back surface 102 of the intermediate obtained in step S30. The second semiconductor layer 30 covers the side wall 601 and the bottom wall of the concave area 110, so that a second groove 60 is formed on the outer surface of the second semiconductor layer 30 corresponding to the concave area 110.

[0074] Step S50, refer to Figure 9 , the second semiconductor layer 30 and the mask layer corresponding to the second semiconductor layer 30 in the second preset area on the back surface obtained in step S40 are removed, a first groove 50 arranged at intervals with the second groove 60 is formed, and an overlapping area 40 is formed at the edges of the first semiconductor layer 20 and the second semiconductor layer 30.

[0075] In this step, part of the second semiconductor layer 30 is etched away to expose the underlying first semiconductor layer 20. The two end edges of the second semiconductor layer 30 respectively cover the edges of the adjacent first semiconductor layer 20 to form an overlapping area 40.

[0076] In steps S40 and S50, the first semiconductor layer 20, the second semiconductor layer 30 and their mask layer 80 can be formed by referring to any corresponding method in the prior art. For example, the first semiconductor layer 20 can be formed by chemical vapor deposition process.

[0077] In steps S40 and S50, the corresponding semiconductor layer and its corresponding mask layer 80 are removed to form the corresponding concave area 110 and the first groove 50, which can be formed by laser etching, chemical etching and any other required techniques.

[0078] Step S60, refer to Figure 10 , a conductive film layer 70 is formed on the back surface obtained in step S50.

[0079] The conductive film layer 70 covers the side wall and the bottom wall of the first groove 50, covers the overlapping area 40, and covers the side wall 601 and the bottom wall of the second groove 60.

[0080] The formation method of the conductive film layer 70 can refer to the corresponding method in the prior art. Exemplarily, the conductive film layer 70 can be formed by magnetron sputtering, evaporation, ion beam evaporation, activated plasma chemical vapor deposition and any other required techniques.

[0081] Step S70, referring to Figure 11 and Figure 12 , in the third preset area on the back surface obtained in step S60, an etching opening is made to form two first isolation areas 710 arranged at intervals on the conductive film layer 70 at the bottom of the second groove 60. Each first isolation area 710 includes at least one first isolation groove 711 arranged at intervals in the X-axis direction.

[0082] The first isolation groove 711 can be formed, for example, by laser, ink corrosion, mask corrosion, and any other required technology.

[0083] Referring to Figure 8 and Figure 13 , in some embodiments, step S40 includes:

[0084] Step S410, forming a passivation layer 310 on the back surface obtained in step S30.

[0085] Step S420, forming an amorphous silicon layer 320 on the passivation layer 310.

[0086] The passivation layer 310 can reduce carrier recombination and optimize the carrier transport path. The material of the passivation layer 310 is, for example, a-Si:H(i), silicon oxide, etc.

[0087] Referring to Figure 9 and Figure 14 , in some embodiments, step S50 includes:

[0088] Step S510, removing the passivation layer 310 and the amorphous silicon layer 320 at the first groove 50.

[0089] Step S520, performing a laser scan on a predetermined area of the amorphous silicon layer 320 at the second groove 60 to form a crystallized microcrystalline silicon region 301.

[0090] Through an etching process, the passivation layer 310 and the amorphous silicon layer 320 in the second preset area are removed to form the first groove 50. At the same time, a laser scan is performed on a part of the amorphous silicon layer 320 in the second groove 60 to form a crystallized microcrystalline silicon region 301.

[0091] Referring to Figures 1 to 3 , Figure 15 , the method for preparing the back contact battery 100 of the present application further includes the steps:

[0092] Step S80, making an etching opening in the fourth preset area on the back surface obtained in step S60 to form a second isolation area 720 on the conductive film layer 70 at the top 401 of the overlapping area 40.

[0093] Through an etching process, a groove is formed in the conductive film layer 70 on the top 401 of the overlapping region 40 to form a second isolation region 720.

[0094] Reference Figures 1 to 3 、 Figure 15 , the method for manufacturing the back contact battery 100 of the present application further includes the steps of:

[0095] Step S90: Further include: etching an opening in the fifth preset area on the back surface obtained in step S60 to form a third isolation region 730 at a position corresponding to the side wall 601 of the second groove 60 in the conductive film layer 70.

[0096] Through an etching process, a groove is formed in the conductive film layer 70 at the side wall 601 of the second groove 60 to form a third isolation region 730.

[0097] In some embodiments, referring to Figure 1 , the method for manufacturing the back contact battery 100 further includes: forming a first electrode 910 and a second electrode 920 in the first groove 50 and the second groove 60 respectively on the back surface obtained in step S70, step S80 or step S90. The first electrode 910 and the second electrode 920 can be formed by printing, transfer printing, electroplating, etc.

[0098] The back contact battery 100 in the embodiments of the present application will be described below in conjunction with some of the above embodiments and related comparative examples.

[0099] Embodiment 1

[0100] Reference Figure 5 As shown, a semiconductor substrate 10 is provided, specifically an N-type silicon wafer, and the N-type silicon wafer is cleaned and polished. A first semiconductor layer 20 is formed on the back surface 102 of the N-type silicon wafer. The first semiconductor layer 20 includes a tunneling oxide layer 210 and an intrinsic polysilicon layer 220 that are sequentially away from the back surface 102 of the N-type silicon wafer. The intrinsic polysilicon layer 220 is subjected to phosphorus diffusion doping to form a phosphorus-doped polysilicon layer. Then, a mask layer 80 is provided, specifically a silicon oxide layer.

[0101] As Figure 6 shown, patterning is performed on the obtained back surface to remove the first semiconductor layer 20 and the mask layer 80 in the concave region 110 to form a concave region 110. Figure 5

[0102] Figure 7 As shown, texturing is performed on the N-type silicon wafer in the concave region 110 to form a textured surface 111.

[0103] As Figure 8 shown, in Figure 7The second semiconductor layer 30 is formed on the obtained back side. The second semiconductor layer 30 includes a passivation layer 310 and an amorphous silicon layer 320 which are sequentially away from the semiconductor substrate 10. The passivation layer 310 is specifically an a-Si:H(i) layer, and the amorphous silicon layer 320 is specifically a P-type doped amorphous silicon thin film layer. The passivation layer 310 of a-Si:H(i) material can be deposited and formed under low temperature (annealing conditions). The P-type doped amorphous silicon thin film layer, such as AlOx or evaporated Al as a doping source, can form aluminum-doped amorphous silicon under low temperature annealing conditions. The low temperature range is less than 250°C, for example, 200°C.

[0104] like Figure 9 , Figure 12 As shown, in Figure 8 The second semiconductor layer 30 is removed from the position of the back surface corresponding to the first groove 50, and a laser with a wavelength of 355 nm is used for scanning to crystallize part of the P-type doped amorphous silicon thin film layer to form a crystallized microcrystalline silicon region 301. A laser with a wavelength of 532 nm can also be used for scanning.

[0105] like Figure 10 As shown, in Figure 9 The resulting back surface is provided with a conductive film layer 70, specifically a tin-doped indium oxide-based film.

[0106] like Figure 11 and Figure 12 As shown, ink etching or laser patterning is performed on the conductive film layer 70 to form a first isolation region 710. The first isolation region 710 includes at least one first isolation groove 711.

[0107] In this embodiment, the width D1 of the overlap region 40 is 10 μm, the width W1 of the slope is 5 μm, the width Wa of the first isolation region 710 is 35 μm, and the width W2 of the crystallized microcrystalline silicon region 301 is 300 μm. In addition, embodiments 2-6 are carried out with reference to embodiment 1, except that the relevant size parameters are different, and refer to Table 1 for details.

[0108] The performance of the back contact batteries obtained in Examples 1-6 was tested using an IV tester and compared with related technologies. The results are shown in Table 1.

[0109] Table 1

[0110]

[0111] According to Table 1, the number of the first isolation trench 711 and the second isolation trench 721 in Examples 1 and 3 is 1; in Examples 2 and 4, the number of the first isolation trench 711 and the second isolation trench 721 is 2; in Examples 5 and 6, the number of the first isolation trench 711 and the second isolation trench 721 is 3. In Table 1, Comparative Examples 1, 2 and 3 are Examples 1, 2 and 7 in the related art, respectively.

[0112] It can be seen from the above results that the conversion efficiency of the back-contact battery 100 of the embodiment of the present invention is higher than that of the comparative example.

[0113] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0114] The above embodiments only represent several implementation manners of the present application, and the description thereof is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A back-contact battery, characterized in that, Comprising: A semiconductor substrate, including a front side and a back side; A first semiconductor layer and a second semiconductor layer, alternately arranged along the X-axis direction on the back side, an overlapping region is formed between the edge of the first semiconductor layer and the edge of the second semiconductor layer in the Z-axis direction, a first groove is formed between adjacent second semiconductor layers, and the outer surface of the second semiconductor layer has a second groove, and the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer; and A conductive film layer is disposed on the outer surfaces of the first groove, the second groove and the overlapping region. Wherein, corresponding to the bottom of the second groove, two first isolation regions are spaced apart on the conductive film layer, and each first isolation region includes at least one first isolation groove spaced apart along the X-axis direction.

2. The back contact battery according to claim 1, wherein Along the X-axis direction, in the same first isolation region, the distance between two adjacent first isolation grooves is 5-15 μm.

3. The back-contact battery according to claim 1, wherein, In the same second groove, the second semiconductor layer between the two first isolation regions includes a crystallized microcrystalline silicon region, and along the X-axis direction, the distance between the crystallized microcrystalline silicon region and any one of the first isolation regions is less than 5 μm.

4. The back-contact battery according to claim 3, characterized in that, The conductive film layers on the opposite side walls of the second groove are slopes biased towards the top of the overlapping region. Along the X-axis direction, the width of the overlapping region is 10-160 μm, the width of the slope is 5-20 μm, the width of the first isolation groove is 35-80 μm, and the width of the crystallized microcrystalline silicon region is 300-600 μm.

5. The back contact battery according to claim 1, characterized in that, In the same second groove, the second semiconductor layer between the two first isolation regions is an amorphous silicon region.

6. The back contact battery according to claim 1, characterized in that, The conductive film layers on the opposite side walls of the second groove are slopes biased towards the top of the overlapping region. In the X-axis direction, in the same second groove, the two first isolation regions are respectively close to one of the slopes, the starting points of the two first isolation regions are relatively far away, the ending points of the two first isolation regions are relatively close, and the distance between the starting point of any one of the first isolation regions and the bottom of the adjacent slope is 0-3 μm.

7. The back-contact battery according to claim 1, characterized in that, The conductive film layer is provided with a second isolation region at the position corresponding to the top of the overlapping region, and the second isolation region includes at least one second isolation groove spaced apart along the X-axis direction.

8. The back-contact battery according to claim 7, characterized in that, Along the X-axis direction, the width of the second isolation groove is 0-80 μm.

9. The back-contact battery according to claim 7, wherein, In the same second isolation region, the distance between two adjacent second isolation grooves is 10-30 μm.

10. The back-contact battery according to claim 1, characterized in that, The conductive film layer is provided with a third isolation region at the position corresponding to the side wall of the second groove.

11. A method for preparing a back-contact battery, characterized in that, The preparation method of the back contact battery includes: Step S10, sequentially forming a first semiconductor layer and a mask layer on the back side of the semiconductor substrate; Step S20, removing the first semiconductor layer and its corresponding mask layer in a first preset area on the back side obtained in step S10 to form a recessed area; Step S30, forming a textured surface at the bottom of the recessed area; Step S40, forming a second semiconductor layer on the back side obtained in step S30, and a second groove is formed on the outer surface of the second semiconductor layer corresponding to the recessed area; Step S50: Remove the second semiconductor layer and the corresponding mask layer within the second preset area on the back surface obtained in step S40 to form first grooves arranged at intervals with the second grooves, and an overlapping area is formed at the edges of the first semiconductor layer and the second semiconductor layer; Step S60: Form a conductive film layer on the back surface obtained in step S50; Step S70: Etch openings in the third preset area on the back surface obtained in step S60, and form two spaced-apart first isolation areas on the conductive film layer at the bottom of the second groove. Each of the first isolation areas includes at least one first isolation groove arranged at intervals in the X-axis direction.

12. The manufacturing method of the back contact battery according to claim 11, characterized in that, The step S40 includes: Form a passivation layer on the back surface obtained in step S30; Form an amorphous silicon layer on the passivation layer.

13. The preparation method of the back contact battery according to claim 12, wherein, The step S50 includes: Remove the passivation layer and the amorphous silicon layer at the first grooves; Perform laser scanning on a predetermined area of the amorphous silicon layer at the second grooves to form a crystallized microcrystalline silicon area.

14. The preparation method of the back contact battery according to claim 11, characterized in that, It further includes: Etch openings in the fourth preset area on the back surface obtained in step S60 to form a second isolation area on the conductive film layer at the top of the overlapping area.

15. The preparation method of the back-contact battery according to claim 11, wherein, It further includes: Etch openings in the fifth preset area on the back surface obtained in step S60 to form a third isolation area at the position of the side wall of the conductive film layer corresponding to the second groove.

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