Back film layer structure for improving efficiency of TOPCon battery and preparation method of back film layer structure

Abstract

The invention relates to the technical field of batteries, in particular to a back film layer structure for improving the efficiency of a TOPCon battery and a preparation method of the back film layer structure. Comprising an N-type silicon substrate, and an oxide layer, a first tunneling layer, a lightly doped layer and a second tunneling layer are sequentially arranged at the bottom of the N-type silicon substrate; the preparation method of the back film layer structure for improving the efficiency of the TOPCon battery comprises the following steps: S1, introducing ozone into an N-type silicon substrate sheet in an alkali polishing drying tank for drying, and depositing at the bottom of the N-type silicon substrate sheet to form an oxide layer; s2, forming a first tunneling layer on deposition of the oxide layer by using a tubular plasma deposition furnace; s3, depositing at the bottom of the first tunneling layer to form a lightly doped layer; s4, depositing at the bottom of the lightly doped layer to form a second tunneling layer; and S5, finally, depositing at the bottom of the second tunneling layer to form a heavily doped layer. According to the back film layer structure for improving the efficiency of the TOPCon battery, the conversion efficiency of the battery can be improved, and the quality of the battery is effectively ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of batteries, and particularly to a back film layer structure for improving the efficiency of TOPCon batteries and a preparation method thereof. Background Art

[0002] The tunneling oxide passivated contact solar cell is a new type of passivated contact solar cell. The front side of the TOPCon battery is a boron-diffused emitter, and an alumina / silicon nitride double passivation film is used; on the back side of the TOPCon battery, an ultrathin oxide layer is deposited to provide good interface passivation, and at the same time, different carrier tunneling barriers are provided. A layer of amorphous silicon is deposited on the oxide layer to increase the electron migration rate and at the same time inhibit the hole migration rate (forming band bending and heterojunction contact). In addition, the amorphous silicon is simultaneously doped with phosphorus and in contact with metal, playing the role of an electron transport bridge. The two together form a passivated contact structure, providing good interface passivation for the back side of the silicon wafer. Among them, the tunneling oxide layer is one of the core structures of the TOPCon battery. The tunneling oxide layer is generally an ultrathin oxide layer with a thickness of 1-2 nm (such as an ultrathin silicon dioxide layer), which can achieve the quantum tunneling effect, allowing electrons to pass through smoothly while preventing hole recombination. Currently, PECVD is generally used to prepare the tunneling oxide layer. An ultrathin oxide layer is deposited on the polished back side of the silicon wafer through PECVD to provide good interface passivation and at the same time provide a tunneling barrier for tunneling carriers.

[0003] In the patent document with the application number "CN202311520474.4" and the name "A Double-sided Tunneling Passivated Contact Solar Cell Structure and Its Preparation Method", it is recorded that "the structure includes a silicon substrate, and a front tunneling oxide layer, a first N-type doped polysilicon layer, an N-type doped silicon carbide layer, and a front antireflection layer or a transparent conductive oxide film provided in the front non-metallized area, and a front tunneling oxide layer, a first N-type doped polysilicon layer, an N-type doped silicon carbide layer, a second N-type doped polysilicon layer, a front antireflection layer or a transparent conductive oxide film, and a front electrode provided in the front metallized area, and an ohmic contact is formed. In the present invention, a tunneling contact structure is constructed in the front metallized area and non-metallized area of the battery, which can not only improve the front passivation effect, but also reduce the front parasitic absorption and improve the front optical utilization rate, thereby constructing a double-sided tunneling passivated contact battery structure with good passivation effect and high conversion efficiency, which is of great significance for the wide application of TOPCon batteries."

[0004] Although the battery wafers manufactured by the above patent document have a certain effect of improving the conversion efficiency, their conversion efficiency performance is relatively insufficient and still needs to be further improved. Based on this, the present invention provides a back film layer structure for improving the efficiency of TOPCon batteries and a preparation method thereof to solve the above-mentioned technical problems. Summary of the Invention

[0005] The object of the present invention is to provide a back surface film layer structure for improving the efficiency of TOPCon cells and a preparation method thereof. The provided back surface film layer structure for improving the efficiency of TOPCon cells can improve the conversion efficiency of the cells and effectively ensure its quality and quality.

[0006] To achieve the above object, the present invention provides the following technical solutions: The first aspect of the present invention: provides a back surface film layer structure for improving the efficiency of TOPCon cells, including an N-type silicon substrate, and an oxide layer, a first tunneling layer, a lightly doped layer, and a second tunneling layer are sequentially arranged at the bottom of the N-type silicon substrate.

[0007] The further setting of the present invention is: a heavily doped layer is arranged at the bottom of the second tunneling layer.

[0008] The further setting of the present invention is: the thickness of the oxide layer is 0.2 - 0.4 nm; the thickness of the first tunneling layer is 0.3 - 0.6 nm; the thickness of the lightly doped layer is 30 - 40 nm; the thickness of the second tunneling layer is 0.3 - 0.8 nm; the thickness of the heavily doped layer is 65 - 75 nm.

[0009] The second aspect of the present invention: also provides a preparation method of the above back surface film layer structure for improving the efficiency of TOPCon cells, including the following steps: S1. Pass ozone into the alkali polishing and drying tank for the N-type silicon substrate to dry it, and deposit an oxide layer at the bottom of the N-type silicon substrate; S2. Use a tube-type plasma deposition furnace to deposit a first tunneling layer at the bottom of the oxide layer; S3. Then deposit a lightly doped layer at the bottom of the first tunneling layer; S4. Deposit a second tunneling layer at the bottom of the lightly doped layer; S5. Finally, deposit a heavily doped layer at the bottom of the second tunneling layer.

[0010] The further setting of the present invention is: in the step S1, the preparation process of the N-type silicon substrate is as follows: Immerse the single-crystal silicon wafer in the immersion liquid at 70 °C in the texturing tank for 115 - 155 s, then take out the single-crystal silicon wafer and place it in an alkaline sodium hydroxide solution with a concentration of 0.5 - 1.5% for 360 - 480 s, and perform anisotropic etching to form a pyramid structure; wherein, the immersion liquid is composed of sodium hydroxide, hydrogen peroxide and pure water mixed according to a mass ratio of 1:6:340; Using a high-temperature tube diffusion furnace, after diffusing boron trichloride for 80 - 120 minutes, then introducing oxygen to form a P-type B-doped layer on the front surface of the single-crystalline silicon wafer at high temperature; Among them, the flow rate of the boron trichloride is 150 - 350 sccm, the diffusion temperature is 850 - 950 °C, the diffusion time is 25 - 35 minutes, the flow rate of the oxygen is 20000 - 30000 sccm, the temperature of the high temperature is 1000 - 1060 °C, and the high-temperature treatment time is 100 - 150 minutes; Etching the back surface of the single-crystalline silicon wafer with hydrofluoric acid with a concentration of 20 - 25% at room temperature, then cleaning it with sodium hydroxide with a concentration of 3 - 7% for 3 - 7 minutes at 60 - 70 °C, and then performing alkaline polishing.

[0011] A further setting of the present invention is that: in the step S1, the temperature of the alkaline polishing and drying tank for depositing and forming the oxide layer 200 is 80 - 100 °C, and the drying time is 500 - 700 s.

[0012] A further setting of the present invention is that: in the step S2, the flow rate of nitrous oxide for depositing and forming the first tunneling layer is 9000 - 13000 sccm, the deposition temperature is 400 - 500 °C, and the time is 100 - 120 s.

[0013] A further setting of the present invention is that: in the step S3, the flow rate of silane for depositing and forming the lightly doped layer is 2000 - 4000 sccm, the flow rate of phosphine is 260 - 310 sccm, the flow rate of hydrogen is 8000 - 12000 sccm, the deposition temperature is 400 - 500 °C, and the deposition time is 180 - 220 s.

[0014] A further setting of the present invention is that: in the step S4, the flow rate of nitrous oxide for depositing and forming the second tunneling layer is 9000 - 13000 sccm, the deposition temperature is 400 - 500 °C, and the deposition time is 70 - 90 s.

[0015] A further setting of the present invention is that: in the step S5, the flow rate of silane for depositing and forming the heavily doped layer is 2000 - 4000 sccm, the flow rate of phosphine is 760 - 860 sccm, the flow rate of hydrogen is 8000 - 12000 sccm, the deposition temperature is 400 - 500 °C, and the deposition time is 300 - 400 s.

[0016] Compared with the prior art, the beneficial effects of the present invention are: The back film layer structure for improving the efficiency of TOPCon cells provided by the present invention includes an N-type silicon substrate, and an oxide layer, a first tunneling layer, a lightly doped layer, a second tunneling layer, and a heavily doped layer sequentially provided at the bottom of the N-type silicon substrate. The provided back film layer structure for improving the efficiency of TOPCon cells can improve the cell conversion efficiency and effectively ensure its quality and quality. The provided back film layer structure for improving the efficiency of TOPCon cells and its preparation method have a broader market prospect and are more suitable for popularization. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic structural diagram of a back film layer structure for improving the efficiency of TOPCon cells.

[0018] Legend: 100, N-type silicon substrate; 200, oxide layer; 300, first tunneling layer; 400, lightly doped layer; 500, second tunneling layer; 600, heavily doped layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the protection scope of the present invention. Embodiment 1

[0020] As Figure 1 shown, this embodiment provides a back film layer structure for improving the efficiency of TOPCon cells, including an N-type silicon substrate 100, and an oxide layer 200, a first tunneling layer 300, a lightly doped layer 400, and a second tunneling layer 500 are sequentially provided at the bottom of the N-type silicon substrate 100.

[0021] In addition, a heavily doped layer 600 is provided at the bottom of the second tunneling layer 500.

[0022] In addition, this embodiment also provides a preparation method for the above-mentioned back film layer structure for improving the efficiency of TOPCon cells, including the following steps: S1. The N-type silicon substrate 100 is dried by introducing ozone into an alkali polishing and drying tank, and an oxide layer 200 is deposited on the bottom of the N-type silicon substrate 100.

[0023] Among them, the preparation process of the N-type silicon substrate 100 is as follows: The single crystal silicon wafer is immersed in the immersion liquid at 70°C in the texturing tank for 115 s, and then the single crystal silicon wafer is taken out and placed in a 0.5% alkaline sodium hydroxide solution for 360 s for anisotropic etching to form a pyramid structure; Among them, the immersion liquid is formed by mixing sodium hydroxide, hydrogen peroxide and pure water in a mass ratio of 1:6:340; Using a high-temperature tube diffusion furnace, after diffusing boron trichloride for 80 min, oxygen is then introduced to form a P-type B-doped layer on the front surface of the single-crystal silicon wafer at high temperature; Among them, the flow rate of boron trichloride is 150 sccm, the diffusion temperature is 850 °C, the diffusion time is 25 min, the flow rate of oxygen is 20000 sccm, the high-temperature is 1000 °C, and the high-temperature treatment time is 100 min; Etch the back surface of the single-crystal silicon wafer with 20% hydrofluoric acid at room temperature, then use 3% sodium hydroxide to clean for 3 min at 60 °C, and then perform alkali polishing.

[0024] In addition, the temperature of the alkali polishing drying tank for depositing the oxide layer 200 is 80 °C, and the drying time is 500 s.

[0025] S2. Use a tube plasma deposition furnace to deposit and form a first tunneling layer 300 at the bottom of the oxide layer 200.

[0026] Among them, the flow rate of nitrous oxide used for depositing and forming the first tunneling layer 300 is 9000 sccm, the deposition temperature is 400 °C, and the time is 100 s.

[0027] S3. Then deposit and form a lightly doped layer 400 at the bottom of the first tunneling layer 300.

[0028] Among them, the flow rate of silane used for depositing and forming the lightly doped layer 400 is 2000 sccm, the flow rate of phosphine is 260 sccm, the flow rate of hydrogen is 8000 sccm, the deposition temperature is 400 °C, and the deposition time is 180 s.

[0029] S4. Deposit and form a second tunneling layer 500 at the bottom of the lightly doped layer 400.

[0030] Among them, the flow rate of nitrous oxide used for depositing and forming the second tunneling layer 500 is 9000 sccm, the deposition temperature is 400 °C, and the deposition time is 70 s.

[0031] S5. Finally, deposit and form a heavily doped layer 600 at the bottom of the second tunneling layer 500.

[0032] Among them, the flow rate of silane used for depositing and forming the heavily doped layer 600 is 2000 sccm, the flow rate of phosphine is 760 sccm, the flow rate of hydrogen is 8000 sccm, the deposition temperature is 400 °C, and the deposition time is 300 - 400 s. Example 2

[0033] Such as Figure 1As shown in the figure, this embodiment provides a back film layer structure for improving the efficiency of TOPCon cells, including an N-type silicon substrate 100, and an oxide layer 200, a first tunneling layer 300, a lightly doped layer 400, and a second tunneling layer 500 are sequentially arranged at the bottom of the N-type silicon substrate 100.

[0034] In addition, a heavily doped layer 600 is arranged at the bottom of the second tunneling layer 500.

[0035] In addition, this embodiment also provides a preparation method for the above-mentioned back film layer structure for improving the efficiency of TOPCon cells, including the following steps: S1. The N-type silicon substrate 100 is dried by introducing ozone into an alkali polishing and drying tank, and an oxide layer 200 is deposited and formed at the bottom of the N-type silicon substrate 100.

[0036] Among them, the preparation process of the N-type silicon substrate 100 is as follows: The single-crystal silicon wafer is immersed in the immersion liquid at 70°C in the texturing tank for 115 s, and then the single-crystal silicon wafer is taken out and placed in a 0.5% alkaline sodium hydroxide solution for 360 s, and anisotropic etching is performed to form a pyramid structure; Among them, the immersion liquid is mixed by sodium hydroxide, hydrogen peroxide and pure water according to a mass ratio of 1:6:340; Using a high-temperature tube diffusion furnace, boron trichloride is diffused for 80 min, and then oxygen is introduced to form a P-type B-doped layer on the front surface of the single-crystal silicon wafer at high temperature. Among them, the flow rate of boron trichloride is 150 sccm, the diffusion temperature is 850°C, the diffusion time is 25 min, the flow rate of oxygen is 20000 sccm, the high-temperature temperature is 1000°C, and the high-temperature treatment time is 100 min; The back surface of the single-crystal silicon wafer is etched at room temperature with 20% hydrofluoric acid, and then it is cleaned with 3% sodium hydroxide at 60°C for 3 min, and then alkali polished.

[0037] In addition, the temperature of the alkali polishing and drying tank for depositing and forming the oxide layer 200 is 82°C, and the drying time is 510 s.

[0038] S2. Using a tube plasma deposition furnace, a first tunneling layer 300 is deposited and formed at the bottom of the oxide layer 200.

[0039] Among them, the flow rate of nitrous oxide used for depositing and forming the first tunneling layer 300 is 9100 sccm, the deposition temperature is 410°C, and the time is 110 s.

[0040] S3. Then a lightly doped layer 400 is deposited and formed at the bottom of the first tunneling layer 300.

[0041] Among them, the flow rate of silane used for depositing the lightly doped layer 400 is 2100 sccm, the flow rate of phosphine is 270 sccm, the flow rate of hydrogen is 8100 sccm, the deposition temperature is 410 °C, and the deposition time is 185 s.

[0042] S4. Deposit and form a second tunneling layer 500 at the bottom of the lightly doped layer 400.

[0043] Among them, the flow rate of nitrous oxide used for depositing the second tunneling layer 500 is 9100 sccm, the deposition temperature is 410 °C, and the deposition time is 72 s.

[0044] S5. Finally, deposit and form a heavily doped layer 600 at the bottom of the second tunneling layer 500.

[0045] Among them, the flow rate of silane used for depositing the heavily doped layer 600 is 2100 sccm, the flow rate of phosphine is 770 sccm, the flow rate of hydrogen is 8100 sccm, the deposition temperature is 410 °C, and the deposition time is 310 s. Example 3

[0046] As Figure 1 shown, this embodiment provides a back surface film layer structure for improving the efficiency of TOPCon cells, including an N-type silicon substrate 100, and an oxide layer 200, a first tunneling layer 300, a lightly doped layer 400, and a second tunneling layer 500 are sequentially arranged at the bottom of the N-type silicon substrate 100.

[0047] In addition, a heavily doped layer 600 is arranged at the bottom of the second tunneling layer 500.

[0048] In addition, this embodiment also provides a preparation method for the above-mentioned back surface film layer structure for improving the efficiency of TOPCon cells, including the following steps: S1. Pass ozone into the alkali polishing and drying tank to dry the N-type silicon substrate 100, and deposit and form an oxide layer 200 at the bottom of the N-type silicon substrate 100.

[0049] Among them, the preparation process of the N-type silicon substrate 100 is as follows: Immerse the single crystal silicon wafer in the immersion liquid at 70 °C in the texturing tank for 115 s, then take out the single crystal silicon wafer and place it in a 0.5% alkaline sodium hydroxide solution for 360 s to form a pyramid structure by anisotropic etching; Among them, the immersion liquid is composed of sodium hydroxide, hydrogen peroxide and pure water mixed in a mass ratio of 1:6:340; Using a high-temperature tube diffusion furnace, diffuse boron trichloride for 80 min, and then pass oxygen to form a P-type B-doped layer on the front surface of the single crystal silicon wafer at high temperature; Among them, the flow rate of boron trichloride is 150 sccm, the diffusion temperature is 850 °C, the diffusion time is 25 min, the flow rate of oxygen is 20000 sccm, the high-temperature temperature is 1000 °C, and the high-temperature treatment time is 100 min; Etch the back of the single-crystalline silicon wafer with hydrofluoric acid at a concentration of 20% at room temperature, then clean it with sodium hydroxide at a concentration of 3% for 3 min at 60 °C, and then perform alkaline polishing.

[0050] In addition, the temperature of the alkaline polishing and drying tank for depositing the oxide layer 200 is 85 °C, and the drying time is 550 s.

[0051] S2. Use a tube-type plasma deposition furnace to deposit and form a first tunneling layer 300 at the bottom of the oxide layer 200.

[0052] Among them, the flow rate of nitrous oxide used for depositing and forming the first tunneling layer 300 is 10000 sccm, the deposition temperature is 420 °C, and the time is 110 s.

[0053] S3. Then deposit and form a lightly doped layer 400 at the bottom of the first tunneling layer 300.

[0054] Among them, the flow rate of silane used for depositing and forming the lightly doped layer 400 is 2400 sccm, the flow rate of phosphine is 280 sccm, the flow rate of hydrogen is 10000 sccm, the deposition temperature is 420 °C, and the deposition time is 190 s.

[0055] S4. Deposit and form a second tunneling layer 500 at the bottom of the lightly doped layer 400.

[0056] Among them, the flow rate of nitrous oxide used for depositing and forming the second tunneling layer 500 is 10000 sccm, the deposition temperature is 420 °C, and the deposition time is 74 s.

[0057] S5. Finally, deposit and form a heavily doped layer 600 at the bottom of the second tunneling layer 500.

[0058] Among them, the flow rate of silane used for depositing and forming the heavily doped layer 600 is 2400 sccm, the flow rate of phosphine is 780 sccm, the flow rate of hydrogen is 9000 sccm, the deposition temperature is 420 °C, and the deposition time is 320 s. Example 4

[0059] As Figure 1 shown, this embodiment provides a back film layer structure for improving the efficiency of TOPCon cells, including an N-type silicon substrate 100, and an oxide layer 200, a first tunneling layer 300, a lightly doped layer 400, and a second tunneling layer 500 are sequentially arranged at the bottom of the N-type silicon substrate 100.

[0060] In addition, a heavily doped layer 600 is provided at the bottom of the second tunneling layer 500.

[0061] In addition, this embodiment also provides a preparation method for the back film layer structure for improving the efficiency of TOPCon cells, including the following steps: S1. Pass ozone into the alkali polishing and drying tank for the N-type silicon substrate 100 to dry it, and deposit an oxide layer 200 on the bottom of the N-type silicon substrate 100.

[0062] Among them, the preparation process of the N-type silicon substrate 100 is as follows: Immerse the single-crystal silicon wafer in the etching solution at 70 °C in the texturing tank for 115 s, then take out the single-crystal silicon wafer and place it in a 0.5% alkaline sodium hydroxide solution for 360 s for anisotropic etching to form a pyramid structure; Among them, the etching solution is composed of sodium hydroxide, hydrogen peroxide and pure water mixed in a mass ratio of 1:6:340; Using a high-temperature tube diffusion furnace, after diffusing boron trichloride for 80 min, then pass oxygen to form a P-type B-doped layer on the front surface of the single-crystal silicon wafer at high temperature. Among them, the flow rate of boron trichloride is 150 sccm, the diffusion temperature is 850 °C, the diffusion time is 25 min, the flow rate of oxygen is 20000 sccm, the high-temperature is 1000 °C, and the high-temperature treatment time is 100 min; Etch the back surface of the single-crystal silicon wafer with 20% hydrofluoric acid at room temperature, then use 3% sodium hydroxide to clean it for 3 min at 60 °C, and then perform alkali polishing.

[0063] In addition, the temperature of the alkali polishing and drying tank for depositing the oxide layer 200 is 90 °C, and the drying time is 600 s.

[0064] S2. Use a tube plasma deposition furnace to deposit a first tunneling layer 300 on the bottom of the oxide layer 200.

[0065] Among them, the flow rate of nitrous oxide for depositing the first tunneling layer 300 is 11000 sccm, the deposition temperature is 440 °C, and the time is 110 s.

[0066] S3. Then deposit a lightly doped layer 400 on the bottom of the first tunneling layer 300.

[0067] Among them, the flow rate of silane for depositing the lightly doped layer 400 is 3000 sccm, the flow rate of phosphine is 290 sccm, the flow rate of hydrogen is 10000 sccm, the deposition temperature is 440 °C, and the deposition time is 200 s.

[0068] S4. Deposit a second tunneling layer 500 on the bottom of the lightly doped layer 400.

[0069] Among them, the flow rate of nitrous oxide used for depositing the second tunneling layer 500 is 11000 sccm, the deposition temperature is 450 °C, and the deposition time is 80 s.

[0070] S5. Finally, a heavily doped layer 600 is deposited on the bottom of the second tunneling layer 500.

[0071] Among them, the flow rate of silane used for depositing the heavily doped layer 600 is 3100 sccm, the flow rate of phosphine is 800 sccm, the flow rate of hydrogen is 11000 sccm, the deposition temperature is 450 °C, and the deposition time is 350 s. Example Five

[0072] As Figure 1 shown, this example provides a back film layer structure for improving the efficiency of TOPCon cells, including an N-type silicon substrate 100, and an oxide layer 200, a first tunneling layer 300, a lightly doped layer 400, and a second tunneling layer 500 are sequentially arranged at the bottom of the N-type silicon substrate 100.

[0073] In addition, a heavily doped layer 600 is arranged at the bottom of the second tunneling layer 500.

[0074] In addition, this example also provides a preparation method for the above-mentioned back film layer structure for improving the efficiency of TOPCon cells, including the following steps: S1. The N-type silicon substrate 100 is dried by introducing ozone into an alkali polishing and drying tank, and an oxide layer 200 is deposited on the bottom of the N-type silicon substrate 100.

[0075] Among them, the preparation process of the N-type silicon substrate 100 is as follows: The single crystal silicon wafer is immersed in the immersion liquid at 70 °C in the texturing tank for 115 s, and then the single crystal silicon wafer is taken out and placed in a 0.5% alkaline sodium hydroxide solution for 360 s, and anisotropic etching is performed to form a pyramid structure; Among them, the immersion liquid is composed of sodium hydroxide, hydrogen peroxide and pure water mixed in a mass ratio of 1:6:340; Using a high-temperature tube diffusion furnace, boron trichloride is diffused for 80 min, and then oxygen is introduced to form a P-type B-doped layer on the front surface of the single crystal silicon wafer at high temperature; Among them, the flow rate of boron trichloride is 150 sccm, the diffusion temperature is 850 °C, the diffusion time is 25 min, the flow rate of oxygen is 20000 sccm, the high temperature is 1000 °C, and the high temperature treatment time is 100 min; The back surface of the single crystal silicon wafer is etched at room temperature with 20% hydrofluoric acid, and then it is cleaned with 3% sodium hydroxide at 60 °C for 3 min, and then alkali polished.

[0076] In addition, the temperature of the alkali polishing and drying tank for depositing the oxide layer 200 is 92 °C, and the drying time is 610 s.

[0077] S2. Use a tubular plasma deposition furnace to deposit and form a first tunneling layer 300 at the bottom of the oxide layer 200.

[0078] Among them, the flow rate of nitrous oxide used for depositing and forming the first tunneling layer 300 is 11500 sccm, the deposition temperature is 460 °C, and the time is 110 s.

[0079] S3. Then deposit and form a lightly doped layer 400 at the bottom of the first tunneling layer 300.

[0080] Among them, the flow rate of silane used for depositing and forming the lightly doped layer 400 is 3100 sccm, the flow rate of phosphine is 260 sccm, the flow rate of hydrogen is 8000 sccm, the deposition temperature is 400 °C, and the deposition time is 180 s.

[0081] S4. Deposit and form a second tunneling layer 500 at the bottom of the lightly doped layer 400.

[0082] Among them, the flow rate of nitrous oxide used for depositing and forming the second tunneling layer 500 is 12000 sccm, the deposition temperature is 400 °C, and the deposition time is 70 s.

[0083] S5. Finally, deposit and form a heavily doped layer 600 at the bottom of the second tunneling layer 500.

[0084] Among them, the flow rate of silane used for depositing and forming the heavily doped layer 600 is 3100 sccm, the flow rate of phosphine is 770 sccm, the flow rate of hydrogen is 11200 sccm, the deposition temperature is 450 °C, and the deposition time is 350 s. Example Six

[0085] As Figure 1 shown, this embodiment provides a back film layer structure for improving the efficiency of TOPCon cells, including an N-type silicon substrate 100. An oxide layer 200, a first tunneling layer 300, a lightly doped layer 400, and a second tunneling layer 500 are sequentially arranged at the bottom of the N-type silicon substrate 100.

[0086] In addition, a heavily doped layer 600 is arranged at the bottom of the second tunneling layer 500.

[0087] In addition, this embodiment also provides a preparation method for the above-mentioned back film layer structure for improving the efficiency of TOPCon cells, including the following steps: S1. Pass ozone into the alkali polishing and drying tank for the N-type silicon substrate 100 for drying, and deposit and form an oxide layer 200 at the bottom of the N-type silicon substrate 100.

[0088] Among them, the preparation process of the N-type silicon substrate 100 is as follows: Immerse the single-crystal silicon wafer in the etching solution at 70 °C in the texturing tank for 115 s, and then take out the single-crystal silicon wafer and place it in an alkaline sodium hydroxide solution with a concentration of 0.5% for 360 s to form a pyramid structure by anisotropic etching; Among them, the etching solution is composed of sodium hydroxide, hydrogen peroxide and pure water mixed in a mass ratio of 1:6:340; Using a high-temperature tube diffusion furnace, after boron trichloride is diffused for 80 min, then oxygen is introduced to form a P-type B doping layer on the front surface of the single-crystal silicon wafer at high temperature; Among them, the flow rate of boron trichloride is 150 sccm, the diffusion temperature is 850 °C, the diffusion time is 25 min, the flow rate of oxygen is 20000 sccm, the high-temperature is 1000 °C, and the high-temperature treatment time is 100 min; Etch the back surface of the single-crystal silicon wafer at room temperature with hydrofluoric acid with a concentration of 20%, then use sodium hydroxide with a concentration of 3% to clean for 3 min at 60 °C, and then perform alkali polishing.

[0089] In addition, the temperature of the alkali polishing and drying tank for depositing the oxide layer 200 is 95 °C, and the drying time is 650 s.

[0090] S2. Use a tube plasma deposition furnace to deposit and form a first tunneling layer 300 at the bottom of the oxide layer 200.

[0091] Among them, the flow rate of nitrous oxide used for depositing the first tunneling layer 300 is 13500 sccm, the deposition temperature is 470 °C, and the time is 105 s.

[0092] S3. Then deposit and form a lightly doped layer 400 at the bottom of the first tunneling layer 300.

[0093] Among them, the flow rate of silane used for depositing the lightly doped layer 400 is 3400 sccm, the flow rate of phosphine is 300 sccm, the flow rate of hydrogen is 11000 sccm, the deposition temperature is 470 °C, and the deposition time is 210 s.

[0094] S4. Deposit and form a second tunneling layer 500 at the bottom of the lightly doped layer 400.

[0095] Among them, the flow rate of nitrous oxide used for depositing the second tunneling layer 500 is 12500 sccm, the deposition temperature is 470 °C, and the deposition time is 82 s.

[0096] S5. Finally, deposit and form a heavily doped layer 600 at the bottom of the second tunneling layer 500.

[0097] Among them, the flow rate of silane used for depositing the heavily doped layer 600 is 3300 sccm, the flow rate of phosphine is 800 sccm, the flow rate of hydrogen is 11000 sccm, the deposition temperature is 470 °C, and the deposition time is 370 s. Example Seven

[0098] As Figure 1 shown, this embodiment provides a back film layer structure for improving the efficiency of TOPCon cells, including an N-type silicon substrate 100, and an oxide layer 200, a first tunneling layer 300, a lightly doped layer 400, and a second tunneling layer 500 are sequentially arranged at the bottom of the N-type silicon substrate 100.

[0099] In addition, a heavily doped layer 600 is arranged at the bottom of the second tunneling layer 500.

[0100] In addition, this embodiment also provides a preparation method for the above-mentioned back film layer structure for improving the efficiency of TOPCon cells, including the following steps: S1. The N-type silicon substrate 100 is dried by introducing ozone into an alkali polishing and drying tank, and an oxide layer 200 is deposited and formed at the bottom of the N-type silicon substrate 100.

[0101] Among them, the preparation process of the N-type silicon substrate 100 is as follows: The single crystal silicon wafer is immersed in the immersion liquid at 70 °C in the texturing tank for 115 s, and then the single crystal silicon wafer is taken out and placed in a 0.5% alkaline sodium hydroxide solution for 360 s for anisotropic etching to form a pyramid structure; Among them, the immersion liquid is composed of sodium hydroxide, hydrogen peroxide and pure water mixed in a mass ratio of 1:6:340; Using a high-temperature tube diffusion furnace, boron trichloride is diffused for 80 min, and then oxygen is introduced to form a P-type B-doped layer on the front surface of the single crystal silicon wafer at high temperature. Among them, the flow rate of boron trichloride is 150 sccm, the diffusion temperature is 850 °C, the diffusion time is 25 min, the flow rate of oxygen is 20000 sccm, the high temperature is 1000 °C, and the high temperature treatment time is 100 min; The back surface of the single crystal silicon wafer is etched at room temperature with 20% hydrofluoric acid, and then it is cleaned with 3% sodium hydroxide at 60 °C for 3 min, and then alkali polished.

[0102] In addition, the temperature of the alkali polishing and drying tank used for depositing and forming the oxide layer 200 is 98 °C, and the drying time is 660 s.

[0103] S2. Using a tube plasma deposition furnace, a first tunneling layer 300 is deposited and formed at the bottom of the oxide layer 200.

[0104] Among them, the flow rate of nitrous oxide used for depositing the first tunneling layer 300 is 12,800 sccm, the deposition temperature is 490 °C, and the time is 118 s.

[0105] S3. Then, a lightly doped layer 400 is deposited and formed at the bottom of the first tunneling layer 300.

[0106] Among them, the flow rate of silane used for depositing the lightly doped layer 400 is 3,800 sccm, the flow rate of phosphine is 260 - 310 sccm, the flow rate of hydrogen is 11,500 sccm, the deposition temperature is 490 °C, and the deposition time is 210 s.

[0107] S4. A second tunneling layer 500 is deposited and formed at the bottom of the lightly doped layer 400.

[0108] Among them, the flow rate of nitrous oxide used for depositing the second tunneling layer 500 is 12,800 sccm, the deposition temperature is 490 °C, and the deposition time is 80 s.

[0109] S5. Finally, a heavily doped layer 600 is deposited and formed at the bottom of the second tunneling layer 500.

[0110] Among them, the flow rate of silane used for depositing the heavily doped layer 600 is 3,800 sccm, the flow rate of phosphine is 830 sccm, the flow rate of hydrogen is 11,500 sccm, the deposition temperature is 490 °C, and the deposition time is 390 s. Example Eight

[0111] As Figure 1 shown, this embodiment provides a back surface film layer structure for improving the efficiency of TOPCon cells, including an N-type silicon substrate 100, and an oxide layer 200, a first tunneling layer 300, a lightly doped layer 400, and a second tunneling layer 500 are sequentially arranged at the bottom of the N-type silicon substrate 100.

[0112] In addition, a heavily doped layer 600 is arranged at the bottom of the second tunneling layer 500.

[0113] In addition, this embodiment also provides a preparation method for the above-mentioned back surface film layer structure for improving the efficiency of TOPCon cells, including the following steps: S1. The N-type silicon substrate 100 is dried by introducing ozone into an alkali polishing and drying tank, and an oxide layer 200 is deposited and formed at the bottom of the N-type silicon substrate 100.

[0114] Among them, the preparation process of the N-type silicon substrate 100 is as follows: The single crystal silicon wafer is immersed in the immersion liquid at 70 °C in a texturing tank for 115 s, and then the single crystal silicon wafer is taken out and placed in a 0.5% alkaline sodium hydroxide solution for 360 s, and anisotropic etching is performed to form a pyramid structure; Among them, the soaking solution is formed by mixing sodium hydroxide, hydrogen peroxide and pure water in a mass ratio of 1:6:340; Using a high-temperature tube diffusion furnace, boron trichloride is diffused for 80 minutes, and then oxygen is introduced to form a P-type B-doped layer on the front surface of the single-crystal silicon wafer at high temperature; Among them, the flow rate of boron trichloride is 150 sccm, the diffusion temperature is 850 °C, the diffusion time is 25 minutes, the flow rate of oxygen is 20000 sccm, the high-temperature is 1000 °C, and the high-temperature treatment time is 100 minutes; Etch the back surface of the single-crystal silicon wafer with 20% hydrofluoric acid at room temperature, then clean it with 3% sodium hydroxide at 60 °C for 3 minutes, and then perform alkaline polishing.

[0115] In addition, the temperature of the alkaline polishing and drying tank for depositing the oxide layer 200 is 100 °C, and the drying time is 700 s.

[0116] S2. Use a tube plasma deposition furnace to deposit a first tunneling layer 300 at the bottom of the oxide layer 200.

[0117] Among them, the flow rate of nitrous oxide used for depositing the first tunneling layer 300 is 13000 sccm, the deposition temperature is 500 °C, and the time is 120 s.

[0118] S3. Then deposit a lightly doped layer 400 at the bottom of the first tunneling layer 300.

[0119] Among them, the flow rate of silane used for depositing the lightly doped layer 400 is 4000 sccm, the flow rate of phosphine is 310 sccm, the flow rate of hydrogen is 12000 sccm, the deposition temperature is 500 °C, and the deposition time is 220 s.

[0120] S4. Deposit a second tunneling layer 500 at the bottom of the lightly doped layer 400.

[0121] Among them, the flow rate of nitrous oxide used for depositing the second tunneling layer 500 is 13000 sccm, the deposition temperature is 500 °C, and the deposition time is 90 s.

[0122] S5. Finally, deposit a heavily doped layer 600 at the bottom of the second tunneling layer 500.

[0123] Among them, the flow rate of silane used for depositing the heavily doped layer 600 is 4000 sccm, the flow rate of phosphine is 860 sccm, the flow rate of hydrogen is 12000 sccm, the deposition temperature is 500 °C, and the deposition time is 400 s.

[0124] Performance test: After completing the back film layer structure in Examples 1 to 8, continue to prepare the battery chip by the following steps: Using a high-temperature annealing furnace, anneal the obtained back film layer structure at an annealing temperature of 880 °C for 20 minutes; Etch the front side at room temperature using hydrofluoric acid with a concentration of 30%, and then use an alkaline solution with a NaOH concentration of 5% and an acid solution with a hydrofluoric acid concentration of 30% to remove the residue on the front side; Using ALD (atomic layer deposition method) at a temperature of 250 °C, react trimethylaluminum TMA (flow rate of 3000) and water (flow rate of 2500 sccm) to deposit Al2O3 on the front side for 10 minutes; then use PECVD to deposit a SiNx antireflection film, with reaction gases silane (flow rate of 2500 sccm), nitrous oxide (flow rate of 9000 sccm), and ammonia (flow rate of 10000 sccm), reaction time of 20 minutes, and refractive index of 2.06%; Use PECVD to deposit a SiNx composite antireflection film, with reaction gases silane (flow rate of 2500 sccm), nitrous oxide (flow rate of 9000 sccm), and ammonia (flow rate of 10000 sccm), reaction time of 20 minutes, and reflectivity of 2.09; Then, through screen printing sintering, light decay recovery, and LECO sintering in sequence, obtain the solar cell wafers, Among them, screen printing sintering: use screen printing of silver (Ag) / silver-aluminum (Ag / Al) metal electrodes to collect current; dry the slurry on the silicon wafer, burn out the organic components of the slurry, and make the slurry and the silicon wafer form a good ohmic contact.

[0125] Light decay recovery is to activate the H in the SiNx thin film by continuous illumination at a high temperature of 800 °C for 2 minutes to reduce the H-X recombination in the silicon wafer body.

[0126] LECO sintering is to use high-intensity laser irradiation on the solar cell wafer to excite charge carriers, and at the same time apply a deflection voltage of 10 V or above, thereby generating a local current of several amperes, and sintering occurs at the corresponding location, triggering the mutual diffusion of the silver paste and silicon, which will significantly reduce the contact resistance between the metal and the semiconductor.

[0127] Obtain the solar cell wafer samples of Examples 1 to 8 respectively.

[0128] Then, use the following method to replace the preparation method of the back film layer structure provided in Example 1, specifically as follows: Use PECVD (plasma-enhanced chemical vapor deposition) method to deposit a SiO2 tunneling oxide layer with a thickness of 2 nm on the back of the N-type silicon substrate wafer at a temperature of 450 °C, with a nitrous oxide content of 12000 sccm and a deposition time of 2 minutes; then mix silane (flow rate of 5000 sccm), nitrous oxide (flow rate of 12000 sccm), and phosphine (flow rate of 4000 sccm), and deposit the mixed gas on the surface of the SiO2 tunneling oxide layer for 10 minutes.

[0129] Then, the above method was adopted to prepare solar cells, which were used as comparative examples.

[0130] The relevant performances of the solar cells provided in Examples 1-8 and the comparative examples were tested respectively.

[0131] The conversion efficiency of each group of solar cells was detected, and the obtained test data were recorded in Table 1 below: Table 1 Test results of conversion efficiency of each group

[0132] Group Conversion Efficiency (%) Example 1 Group 25.912 Example 2 Group 26.162 Example 3 Group 25.972 Example 4 Group 26.004 Example 5 Group 26.061 Example 6 Group 26.251 Example 7 Group 25.929 Example 8 Group 26.249 Control Group 25.898

[0133] By comparing and analyzing the relevant data in Table 1, it can be seen that the back film layer structure for improving the efficiency of TOPCon solar cells provided by the present invention can improve the conversion efficiency of solar cells and effectively ensure its quality and quality. This shows that the back film layer structure for improving the efficiency of TOPCon solar cells provided by the present invention and its preparation method have a broader market prospect and are more suitable for popularization.

[0134] In the description of this specification, the descriptions referring to the terms "one embodiment", "example", "specific example", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0135] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and utilize the present invention well. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A back film layer structure for improving the efficiency of TOPCon cells, characterized in that, It includes an N-type silicon substrate (100), and an oxide layer (200), a first tunneling layer (300), a lightly doped layer (400) and a second tunneling layer (500) are sequentially arranged at the bottom of the N-type silicon substrate (100).

2. The back film layer structure for improving the efficiency of TOPCon cells according to claim 1, characterized in that, A heavily doped layer (600) is arranged at the bottom of the second tunneling layer (500).

3. A preparation method for a back film layer structure for improving the efficiency of TOPCon cells, characterized in that, It includes the following steps: S1. Pass ozone into the alkali polishing and drying tank for the N-type silicon substrate (100) to dry it, and deposit an oxide layer (200) at the bottom of the N-type silicon substrate (100). S2. Use a tube-type plasma deposition furnace to deposit a first tunneling layer (300) at the bottom of the oxide layer (200). S3. Then deposit a lightly doped layer (400) at the bottom of the first tunneling layer (300). S4. Deposit a second tunneling layer (500) at the bottom of the lightly doped layer (400). S5. Finally, deposit a heavily doped layer (600) at the bottom of the second tunneling layer (500).

4. The preparation method of a back film layer structure for improving the efficiency of TOPCon cells according to claim 3, characterized in that, In the step S1, the temperature of the alkali polishing and drying tank for depositing the oxide layer (200) is 80 - 100 °C, and the drying time is 500 - 700 s.

5. The preparation method of a back film layer structure for improving the efficiency of TOPCon cells according to claim 3, characterized in that, In the step S2, the nitrous oxide flow rate for depositing the first tunneling layer (300) is 9000 - 13000 sccm, the deposition temperature is 400 - 500 °C, and the time is 100 - 120 s.

6. The preparation method of a back film layer structure for improving the efficiency of TOPCon cells according to claim 3, characterized in that, In the step S3, the silane flow rate for depositing the lightly doped layer (400) is 2000 - 4000 sccm, the phosphine flow rate is 260 - 310 sccm, the hydrogen flow rate is 8000 - 12000 sccm, the deposition temperature is 400 - 500 °C, and the deposition time is 180 - 220 s.

7. The preparation method of a back film layer structure for improving the efficiency of TOPCon cells according to claim 3, characterized in that, In the step S4, the nitrous oxide flow rate for depositing the second tunneling layer (500) is 9000 - 13000 sccm, the deposition temperature is 400 - 500 °C, and the deposition time is 70 - 90 s.

8. The preparation method of a back film layer structure for improving the efficiency of TOPCon cells according to claim 3, characterized in that, In the step S5, the silane flow rate for depositing the heavily doped layer (600) is 2000 - 4000 sccm, the phosphine flow rate is 760 - 860 sccm, the hydrogen flow rate is 8000 - 12000 sccm, the deposition temperature is 400 - 500 °C, and the deposition time is 300 - 400 s.

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