Laminated battery and manufacturing method thereof

Abstract

The embodiment of the invention relates to the photovoltaic field, and provides a laminated cell and a manufacturing method thereof, and the laminated cell comprises a crystalline silicon bottom cell which comprises a substrate and a doped conductive layer located on the surface of the substrate; the composite layer is located on the surface of the crystalline silicon bottom battery, the composite layer is made of metal oxide, and the part, close to the composite layer, of the doped conductive layer is doped with metal elements which are the same as the metal elements in the composite layer; and the perovskite top cell is located on the surface, far away from the crystalline silicon bottom cell, of the composite layer, and the photoelectric conversion efficiency of the laminated cell can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of photovoltaics, and particularly to a tandem cell and a manufacturing method thereof. Background Art

[0002] Currently, with the gradual depletion of fossil energy, solar cells, as a new energy alternative, are being used more and more widely. A solar cell is a device that converts the light energy of the sun into electrical energy. The solar cell utilizes the photovoltaic effect to generate carriers, and then uses electrodes to extract the carriers, thereby facilitating the effective utilization of electrical energy.

[0003] Current solar cells mainly include single-layer cells, such as IBC cells (Interdigitated Back Contact), TOPCON (Tunnel Oxide Passivated Contact) cells, PERC cells (Passivated emitter and real cell), HIT / HJT cells (Heterojunction Technology), and perovskite cells. By setting different film layers and functional limitations, optical losses are reduced and the recombination of photo-generated carriers on and in the silicon substrate surface is reduced to improve the photoelectric conversion efficiency of the solar cell.

[0004] It has been found in research that perovskite cells have the property of being semi-transparent, which means that photons can pass through the perovskite cell sheet. That is to say, we can further add a photovoltaic cell sheet under the perovskite cell, so as to break through the limit of the single-junction efficiency by the way of "stacking", namely the tandem cell. The principle of the tandem cell is that the wide-bandgap top cell absorbs high-energy photons, and the narrow-bandgap bottom cell improves the utilization rate of photons. The cooperation between the two can break through the theoretical efficiency limit of the single-junction cell and open the ceiling of the conversion efficiency. However, it is necessary to further improve the photoelectric conversion efficiency of the tandem cell at present. Summary of the Invention

[0005] Embodiments of the present disclosure provide a tandem cell and a manufacturing method thereof, which can at least improve the photoelectric conversion efficiency of the tandem cell.

[0006] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a tandem cell, comprising: a crystalline silicon bottom cell, the crystalline silicon bottom cell comprising a substrate and a doped conductive layer on the surface of the substrate; a composite layer, the composite layer being on the surface of the crystalline silicon bottom cell, the material of the composite layer being a metal oxide, wherein a portion of the doped conductive layer close to the composite layer is doped with the same metal element as the metal element in the composite layer; and a perovskite top cell, the perovskite top cell being on the surface of the composite layer away from the crystalline silicon bottom cell.

[0007] In some embodiments, the thickness of the doped conductive layer doped with the metal element is 10 nm to 20 nm.

[0008] In some embodiments, in the direction of the composite layer pointing to the doped conductive layer, the concentration of the metal element in the doped conductive layer gradually decreases.

[0009] In some embodiments, the material of the composite layer is indium tin oxide.

[0010] In some embodiments, the ratio of the doping concentration of tin ions to the doping concentration of indium ions in the doped conductive layer is 7 to 13.

[0011] In some embodiments, the ratio of the doping concentration of tin to the doping concentration of indium in the composite layer is 4 to 19.

[0012] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a method for manufacturing a tandem cell, comprising: providing a crystalline silicon bottom cell, the crystalline silicon bottom cell comprising a substrate and a doped conductive layer on the surface of the substrate; forming a composite layer, the composite layer being on the surface of the crystalline silicon bottom cell, the material of the composite layer being a metal oxide, wherein during the formation of the composite layer, controlling the diffusion of the metal element of the composite layer into the doped conductive layer; and forming a perovskite top cell, the perovskite top cell being on the surface of the composite layer away from the crystalline silicon bottom cell.

[0013] In some embodiments, the method for forming the composite layer comprises: constructing a magnetic field environment, the crystalline silicon bottom cell being within the magnetic field environment; performing a magnetron sputtering process, the magnetron sputtering process comprising: providing a target, bombarding the target with a plasma, and providing an oxidation gas to bombard the metal element contained in the target onto the surface of the doped conductive layer to form the composite layer; and during the formation of the composite layer, controlling the doping of the metal element into the doped conductive layer.

[0014] In some embodiments, the magnetic field strength of the magnetic field environment is 0.5T to 1.5T, and the process parameters of the magnetron sputtering include: the sputtering power is 0.5KW to 1KW, and the temperature environment is 350°C to 450°C.

[0015] In some embodiments, during the formation of the composite layer, it further includes: detecting the thickness of the composite layer; when the thickness of the formed composite layer is less than 5nm, the magnetic field strength is the first preset magnetic field strength; when the thickness of the formed composite layer is 5nm to 20nm, the magnetic field strength is the second preset magnetic field strength; when the thickness of the formed composite layer is greater than 20nm, the magnetic field strength is the third preset magnetic field strength, where the first preset magnetic field strength is less than the second preset magnetic field strength and the second preset magnetic field strength is less than the third preset magnetic field strength.

[0016] In some embodiments, the method for forming the composite layer includes: providing a laser, and the laser irradiates the surface of the doped conductive layer; performing a magnetron sputtering process, and the magnetron sputtering process includes: providing a target, bombarding the target with plasma, and providing an oxidation gas to bombard the metal elements contained in the target onto the surface of the doped conductive layer irradiated by the laser to form the composite layer; during the formation of the composite layer, controlling the doping of the metal elements into the doped conductive layer.

[0017] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: on the one hand, by setting the part of the doped conductive layer close to the composite layer to be doped with the same metal elements as those in the composite layer, the interface difference between the doped conductive layer and the composite layer can be reduced, and the reliability of the contact between the doped conductive layer and the composite layer can be improved. At the same time, the part of the doped conductive layer close to the composite layer is doped with the same metal elements as those in the composite layer, reducing the interface pores of the doped conductive layer, realizing the passivation of part of the doped conductive layer, and thus improving the photoelectric conversion efficiency of the stacked battery. Description of the Drawings

[0018] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments unless otherwise stated. The figures in the drawings do not constitute a proportional limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the conventional technology, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a schematic structural diagram of a stacked battery provided by an embodiment of the present disclosure; Figure 2Flow chart of a manufacturing method of a stacked cell provided by an embodiment of the present disclosure; Figure 3 Schematic structural diagram of a crystalline silicon bottom cell provided by an embodiment of the present disclosure; Figure 4 Schematic structural diagram of a composite layer and a perovskite top cell formed on the crystalline silicon bottom cell provided by an embodiment of the present disclosure.

[0020] Explanation of reference numerals: 100, crystalline silicon bottom cell; 110, substrate; 120, doped conductive layer; 101, composite layer; 102, perovskite top cell; 130, tunneling layer; 140, emitter; 150, first passivation layer; 160, first surface; 170, second surface; 112, first transport layer; 122, perovskite substrate; 132, second passivation layer; 142, second transport layer; 152, third transport layer; 162, transparent conductive layer; 103, back electrode; 104, front electrode. Detailed implementation manners

[0021] As can be seen from the background art, it is necessary to improve the photoelectric conversion efficiency of stacked cells at present.

[0022] The embodiments of the present disclosure provide a stacked cell and a manufacturing method thereof. On the one hand, a part of the doped conductive layer close to the composite layer is doped with the same metal element as the metal element in the composite layer, which can reduce the interface difference between the doped conductive layer and the composite layer, improve the reliability of the contact between the doped conductive layer and the composite layer. At the same time, a part of the doped conductive layer close to the composite layer is doped with the same metal element as the metal element in the composite layer, reducing the interface pores of the doped conductive layer, realizing the passivation of part of the doped conductive layer, thereby improving the photoelectric conversion efficiency of the stacked cell.

[0023] In the description of the embodiments of the present disclosure, technical terms such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of the present disclosure, "a plurality" means more than two, unless otherwise clearly and specifically defined.

[0024] Referring to "embodiments" herein means that specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present disclosure. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0025] In the description of the embodiments of the present disclosure, the term "and / or" is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can mean: there is A, there is both A and B, and there is B, these three situations. Additionally, in this text, the character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0026] In the description of the embodiments of the present disclosure, the term "plural" refers to two or more (including two). Similarly, "multiple groups" refers to two or more groups (including two groups), and "multiple pieces" refers to two or more pieces (including two pieces).

[0027] In the description of the embodiments of the present disclosure, for technical terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the embodiments of the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the embodiments of the present disclosure.

[0028] In the description of the embodiments of the present disclosure, unless otherwise clearly specified and limited, technical terms such as "install", "connect", "join", "fix", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0029] In the corresponding drawings of the embodiments of the present disclosure, for better understanding and convenience of description, the thickness and area of the layer are enlarged. When describing a component (such as a layer, a film, a region, or a substrate) on another component or on the surface of another component, the component can be "directly" on the surface of the other component, or there can be a third component between the two components. On the contrary, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. Additionally, when describing a component "substantially" formed on another component, it means that the component is not formed on the entire surface (or the front surface) of the other component, nor on a partial edge of the entire surface.

[0030] In the description of the embodiments of the present disclosure, when a certain component "includes" another component, unless otherwise specified, other components are not excluded, and other components may further be included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it may be "directly on" the other component (i.e., located on the surface of the other component with no other components therebetween), or there may be other components therebetween. In addition, when a layer, film, region, plate, etc. component is "directly located on" another component, or when a layer, film, region, plate, etc. component is located on the surface of another component, it means that no other components are located therebetween.

[0031] The terms used in the description of the various embodiments herein are only for describing specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is also intended to include the plural form unless the context clearly indicates otherwise. Among them, the component includes components such as a layer, film, region, or plate.

[0032] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are presented for the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed by the present disclosure can still be implemented.

[0033] Reference Figure 1 , Figure 1 is a schematic structural diagram of a stacked battery provided for an embodiment of the present disclosure.

[0034] In some embodiments, the stacked battery may include: a crystalline silicon bottom cell 100, the crystalline silicon bottom cell 100 including a substrate 110 and a doped conductive layer 120 located on the surface of the substrate 110.

[0035] The stacked battery may further include: a composite layer 101, the composite layer 101 being located on the surface of the crystalline silicon bottom cell 100, the material of the composite layer 101 being a metal oxide, wherein a portion of the doped conductive layer 120 close to the composite layer 101 is doped with the same metal element as the metal element in the composite layer 101.

[0036] The stacked battery may further include: a perovskite top cell 102, the perovskite top cell 102 being located on the surface of the composite layer 101 away from the crystalline silicon bottom cell 100.

[0037] In the embodiments of the present disclosure, on the one hand, the part of the doped conductive layer 120 close to the composite layer 101 is doped with the same metal element as the metal element in the composite layer 101, which can reduce the interface difference between the doped conductive layer 120 and the composite layer 101, improve the reliability of the contact between the doped conductive layer 120 and the composite layer 101. At the same time, the part of the doped conductive layer 120 close to the composite layer 101 is doped with the same metal element as the metal element in the composite layer 101, reducing the interface pores of the doped conductive layer 120, realizing the passivation of part of the doped conductive layer 120, thereby improving the photoelectric conversion efficiency of the stacked cell.

[0038] The crystalline silicon bottom cell 100 includes any one of a PERC cell (Passivated Emitter and Rear Cell), a PERT cell (Passivated Emitter and Rear Totally-diffused cell), a TOPCon cell (Tunnel Oxide Passivated Contact), a HIT / HJT cell (Heterojunction Technology), or a BC cell (BackContact).

[0039] Hereinafter, the crystalline silicon bottom cell 100 being a TOPCon cell will be taken as an example for illustration. It should be noted that when the crystalline silicon bottom cell 100 is other types of cells, the other structures of the crystalline silicon bottom cell 100 can be correspondingly adjusted, which will not be elaborated here.

[0040] In some embodiments, the crystalline silicon bottom cell 100 includes: a substrate 110, the substrate 110 including opposite first surface 160 and second surface 170; a tunneling layer 130, the tunneling layer 130 being located on the second surface 170; a doped conductive layer 120, the doped conductive layer 120 being located on the surface of the tunneling layer 130 away from the substrate 110; an emitter 140, the emitter 140 being located in the substrate 110 or on the first surface 160 of the substrate 110; a first passivation layer 150, the first passivation layer 150 being located on the surface of the emitter away from the substrate 110.

[0041] Among them, both the first surface 160 and the second surface 170 of the substrate 110 can be used as the light-receiving surface for receiving incident light. The first surface 160 and / or the second surface 170 of the substrate 110 may also have a textured surface structure to increase light reflection and improve the utilization rate of light.

[0042] The tunneling layer 130 can passivate the substrate 110. Due to the interface state defects at the interface between the substrate 110 and the tunneling layer 130, the interface state density on the back surface of the substrate 110 is relatively large. The increase in the interface state density will promote the recombination of photo-generated carriers, reduce the fill factor, short-circuit current, and open-circuit voltage of the solar cell, and lower the photoelectric conversion efficiency of the solar cell. The tunneling layer 130 is disposed on the surface of the substrate 110, so that the tunneling layer 130 chemically passivates the surface of the substrate 110. Specifically, by saturating the dangling bonds of the substrate 110, the defect state density of the substrate 110 is reduced, and the recombination centers of the substrate 110 are reduced to lower the carrier recombination rate, thereby increasing the fill factor, short-circuit current, and open-circuit voltage of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0043] The material of the tunneling layer 130 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or magnesium fluoride.

[0044] The doped conductive layer 120 can also play a role in field passivation, forming an electrostatic field pointing into the substrate 110 on the surface of the substrate 110, causing minority carriers to escape from the interface, thereby reducing the minority carrier concentration, reducing the carrier recombination rate at the interface of the substrate 110, and increasing the open-circuit voltage, short-circuit current, and fill factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0045] In some embodiments, the thickness of the metal element doped in the doped conductive layer 120 is 10 nm to 20 nm, such as 10 nm, 12 nm, 14 nm, 15 nm, 18 nm, 19 nm, or 20 nm, etc. For the doped conductive layer 120, if the thickness of the part doped with the metal element in the doped conductive layer 120 is too thick, it may cause the metal element to further diffuse towards the tunneling layer 130 or the substrate 110, which will affect the performance of the tunneling layer 130 and the substrate 110. If the thickness of the part doped with the metal element in the doped conductive layer 120 is too thin, the performance improvement of the stacked cell is not good, affecting the improvement effect.

[0046] In some embodiments, in the direction of the composite layer 101 pointing to the doped conductive layer 120, the concentration of the metal element in the doped conductive layer 120 gradually decreases. That is to say, the doping concentration of the part close to the composite layer 101 is relatively large, and the doping concentration of the part close to the substrate 110 is relatively small. In this way, a gradient change in the doping concentration can be formed in the doped conductive layer 120, thereby avoiding the sudden change in the doping concentration of the metal element in the doped conductive layer 120 to further improve the reliability of the stacked cell.

[0047] In some embodiments, the material of the composite layer 101 is indium tin oxide. The ratio of the doping concentration of tin ions to the doping concentration of indium ions in the doped conductive layer 120 is 7 to 13, such as 8, 9, 10, 11, 12, or 13. For the doped conductive layer 120, too high a doping concentration of indium ions may lead to too high a hole concentration, triggering Auger recombination, and too high a doping concentration of tin ions may introduce lattice defects. By using the combined action of tin ions and indium ions and controlling the ratio of the doping concentrations of tin ions and indium ions to be 7 to 13, the conductivity and recombination loss of the doped conductive layer 120 are balanced.

[0048] For indium ions, the solubility of indium in the doped conductive layer 120 is relatively low, and excessive doping easily leads to precipitation defects. Tin ions are used to balance the precipitation problem of indium ions, thereby reducing the defect problem caused by indium ion precipitation.

[0049] It can be understood that the doping concentration of indium ions and the doping concentration of tin ions here refer to the average doping concentrations of indium ions and tin ions in the doped conductive layer 120.

[0050] Therefore, setting the thickness of the doped conductive layer 120 doped with metal elements to be 10 nm to 20 nm can achieve lattice matching between the doped conductive layer 120 and the composite layer 101, reduce the density of interface defect states, and at the same time avoid affecting other structures of the crystalline silicon bottom cell 100, thereby improving the performance of the stacked cell while avoiding affecting the reliability of the stacked cell.

[0051] The doping element in the emitter 140 is opposite to the doping element in the substrate 110, thereby forming a PN junction for separately transporting electrons and holes. The first passivation layer 150 can be a single-layer structure or a stacked structure, and the material of the first passivation layer 150 can be one or more of materials such as silicon oxide, silicon nitride, silicon oxynitride, carbon oxynitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0052] In some embodiments, the material of the composite layer 101 can be indium tin oxide. Indium tin oxide has high conductivity, can effectively transport carriers, reduce the series resistance between the crystalline silicon bottom cell 100 and the perovskite top cell 102, and improve the fill factor. Moreover, the indium tin oxide material has a relatively high light transmittance, allowing the unabsorbed light to penetrate between the crystalline silicon bottom cell 100 and the perovskite top cell 102, thereby further improving the light absorption rate.

[0053] In some embodiments, the ratio of the doping concentration of tin to the doping concentration of indium in the composite layer 101 is 4 to 19, such as 5, 7, 9, 10, 12, 14, 16, 18 or 19. In other words, the ratio of the doping concentration of tin to the doping concentration of indium in the composite layer 101 is 80:20 to 95:5. The higher the doping concentration of tin, the lower the cost required to form the composite layer 101. However, if the doping concentration of tin is too high, the sputtering process will be unstable during the formation of the composite layer 101, affecting the reliability of the formed composite layer 101.

[0054] In some embodiments, the material of the composite layer 101 can also be AZO (aluminum-doped zinc oxide), FTO (fluorine-doped tin oxide), ATO (antimony-doped tin oxide), etc.

[0055] In some embodiments, the perovskite top cell 102 includes: a first transport layer 112, a perovskite substrate 122, a second passivation layer 132, a second transport layer 142, a third transport layer 152, and a transparent conductive layer 162 that are stacked.

[0056] Among them, the first transport layer 112 can be a hole transport layer, and the material of the first transport layer 112 can be composed of materials such as poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA), 2,2',7,7'-tetrakis[N,N-bis(4-methoxyphenyl)amino]-9,9'-spirobifluorene (Spiro-OMeTAD), nickel oxide (NiO x ) or cuprous thiocyanate (CuSCN), etc.

[0057] The second passivation layer 132 is used to passivate the perovskite substrate 122, thereby repairing the perovskite substrate 122 to reduce the carrier recombination of the perovskite top cell 102, thereby improving the carrier transport efficiency of the stacked cell.

[0058] The second transport layer 142 and the third transport layer 152 can be electron transport layers, and the electron transport layers can be composed of materials such as tin oxide SnOx, titanium dioxide TiO2, fullerenes and their derivatives including C60 and PCBM.

[0059] The transparent conductive layer 162 can be ITO, AZO, FTO or ATO, or a polymer transparent material such as PDMS (polydimethylsiloxane) or PMMA (polymethyl methacrylate).

[0060] In some embodiments, the stacked cell can further include: a back electrode 103 and a front electrode 104. The back electrode 103 is located on the side of the crystalline silicon bottom cell 100 away from the composite layer 101 and is electrically connected to the emitter 140; the front electrode is located on the side of the perovskite top cell 102 away from the composite layer 101 and is electrically connected to the transparent conductive layer 162.

[0061] When the crystalline silicon bottom cell 100 is a BC cell, since the electrodes of the BC cell are all located on the back of the BC cell, the tandem cell has a three-terminal output, that is, three terminals output, and the three-terminal output respectively corresponds to two output terminals on the back of the BC cell and the output terminal on the top surface of the perovskite top cell 102.

[0062] In an embodiment of the present disclosure, on the one hand, the part of the doped conductive layer 120 close to the composite layer 101 is doped with the same metal element as the metal element in the composite layer 101, which can reduce the interface difference between the doped conductive layer 120 and the composite layer 101, and can improve the reliability of the contact between the doped conductive layer 120 and the composite layer 101. At the same time, the part of the doped conductive layer 120 close to the composite layer 101 is doped with the same metal element as the metal element in the composite layer 101, reducing the interface pores of the doped conductive layer 120, realizing the passivation of part of the doped conductive layer 120, thereby improving the photoelectric conversion efficiency of the tandem cell.

[0063] Another embodiment of the present disclosure further provides a method for manufacturing a tandem cell. This manufacturing method can be used to form the tandem cell in some or all of the above embodiments. The method for manufacturing the tandem cell provided in another embodiment of the present disclosure will be described below with reference to the drawings. It should be noted that for the same or corresponding parts in the foregoing embodiments, reference may be made to the corresponding descriptions in the foregoing embodiments, and details will not be repeated below.

[0064] Reference Figures 2 to 4 wherein, Figure 2 is a flowchart of a method for manufacturing a tandem cell provided in an embodiment of the present disclosure, Figures 3 to 4 is a schematic structural diagram corresponding to each step of a method for manufacturing a tandem cell provided in an embodiment of the present disclosure.

[0065] In some embodiments, the method for manufacturing a tandem cell may include: S10: providing a crystalline silicon bottom cell, the crystalline silicon bottom cell including a substrate and a doped conductive layer located on the surface of the substrate.

[0066] The method for manufacturing a tandem cell may further include: S11: forming a composite layer, the composite layer being located on the surface of the crystalline silicon bottom cell, the material of the composite layer being a metal oxide, wherein, during the formation of the composite layer, the metal element of the composite layer is controlled to diffuse into the doped conductive layer.

[0067] The method for manufacturing a tandem cell may include: S12: forming a perovskite top cell, the perovskite top cell being located on the surface of the composite layer 101 away from the crystalline silicon bottom cell.

[0068] By controlling the diffusion of metal elements in the composite layer 101 into the doped conductive layer 120 during the formation of the doped conductive layer 120, the interface difference at the contact interface between the doped conductive layer 120 and the composite layer 101 is reduced, thereby improving the reliability of the contact between the doped conductive layer 120 and the composite layer 101. At the same time, the part of the doped conductive layer 120 close to the composite layer 101 is doped with the same metal elements as those in the composite layer 101, reducing the interface pores of the doped conductive layer 120, realizing the passivation of part of the doped conductive layer 120, and thus improving the photoelectric conversion efficiency of the stacked cell.

[0069] Reference Figure 3 and Figure 4 , Figure 3 FIG. is a schematic structural diagram corresponding to a crystalline silicon bottom cell. Figure 4 FIG. is a schematic structural diagram of a composite layer formed on a crystalline silicon bottom cell and a perovskite top cell.

[0070] In some embodiments, after forming the crystalline silicon bottom cell 100, the surface of the crystalline silicon bottom cell 100 can be cleaned with hydrofluoric acid, and whether it is cleaned can be judged by observing the surface color of the crystalline silicon bottom cell 100. Among them, the concentration of hydrofluoric acid can be 1% - 5%, and the cleaning time can be 10 min - 20 min.

[0071] It can be understood that the provided crystalline silicon bottom cell 100 includes: a substrate 110, a tunneling layer 130, a doped conductive layer 120, an emitter 140, and a first passivation layer 150. The same or corresponding descriptions can refer to the above embodiments and will not be elaborated here.

[0072] In some embodiments, the method for forming the composite layer 101 can include: constructing a magnetic field environment, with the crystalline silicon bottom cell 100 located in the magnetic field environment; performing a magnetron sputtering process, which includes: providing a target, bombarding the target with plasma, and providing an oxidizing gas to bombard the metal elements contained in the target onto the surface of the doped conductive layer 120 to form the composite layer 101; during the formation of the composite layer 101, controlling the doping of metal elements into the doped conductive layer 120. That is to say, an additional magnetic field is added during the formation of the composite layer 101, so as to increase the density of the plasma when bombarding the target with the plasma, and at the same time make the energy of the metal ions sputtered from the target more uniform and easier to adhere to the surface of the crystalline silicon bottom cell 100 to form a denser and better crystalline thin film; on the other hand, increasing the magnetic field Huakeyi makes the metal ions adhere to the surface of the doped conductive layer 120 more widely and stably, which can reduce the pores or amorphous regions at the contact interface between the formed composite layer 101 and the doped conductive layer 120, improve the reliability of the formed composite layer 101 while passivating the doped conductive layer 120, and further improve the efficiency of the stacked cell.

[0073] In some embodiments, the magnetic field strength of the magnetic field environment is 0.5T to 1.5T, such as 0.5T, 0.7T, 1T, 1.2T, 1.4T or 1.5T, etc. The process parameters of magnetron sputtering include: the sputtering power is 0.5KW to 1KW, such as 0.5KW, 0.6KW, 0.7KW, 0.8KW, 0.9KW or 1KW, etc., and the temperature environment is 350°C to 450°C, such as 350°C, 370°C, 400°C, 420°C, 440°C or 450°C, etc.

[0074] For the magnetic field strength, the higher the magnetic field strength, the greater the kinetic energy of the plasma bombarding the target, which is more conducive to the formation of the composite layer 101. At the same time, if the magnetic field strength is too large, it may cause the energy of the plasma bombarding the target to be too large, which may lead to excessive etching of the target, reduce the target life, and may cause target contamination, affecting the reliability of the subsequent formation of the composite layer 101.

[0075] For the sputtering power and the ambient temperature, the sputtering power is proportional to the rate of forming the composite layer 101. However, too high a power may cause the local temperature on the surface of the target to rise, which may lead to situations such as cracking of the target. And too low a sputtering power may result in uneven thickness of the formed composite layer 101. Providing a certain temperature environment can provide sufficient thermal energy to enable the atoms deposited on the crystalline silicon bottom cell 100 to overcome the diffusion barrier and migrate to lattice positions with lower energy, promoting the growth of the composite layer 101. If the provided temperature environment is too low, it may cause warping of the crystalline silicon bottom cell 100.

[0076] In some embodiments, the greater the sputtering power, the lower the ambient temperature can be set. The problem of insufficient thermal energy can be compensated by the sputtering power, thereby improving the crystallinity of the composite layer 101. The greater the ambient temperature, the smaller the sputtering power, so as to avoid over-bombarding and damaging the already formed composite layer 101.

[0077] In some embodiments, the process of forming the composite layer 101 further includes: detecting the thickness of the composite layer 101; when the thickness of the formed composite layer 101 is less than 5 nm, the magnetic field strength is the first preset magnetic field strength; when the thickness of the formed composite layer 101 is 5 nm to 20 nm, the magnetic field strength is the second preset magnetic field strength; when the thickness of the formed composite layer 101 is greater than 20 nm, the magnetic field strength is the third preset magnetic field strength, wherein the first preset magnetic field strength is less than the second preset magnetic field strength is less than the third preset magnetic field strength. That is to say, different magnetic field strengths are set according to the different thicknesses of the formed composite layer 101. It can be understood that when the thickness of the formed composite layer 101 is less than 5 nm, a higher magnetic field strength needs to be set to facilitate the formation of the composite layer 101 with an initial thickness. When the thickness of the formed composite layer 101 is 5 nm to 20 nm, at this time, the composite layer 101 with an initial thickness has been formed, and it is easier to form the composite layer 101 on the composite layer 101 than on the crystalline silicon bottom cell 100. Therefore, after adjusting the magnetic field strength, a composite layer 101 with better uniformity can also be formed. When the thickness of the formed composite layer 101 is greater than 20 nm, at this time, the composite layer 101 has a certain thickness, and it is easier to form the subsequent composite layer 101.

[0078] Furthermore, when the thickness of the formed composite layer 101 is less than 5 nm, at this time, the composite layer 101 is formed on the surface of the doped conductive layer 120, and the lattice difference between the doped conductive layer 120 and the composite layer 101 is relatively large. A larger magnetic field strength is required to facilitate the formation of the composite layer 101, and the uniformity of the formed composite layer 101 can be improved by a larger magnetic field strength. When the thickness of the formed composite layer 101 is 5 nm to 20 nm, during this process, the composite layer 101 is formed on the surface of the composite layer 101, and the formation difficulty is reduced. By reducing the magnetic field strength, the uniformity of the composite layer 101 formed during this process and the composite layer 101 formed on the surface of the doped conductive layer 120 can be balanced. When the thickness of the formed composite layer 101 is greater than 20 nm, at this time, the difficulty of forming the subsequent composite layer 101 is the lowest. By further reducing the magnetic field strength, the uniformity between the composite layers 101 with different thicknesses can be relatively unified, and the reliability of the formed composite layer 101 can be improved.

[0079] In some embodiments, an in-situ detection device: an integrated plasma spectrometer or a thin film thickness sensor can be used to monitor the thickness of the formed composite layer 101 in real time.

[0080] In some embodiments, the method of forming the composite layer 101 includes: providing a laser, irradiating the surface of the doped conductive layer 120 with the laser; performing a magnetron sputtering process, the magnetron sputtering process including: providing a target, bombarding the target with plasma, and providing an oxidation gas, bombarding the metal elements contained in the target onto the surface of the doped conductive layer 120 irradiated by the laser to form the composite layer 101; during the formation of the composite layer 101, controlling the doping of metal elements into the doped conductive layer 120. The laser energy is precisely applied to the deposition interface in the magnetron sputtering process, thus facilitating the formation of the composite layer 101.

[0081] In some embodiments, the laser wavelength of the laser can be 248 nm or 532 nm, etc., the laser energy density of the laser is 0.5 J / cm² to 5 J / cm², such as 0.5 J / cm², 1 J / cm², 2 J / cm², 3 J / cm², 4 J / cm² or 5 J / cm², etc., the pulse frequency can be 20 Hz to 50 Hz, such as 20 Hz, 30 Hz, 40 Hz or 50 Hz, etc., and the laser incident angle is 30° to 60°, such as 30°, 45°, 50° or 60°, etc.

[0082] Regarding the laser wavelength of the laser, select a laser with a wavelength adapted to the absorption characteristics of the composite layer 101 material to facilitate the formation of the composite layer 101; regarding the energy density, too high an energy density may cause local overheating of the target and damage to the target, or may cause damage to the doped polysilicon layer, while too low an energy density cannot effectively enhance the ion kinetic energy; regarding the pulse frequency, the higher the pulse frequency, the higher the rate of forming the composite layer 101, but too high a pulse frequency will result in poor uniformity of the formed composite layer 101; regarding the incident angle, selecting a specific incident angle can optimize the energy transfer efficiency.

[0083] In some embodiments, the process method of forming the perovskite top cell 102 may include: sequentially forming a first transport layer 112, a perovskite substrate 122, a second passivation layer 132, a second transport layer 142, a third transport layer 152, and a transparent conductive layer 162.

[0084] The method of forming the first transport layer 112 may include: weighing a certain mass of a hole transport material and dissolving it in a solvent solution, adding a magnetic stirrer, and completely dissolving the hole transport material in the solvent solution to obtain a reaction solution. Then, an appropriate amount of the reaction solution is dropped onto the surface of the crystalline silicon bottom cell 100 and spin-coated at a spin-coating rate of 4000 rpm to 5000 rpm for 20 s to 30 s, and then annealed at 100°C to 140°C for 10 min to 20 min to complete the preparation of the first transport layer 112.

[0085] In some embodiments, the hole transporting material may be a carbazole-based hole transporting material, such as 2PACZ, and the solvent solution may be an ethanol solution.

[0086] The method of forming the perovskite substrate 122 may include: after the formed first transport layer 112 is cooled to room temperature, taking a certain amount of perovskite solution to cover the surface of the first transport layer 112, and spin-coating at a spin-coating rate of 3000 rpm to 5000 rpm for 20 s to 30 s, and then annealing at 90 °C to 100 °C for 10 min to 20 min to prepare the perovskite substrate 122.

[0087] The perovskite solution is prepared by mixing cesium iodide (CsI), lead iodide (PbI2), lead bromide (PbBr2), formamidinium hydroiodide (FAI), and methylammonium iodide (MAI) in a certain molar ratio in N,N-dimethylformamide (DMF) and dimethyl sulfoxide (DMSO).

[0088] The method of forming the second passivation layer 132 may include: directly forming the second passivation layer 132 by deposition. The method of forming the second transport layer 142 may include: directly forming the second transport layer 142 on the surface of the second passivation layer 132 by using an evaporation machine. The method of forming the third transport layer 152 may include: depositing and forming the third transport layer 152 by using an atomic layer deposition device. The method of forming the transparent conductive layer 162 may include: forming the transparent conductive layer 162 by a magnetron sputtering process, by providing a target, and by plasma bombardment.

[0089] In some embodiments, during the process of forming the transparent conductive layer 162, a magnetic field environment may be constructed or the density and uniformity of the formed transparent conductive layer 162 may be improved by increasing the laser. The description of constructing the magnetic field environment and increasing the laser may refer to the part of forming the composite layer 101 above, and will not be elaborated here.

[0090] In some embodiments, the process of forming the stacked cell further includes: forming a front electrode and a back electrode. The process of forming the front electrode and the back electrode may include: evaporating the electrode material on the crystalline silicon bottom cell 100 and the perovskite top cell 102, and completing the formation of the front electrode and the back electrode by sintering.

[0091] The stacked cell prepared and formed in the embodiments of the present disclosure has good structural stability, can be stored outdoors for 1000 h, and the battery attenuation is within 2%. Refer to Table 1 below. Table 1 is the device performance measured for the stacked cell provided in the embodiments of the present disclosure.

[0092]

[0093] Table 1 It should be noted that the above measurement is carried out by adjusting the power of the solar simulator to 100 mw / cm 2 to simulate the AM1.5G radiation standard, and the current and voltage values of the device are read through a power meter. Before measuring the current density-voltage curve, the light intensity is also calibrated by Newport standard. The device adopts a forward and reverse scan mode with a scan rate of 0.05V / s.

[0094] As can be seen from the above table, the open-circuit voltage, fill factor, and photoelectric conversion efficiency of the tandem cell provided by the embodiments of the present disclosure have all been significantly improved, and the short-circuit current has also increased.

[0095] For the tandem cell in the comparative example, the diffusion of metal elements in the composite layer 101 into the doped conductive layer 120 is not controlled, and no magnetic field environment is constructed and no laser is used during the formation of the composite layer 101.

[0096] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure. In practical applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be determined by the scope defined by the claims.

Claims

1. A stacked battery, characterized in that, Comprising: A crystalline silicon bottom cell, the crystalline silicon bottom cell comprising a substrate and a doped conductive layer on the surface of the substrate; A composite layer, the composite layer being on the surface of the crystalline silicon bottom cell, the material of the composite layer being a metal oxide, wherein a portion of the doped conductive layer close to the composite layer is doped with the same metal element as the metal element in the composite layer; A perovskite top cell, the perovskite top cell being on the surface of the composite layer away from the crystalline silicon bottom cell.

2. The stacked battery according to claim 1, wherein The thickness of the doped conductive layer doped with the metal element is 10 nm to 20 nm.

3. The stacked battery according to claim 1, wherein In the direction of the composite layer pointing to the doped conductive layer, the concentration of the metal element in the doped conductive layer gradually decreases.

4. The stacked battery according to claim 1 or 2, characterized in that, The material of the composite layer is indium tin oxide.

5. The stacked battery according to claim 4, wherein The ratio of the doping concentration of tin ions to the doping concentration of indium ions in the doped conductive layer is 7 to 13.

6. The stacked battery according to claim 4, characterized in that, The ratio of the doping concentration of tin to the doping concentration of indium in the composite layer is 4 to 19.

7. A method for manufacturing a stacked battery, characterized in that, Comprising: Providing a crystalline silicon bottom cell, the crystalline silicon bottom cell comprising a substrate and a doped conductive layer on the surface of the substrate; Forming a composite layer, the composite layer being on the surface of the crystalline silicon bottom cell, the material of the composite layer being a metal oxide, wherein during the formation of the composite layer, the metal element of the composite layer is controlled to diffuse into the doped conductive layer; Forming a perovskite top cell, the perovskite top cell being on the surface of the composite layer away from the crystalline silicon bottom cell.

8. The manufacturing method of the stacked battery according to claim 7, characterized in that, The method for forming the composite layer includes: Constructing a magnetic field environment, the crystalline silicon bottom cell being within the magnetic field environment; Performing a magnetron sputtering process, the magnetron sputtering process including: providing a target, bombarding the target with plasma, and providing an oxidation gas to bombard the metal element contained in the target onto the surface of the doped conductive layer to form the composite layer; During the formation of the composite layer, controlling the metal element to be doped into the doped conductive layer.

9. The manufacturing method of the stacked battery according to claim 8, characterized in that, The magnetic field intensity of the magnetic field environment is 0.5 T to 1.5 T, and the process parameters of the magnetron sputtering include: the sputtering power is 0.5 KW to 1 KW, and the temperature environment is 350 °C to 450 °C.

10. The manufacturing method of the stacked battery according to claim 8, wherein, During the formation of the composite layer, it further includes: detecting the thickness of the composite layer; When the thickness of the formed composite layer is less than 5 nm, the magnetic field intensity is the first preset magnetic field intensity; When the thickness of the formed composite layer is 5 nm to 20 nm, the magnetic field intensity is the second preset magnetic field intensity; When the thickness of the formed composite layer is greater than 20 nm, the magnetic field intensity is the third preset magnetic field intensity, wherein the first preset magnetic field intensity is less than the second preset magnetic field intensity is less than the third preset magnetic field intensity.

11. The manufacturing method of the stacked battery according to claim 7, characterized in that, The method for forming the composite layer includes: providing a laser, the laser irradiating the surface of the doped conductive layer; Performing a magnetron sputtering process, the magnetron sputtering process including: providing a target, bombarding the target with plasma, and providing an oxidation gas to bombard the metal element contained in the target onto the surface of the doped conductive layer irradiated by the laser to form the composite layer; During the formation of the composite layer, controlling the metal element to be doped into the doped conductive layer.

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