Method and device for determining flight time

Abstract

A first communication device receives an analog receive signal via a communication medium. An ADC of the first communication device converts the analog receive signal into a digital receive signal. Logic circuitry of the first communication device detects a plurality of timing signals from a second communication device based on analyzing the digital receive signal. The logic circuitry adjusts a sampling phase of the ADC in conjunction with at least some of the timing signals such that when a different one of the timing signals is detected, the ADC uses a different sampling phase. When different ones of the timing signals are detected, the logic circuitry determines timing information based on the detection of the plurality of timing signals when the ADC uses different sampling phases. The first communication device determines a time of flight between the first communication device and the second communication device based on the timing information.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 417,984, filed on Oct. 20, 2022, entitled “Clock-Based Topology Discovery,” the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to in-vehicle communication networks, and more particularly to topology discovery within in-vehicle communication networks. Background Art

[0004] In-vehicle communication networks allow components within a vehicle to exchange data. The Institute of Electrical and Electronics Engineers (IEEE) 802.3cg standard defines a communication protocol for communicating at speeds up to 10 megabits per second (Mbps) via a single twisted pair cable, sometimes referred to as 10BASE-T1S, which is targeted for use in vehicles. The 10BASE-T1S standard supports point-to-point and multi-point communication. With multi-point communication, three or more communication devices can communicate via a single cable.

[0005] In a multi-point network using the 10BASE-T1S standard, multiple identical devices can be connected to a single twisted pair cable, where the function of each device depends on its physical location within the vehicle. For example, multiple identical radar sensors can be connected to a single twisted pair cable, where a first radar is located at the rear of the vehicle, a second radar is located at the front of the vehicle, a third radar is located near the driver's side in the front row, and a fourth radar is located near the passenger's side in the front row. Due to its location, the first radar will be used to provide object detection behind the vehicle (e.g., for when the vehicle is moving in the reverse direction); the second radar will be used to provide object detection in front of the vehicle; the third radar will be used to provide object detection in a side view of the driver's side of the vehicle; and the fourth radar will be used to provide object detection in a side view of the passenger's side of the vehicle.

[0006] When the overall physical layout of the cables within the vehicle is known, a controller connected to the cable can identify the functional devices connected to the cable based on the respective distances of the devices along the cable from the controller. Figure 1FIG. 0 is a simplified diagram of a vehicle 100 having an in-vehicle communication network 102 that includes an electronic control unit (ECU) 104 and sensors 108, 112, 116, and 120 (such as radar sensors, lidar sensors, etc.) electrically connected to a cable 124. Sensor 108 is positioned at a first distance D1 from ECU 104 along cable 124; sensor 112 is positioned at a second distance D2 from ECU 104 along cable 124; sensor 116 is positioned at a third distance D3 from ECU 104 along cable 124; and sensor 120 is positioned at a fourth distance D4 from ECU 104 along cable 124. When ECU 104 knows the overall physical layout of cable 124 within the vehicle and knows the respective distances of sensors 108, 112, 116, and 120 from ECU 104 along cable 124, ECU 104 can determine the respective functions of sensors 108, 112, 116, and 120. For example, when sensors 108, 112, 116, and 120 are radar sensors, ECU 104 can use the respective distances from ECU 104 to determine: i) radar sensor 108 is a rearward radar; ii) sensor 112 is a lateral driver-side radar; iii) sensor 116 is a forward radar; and iv) sensor 120 is a lateral passenger-side radar.

[0007] Although Figure 1 FIG. shows a communication network including an ECU and sensors, but the communication network includes other suitable components, such as actuators (e.g., for door locks, windows, sunroofs, side mirrors, etc.), buttons, lights, etc.

[0008] One technique for determining the distance between two devices in a network (such as in-vehicle communication network 102) is to measure the time (sometimes referred to as "time of flight") it takes for a signal (such as a pulse) to travel from a first device to a second device via a communication medium. For example, the first device can send a forward pulse to the second device, and in response to receiving the forward pulse, the second device sends a reverse pulse to the first device. The first device measures the duration between the transmission of the forward pulse and the reception of the reverse pulse, and uses that duration to calculate the distance between the first device and the second device. To improve accuracy, the first device and the second device can repeatedly send forward pulses and reverse pulses, and measure the total duration of sending and receiving the forward and reverse pulses. For example, in response to receiving the reverse pulse, the first device sends another forward pulse to the second device, which in turn sends another reverse pulse to the first device, and so on. Then, the first device measures the duration between the transmission of the initial forward pulse and the reception of the last reverse pulse, and uses that duration to calculate the distance between the first device and the second device. SUMMARY OF THE INVENTION

[0009] In an embodiment, a transceiver associated with a first communication device includes: an analog-to-digital converter (ADC) configured to generate a digital received signal based on an analog received signal received via a communication medium; a timing signal detection circuitry coupled to the ADC, the timing signal detection circuitry configured to detect a plurality of timing signals from a second communication device based on analyzing the digital received signal; a sampling phase generation circuitry coupled to the ADC, the sampling phase generation circuitry configured to adjust a sampling phase used by the ADC in combination with at least some of the timing signals such that when different timing signals among the timing signals are detected, the ADC uses different sampling phases; a timing information determination circuitry configured to determine timing information based on the detection of the plurality of timing signals when different timing signals among the timing signals are detected and when the ADC uses different sampling phases; and a processor configured to determine a time of flight based on the timing information.

[0010] In another embodiment, a method for measuring a time of flight between a first communication device and a second communication device includes: at the first communication device, receiving an analog received signal via a communication medium; at an ADC of the first communication device, converting the analog received signal into a digital received signal; at a logic circuitry of the first communication device, detecting a plurality of timing signals from the second communication device based on analyzing the digital received signal; at the logic circuitry, adjusting a sampling phase of the ADC in combination with at least some of the timing signals such that when different timing signals among the timing signals are detected, the ADC uses different sampling phases; at the logic circuitry, determining timing information based on the detection of the plurality of timing signals when different timing signals among the timing signals are detected and when the ADC uses different sampling phases; and at the first communication device, determining a time of flight based on the timing information.

[0011] In yet another embodiment, a transceiver associated with a first communication device includes: a forward signal generation circuitry configured to generate a digital transmit signal including a plurality of forward timing signals; a digital-to-analog converter (DAC) configured to generate an analog transmit signal based on the digital transmit signal; a clock phase adjustment circuitry configured to adjust a clock phase provided to the DAC in combination with at least some of the forward timing signals such that when different ones of the forward timing signals are transmitted, the DAC uses different phases of the clock; a driver circuitry configured to transmit the analog transmit signal via a communication medium, wherein each forward timing signal prompts the second communication device to transmit a corresponding reverse timing signal, and wherein when different ones of the forward timing signals are transmitted, the DAC's use of different phases of the clock affects the timing of the corresponding transmission of the corresponding reverse timing signal; an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received via the communication medium; a timing signal detection circuitry coupled to the ADC and configured to detect a plurality of reverse timing signals from the second communication device based on analyzing the digital receive signal; a timing information determination circuitry configured to determine timing information based on the detection of the plurality of reverse timing signals; and a processor configured to determine a time of flight based on the timing information.

[0012] In yet another embodiment, a method for measuring a time of flight between a first communication device and a second communication device includes: at the first communication device, generating a digital transmit signal including a plurality of forward timing signals; at a DAC of the first communication device, generating an analog transmit signal based on the digital transmit signal; at a logic circuitry of the first communication device, adjusting a clock phase provided to the DAC in combination with at least some of the forward timing signals such that when different ones of the forward timing signals are transmitted, the DAC uses different phases of the clock; by the first communication device, transmitting the analog transmit signal via a communication medium, wherein each forward timing signal prompts the second communication device to transmit a corresponding reverse timing signal, and wherein when different ones of the forward timing signals are transmitted, the DAC's use of different phases of the clock affects the timing of the corresponding transmission of the corresponding reverse timing signal; at the first communication device, receiving the analog receive signal via the communication medium; at an analog-to-digital converter (ADC) of the first communication device, converting the analog receive signal to a digital receive signal; at the logic circuitry, detecting a plurality of reverse timing signals from the second communication device based on analyzing the digital receive signal; at the logic circuitry, determining timing information based on the detection of the plurality of reverse timing signals; and at the first communication device, determining a time of flight based on the timing information. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1is a simplified diagram of an example vehicle having an in-vehicle communication network that implements various aspects, features, and elements described herein.

[0014] Figure 2 is a simplified diagram of an example communication network that implements various aspects, features, and elements described herein according to an embodiment of the present disclosure.

[0015] Figure 3 is a simplified diagram of an example communication device that implements various aspects, features, and elements described herein according to an embodiment of the present disclosure.

[0016] Figure 4 is according to an embodiment Figure 3 of the sampling phase of the phase generator output of the communication device as a function of the amount of reverse pulses received by the Figure 3 communication device, an illustrative example graph.

[0017] Figure 5 is according to an embodiment Figure 3 of a simplified diagram of an example phase generator of the communication device.

[0018] Figure 6 is a diagram illustrating, according to an embodiment, when Figure 3 the analog-to-digital converter (ADC) of the communication device uses different sampling phases Figure 3 a set of graphs of the communication device receiving multiple reverse pulses.

[0019] Figure 7 is a flowchart of an example method for measuring the time of flight between a first communication device and a second communication device according to an embodiment.

[0020] Figure 8 is a simplified diagram of another example communication device that implements various aspects, features, and elements described herein according to an embodiment of the present disclosure.

[0021] Figure 9 is a diagram illustrating, according to an embodiment, when transmitting a corresponding forward pulse that prompts a reverse pulse Figure 8 the communication device uses a digital-to-analog converter (DAC) with different clock phases to receive a set of graphs of multiple reverse pulses.

[0022] Figure 10 is a flowchart of another example method for measuring the time of flight between a first communication device and a second communication device according to another embodiment. Detailed Description

[0023] The Open Alliance in "TC14-10BASE-T1S Topology Discovery" has proposed a process for measuring the distance between devices using the 10BASE-T1S standard in a multi-point configuration. The first device initializes a counter to zero and sends an initial forward pulse to the second device via a twisted pair cable. In response to receiving the forward pulse, the second device sends a reverse pulse to the first device via the cable. In conjunction with receiving the reverse pulse, the first device increments the counter. Additionally, in response to receiving the reverse pulse, the first device sends another forward pulse to the second device via the cable. In response to receiving the forward pulse, the second device sends a reverse pulse to the first device via the cable. Sending pulses in this way continues for a predetermined duration. Then, based on i) the number of reverse pulses received by the first device indicated by the counter and ii) the time required to receive the reverse pulses, the distance between the first device and the second device is calculated.

[0024] The Open Alliance also proposes that the accuracy of the distance measurement is ±15 centimeters (cm), which corresponds to a time measurement resolution on the order of 100 picoseconds (ps). If pulse detection is implemented in the digital domain, this measurement accuracy means that the analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) of the transceivers performing the process are timed to provide a sampling rate of 10 gigahertz (GHz). However, the 10BASE-T1S standard specifies a transmission speed corresponding to a clock rate of 10 to 100 megahertz (MHz), i.e., several orders of magnitude lower than 10 GHz. For example, in a transceiver operating at a transmission speed of 10 MHz to 100 MHz, including ADCs and DACs capable of operating at a 10 GHz sampling rate would significantly increase costs compared to ADCs and DACs capable of operating at a 10 MHz to 100 MHz sampling rate.

[0025] In the embodiments described below, techniques for achieving relatively high measurement accuracy with a relatively low sampling rate are used to measure the time required for a signal to propagate between devices via a communication medium ("time of flight"). For example, in some embodiments, the sampling phase of an ADC is adjusted in conjunction with receiving multiple timing signals (e.g., pulses) such that the ADC uses different corresponding sampling phases in conjunction with receiving different timing signals among the timing signals. When calculating the time of flight based on the reception of multiple timing signals that are received when the ADC uses different sampling phases, at least in some embodiments, significantly higher resolution is achieved compared to controlling the sampling phase of the ADC according to prior art methods.

[0026] In other embodiments, multiple timing signals (e.g., pulses) are combined to adjust the phase of the clock used by the DAC such that different phases of the clock are provided to the DAC in combination with different ones of the timing signals. When calculating the time of flight based on the transmission of multiple timing signals, which corresponds to times when the clock provided to the DAC has different phases, in at least some embodiments, significantly higher resolution is achieved compared to when the phase of the clock provided to the DAC is constant.

[0027] In at least some embodiments, the application of different sampling phases and / or different clock phases, such as those described above, achieves a relatively high measurement resolution at a relatively low clock rate. Thus, costs can be reduced because ADCs and DACs that operate at a relatively low speed can be used.

[0028] Figure 2 FIG. is a simplified diagram of an example communication network 200 (sometimes referred to herein as "network 200") that implements various aspects, features, and elements described herein according to an embodiment of the present disclosure. The network includes a first communication device 204 and a second communication device 208 communicatively coupled via a cable 212. In an embodiment, network 200 includes one or more other communication devices (not shown) electrically connected to cable 212. In an embodiment, cable 212 is a single twisted pair cable, and first communication device 204 and second communication device 208 are configured to operate according to 10BASE-T1S. In other embodiments, cable 212 is another suitable type of cable (e.g., including multiple twisted pairs, coaxial cables, fiber optic cables, etc.). In other embodiments, cable 212 is omitted, and first communication device 204 and second communication device 208 communicate wirelessly. In some embodiments, first communication device 204 and second communication device 208 communicate according to another suitable communication protocol different from 10BASE-T1S.

[0029] In an embodiment, network 200 corresponds to Figure 1 network 102, and for purposes of explanation, reference is made to Figure 1 described Figure 2 . For example, in an embodiment, first communication device 204 corresponds to ECU 104, and second communication device 208 corresponds to one of sensors 108, 112, 116, and 120. However, in other embodiments, first communication device 204 is one of sensors 108, 112, 116, and 120, and second communication device 208 is ECU 104. In other embodiments, network 200 corresponds to another suitable network different from network 102.

[0030] The first communication device 204 and the second communication device 208 are configured to perform a process for determining the distance along the cable 212 between the first communication device 304 and the second communication device 208. For example, the process includes exchanging timing signals (such as pulses or other suitable timing signals), and using the exchange of the timing signals to measure the time of flight between the first communication device 204 and the second communication device 208. The first communication device 204 and / or the second communication device 208 are configured to use the time of flight to determine the distance between the first communication device 204 and the second communication device 208.

[0031] As part of the process for determining the distance, the first communication device 204 is configured to transmit an initial forward timing signal 220 (such as a pulse) to the second communication device 208 via the cable 212. In response to receiving the forward timing signal 220, the second device transmits a reverse timing signal 224 (such as a pulse) to the second communication device 208 via the cable 212. In an embodiment, the forward timing signal 220 and the reverse timing signal 224 are pulses, and for simplicity, are sometimes referred to herein as "forward pulse 220" and "reverse pulse 224". However, according to other embodiments, the forward timing signal 220 and the reverse timing signal 224 are suitable timing signals other than pulses.

[0032] In conjunction with receiving the reverse pulse 224, the first communication device 204 transmits another forward pulse 220 to the second communication device 208 via the cable 212. In response to receiving the forward pulse 220, the second communication device 208 transmits a reverse pulse 224 to the first communication device 204 via the cable 212. The transmission of pulses 220, 224 continues in this manner until the end of a time period, the first communication device 204 transmits a first number of forward pulses 220, and / or the first communication device 204 receives a second number of reverse pulses 224, etc.

[0033] The first communication device 204 includes front-end circuitry 240 communicatively coupled to the cable 212. The front-end circuitry 240 includes an ADC 244 that converts an analog received signal to a digital received signal. The front-end circuitry 240 also includes a DAC 248 that converts a digital transmit signal to an analog transmit signal. The ADC 244 and the DAC 248 are communicatively coupled to the cable 212. In some embodiments, the front-end circuitry 240 includes other circuitry (such as one or more of hybrid circuitry, amplifiers, drivers, filters, etc.) not shown for simplicity. In some embodiments where the cable 212 is not a single twisted pair cable or is completely omitted, the front-end circuitry 240 has another structure suitable for the communication medium used.

[0034] In some embodiments, the sampling phase of the ADC 244 is adjusted in conjunction with receiving a plurality of reverse pulses 224 such that the ADC uses different respective sampling phases in conjunction with different timing signals in the received timing signal. When calculating the time of flight based on the reception of a plurality of reverse pulses 224, which are received when the ADC 244 uses different sampling phases, in at least some embodiments, significantly higher resolution is achieved compared to controlling the sampling phase of the ADC 244 according to prior art methods.

[0035] In other embodiments, the clock phase used by the DAC 248 is adjusted in conjunction with transmitting a plurality of forward pulses 220 such that different respective phases of the clock are provided to the DAC 248 in conjunction with different forward pulses 220 in the transmitted plurality of forward pulses 220. When calculating the time of flight based on the transmission of a plurality of forward pulses 220, corresponding to times when the clock provided to the DAC 248 has different phases, in at least some embodiments, significantly higher resolution is achieved compared to the clock phase provided to the DAC 248 being constant.

[0036] Figure 3 is a simplified diagram of an example communication device 300 according to an embodiment. In the embodiment, the communication device 300 is used for Figure 2 in the network 200, and for purposes of explanation, reference is made to Figure 2 description Figure 3 . For example, in the embodiment, the communication device 300 corresponds to Figure 2 the first communication device 204. In other embodiments, the first communication device 204 has a suitable structure different from that of the communication device 300, and / or the communication device 300 is used in a different suitable communication network from the network 200.

[0037] The communication device 300 includes a transmitting circuitry 308 and a receiving circuitry 312, both of which are coupled to an analog front-end circuitry 316. The front-end circuitry 316 is communicatively coupled to a cable 320. In the embodiment, the cable 320 is a single twisted pair cable, and the communication device 300 is configured to operate according to 10BASE-T1S. In other embodiments, the cable 320 is another suitable type of cable (e.g., including multiple twisted pairs, coaxial cables, fiber optic cables, etc.). In other embodiments, the cable 320 is omitted, and the communication device 300 communicates wirelessly. In some embodiments, the communication device 300 is configured to operate according to another suitable communication protocol different from 10BASE-T1S.

[0038] The front-end circuit device 316 includes an ADC 324 that converts an analog received signal received via a cable 320 into a digital received signal. The front-end circuit device 316 also includes a DAC 328 that converts a digital transmit signal into an analog transmit signal for transmission via the cable 320. The front-end circuit device 316 further includes a driver circuit device 332 coupled to the output of the DAC 328. The driver circuit device 332 and the ADC 244 are communicatively coupled to the cable 320 via a hybrid circuit 336. In some embodiments, the front-end circuit device 316 includes other circuit devices (such as one or more of an amplifier, a driver, a filter, etc.), which are not shown for simplicity. In some embodiments where the cable 320 is not a single twisted pair cable or is completely omitted, the front-end circuit device 316 has another structure suitable for the communication medium used.

[0039] The communication device 300 includes a timing measurement system 340 configured to determine a time of flight relative to another communication device (not shown) based on a timing signal received via the cable 320 from another communication device.

[0040] The transmit circuit device 308 and the timing measurement system 340 are selectively coupled to the DAC 328 via a switch 344. The receive circuit device 312 and the timing measurement system 340 are selectively coupled to the ADC 324 via a switch 348 and a switch 352. During normal operation (e.g., when the communication device 300 transmits user information via the cable 320), the switches 344, 348, 352 are controlled to i) couple the transmit circuit device 308 and the receive circuit device 312 to the analog front end 316, and ii) isolate the timing measurement system 340 from the analog front end 316. However, during the time of flight measurement process, the control switches 344, 348, 352 are controlled to i) couple the timing measurement system 340 to the analog front end 316, and ii) isolate the transmit circuit device 308 and the receive circuit device 312 from the analog front end 316.

[0041] The timing measurement system 340 includes a pulse generator 368 whose output is coupled to the input of the switch 344. The pulse generator 368 is configured to generate a digital transmit signal including a plurality of positive pulses (such as the positive pulse 220). When the pulse generator 368 is coupled to the DAC 328 via the switch 344, the DAC 328 converts the digital transmit signal into an analog transmit signal including a plurality of analog positive pulses for transmission via the cable 320.

[0042] The timing measurement system 340 further includes a pulse detector 360, and an input of the pulse detector 360 is coupled to the output of the switch 348. The pulse detector 360 is configured to analyze the digital received signal output by the ADC 324 to detect a plurality of reverse pulses in the digital received signal, such as the reverse pulse 224. Thus, when the pulse detector 360 is coupled to the ADC 324 through the switch 348, the pulse detector 360 analyzes the digital received signal output by the ADC 324 to detect a plurality of reverse pulses received from other communication devices via the cable 320. When the pulse detector 360 detects a pulse in the digital received signal, the pulse detector generates a pulse detection signal.

[0043] A counter 364 (referred to herein as "pulse counter 364") is coupled to the pulse detector 360. The pulse counter 364 counts the reverse pulses detected by the pulse detector 360. The pulse counter 364 is configured to increment the count in response to each pulse detection signal output by the pulse detector 360.

[0044] A pulse generator 368 is also coupled to the pulse detector 360. The pulse generator 368 is configured to generate a forward pulse in the digital transmit signal in response to each pulse detection signal in at least some of the pulse detection signals output by the pulse detector 360. In an embodiment, the pulse generator 368 is configured to introduce a time delay between when the pulse detector 360 outputs a pulse detection signal and the start of the corresponding forward pulse output by the pulse generator 368. Thus, in response to the communication device 300 receiving a reverse pulse via the cable 320, the communication device 300 transmits a forward pulse.

[0045] The timing measurement system 340 further includes a processor 372. The processor 372 is configured to control the operation of the timing measurement system 340 during a time-of-flight measurement process. For example, in an embodiment, the processor 372 is configured to prompt the pulse generator 368 to send an initial positive pulse during the time-of-flight measurement process. In conjunction with the end of the time-of-flight measurement process, the processor 372 is further configured to calculate the time of flight based on i) the count of the reverse pulses output by the pulse counter 364, and ii) the time period from when the initial positive pulse is sent to when the last reverse pulse is received. In an embodiment, the processor 372 includes a counter 376 that is used to count the number of clock cycles from when the initial positive pulse is sent to when the last reverse pulse is received, wherein the number of clock cycles output by the counter 376 indicates the time period from when the initial positive pulse is sent to when the last reverse pulse is received. In an embodiment, the processor 372 starts the counter 376 in conjunction with the communication device 300 sending the initial positive pulse of the time-of-flight measurement process, and stops the counter 376 in conjunction with the communication device 300 receiving the last reverse pulse of the time-of-flight measurement process. In an embodiment, the processor 372 starts the counter 376 in response to the start of the time-of-flight measurement process, and stops the counter 376 in response to the pulse detector 360 detecting the last reverse pulse of the time-of-flight measurement process.

[0046] In another embodiment, the counter 376 is a countdown counter, and the processor 372 starts the counter 376 in response to the start of the time-of-flight measurement process. When the counter 376 reaches a predetermined value (e.g., zero), the processor 372 determines that the time-of-flight measurement process has ended.

[0047] The timing measurement system 340 further includes a phase generator 380, and the output of the phase generator 380 is coupled to the input of the switch 352. During normal operation, the switch 352 couples the output of the receiving circuitry 312 to the sampling phase input of the ADC 324, and the receiving circuitry 312 controls the sampling phase of the ADC 324 to adjust the clock at which another communication device (not shown) sends transmission symbols to the communication device 300. On the other hand, during the time-of-flight measurement process, the sampling phase of the ADC 324 is adjusted by the phase generator 380.

[0048] The phase generator 380 is configured to provide different sampling phases to the ADC 324 in conjunction with the reception of reverse pulses by the communication device 300, such that the ADC 324 uses different corresponding sampling phases in conjunction with different reverse pulses in the received reverse pulses. In an embodiment, the phase generator 380 is coupled to the pulse detector 360 and is configured to change the sampling phase in response to the pulse detector 360 detecting a reverse pulse. In an embodiment, the phase generator 380 changes the sampling phase in response to each reverse pulse detected by the pulse detector 360. In other embodiments, the phase generator 380 changes the sampling phase at some other suitable frequency, such as i) every Nth reverse pulse detected by the pulse detector 360, where N is a suitable integer greater than 1, ii) every M clock cycles, where M is a suitable positive integer, iii) a suitable time frequency, etc. In an embodiment, the phase generator 380 is configured to change the sampling phase by incrementing the sampling phase by a fixed amount at a suitable frequency such as those described above. In an embodiment, the phase generator 380 increments the sampling phase in a modulo fashion such that the sampling phase remains within a predetermined sampling phase range. For example, the phase generator 380 increments the sampling phase by a predetermined amount in a modulo fashion at a suitable frequency such as those described above.

[0049] In some embodiments, the timing measurement system 340 includes logic circuitry configured to perform actions such as those described above. For example, in some embodiments, the processor 372 includes logic circuitry, such as a hardware state machine, configured to perform actions corresponding to the processor 372 as described above. In other embodiments, the timing measurement system 340 further includes a processor that executes machine-readable instructions stored in a memory coupled to the processor, where the machine-readable instructions, when executed by the processor, cause the processor to perform actions such as those described above. For example, the processor 372 includes a processor that executes machine-readable instructions that, when executed by the processor, cause the processor to perform actions corresponding to the processor 372 as described above.

[0050] Figure 4 is a diagram illustrating an illustrative example of the sampling phase output by the phase generator 380 as a function of the amount of reverse pulses received by the communication device 300. In other embodiments, the phase generator 380 outputs other suitable sampling phases different from the Figure 4 example. As Figure 4 illustrated, as the number of reverse pulses increases, the sampling phase increases incrementally in a modulo fashion such that the sampling phase remains within a fixed sampling phase range.

[0051] Figure 5 is a simplified diagram of an example phase generator 500 according to an embodiment. In an embodiment, the phase generator 500 corresponds to Figure 3phase generator 380, and for purposes of explanation, reference is made to Figure 3 Description Figure 5 . In other embodiments, phase generator 380 has a suitable structure different from that of phase generator 500, and / or phase generator 500 is used in a suitable communication device different from communication device 300.

[0052] Phase generator 500 includes a multiplexer 504 having a first input set to zero and a second input set to a value that adjusts the sampling phase ("phase increment"). The select input of multiplexer 504 is coupled to the output of pulse detector 360. When pulse detector 360 does not detect a reverse pulse, multiplexer 504 outputs zero. On the other hand, when pulse detector 360 detects a reverse pulse, multiplexer 504 outputs the phase increment.

[0053] The output of multiplexer 504 is coupled to the first input of adder 508. The output of adder 508 is coupled to the input of register 512. The output of register 512 is coupled to the second input of adder 508.

[0054] In operation, phase generator 500 starts with an output of zero. Each time a reverse pulse is detected, the output of phase generator 500 increments by the phase increment. Due to the limited number of bits of adder 508 and register 512, the sampling phase (e.g., the output of register 512) wraps around in a manner similar to Figure 4 the illustrated sampling phase. Thus, in an embodiment, phase generator 500 increments the sampling phase in a modulo fashion such that the sampling phase remains within a fixed sampling phase range.

[0055] Referring again to Figure 3 , in other embodiments, phase generator 380 is configured to adjust the sampling phase in a different suitable manner such that the sampling phase output by phase generator 380 does not increment as described above with reference to Figure 4 and 5 described. For example, phase generator 380 adjusts the sampling phase such that the sampling phase output by phase generator 380 is similar to that described above with reference to Figure 4 and 5The modulo of the described method / apparatus decreases. As another example, according to an embodiment, the phase generator 380 adjusts the sampling phase in a predetermined manner (e.g., according to a pseudo-random sequence of different sampling phases, a repeated fixed sequence of different sampling phases, etc.) such that each sampling phase from the set of sampling phases is used in combination with detecting approximately an equal number of timing signals during the measurement (i.e., compared to any other sampling phase during the measurement process, a sampling phase is not used in combination with detecting more than one additional timing signal). In other words, according to an embodiment, each sampling phase is used in combination with detecting at least X timing signals during the measurement process, and a sampling phase is not used in combination with detecting more than X + 1 timing signals during the measurement process, where X is a suitable positive integer greater than 1.

[0056] As an illustrative example, according to an embodiment, the measurement process has a duration spanning multiple time intervals, and the phase generator 380 adjusts the sampling phase in a predetermined manner such that each sampling phase from the set of sampling phases is used in combination with detecting only an equal number (e.g., one, two, three, etc.) of timing signals during each time interval.

[0057] More generally, according to some embodiments, the measurement process has a duration spanning multiple time intervals, and the phase generator 380 adjusts the sampling phase such that each sampling phase from the set of sampling phases is used in combination with detecting only an equal number (e.g., one, two, three, etc.) of timing signals during each time interval.

[0058] Figure 6 is an atlas of multiple reverse pulses received by the communication device 300 when the ADC 324 uses different sampling phases according to an embodiment.

[0059] FIG. 604 illustrates reverse pulse 1 received when the ADC 324 uses a zero sampling phase. The rising edge of reverse pulse 1 appears between clock edge L and clock edge L + 1. As a result, reverse pulse 1 is not reflected in the output of the ADC 324 until clock edge L + 1, and the pulse detector 360 does not detect reverse pulse 1 until after clock edge L + 1.

[0060] FIG. 608 illustrates reverse pulse 2 received when the ADC 324 uses a sampling phase of Δ. Similarly, the rising edge of reverse pulse 2 appears between clock edge L and clock edge L + 1. As a result, reverse pulse 2 is not reflected in the output of the ADC 324 until clock edge L + 1, and the pulse detector 360 does not detect reverse pulse 2 until after clock edge L + 1.

[0061] Figure 612 illustrates reverse pulse 3 received when the ADC 324 uses a sampling phase of 2Δ. Similarly, the rising edge of reverse pulse 3 occurs between clock edge L and clock edge L+1. As a result, reverse pulse 3 is not reflected in the output of the ADC 324 until clock edge L+1, and the pulse detector 360 does not detect reverse pulse 3 until after clock edge L+1.

[0062] Figure 616 illustrates reverse pulse 4 received when the ADC 324 uses a sampling phase of 3Δ. Similarly, the rising edge of reverse pulse 4 occurs between clock edge L and clock edge L+1. As a result, reverse pulse 4 is not reflected in the output of the ADC 324 until clock edge L+1, and the pulse detector 360 does not detect reverse pulse 4 until after clock edge L+1.

[0063] Figure 620 illustrates reverse pulse 5 received when the ADC 324 uses a sampling phase of 4Δ. Now, the rising edge of reverse pulse 5 occurs before clock edge L. As a result, reverse pulse 5 is reflected in the output of the ADC 324 at clock edge L, and the pulse detector 360 detects reverse pulse 5 in conjunction with clock edge L.

[0064] Figure 624 illustrates reverse pulse 6 received when the ADC 324 uses a sampling phase of 5Δ. The rising edge of reverse pulse 6 occurs before clock edge L. As a result, reverse pulse 6 is reflected in the output of the ADC 324 at clock edge L, and the pulse detector 360 detects reverse pulse 6 in conjunction with clock edge L.

[0065] More generally, during the timing measurement process of adjusting the sampling phase of the ADC 324 as described above, m reverse pulses will be detected in conjunction with clock edge L, and n reverse pulses will be detected in conjunction with clock edge L+1, where the ratio of m to n varies depending on how far the reverse pulse appears from clock edge L when the sampling phase is zero.

[0066] The total measurement time with respect to receiving m + n reverse pulses can be expressed as:

[0067] (m*L + n*(L + 1))*T Equation 1

[0068] where T is the period of the sampling clock. The average time to receive each reverse pulse can be expressed as:

[0069] (L + n / (m + n))*T Equation 2

[0070] As can be seen from Equation 2, at least in some embodiments, adjusting the sampling phase of the ADC 324 as described above while receiving multiple reverse pulses provides a higher resolution time measurement compared to receiving multiple reverse pulses while keeping the sampling phase of the ADC 324 constant. For example, the term n / (m + n) indicates the position where a reverse pulse occurs between clock edges L and L+1 when the sampling phase is zero.

[0071] Figure 7 is a flowchart of an example method 700 for measuring the time of flight between a first communication device and a second communication device according to an embodiment. According to an embodiment, method 700 is implemented in the network 102 of the vehicle 100 of Figure 1 . Additionally or alternatively, in some embodiments, method 700 is implemented by a communication device having a structure similar to that of the communication device 300 of Figure 3 . For ease of explanation, reference is made to Figure 3 for description Figure 7 . In other embodiments, method 700 is implemented in another suitable vehicle different from the vehicle 100 of Figure 1 and / or in another suitable communication device different from the communication device 300 of Figure 3 .

[0072] At block 704, the first communication device receives an analog received signal via a communication medium. For example, the communication device 300 receives an analog received signal via the cable 320.

[0073] At block 708, the ADC of the first communication device converts the analog received signal into a digital received signal. For example, the ADC 324 converts the analog received signal received via the cable 320 into a digital received signal.

[0074] At block 712, the logic circuitry of the first communication device detects a plurality of timing signals from the second communication device based on analyzing the digital received signal. For example, the pulse detector 360 detects a plurality of reverse pulses from the second communication device based on analyzing the digital received signal output by the ADC 324. In other embodiments, the timing signal is a suitable signal other than a pulse. For example, in other embodiments, the timing signal includes a predetermined pattern and the logic circuitry includes correlation or autocorrelation circuitry for detecting the predetermined pattern.

[0075] At block 716, the logic circuitry adjusts the sampling phase of the ADC in combination with at least some of the timing signals such that when different timing signals among the timing signals are detected, the ADC uses different sampling phases. For example, the output of the phase generator 380 is used to adjust the sampling phase of the ADC 324.

[0076] At block 716, adjusting the sampling phase of the ADC includes adjusting the sampling phase in conjunction with detecting each of at least some of the timing signals. For example, the phase generator 380 adjusts the sampling phase in response to the pulse detector 360 detecting a reverse pulse. In an embodiment, the phase generator 380 increments the sampling phase by a predetermined amount in response to the pulse detector 360 detecting a reverse pulse. In an embodiment, the phase generator 380 increments the sampling phase in a modulo fashion such that the sampling phase remains within a fixed sampling phase range.

[0077] In an embodiment, at block 716, adjusting the sampling phase includes adjusting the sampling phase in response to each of the timing signals detected at block 712. In other embodiments, adjusting the sampling phase at block 716 includes adjusting the sampling phase at some other suitable frequency, such as i) every Nth timing signal detected at block 712, where N is a suitable integer greater than 1, ii) every M clock cycles, where M is a suitable positive integer, iii) a suitable time frequency, and the like.

[0078] In an embodiment, adjusting the sampling phase at block 716 includes incrementing the sampling phase by a fixed amount at a suitable frequency such as those described above. In an embodiment, the sampling phase is incremented in a modulo fashion such that the sampling phase remains within a fixed sampling phase range.

[0079] In an embodiment, adjusting the sampling phase at block 716 includes adjusting the sampling phase in response to each of at least some of the timing signals detected at block 712.

[0080] At block 720, when different timing signals among the timing signals are detected and when the ADC uses different sampling phases, the logic circuitry determines timing information based on detecting a plurality of timing signals at block 712. For example, the pulse counter 364 counts the detected reverse pulses, and the counter 376 measures the time period (e.g., number of clocks) during which the communication device 300 receives the detected reverse pulses.

[0081] At block 724, the first communication device determines the time of flight based on the timing information. For example, the processor 372 determines the time of flight based on the count of the detected reverse pulses (measured by the pulse counter 364) and the time period during which the communication device 300 receives the detected reverse pulses (measured by the counter 376).

[0082] In an embodiment, determining timing information at block 720 includes: at a logic circuit device, counting a timing signal detected by the logic circuit device and determining, at a first communication device, a time period until a plurality of timing signals are detected; and determining a time of flight at block 724 includes determining the time of flight based on i) the number of timing signals and ii) the time period. In an embodiment, determining the time period includes counting the number of cycles of a clock until a plurality of timing signals are detected; and determining the time of flight includes determining the time of flight based on i) the number of timing signals and ii) the number of cycles of the clock.

[0083] In another embodiment, the timing signal is a reverse timing signal; and method 700 further includes: at a first communication device, generating an analog transmit signal including a plurality of forward timing signals; and transmitting, by the first communication device, the analog transmit signal via a communication medium, wherein each forward timing signal prompts the second communication device to transmit a corresponding reverse timing signal.

[0084] In some embodiments, the clock phase provided to a communication device is adjusted in conjunction with transmitting forward timing signals, rather than adjusting the sampling phase of an ADC in conjunction with receiving a reverse timing signal.

[0085] Figure 8 is a simplified diagram of another exemplary communication device 800 according to another embodiment. In an embodiment, communication device 800 is used in Figure 2 network 200, and for purposes of explanation, reference is made to Figure 2 for description Figure 8 . For example, in an embodiment, communication device 800 corresponds to Figure 2 the first communication device 204. In other embodiments, the first communication device 204 has a suitable structure different from that of communication device 800, and / or communication device 800 is used in a suitable communication network different from network 200.

[0086] Communication device 800 is similar to Figure 3 communication device 300, and includes elements with similar numbers, and these elements are not described in detail for the sake of brevity.

[0087] Different from communication device 300, communication device 800 omits phase generator 380, and the input of switch 352 is changed to receive a constant phase input. During normal operation, switch 352 couples the output of receiving circuitry 312 to the sampling phase input of ADC 324, and receiving circuitry 312 controls the sampling phase of ADC 324 to adjust the clock at which another communication device (not shown) transmits transmit symbols to communication device 300. On the other hand, in an embodiment, during a time-of-flight measurement process, the sampling phase of ADC 324 is set to a fixed sampling phase.

[0088] Similarly different from the communication device 300, the communication device 800 includes a phase generator 824 having i) an input for receiving a clock, and ii) an output coupled to the clock input of the DAC 328. The phase generator 824 includes another input coupled to the pulse detector 360. According to an embodiment, during normal operation, the phase generator 824 passes the clock to the DAC 328 without adjusting the phase of the clock. On the other hand, during the time-of-flight measurement process, the phase generator 824 adjusts the clock phase provided to the DAC 328.

[0089] The phase generator 824 is configured to provide different clock phases to the DAC 328 in conjunction with the communication device 800 transmitting forward pulses, such that the DAC 328 uses different corresponding clock phases in conjunction with different forward pulses among the transmitted forward pulses. In an embodiment, the phase generator 824 is configured to change the clock phase in response to the pulse detector 360 detecting a reverse pulse. In an embodiment, the phase generator 824 changes the clock phase in response to each reverse pulse detected by the pulse detector 360. In other embodiments, the phase generator 824 changes the clock phase at some other suitable frequency, such as i) every N reverse pulses detected by the pulse detector 360, where N is a suitable integer greater than 1, ii) every M clock cycles, where M is a suitable positive integer, iii) a suitable time frequency, etc. In an embodiment, the phase generator 824 is configured to change the clock phase by incrementing the clock phase by a fixed amount at a suitable frequency such as those described above. In an embodiment, the phase generator 824 increments the clock phase in a modulo manner such that the clock phase remains within a predetermined clock phase range. For example, the phase generator 824 increments the clock phase in a modulo manner by a predetermined amount at a suitable frequency such as those described above.

[0090] In some embodiments, the timing measurement system 820 includes logic circuitry configured to perform actions such as those described above. For example, in some embodiments, the processor 372 includes logic circuitry, such as a hardware state machine, configured to perform actions corresponding to the processor 372 as described above. In other embodiments, the timing measurement system 820 further includes a processor that executes machine-readable instructions stored in a memory coupled to the processor, where the machine-readable instructions, when executed by the processor, cause the processor to perform actions such as those described above. For example, the processor 372 includes a processor that executes machine-readable instructions that, when executed by the processor, cause the processor to perform actions corresponding to the processor 372 as described above.

[0091] In an embodiment where another communication device transmits a reverse timing signal (e.g., a reverse pulse) in response to a forward timing signal (e.g., a forward pulse), when different forward timing signals in the forward timing signal are transmitted, the use of different phases of the clock by the DAC 328 affects the timing of the corresponding transmission of the corresponding reverse timing signal in a manner similar to that discussed above with reference to Figure 3 and Figure 6 which affects the timing of the corresponding transmission of the corresponding reverse timing signal.

[0092] Figure 9 FIG. 900 is a set of diagrams illustrating that the communication device 800 receives multiple reverse pulses in combination with the DAC 328 using different clock phases when transmitting the corresponding forward pulses that prompt the reverse pulses according to an embodiment.

[0093] FIG. 904 illustrates a reverse pulse 1 corresponding to the DAC 328, which uses a zero sampling phase in combination with transmitting a transmit pulse 1 that prompts the reverse pulse 1. The rising edge of the reverse pulse 1 appears between the clock edge L and the clock edge L + 1. As a result, the reverse pulse 1 is not reflected in the output of the ADC 324 until the clock edge L + 1, and the pulse detector 360 does not detect the reverse pulse 1 until after the clock edge L + 1.

[0094] FIG. 908 illustrates a reverse pulse 2 corresponding to the DAC 328, which uses a -Δ sampling phase in combination with transmitting a transmit pulse 2 that prompts the reverse pulse 2. Similarly, the rising edge of the reverse pulse 2 appears between the clock edge L and the clock edge L + 1. As a result, the reverse pulse 2 is not reflected in the output of the ADC 324 until the clock edge L + 1, and the pulse detector 360 does not detect the reverse pulse 2 until after the clock edge L + 1.

[0095] FIG. 912 illustrates a reverse pulse 3 corresponding to the DAC 328, and the DAC 328 uses a -2Δ sampling phase in combination with transmitting a transmit pulse 3 that prompts the reverse pulse 3. Similarly, the rising edge of the reverse pulse 3 appears between the clock edge L and the clock edge L + 1. As a result, the reverse pulse 3 is not reflected in the output of the ADC 324 until the clock edge L + 1, and the pulse detector 360 does not detect the reverse pulse 3 until after the clock edge L + 1.

[0096] FIG. 916 illustrates a reverse pulse 4 corresponding to the DAC 328, which uses a -3Δ sampling phase in combination with transmitting a transmit pulse 4 that prompts the reverse pulse 4. Similarly, the rising edge of the reverse pulse 4 appears between the clock edge L and the clock edge L + 1. As a result, the reverse pulse 4 is not reflected in the output of the ADC 324 until the clock edge L + 1, and the pulse detector 360 does not detect the reverse pulse 4 until after the clock edge L + 1.

[0097] Figure 920 illustrates a reverse pulse 5 corresponding to the DAC 328, and the DAC 328 uses a sampling phase of -4Δ in combination with a transmission pulse 5 that sends a prompt reverse pulse 5. Now, the rising edge of the reverse pulse 5 appears before the clock edge L. As a result, the reverse pulse 5 is reflected in the output of the ADC 324 at the clock edge L, and the pulse detector 360 detects the reverse pulse 5 in combination with the clock edge L.

[0098] Figure 924 illustrates a reverse pulse 6 corresponding to the DAC 328, and the DAC 328 uses a -5Δ sampling phase in combination with a transmission pulse 6 that sends a prompt reverse pulse 6. The rising edge of the reverse pulse 6 appears before the clock edge L. As a result, the reverse pulse 6 is reflected in the output of the ADC 324 at the clock edge L, and the pulse detector 360 detects the reverse pulse 6 in combination with the clock edge L.

[0099] More generally, during the timing measurement process of adjusting the sampling phase of the DAC 328 as described above, m reverse pulses will be detected in combination with the clock edge L, and n reverse pulses will be detected in combination with the clock edge L+1, where the ratio of m to n varies depending on how far the reverse pulse appears from the clock edge L when the sampling phase is zero.

[0100] The total measurement time (in clock cycles) for receiving m + n multiple reverse pulses can be expressed as indicated in Equation 1, and the average value of the time for receiving each reverse pulse (in clock cycles) can be expressed as indicated in Equation 2. It can be seen from Equation 2 that, at least in some embodiments, adjusting the clock phase of the DAC 328 as described above while sending multiple positive pulses provides a higher-resolution time measurement compared to sending multiple positive pulses while keeping the clock phase of the DAC 328 constant. For example, the term n / (m + n) indicates the position where the reverse pulse occurs between the clock edges L and L+1 when the sampling phase is zero.

[0101] Figure 10 is a flowchart of an example method 1000 for measuring the time of flight between a first communication device and a second communication device according to an embodiment. According to an embodiment, in Figure 1 the network 102 of the vehicle 100. Additionally or alternatively, in some embodiments, the method 1000 is implemented by a communication device having a structure similar to that of Figure 8 the communication device 800. For ease of explanation, reference is made to Figure 8 for description Figure 10 . In other embodiments, in another suitable vehicle different from Figure 1 the vehicle 100 and / or in Figure 8Implement method 1000 in another suitable communication device different from communication device 800.

[0102] In block 1004, the first communication device generates a digital transmission signal including a plurality of forward timing signals. For example, the pulse generator 368 generates a digital transmission signal including a plurality of forward pulses. In other embodiments, the forward timing signal is a suitable signal other than a pulse. For example, in other embodiments, the forward timing signal includes a predetermined pattern, and the first communication device includes circuitry configured to generate each forward signal according to the predetermined pattern.

[0103] In block 1008, the DAC of the first communication device generates an analog transmission signal based on the digital transmission signal. For example, the DAC 328 generates an analog transmission signal based on the digital transmission signal. According to an embodiment, the analog transmission signal is used for transmission via the cable 320. The analog transmission signal includes an analog version of the forward timing signal in the digital transmission signal.

[0104] In block 1012, the logic circuitry of the first communication device adjusts the clock phase provided to the DAC in combination with at least some of the forward timing signals such that when different forward timing signals in the forward timing signals are transmitted by the first communication device, the DAC uses different phases of the clock. Adjusting the phase of the clock in block 2008 is discussed further below.

[0105] In block 1016, the first communication device transmits the analog transmission signal via a communication medium. For example, the communication device 800 transmits the analog transmission signal via the cable 320. In an embodiment, the analog version of each forward timing signal prompts the second communication device to transmit a corresponding reverse timing signal. In an embodiment, when different analog versions in the analog version of the forward timing signal are transmitted, the use of different phases of the clock by the DAC affects the timing of the corresponding transmission of the corresponding reverse timing signal.

[0106] In block 1020, the first communication device receives an analog reception signal via the communication medium. For example, the communication device 800 receives the analog reception signal via the cable 320.

[0107] In block 1024, the ADC of the first communication device converts the analog reception signal into a digital reception signal. For example, the ADC 324 converts the analog reception signal received via the cable 320 into a digital reception signal.

[0108] At block 1028, the logic circuitry detects a plurality of reverse timing signals from a second communication device based on analyzing a digital received signal. For example, the pulse detector 360 detects a plurality of reverse pulses from the second communication device based on analyzing the digital received signal output by the ADC 324. In other embodiments, the timing signal is a suitable signal other than a pulse. For example, in other embodiments, the timing signal includes a predetermined pattern, and the logic circuitry includes a correlation or autocorrelation circuitry for detecting the predetermined pattern.

[0109] Referring again to block 1012, adjusting the phase of the clock provided to the DAC at block 1012 includes adjusting the phase of the clock in combination with each of the at least some detected reverse timing signals detected at block 1028. For example, the phase generator 380 adjusts the phase of the clock in response to the pulse detector 360 detecting a reverse pulse. In an embodiment, the phase generator 380 increments the phase of the clock by a predetermined amount in response to the pulse detector 360 detecting a reverse pulse. In an embodiment, the phase generator 380 increments the phase of the clock in a modulo fashion such that the phase of the clock remains within a predetermined clock phase range.

[0110] In an embodiment, adjusting the phase of the clock at block 1012 includes adjusting the phase of the clock in response to each of the detected reverse timing signals detected at block 1028. In other embodiments, adjusting the phase of the clock at block 1012 includes adjusting the clock phase at some other suitable frequency, such as i) every N detected reverse timing signals detected at block 1028, where N is a suitable integer greater than 1, ii) every M clock cycles, where M is a suitable positive integer, iii) a suitable time frequency, etc.

[0111] In an embodiment, adjusting the phase of the clock at block 1012 includes incrementing the phase of the clock by a fixed amount at a suitable frequency such as those described above. In an embodiment, the phase of the clock is incremented in a modulo fashion such that the phase of the clock remains within a predetermined sampling phase range.

[0112] In an embodiment, adjusting the phase of the clock at block 1012 includes adjusting the phase of the clock in response to each of the at least some detected reverse timing signals detected at block 1028.

[0113] At block 1032, the logic circuitry determines timing information based on the plurality of reverse timing signals detected at block 1028. For example, the pulse counter 364 counts the detected reverse pulses, and the counter 376 measures the time period (e.g., the number of clocks) during which the detected reverse pulses are received by the communication device 300.

[0114] At block 1036, the first communication device determines the time of flight based on the timing information determined at block 1032. For example, the processor 372 determines the time of flight based on the count of the detected reverse pulses (measured by the pulse counter 364) and the time period during which the detected reverse pulses are received by the communication device 800 (measured by the counter 376).

[0115] In an embodiment, determining the timing information at block 1036 includes: at the logic circuitry, counting the reverse timing signals detected by the logic circuitry and determining, at the first communication device, the time period until a plurality of reverse timing signals are detected; and determining the time of flight at block 1036 includes determining the time of flight based on i) the number of reverse timing signals and ii) the time period. In an embodiment, determining the time period includes counting the number of cycles of a clock until a plurality of reverse timing signals are detected; and determining the time of flight includes determining the time of flight based on i) the number of reverse timing signals and ii) the number of cycles of the clock.

[0116] Although the time of flight measurement techniques are described above for illustrative purposes in the context of a vehicular communication network, similar time of flight measurement techniques are also implemented in other suitable environments, such as industrial communication networks (e.g., within a processing plant, a manufacturing plant, etc.), sensor networks, remote sensing applications, indoor or outdoor positioning applications, and the like.

[0117] Some of the various blocks, operations, and techniques described above can be implemented using hardware, a processor executing firmware instructions, a processor executing software instructions, or any suitable combination thereof. When implemented using a processor executing software or firmware instructions, the software or firmware instructions can be stored in any suitable computer-readable memory, such as random access memory (RAM), read-only memory (ROM), solid-state memory (e.g., flash memory), and the like. The software or firmware instructions can include machine-readable instructions that, when executed by one or more processors, cause the one or more processors to perform various actions such as those described above.

[0118] Embodiment 1: A transceiver associated with a first communication device, comprising: an analog-to-digital converter (ADC) configured to generate a digital received signal based on an analog received signal received via a communication medium; a timing signal detection circuit coupled to the ADC, the timing signal detection circuit being configured to detect a plurality of timing signals from a second communication device based on analyzing the digital received signal; a sampling phase generation circuit coupled to the ADC, the sampling phase generation circuit being configured to adjust a sampling phase used by the ADC in combination with at least some of the timing signals such that when different timing signals among the timing signals are detected, the ADC uses different sampling phases; a timing information determination circuit configured to determine timing information based on the detection of the plurality of timing signals when different timing signals among the timing signals are detected and when the ADC uses different sampling phases; and a processor configured to determine a time of flight based on the timing information.

[0119] Embodiment 2: The transceiver according to Embodiment 1, wherein the sampling phase generation circuit is configured to adjust the sampling phase in combination with detecting each of at least some of the timing signals.

[0120] Embodiment 3: The transceiver according to Embodiment 2, wherein the sampling phase generation circuit is configured to adjust the sampling phase in response to detecting each of at least some of the timing signals.

[0121] Embodiment 4: The transceiver according to any one of Embodiments 1 to 3, wherein the sampling phase generation circuit is configured to adjust the sampling phase such that for each of a plurality of time intervals during a time-of-flight measurement period, each sampling phase from a set of a plurality of sampling phases is used by the ADC in combination with detecting only the same number of timing signals.

[0122] Embodiment 5: The transceiver according to Embodiment 4, wherein the sampling phase generation circuit is configured to adjust the sampling phase such that for each of a plurality of time intervals during a time-of-flight measurement period, each sampling phase from a set of a plurality of sampling phases is used by the ADC in combination with detecting only one corresponding timing signal.

[0123] Embodiment 6: The transceiver according to any one of Embodiments 1 to 5, wherein the sampling phase generation circuit is configured to adjust the sampling phase such that during a time-of-flight measurement period, each sampling phase from a set of a plurality of sampling phases is used by the ADC in combination with detecting at least X timing signals during a measurement process and not used by the ADC in combination with detecting more than X + 1 timing signals during the measurement process, where X is a suitable positive integer greater than 1.

[0124] Embodiment 7: The transceiver according to any one of Embodiments 1 to 6, wherein the sampling phase generation circuit means is configured to adjust the sampling phase by incrementing the sampling phase by the same amount in a modulo manner at least.

[0125] Embodiment 8: The transceiver according to any one of Embodiments 1 to 6, wherein the sampling phase generation circuit means is configured to adjust the sampling phase by decrementing the sampling phase by the same amount in a modulo manner at least.

[0126] Embodiment 9: The transceiver according to any one of Embodiments 1 to 8, wherein the sampling phase generation circuit means is configured to adjust the sampling phase according to a repetitive fixed sequence of different sampling phases.

[0127] Embodiment 10: The transceiver according to any one of Embodiments 1 to 6, wherein the sampling phase generation circuit means is configured to adjust the sampling phase pseudo-randomly.

[0128] Embodiment 11: The transceiver according to any one of Embodiments 1 to 10, wherein: the timing information determination circuit means includes a counter configured to count the timing signals detected by the timing signal detection circuit means; and the processor is configured to: determine the time period until a plurality of timing signals are detected, and determine the time of flight based on i) the number of timing signals and ii) the time period.

[0129] Embodiment 12: The transceiver according to Embodiment 11, wherein the counter is a first counter, and wherein: the processor includes a second counter configured to count the number of cycles of a clock until a plurality of timing signals are detected, the number of cycles of the clock indicating the time period; and the processor is configured to determine the time of flight based on i) the number of timing signals and ii) the number of cycles of the clock.

[0130] Embodiment 13: The transceiver according to any one of Embodiments 1 to 12, wherein the timing signal is a reverse timing signal, and wherein the transceiver further includes a transmission circuit means configured to: generate an analog transmission signal including a plurality of forward timing signals; and transmit the analog transmission signal via a communication medium, wherein each forward timing signal prompts the second communication device to transmit a corresponding reverse timing signal.

[0131] Embodiment 14: A communication system including the transceiver according to Embodiment 13, the communication system further including a second communication device.

[0132] Embodiment 15: A communication system including the transceiver according to any one of Embodiments 1 to 13 and / or the communication system according to Embodiment 14, the communication system further including a communication medium.

[0133] Example 16: A method for measuring the time of flight between a first communication device and a second communication device, the method comprising: at the first communication device, receiving an analog received signal via a communication medium; at an analog-to-digital converter (ADC) of the first communication device, converting the analog received signal into a digital received signal; at a logic circuit device of the first communication device, detecting a plurality of timing signals from the second communication device based on analyzing the digital received signal; at the logic circuit device, adjusting a sampling phase of the ADC in combination with at least some of the timing signals such that when different timing signals are detected, the ADC uses different sampling phases; at the logic circuit device, when different timing signals are detected and when the ADC uses different sampling phases, determining timing information based on the detection of the plurality of timing signals; and at the first communication device, determining the time of flight based on the timing information.

[0134] Example 17: The method according to Example 16, wherein adjusting the sampling phase of the ADC includes adjusting the sampling phase in combination with each of at least some of the detected timing signals.

[0135] Example 18: The method according to Example 17, wherein adjusting the sampling phase in combination with each of at least some of the detected timing signals includes adjusting the sampling phase in response to detecting each of at least some of the timing signals.

[0136] Example 19: The method according to any one of Examples 16 to 18, wherein adjusting the sampling phase of the ADC includes adjusting the sampling phase such that for each of a plurality of time intervals during a time-of-flight measurement period, each sampling phase from a set of a plurality of sampling phases is used by the ADC in combination with detecting only the same number of timing signals.

[0137] Example 20: The method according to Example 19, wherein adjusting the sampling phase of the ADC includes adjusting the sampling phase such that for each of a plurality of time intervals during a time-of-flight measurement period, each sampling phase from a set of a plurality of sampling phases is used by the ADC in combination with detecting only one corresponding timing signal.

[0138] Example 21: The method according to any one of Examples 16 to 20, wherein adjusting the sampling phase of the ADC includes adjusting the sampling phase such that during a time-of-flight measurement period, each sampling phase from a set of a plurality of sampling phases is used by the ADC in combination with detecting at least X timing signals during the measurement process, and the ADC does not use the sampling phase in combination with detecting more than X + 1 timing signals during the measurement process, where X is a suitable positive integer greater than 1.

[0139] Example 22: The method according to any one of Examples 16 to 21, wherein adjusting the sampling phase of the ADC includes adjusting the sampling phase by incrementing the sampling phase by the same amount in a modulo manner at least.

[0140] Example 23: The method according to any one of Examples 16 to 21, wherein adjusting the sampling phase of the ADC includes adjusting the sampling phase by decrementing the sampling phase by the same amount in a modulo manner at least.

[0141] Example 24: The method according to any one of Examples 16 to 23, wherein adjusting the sampling phase of the ADC includes adjusting the sampling phase according to a repeating fixed sequence of different sampling phases.

[0142] Example 25: The method according to any one of Examples 16 to 21, wherein adjusting the sampling phase of the ADC includes adjusting the sampling phase pseudo-randomly.

[0143] Example 26: The method according to any one of Examples 16 to 25, wherein: determining the timing information includes: at the logic circuit device, counting the timing signals detected by the logic circuit device, and determining, at the first communication device, the time period until a plurality of timing signals are detected; and determining the time of flight includes determining the time of flight based on i) the number of timing signals and ii) the time period.

[0144] Example 27: The method according to Example 26, wherein: determining the time period includes counting the number of cycles of a clock until a plurality of timing signals are detected; and determining the time of flight includes determining the time of flight based on i) the number of timing signals and ii) the number of cycles of the clock.

[0145] Example 28: The method according to any one of Examples 16 to 27, wherein the timing signal is a reverse timing signal, and wherein the method further includes: at the first communication device, generating an analog transmission signal including a plurality of forward timing signals; and transmitting, by the first communication device, the analog transmission signal via a communication medium, wherein each forward timing signal prompts the second communication device to transmit a corresponding reverse timing signal.

[0146] Example 29: The method according to any one of Examples 16 to 28, further including: at the second communication device, receiving a plurality of forward timing signals via the communication medium; at the second communication device, detecting at least some of the plurality of forward timing signals; and in response to receiving each of the at least some of the forward timing signals, transmitting, by the first communication device, a corresponding reverse timing signal.

[0147] Embodiment 30: A transceiver associated with a first communication device, comprising: a forward signal generation circuit device configured to generate a digital transmission signal including a plurality of forward timing signals; a digital-to-analog converter (DAC) configured to generate an analog transmission signal based on the digital transmission signal; a clock phase adjustment circuit device configured to adjust the clock phase provided to the DAC in combination with at least some of the forward timing signals such that when different forward timing signals among the forward timing signals are transmitted, the DAC uses different phases of the clock; a driver circuit device configured to transmit the analog transmission signal via a communication medium, wherein each forward timing signal prompts the second communication device to transmit a corresponding reverse timing signal, and wherein when different forward timing signals among the forward timing signals are transmitted, the use of different phases of the clock by the DAC affects the timing of the corresponding transmission of the corresponding reverse timing signal; an analog-to-digital converter (ADC) configured to generate a digital reception signal based on an analog reception signal received via the communication medium; a timing signal detection circuit device coupled to the ADC and configured to detect a plurality of reverse timing signals from the second communication device based on analyzing the digital reception signal; a timing information determination circuit device configured to determine timing information based on the detection of the plurality of reverse timing signals; and a processor configured to determine a time of flight based on the timing information.

[0148] Embodiment 31: The transceiver according to Embodiment 30, wherein the clock phase adjustment circuit device is configured to adjust the clock phase in combination with each of at least some of the forward timing signals transmitted by the transceiver.

[0149] Embodiment 32: The transceiver according to Embodiment 31, wherein the clock phase adjustment circuit device is configured to adjust the clock phase in response to each of at least some of the forward timing signals transmitted by the transceiver.

[0150] Embodiment 33: The transceiver according to Embodiment 30, wherein the clock phase adjustment circuit device is configured to adjust the clock phase in combination with each of at least some of the reverse timing signals detected by the timing signal detection circuit device.

[0151] Embodiment 34: The transceiver according to Embodiment 33, wherein the clock phase adjustment circuit device is configured to adjust the clock phase in response to each of at least some of the reverse timing signals detected by the timing signal detection circuit device.

[0152] Embodiment 35: The transceiver according to any one of Embodiments 30 to 34, wherein the clock phase adjustment circuit device is configured to adjust the clock phase such that for each of a plurality of time intervals during a time of flight measurement period, each phase from a set of a plurality of clock phases is used by the DAC in combination with transmitting only the same number of forward timing signals.

[0153] Example 36: The transceiver according to Example 35, wherein the clock phase adjustment circuit device is configured to adjust the clock phase such that for each of a plurality of time intervals during the time-of-flight measurement period, each phase from a set of a plurality of clock phases is used by the DAC in combination with transmitting only one positive timing signal.

[0154] Example 37: The transceiver according to any one of Examples 30 to 36, wherein the clock phase adjustment circuit device is configured to adjust the clock phase such that during the time-of-flight measurement period, each clock phase from a set of a plurality of clock phases is used by the DAC in combination with transmitting at least X positive timing signals during the measurement process, and a clock phase is not used by the DAC in combination with transmitting more than X + 1 positive timing signals during the measurement process, where X is a suitable positive integer greater than 1.

[0155] Example 38: The transceiver according to any one of Examples 30 to 37, wherein the clock phase adjustment circuit device is configured to adjust the clock phase at least by incrementing the clock phase by the same amount in a modulo manner.

[0156] Example 39: The transceiver according to any one of Examples 30 to 37, wherein the clock phase adjustment circuit device is configured to adjust the clock phase at least by decrementing the clock phase by the same amount in a modulo manner.

[0157] Example 40: The transceiver according to any one of Examples 30 to 39, wherein the clock phase adjustment circuit device is configured to adjust the clock phase according to a repeating fixed sequence of different clock phases.

[0158] Example 41: The transceiver according to any one of Examples 30 to 37, wherein the clock phase adjustment circuit device is configured to adjust the clock phase pseudo-randomly.

[0159] Example 42: The transceiver according to any one of Examples 30 to 41, wherein: the timing information determination circuit device includes a counter configured to count the reverse timing signals detected by the timing signal detection circuit device; and the processor is configured to: determine the time period until a plurality of reverse timing signals are detected, and determine the time of flight based on i) the number of reverse timing signals and ii) the time period.

[0160] Example 43: The transceiver according to Example 42, wherein the counter is a first counter, and wherein: the processor includes a second counter configured to count the number of cycles of the clock until a plurality of reverse timing signals are detected, the number of cycles of the clock indicating the time period; and the processor is configured to determine the time of flight based on i) the number of reverse timing signals and ii) the number of cycles of the clock.

[0161] Example 44: A communication system includes a transceiver according to any one of Examples 30 to 43, and the communication system further includes a second communication device.

[0162] Example 45: A communication system includes a transceiver according to any one of Examples 30 to 43 and / or the communication system of Example 44, and the communication system further includes a communication medium.

[0163] Example 46: A method for measuring the time of flight between a first communication device and a second communication device, the method comprising: at the first communication device, generating a digital transmission signal including a plurality of forward timing signals; at a digital-to-analog converter (DAC) of the first communication device, generating an analog transmission signal based on the digital transmission signal; at a logic circuit of the first communication device, adjusting a clock phase provided to the DAC in combination with at least some of the forward timing signals such that when different forward timing signals among the forward timing signals are transmitted, the DAC uses different phases of the clock; by the first communication device, transmitting the analog transmission signal via a communication medium, wherein each forward timing signal prompts the second communication device to transmit a corresponding reverse timing signal, and wherein when different forward timing signals among the forward timing signals are transmitted, the use of different phases of the clock by the DAC affects the timing of the corresponding transmission of the corresponding reverse timing signal; at the first communication device, receiving an analog reception signal via the communication medium; at an analog-to-digital converter (ADC) of the first communication device, converting the analog reception signal into a digital reception signal; at the logic circuit, detecting a plurality of reverse timing signals from the second communication device based on analyzing the digital reception signal; at the logic circuit, determining timing information based on the detection of the plurality of reverse timing signals; and at the first communication device, determining the time of flight based on the timing information.

[0164] Example 47: The method according to Example 46, wherein adjusting the clock phase provided to the DAC includes: adjusting the clock phase in combination with transmitting each of at least some of the forward timing signals.

[0165] Example 48: The method according to Example 47, wherein adjusting the clock phase provided to the DAC includes: adjusting the clock phase in response to transmitting each of at least some of the forward timing signals.

[0166] Example 49: The method according to Example 46, wherein adjusting the clock phase provided to the DAC includes adjusting the clock phase in combination with detecting each of at least some of the reverse timing signals.

[0167] Example 50: The method according to Example 49, wherein adjusting the clock phase in combination with detecting each of at least some of the reverse timing signals includes adjusting the clock phase in response to detecting each of at least some of the reverse timing signals.

[0168] Example 51: The method according to any one of Examples 46 to 50, wherein adjusting the clock phase includes adjusting the clock phase such that for each of a plurality of time intervals during the time-of-flight measurement period, each clock phase from a set of a plurality of clock phases is used by the DAC in combination with transmitting only the same number of forward timing signals.

[0169] Example 52: The method according to Example 51, wherein adjusting the clock phase includes adjusting the clock phase such that for each of a plurality of time intervals during the time-of-flight measurement period, each clock phase from a set of a plurality of clock phases is used by the DAC in combination with transmitting only one forward timing signal.

[0170] Example 53: The method according to any one of Examples 46 to 52, wherein adjusting the clock phase includes adjusting the clock phase such that during the time-of-flight measurement period, each clock phase from a set of a plurality of clock phases is used by the DAC in combination with transmitting at least X forward timing signals during the measurement process, and a clock phase is not used by the DAC in combination with transmitting more than X + 1 forward timing signals during the measurement process, where X is a suitable positive integer greater than 1.

[0171] Example 54: The method according to any one of Examples 46 to 53, wherein adjusting the clock phase includes adjusting the clock phase by incrementing the clock phase by the same amount in a modulo manner at least.

[0172] Example 55: The method according to any one of Examples 46 to 53, wherein adjusting the clock phase includes adjusting the clock phase by decrementing the clock phase by the same amount in a modulo manner at least.

[0173] Example 56: The method according to any one of Examples 46 to 55, wherein adjusting the clock phase includes adjusting the clock phase according to a repeating fixed sequence of different sampling phases.

[0174] Example 57: The method according to any one of Examples 46 to 53, wherein adjusting the clock phase includes adjusting the clock phase pseudo-randomly.

[0175] Example 58: The method according to any one of Examples 46 to 57, wherein: determining timing information includes: at a logic circuit device, counting reverse timing signals detected by the logic circuit device, and determining, at a first communication device, a time period until a plurality of reverse timing signals are detected; and determining a time of flight includes determining the time of flight based on i) the number of reverse timing signals and ii) the time period.

[0176] Example 59: The method according to Example 58, wherein: determining the time period includes counting the number of cycles of a clock until a plurality of reverse timing signals are detected; and determining the time of flight includes determining the time of flight based on i) the number of reverse timing signals and ii) the number of cycles of the clock.

[0177] Example 60: The method according to any one of Examples 46 to 59, further comprising: at a second communication device, receiving a plurality of forward timing signals via a communication medium; at the second communication device, detecting at least some of the plurality of forward timing signals; and in response to receiving each of the at least some of the forward timing signals, transmitting, by the first communication device, a corresponding reverse timing signal.

[0178] Example 61: A first communication device, comprising a transceiver configured to perform the method according to any one of Examples 46 to 60.

[0179] Example 62: A communication system, comprising a first communication device according to Example 61, the communication system further comprising a second communication device.

[0180] Example 63: A communication system, comprising a first communication device according to Example 61 and / or the communication system according to Example 62, the communication system further comprising a communication medium.

[0181] Example 64: A first communication device, comprising a transceiver configured to perform the method according to any one of Examples 16 to 29.

[0182] Example 65: A communication system, comprising a first communication device according to Example 64, the communication system further comprising a second communication device.

[0183] Example 66: A communication system, comprising a first communication device according to Example 64 and / or the communication system according to Example 65, the communication system further comprising a communication medium.

[0184] When implemented in hardware, the hardware may include one or more of discrete components, integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), etc.

[0185] Although the present invention has been described with reference to specific examples, which are intended to be illustrative only and not limiting of the present invention, changes, additions, and / or deletions may be made to the disclosed embodiments without departing from the scope of the present invention.

Claims

1. A transceiver associated with a first communication device, comprising: an analog-to-digital converter (ADC) configured to generate a digital received signal based on an analog received signal received via a communication medium; a timing signal detection circuit coupled to the ADC, the timing signal detection circuit being configured to detect a plurality of timing signals from a second communication device based on analyzing the digital received signal; a sampling phase generation circuit coupled to the ADC, the sampling phase generation circuit being configured to adjust a sampling phase used by the ADC in combination with at least some of the timing signals such that different sampling phases are used by the ADC when different ones of the timing signals are detected; a timing information determination circuit configured to determine timing information based on the detection of the plurality of timing signals when different ones of the timing signals are detected and when different sampling phases are used by the ADC; and a processor configured to determine the time of flight based on the timing information.

2. The transceiver according to claim 1, wherein the sampling phase generation circuit is configured to adjust the sampling phase in combination with each of the at least some of the timing signals detected.

3. The transceiver according to claim 2, wherein the sampling phase generation circuit is configured to adjust the sampling phase in response to detecting each of the at least some of the timing signals.

4. The transceiver according to claim 1, wherein: the timing information determination circuit includes a counter configured to count the timing signals detected by the timing signal detection circuit; and the processor is configured to: determine a period until a plurality of timing signals are detected, and determine the time of flight based on i) the number of the timing signals, and ii) the period.

5. The transceiver according to claim 4, wherein the counter is a first counter, and wherein: the processor includes a second counter configured to count the number of cycles of a clock until the plurality of timing signals are detected, the number of cycles of the clock indicating the period; and the processor is configured to determine the time of flight based on i) the number of the timing signals, and ii) the number of cycles of the clock.

6. The transceiver according to claim 1, wherein the timing signals are reverse timing signals, and wherein the transceiver further includes a transmission circuit configured to: generate an analog transmission signal including a plurality of forward timing signals; and transmit the analog transmission signal via the communication medium, wherein each forward timing signal prompts the second communication device to transmit a corresponding reverse timing signal.

7. A method for measuring the time of flight between a first communication device and a second communication device, the method comprising: at the first communication device, receiving an analog received signal via a communication medium; At an analog-to-digital converter (ADC) of the first communication device, convert the analog received signal into a digital received signal; At logic circuitry of the first communication device, detect a plurality of timing signals from the second communication device based on analyzing the digital received signal; At the logic circuitry, adjust a sampling phase of the ADC in combination with at least some of the timing signals such that when different ones of the timing signals are detected, the ADC uses different sampling phases; At the logic circuitry, when different ones of the timing signals are detected and when the ADC uses different sampling phases, determine timing information based on the detection of the plurality of timing signals; And At the first communication device, determine the time of flight based on the timing information.

8. The method according to claim 7, wherein adjusting the sampling phase of the ADC includes adjusting the sampling phase in combination with each of the at least some of the timing signals detected.

9. The method according to claim 8, wherein adjusting the sampling phase in combination with each of the at least some of the timing signals detected in the timing signal comprises: Adjust the sampling phase in response to detecting each of the at least some of the timing signals.

10. The method according to claim 7, wherein: Determining the timing information includes: At the logic circuitry, count the timing signals detected by the logic circuitry, and At the first communication device, determine a period until a plurality of timing signals are detected; and Determining the time of flight includes determining the time of flight based on i) the number of the timing signals, and ii) the period.

11. The method according to claim 10, wherein: Determining the period includes counting the number of cycles of a clock until the plurality of timing signals are detected; and Determining the time of flight includes determining the time of flight based on i) the number of the timing signals, and ii) the number of the cycles of the clock.

12. The method according to claim 7, wherein the timing signals are reverse timing signals, and wherein the method further includes: At the first communication device, generate an analog transmit signal including a plurality of forward timing signals; By the first communication device, transmit the analog transmit signal via the communication medium, wherein each forward timing signal prompts the second communication device to transmit a corresponding reverse timing signal.

13. A transceiver associated with a first communication device, comprising: Forward signal generation circuitry configured to generate a digital transmit signal including a plurality of forward timing signals; A digital-to-analog converter (DAC) configured to generate an analog transmit signal based on the digital transmit signal; Clock phase adjustment circuitry configured to adjust a clock phase provided to the DAC in combination with at least some of the forward timing signals such that when different ones of the forward timing signals are transmitted, the DAC uses different phases of the clock; A driver circuit device configured to transmit the analog transmission signal via the communication medium, wherein each forward timing signal prompts the second communication device to transmit a corresponding reverse timing signal, and wherein when different forward timing signals among the forward timing signals are transmitted, the use of different phases of the clock by the DAC affects the timing of the corresponding transmission of the corresponding reverse timing signal among the reverse timing signals; An analog-to-digital converter (ADC) configured to generate a digital reception signal based on an analog reception signal received via the communication medium; A timing signal detection circuit device coupled to the ADC, the timing signal detection circuit device configured to detect a plurality of reverse timing signals from the second communication device based on analyzing the digital reception signal; A timing information determination circuit device configured to determine timing information based on the detection of the plurality of reverse timing signals; And A processor configured to determine the time of flight based on the timing information.

14. The transceiver according to claim 13, wherein the clock phase adjustment circuit device is configured to adjust the clock phase in combination with each forward timing signal among at least some of the forward timing signals transmitted by the transceiver.

15. The transceiver according to claim 14, wherein the clock phase adjustment circuit device is configured to adjust the clock phase in response to each forward timing signal among at least some of the forward timing signals transmitted by the transceiver.

16. The transceiver according to claim 13, wherein the clock phase adjustment circuit device is configured to adjust the clock phase in combination with each reverse timing signal among at least some of the reverse timing signals detected by the timing signal detection circuit device.

17. The transceiver according to claim 16, wherein the clock phase adjustment circuit device is configured to adjust the phase of the clock in response to each reverse timing signal among at least some of the reverse timing signals detected by the timing signal detection circuit device.

18. The transceiver according to claim 13, wherein: The timing information determination circuit device includes a counter configured to count the reverse timing signals detected by the timing signal detection circuit device; and The processor is configured to: Determine a time period until a plurality of reverse timing signals are detected, and Determine the time of flight based on i) the number of the reverse timing signals, and ii) the time period.

19. The transceiver according to claim 18, wherein the counter is a first counter, and wherein: The processor includes a second counter configured to count the number of cycles of the clock until the plurality of reverse timing signals are detected, the number of cycles of the clock indicating the time period; and The processor is configured to determine the time of flight based on i) the number of the reverse timing signals, and ii) the number of cycles of the clock.

20. A method for measuring the time of flight between a first communication device and a second communication device, the method comprising: At the first communication device, generating a digital transmission signal including a plurality of forward timing signals; At a digital-to-analog converter (DAC) of the first communication device, generating an analog transmission signal based on the digital transmission signal; At a logic circuit of the first communication device, adjusting a clock phase provided to the DAC in combination with at least some of the forward timing signals such that when different forward timing signals among the forward timing signals are transmitted, the DAC uses different phases of the clock; By the first communication device, transmitting the analog transmission signal via the communication medium, wherein each forward timing signal prompts the second communication device to transmit a corresponding reverse timing signal, and wherein when different forward timing signals among the forward timing signals are transmitted, the use of the different phases of the clock by the DAC affects the timing of the corresponding transmission of the corresponding reverse timing signals among the reverse timing signals; At the first communication device, receiving an analog reception signal via the communication medium; At an analog-to-digital converter (ADC) of the first communication device, converting the analog reception signal into a digital reception signal; At the logic circuit, detecting a plurality of reverse timing signals from the second communication device based on analyzing the digital reception signal; At the logic circuit, determining timing information based on the detection of the plurality of reverse timing signals; And At the first communication device, determining the time of flight based on the timing information.

21. The method according to claim 20, wherein adjusting the phase of the clock supplied to the DAC comprises: Adjusting the phase of the clock in combination with each of the at least some of the forward timing signals among the forward timing signals.

22. The method according to claim 21, wherein adjusting the phase of the clock provided to the DAC comprises: Adjusting the phase of the clock in response to transmitting each of the at least some of the forward timing signals among the forward timing signals.

23. The method according to claim 20, wherein: Determining the timing information includes: At the logic circuit, counting the reverse timing signals detected by the logic circuit, and At the first communication device, determining a time period until a plurality of reverse timing signals are detected; and Determining the time of flight includes determining the time of flight based on i) the number of the reverse timing signals, and ii) the time period.

24. The method according to claim 23, wherein: Determining the time period includes counting the number of cycles of the clock until the plurality of reverse timing signals are detected; and Determining the time of flight includes determining the time of flight based on i) the number of the reverse timing signals, and ii) the number of cycles of the clock.

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