Double-channel access device for vertical three-dimensional memory

Abstract

Systems, methods, and apparatus are provided for dual channel access devices, dual storage node memory cells in vertical three-dimensional memory. The memory cell has a horizontally directed access device having a first source / drain region and a second source / drain region separated by a first channel region. The first channel is actuated by a first gate separated from the first channel region by a first gate dielectric. The access device further includes a third source / drain region and a fourth source / drain region separated by a second channel region. The second channel is actuated by a second gate separated from the second channel region by a second gate dielectric. The first and second gates are connected. A horizontal directional storage node is coupled to the second and / or fourth source / drain regions of the dual channel access device.

Description

Technical Field

[0001] The present disclosure generally relates to memory devices, and more particularly, to dual-channel access devices for vertical three-dimensional (3D) memory. Background Art

[0002] Memory is typically implemented in electronic systems such as computers, mobile phones, handheld devices, etc. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and may include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can provide persistent data by retaining stored data when not powered and may include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase change memory (such as phase change random access memory), resistive memory (such as resistive random access memory), cross-point memory, ferroelectric random access memory (FeRAM), or the like. Memory devices can be used in various electronic applications. Brief Description of the Drawings

[0003] Figure 1 is a schematic diagram showing a perspective view of an array of dual-channel access devices for vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0004] Figure 2 is a perspective view of a schematic diagram showing an array of dual-channel access devices for vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0005] Figure 3A is a perspective view showing a part of a unit cell of a dual-channel access device for vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0006] Figure 3B is a schematic diagram showing a perspective view of an array of dual-channel access devices for vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0007] Figure 4 shows a view of a semiconductor structure at a specific time in a manufacturing process according to several embodiments of the present disclosure.

[0008] Figures 5A to 5D shows several views of a semiconductor structure at a specific time in a manufacturing process according to several embodiments of the present disclosure.

[0009] Figures 6A to 6E shows several views of a semiconductor structure at a specific time in a manufacturing process according to several embodiments of the present disclosure.

[0010] Figures 7A to 7C Illustrate several views of a semiconductor structure at a specific time in a manufacturing process according to several embodiments of the present disclosure.

[0011] Figures 8A to 8B Illustrate several views of a semiconductor structure at a specific time in a manufacturing process according to several embodiments of the present disclosure.

[0012] Figures 9A to 9B Illustrate several views of a semiconductor structure at a specific time in a manufacturing process according to several embodiments of the present disclosure.

[0013] Figures 10A to 10B Illustrate several views of a semiconductor structure at a specific time in a manufacturing process according to several embodiments of the present disclosure.

[0014] Figures 11A to 11C Illustrate several views of a semiconductor structure at a specific time in a manufacturing process according to several embodiments of the present disclosure.

[0015] Figures 12A to 12D Illustrate several views of a semiconductor structure at a specific time in a manufacturing process according to several embodiments of the present disclosure.

[0016] Figures 13A to 13B Illustrate several views of a semiconductor structure at a specific time in a manufacturing process according to several embodiments of the present disclosure.

[0017] Figure 14 Illustrate views of a semiconductor structure at a specific time in a manufacturing process according to several embodiments of the present disclosure.

[0018] Figure 15 Is a block diagram of a device according to several embodiments of the present disclosure. Detailed Description

[0019] Embodiments of the present disclosure describe a dual-channel access device for vertical three-dimensional (3D) memory. In one embodiment, the dual-channel access device includes two transistors and a shared storage node (in the form of a capacitor) to form a dynamic random access memory (DRAM) cell in the 3D memory. In some embodiments, the dual-channel access device includes two transistors and two storage nodes (e.g., two capacitors) to form a 2-transistor 2-capacitor (2T2C) unit cell. The dual-channel access device is horizontally oriented and coupled to horizontally oriented storage nodes within the same plane (e.g., level) of the vertical 3D memory. The horizontally oriented transistors are integrated with horizontally oriented gates and integrated with vertically oriented digital lines. This provides good retention and scalability, in part due to the smaller horizontal area (e.g., footprint) of the memory cells of the vertical three-dimensional memory. Additionally, the dual-channel access device can provide a shared storage node, providing better retention compared to a 1-transistor 1-capacitor (1T1C) memory cell of the same size, and providing better signal margin for improved sensing performance.

[0020] As DRAM scaling becomes difficult, a fully 3D architecture is sought where multiple tiers can be formed together similar to 3D NAND. As the horizontal area (e.g., footprint) of the memory cells of the vertical three-dimensional memory decreases, the aspect ratio, staircase, and drivers are burdened. Additionally, the unit storage capacitance may become more negligible. There is a need to increase the access on-current (“Ion”) as there is uncertainty in variability, especially for a large number of tiers of 3D memory.

[0021] Embodiments described herein can achieve two times (“two times” or 2x) higher Ion and can provide 1.5x higher capacitance for a previous 3D vertical DRAM architecture at the same unit volume. Alternatively, according to specific scaled-size design rules, the architecture can achieve 2x higher Ion at the same unit capacitance, with the unit volume reduced by approximately twenty percent (20%). For example, for a specific design rule, the unit height can include an increase of approximately twenty-five percent (25%) in unit height, but the unit length is reduced by approximately forty percent (40%).

[0022] According to embodiments described herein, the dual-channel access device for 3D memory uses two channels to effectively double the channel width. In some embodiments, each channel is coupled to a smaller length storage node container (e.g., capacitor cell), thus having a smaller horizontal area footprint of the memory cell. This provides approximately 2x higher Ion improvement and approximately 1.2x capacitance improvement at the same Mbit density. The improved performance can be exploited in different ways, including trading 2x Ion improvement for greater than (>) 5x improvement in Ioff. In some embodiments, Vccp can be reduced to less than (<) approximately 1.8 volts (V), which can have a significant impact on high-voltage CMOS scaling and area efficiency (AE) improvement.

[0023] In addition, according to an embodiment, a dual-channel access device, a dual-storage-node memory cell can reduce the horizontal area consumed by a vertical three-dimensional (3D) vertical memory to improve scaling and 3D vertical storage density. Additionally, a shared storage node can improve the sensed signal margin relative to the same capacitor size in a 1 transistor 1 capacitor (1T1C) architecture. And as an additional benefit, the arrangement of a two-channel access device and a two-storage-node memory cell relaxes the "off-current" ("Ioff") requirement to reduce current leakage in the "off" state of the access device, while achieving equivalent charge storage retention for thin-film transistor (TFT) applications.

[0024] The figures in this document follow a numbering convention where the first or first few digits correspond to the figure number of the drawing and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures can be identified by using similar numbers. For example, reference numeral 223 can refer to Figure 2 the element "23" in Figure 2 and a similar element in FIG. 3 can be referred to as 323. Multiple similar elements within a single figure can be referred to by a reference numeral followed by a hyphen and another number or letter. For example, 207-1 can refer to

[0025] Figure 1 and 2 are schematic diagrams of portions of a vertical 3D memory according to several embodiments of the present disclosure. Figure 1 Illustrates a circuit diagram showing a cell array of a 3D semiconductor memory device according to an embodiment of the present disclosure, having vertically oriented digital lines (e.g., vertically oriented DLs 103-1, 103-2,..., 103-Q) oriented in a third direction (D3) 111 and horizontally oriented gates (e.g., word lines or access lines (ALs) 107-1, 107-2,..., 107-Q) oriented in a first direction (D1) 109.

[0026] Figure 1The illustrative cell array may have a plurality of sub - cell arrays 101 - 1, 101 - 2, …, 101 - N. The sub - cell arrays 101 - 1, 101 - 2, …, 101 - N may be arranged along a second direction (D2) 105. Each of the sub - cell arrays (e.g., sub - cell array 101 - 2) may include horizontally - oriented gates 107 - 1, 107 - 2, …, 107 - Q. Each of the sub - cell arrays may include vertically - oriented digit lines 103 - 1, 103 - 2, …, 103 - Q associated with each dual - channel access device memory cell. According to an embodiment, a first direction (D1) 109 and a second direction (D2) 105 may be considered to be in a horizontal (“X - Y”) plane. A third direction (D3) 111 may be considered to be in a vertical (“Z”) plane. Thus, according to the embodiments described herein, the horizontally - oriented gates 107 - 1, 107 - 2, …, 107 - Q (e.g., word lines or access lines (AL)) extend in a horizontal direction (e.g., the first direction (D1) 109).

[0027] A memory cell (e.g., 110) may include two transistors 115 - A and 115 - B oriented in the second direction (D2) 105 and a shared capacitor or a pair of capacitors 101 located at the intersection of horizontally - oriented gates 107 - 1, 107 - 2, …, 107 - Q (e.g., word lines (WL)) oriented in the first direction (D1) 109 and vertically - oriented digit lines 103 - 1, 103 - 2, …, 103 - Q oriented in the third direction (D3) 111. The memory cell may be written to or read using the horizontally - oriented gates 107 - 1, 107 - 2, …, 107 - Q and the vertically - oriented digit lines 103 - 1, 103 - 2, …, 103 - Q.

[0028] Figure 2 The illustration shows a circuit diagram of a cell array of a 3D semiconductor memory device according to an embodiment of the present disclosure, having vertically - oriented digit lines (DL) 203 - 1, 203 - 2, …, 203 - Q oriented in a third direction (D3) 211 and horizontally - oriented gates (e.g., horizontally - oriented WL) 207 - 1, 207 - 2, …, 207 - Q oriented in a first direction (D1) 209. Figure 2 is a perspective view of a portion of the sub - cell array 101 - 2 shown in Figure 1 as a vertically - oriented stack of memory cells in an array according to some embodiments of the present disclosure.

[0029] As Figure 2As shown in the exemplary embodiments, the vertically oriented memory cell array can extend in the vertical direction (e.g., the third direction (D3) 211). According to some embodiments, the vertically oriented memory cell stack can be fabricated such that memory cells are formed on a plurality of vertical tiers (e.g., the first tier 213-1 (L1), the second tier 213-2 (L2), and the third tier 213-Q (L3)).

[0030] Figures 3A to 3B is a perspective view showing a part of a semiconductor device according to several embodiments of the present disclosure. Figure 3A Illustrates an exemplary embodiment of a dual-channel access device unit cell having a horizontally oriented access device coupled to a horizontally oriented storage node. In Figure 3A the exemplary embodiments shown, each respective channel is separately coupled to a respective storage node within the unit cell. In this embodiment, the unit memory cell is formed as a 2 transistor 2 capacitor (2T2C) memory cell (e.g., Figure 1 110 in) within a sub-unit array 101-2 within the vertically stacked memory cell array (e.g., Figure 1 ). Figure 3B Illustrates an embodiment of multiple unit cells in multiple levels within a three-dimensional (3D) memory array.

[0031] In Figure 3A the exemplary embodiments, the unit cell includes a first source / drain region 321-A and a second source / drain region 323-A separated by a first channel region 325-A. The first channel region 325-A is controlled by a gate 307, which is separated from the first channel region 325-A by a gate dielectric 304. As Figure 3A further shown in the exemplary embodiments, the unit cell includes a third source / drain region 321-B separated from a fourth source / drain region 323-B by a second channel region 325-B. The second channel region 325-B of the dual-channel access device can also be controlled by the gate 307, which is separated from the second channel region 325-B by a gate dielectric 304. According to an embodiment, the gate 307 is shown as a horizontally oriented gate extending in the first direction (D1) 309. The first, second, third, and fourth source / drain regions 321-A, 323-A, 321-B, and 323-B can be impurity-doped regions and can be formed of n-type or p-type dopants. The embodiments are not limited thereto.

[0032] For example, for an n-type conductivity transistor structure, the body region of the access device and / or the dual channels 325-A and 325-B may be formed of a lightly doped (p-) p-type semiconductor material. In one embodiment, the dual channels 325-A and 325-B of the access device that separate the first, second, third, and fourth source / drain regions 321-A, 323-A, 321-B, and 323-B, respectively, may comprise a lightly doped p-type (e.g., low dopant concentration (p-)) polycrystalline silicon (Si) material, which consists of boron (B) atoms as impurity dopants of a semiconductor material (e.g., polycrystalline silicon and others). The dual channels 325-A and 325-B of the access device may also include a metal and / or metal composite material formed using an atomic layer deposition process or the like, which contains ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), highly doped degenerate semiconductor material, and / or indium oxide (In2O3) or indium tin oxide (In 2-x Sn x O3), or at least one of them. However, the embodiments are not limited to these examples. As used herein, degenerate semiconductor material is preferably meant to refer to a semiconductor material containing a high doping degree and a significant interaction between dopants (e.g., phosphorus (P), boron (B), etc.), such as polycrystalline silicon. In contrast, a non-degenerate semiconductor contains a medium doping degree, where dopant atoms are well separated from each other in the semiconductor host lattice and the interaction is negligible.

[0033] In some embodiments, the dual channels 325-A and 325-B may comprise silicon, germanium, silicon germanium, and / or indium gallium zinc oxide (IGZO). The gate dielectric material 304 may comprise, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, etc., or a combination thereof. The embodiments are not limited thereto. For example, in the case of a high-k dielectric material example, the gate dielectric material 304 may comprise one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0034] For an n-type conductivity transistor structure, the first, second, third, and fourth source / drain regions 321-A, 323-A, 321-B, and 323-B may comprise a high dopant concentration, n-type conductivity impurity (e.g., high dopant (n+) or (n++)) doped in the source / drain regions. In some embodiments, the high dopant, n-type conductivity first, second, third, and fourth source / drain regions 321-A, 323-A, 321-B, and 323-B may comprise a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the dual channels 325-A and 325-B of the access device may be of n-type conductivity structure, in which case the conductivity type of the impurity (e.g., dopant) will be reversed.

[0035] As Figure 3A shown in the example embodiments of, the dual channels 325-A and 325-B of the access device are separately coupled to corresponding storage nodes within a unit cell. However, the embodiments are not limited thereto, and in other embodiments, the dual channels 325-A and 325-B of the access device may share a common storage node. As Figure 3A shown in the example embodiments of, the first electrode (e.g., bottom electrode (BE)) 361-A of the first horizontally oriented storage node is coupled to the second source / drain region 323-A of the dual-channel access device. The first electrode (e.g., bottom electrode (BE)) 361-B of the second horizontally oriented storage node is coupled to the fourth source / drain region 323-B of the dual-channel access device. As Figure 3A shown in the embodiments of, the cell dielectric 363 separates the first electrodes 361-A and 361-B from the second electrode (e.g., top electrode (TE)) 356. As Figure 3A shown in the embodiments of, the second electrode 356 may be a common electrode 356. Additionally, as Figure 3A shown in the embodiments of, the first source / drain region 321-A and the third source / drain region 321-A of the dual-channel access device are coupled to the vertically oriented digital line 303.

[0036] Thus, in the example embodiments shown in Figure 3A , the first and second channels 325-A and 325-B of the dual-channel access device are formed in a dual-gate structure having a top gate portion vertically above the first channel 325-A and a bottom gate portion vertically below the first channel 325-A. Similarly, the dual-gate structure includes a top gate portion vertically above the second channel 325-B and a bottom gate portion vertically below the second channel 325-B. In this embodiment, the top gate portion of the first channel 325-A is shared as the bottom gate portion of the second channel 325-B, as a shared gate portion between the first channels 325-A. In this way, the dual-channel 325-A and 325-B access device can be regarded as having a first horizontal gate portion, a second horizontal gate portion, and a third horizontal gate portion. The first, second, and third horizontal gate portions are electrically coupled together to form a two-sided gate (G2S) structure and / or a gate-all-around (GAA) structure on opposite sides of the first and second horizontal channel regions 325-A and 325-B, respectively.

[0037] Since the second horizontal gate is shared as the top portion of the first channel 325-A and the bottom portion of the second channel 325, in some embodiments, the second horizontal gate has a vertical height (h2) that is less than the vertical height (h1) of the first horizontal gate and less than the vertical height (h3) of the third horizontal gate. When actuated, the second horizontal gate portion reverses the conduction paths in two opposite sides of the first and second horizontal channel regions 325-A and 325-B to double the width of the conduction paths in the first and second horizontal channel regions 325-A and 325-B.

[0038] As Figure 3A shown in the embodiments of, the first and second channel regions 325-A and 325-B have a first horizontal length (L1) and the first and second horizontal storage nodes have a second horizontal length (L2). According to some embodiments, the second horizontal length (L2) is at least twenty-five percent (25%) shorter than the storage node length, which is used to maintain an equal storage capacitance value relative to the same horizontal memory device layout architecture with only single-channel horizontal access devices using the same set of operating parameters. Additionally, the first and second channel regions 325-A and 325-B can have a cumulative channel width that doubles the on-current (“Ion”) value relative to the same horizontal memory device layout architecture with only single-channel horizontal access devices using the same set of operating parameters. In some embodiments, the power operating voltage (“Vccp”) of the dual-channel access device of the memory device is less than 2.0 volts. In some embodiments, the dual-channel horizontally oriented access device forms the first and second horizontally oriented thin film transistors (TFTs), and the first and second horizontally oriented storage nodes are horizontally oriented capacitors located in the same horizontal level for forming a dual-transistor dual-capacitor (2T2C) memory cell. However, the embodiments are not limited thereto, and in some embodiments, the first and second horizontally oriented storage nodes are horizontally oriented ferroelectric storage nodes.

[0039] Figure 3B is a perspective view illustrating a vertical dual-channel memory cell array for 3D memory according to an embodiment of the present disclosure. As Figure 3B shown, vertically stacked horizontally oriented dual-channel access devices, a dual-storage node memory cell array can be provided in a vertically oriented three-dimensional (3D) multi-level (e.g., multi-tier) 313-1, 313-2, …, 313-N memory array, where each tier 313-1, 313-2, …, 313-N has dual-channel, horizontally oriented access devices and first and second horizontally oriented storage nodes. As Figure 3AAs described, each memory cell includes a first source / drain region 321-1A, 321-2A, ..., 321-QA and a second source / drain region 323-1A, 323-2A, ..., 323-QA separated by a first channel region 325-1A, 325-2A, ..., 325-QA. The first channel regions 325-1A, 325-2A, ..., 325-QA are operatively controlled by horizontal gates 307-1, 307-2, ..., 307-Q that extend in a first direction (D1) 309 along rows within levels 313-1 (L1), 313-2 (L2), ..., 313-Q (L3) of the vertically oriented memory cells. The horizontal gates 307-1, 307-2, ..., 307-Q are separated from the first channel regions 325-1A, 325-2A, ..., 325-QA by gate dielectrics 304-1, 304-2, ..., 304-Q. A third source / drain region 321-1B, 321-2B, ..., 321-QB and a fourth source / drain region 323-1B, 323-2B, ..., 323-QB are separated by a second channel region 325-1B, 325-2B, ..., 325-QB operatively controlled by the horizontal gates 307-1, 307-2, ..., 307-Q and are separated from the second channel regions 325-1B, 325-2B, ..., 325-QB by gate dielectrics 304-1, 304-2, ..., 304-Q.

[0040] As Figure 3BAs shown in the embodiments, the first electrodes 361-1A, 361-2A, 361-QA of the first horizontally oriented storage nodes are coupled to the second source / drain regions 323-1A, 323-2A, …, 323-QA of the first horizontally oriented channels 325-1A, 325-2A, …, 325-QA. In addition, the first electrodes 361-1B, 361-2B, …, 361-QB of the second horizontally oriented storage nodes are coupled to the fourth source / drain regions 323-1B, 323-2B, …, 323-QB of the second horizontal channels 325-1B, 325-2B, …, 325-Q. The cell dielectric 363 separates the first electrodes 361-1A, 361-2A, 361-QA and 361-1B, 361-2B, …, 361-QB from the second electrodes 356-1, 356-2, …, 356-Q (e.g., the top electrode (TE)), and the second electrodes can be the common electrodes (CE) of a column of vertically oriented memory cells in the third direction (D3) 311. The vertical digit lines 303-1, 303-2, …, 303-Q are coupled to the first source / drain regions 321-1A, 321-2A, …, 321-QA of the first horizontally oriented channels 325-1A, 325-2A, …, 325-QA and the third source / drain regions 321-1B, 321-2B, …, 321-QB of the second horizontal channels in the columns of the vertically oriented memory cells in the third direction (D3) 311.

[0041] As Figure 3A described, the gate structures 307-1, 307-2, …, 307-Q extending along the rows within the levels 313-1 (L1), 313-2 (L2), …, 313-Q (L3) of the vertically oriented memory cells and in the first direction (D1) 309 can be electrically coupled together and form a gate-all-around (GAA) structure opposite to the first and second horizontal channels 325-1A, 325-2A, …, 325-QA and 325-1B, 325-2B, …, 325-Q along the rows within each level 313-1 (L1), 313-2 (L2), …, 313-Q (L3). When actuated, the GAA structure reverses the conduction paths in the opposite sides of the first and second horizontal channels 325-1A, 325-2A, …, 325-QA and 325-1B, 325-2B, …, 325-Q to double the width of the conduction paths in the first and second horizontal channels 325-1A, 325-2A, …, 325-QA and 325-1B, 325-2B, …, 325-Q.

[0042] As combined with Figures 4 to 12. Further described, embodiments of the dual-channel access device described herein may have a total vertical height (ht) of less than one hundred and fifty (150) nanometers (nm). The second horizontal gate (e.g., the middle gate) between the first and second horizontal channels 325-1A, 325-2A, …, 325-QA and 325-1B, 325-2B, …, 325-Q may have a vertical height (h2) of less than ten (10) nanometers (nm). And the first and second horizontal channels 325-1A, 325-2A, …, 325-QA and 325-1B, 325-2B, …, 325-Q may each individually have a vertical height (hc1 / hc2) of less than fifteen (15) nanometers (nm). In some embodiments, the first and second horizontally oriented storage nodes each have a horizontal length (L2) of less than three hundred (300) nanometers (nm). And in some embodiments, the first and second horizontally oriented storage nodes each have a horizontal length (L2) of less than two hundred (200) nanometers (nm). However, the embodiments are not limited to these examples, and other design rule dimensions are included within the scope of the embodiments.

[0043] Figure 4 is a cross-sectional view of an example embodiment of a semiconductor device manufacturing process of a dual-channel access device for a memory cell in a vertical 3D memory. In Figure 4In the embodiments shown, the semiconductor device manufacturing process includes depositing alternating layers of a first dielectric material 430-1, 430-2, …, 430-N (collectively referred to herein as the “first” dielectric material “430”), a second dielectric material 433-1A, 433-2A, …, 433-NA, a first semiconductor material 432-1A, 432-2A, …, 432-NA, a third dielectric material 429-1, 429-2, …, 429-N (the third dielectric material, sometimes collectively referred to herein as the third dielectric material “429”), a second semiconductor material 432-1B, 432-2B, …, 432-NB (the first and second semiconductor materials, sometimes collectively referred to herein as “semiconductor material 432”), and a fourth dielectric material 433-1B, 433-2B, …, 433-NB (the second and fourth dielectric materials, sometimes collectively referred to herein as “second dielectric material 433”) in repeating iterations to form a vertical stack 416 on the working surface of a substrate 400. The alternating materials in the repeating vertical stack 416 can be separated from the substrate 400 by an insulator material 420. In one embodiment, the first dielectric material 430 can be deposited to have a thickness in the range of twenty (20) nanometers (nm) to sixty (60) nm, such as a vertical height in the third direction (D3). In one embodiment, the semiconductor material 432 can be deposited to have a thickness in the range of twenty (20) nm to one hundred (100) nm, such as a vertical height. In one embodiment, the second dielectric material 433 can be deposited to have a thickness in the range of ten (10) nm to thirty (30) nm, such as a vertical height. In one embodiment, the second dielectric material 429 can be deposited to have a thickness in the range of five (5) nm to twenty (20) nm, such as a vertical height. However, the embodiments are not limited to these examples. As Figure 4 shown, the vertical direction 411 is illustrated as the third direction (D3), such as the z direction in an x-y-z coordinate system.

[0044] In some embodiments, the first dielectric materials 430-1, 430-2, …, 430-N can be interlayer dielectrics (ILDs). By way of example and not limitation, the first dielectric materials 430-1, 430-2, …, 430-N can include oxide materials such as SiO2. In another example, the first dielectric materials 430-1, 430-2, …, 430-N can include silicon nitride (Si3N4) materials (also referred to herein as “SiN”). In another example, the first dielectric materials 430-1, 430-2, …, 430-N can include silicon oxycarbide (SiO x C y ) materials. In another example, the first dielectric materials 430-1, 430-2, …, 430-N can include silicon oxynitride (SiO x N y) The material (also referred to as "SiON" herein) and / or its combinations. The embodiments are not limited to these examples. According to an embodiment, the first dielectric material 430 can be selectively etched relative to the second and third dielectric materials 433 and 429.

[0045] In some embodiments, the semiconductor materials 432-1, 432-2, …, 432-N can include silicon (Si) materials in polycrystalline and / or amorphous states. The semiconductor material 432 can be a low-doped p-type (p-) silicon material. The semiconductor material 432 can be formed by doping boron atoms (B) as an impurity dopant in a low concentration in the gas phase to form a low-doped p-type (p-) silicon material. The low-doped p-type (p-) silicon material can be a polysilicon material. However, the embodiments are not limited to these examples.

[0046] In some embodiments, the second dielectric material 433 can include a nitride material. The nitride material can be a silicon nitride (Si3N4) material (also referred to as "SiN" herein). In another example, the second dielectric material 433 can include a silicon oxycarbide (SiOC) material. In another example, the second dielectric material 433 can contain silicon oxynitride (SiON) and / or its combinations. The embodiments are not limited to these examples. However, according to an embodiment, the second dielectric material 433 is intentionally selected to be different in material or composition from the first dielectric material 430 and the third dielectric material 429, such that a selective etching process can be performed on one of the first, second, and third dielectric layers, selected relative to the others of the first, second, and third dielectric layers. For example, the second dielectric material 433 can be selectively etched relative to the semiconductor material 432, the first dielectric material 430, and the third dielectric material 429.

[0047] The alternating first dielectric materials 430-1, 430-2, …, 430-N, second dielectric materials 433-1A, 433-2A, …, 433-NA, first semiconductor materials 432-1A, 432-2A, …, 432-NA, third dielectric materials 429-1, 429-2, …, 429-N, second semiconductor materials 432-1B, 432-2B, …, 432-NB, and fourth dielectric materials 433-1B, 433-2B, …, 433-NB layers can be deposited in a semiconductor manufacturing apparatus according to a semiconductor manufacturing process such as chemical vapor deposition (CVD). However, the embodiments are not limited to this example and other suitable semiconductor manufacturing techniques can be used to deposit alternating layers of the first dielectric material 430, second dielectric material 433-A, first semiconductor material 432-A, third dielectric material 429, second semiconductor material 432-B, and fourth dielectric material 433-B in the iterative process to form the vertical stack 416.

[0048] The layers can occur vertically in the iterative process. In Figure 4In an example, three levels (numbered 1, 2, and N) of repetitive iterations from 1 to N, 413-1, 413-2, …, 413-N are shown. However, the embodiments are not limited to the number “N” of levels. For example, in some embodiments, fifty (50) or more levels (N≥50) may be included. However, the embodiments are not limited to this example and may include more or fewer repetitive iterations.

[0049] Figures 5A to 5D A view of a semiconductor device in fabrication in another stage of a semiconductor device manufacturing process according to several embodiments of the present disclosure.

[0050] Figure 5A A top view illustrating an example method for forming a vertically stacked memory cell array having a dual-channel access device for a vertical three-dimensional (3D) memory in another stage of a semiconductor manufacturing process. In one embodiment, the array includes two access devices and two storage nodes per unit cell, the unit cell being formed by a horizontally oriented access device, a horizontally oriented storage node, and a horizontally oriented access line (e.g. Figure 1 as illustrated in 3) and according to several embodiments of the present disclosure. In Figure 5A an example embodiment, the method includes using a lithography process to pattern a lithography mask 535. Figure 5A The method in further illustrates using one or more etchant processes to form a vertical opening 551 through the vertical stack and extending primarily in a first horizontal direction (D1) 509 in a storage node region. The one or more etchant processes form the vertical opening 551 to expose sidewalls which, in a repetitive iteration of alternating layers of a first dielectric material 530-1, 530-2, …, 530-N, a second dielectric material 533-1A, 533-2A, …, 533-NA, a first semiconductor material 532-1A, 532-2A, …, 532-NA, a third dielectric material 529-1, 529-2, …, 529-N, a second semiconductor material 532-1B, 532-2B, …, 532-NB, and a fourth dielectric material 533-1B, 533-2B, …, 533-NB, are in Figures 5B to 5D the vertical stack shown in, adjacent the storage node region of the semiconductor material.

[0051] In some embodiments, this process may be performed after the access device semiconductor manufacturing process described in conjunction with FIGS. 9-12. However, Figures 5B to 5D the embodiment shown in illustrates a sequence of performing the storage node manufacturing process “before access device formation”.

[0052] Figure 5B Illustrating along Figure 5AA cross-sectional view taken along the cut line A-A' therein, showing another view of the semiconductor structure at this point in an exemplary semiconductor manufacturing process of an embodiment of the present disclosure. According to Figure 5B In this exemplary embodiment shown, the method includes forming a first vertical opening 551 in a vertical stack ( Figure 4 shown in), and selectively etching a first semiconductor material 532-1A, 532-2A, …, 532-NA and a second semiconductor material 532-1B, 532-2B, …, 532-NB in a storage node region to form a first horizontal opening 579 that retreats a first horizontal distance (L1) from the vertical opening 551 in the vertical stack ( Figure 4 ). According to an embodiment, selectively etching the storage node region of the first semiconductor material 532-1A, 532-2A, …, 532-NA and the second semiconductor material 532-1B, 532-2B, …, 532-NB may include using an atomic layer etching (ALE) process. However, the embodiment is not limited to this example.

[0053] Figure 5C Illustrates a cross-sectional view taken along Figure 5A the cut line A-A' therein, showing another view of the semiconductor structure at another point in an exemplary semiconductor manufacturing process of an embodiment of the present disclosure. As Figure 5C shown in the exemplary embodiment of, source / drain regions 523-1A and 523-1B, 523-2A and 523-2B, …, 523-NA and 523-NB (e.g., second and fourth source / drain regions) may be formed in the first semiconductor material 532-1A, 532-2A, …, 532-NA and the second semiconductor material 532-1B, 532-2B, …, 532-NB at an end of the first horizontal opening 579 away from the vertical opening 551.

[0054] The source / drain regions 523-1A and 523-1B, 523-2A and 523-2B, …, 523-NA and 523-NB may be formed by vapor doping dopants into edge surface portions of the semiconductor material 532. In some embodiments, the source / drain regions 523-1A and 523-1B, 523-2A and 523-2B, …, 523-NA and 523-NB may be adjacent to a channel region. In one example, vapor doping may be used to achieve highly isotropic (e.g., non-directional) doping to form the second and fourth source / drain regions 523-1A and 523-1B, 523-2A and 523-2B, …, 523-NA and 523-NB of a horizontally oriented access device region. In another example, thermal annealing using a doping gas (e.g., phosphorus) may be used in conjunction with high-energy plasma assistance to break the bond. However, the embodiment is not limited to this and other suitable semiconductor manufacturing techniques may be utilized.

[0055] According to one example embodiment, as Figure 5C shown, dopants can be introduced into the first semiconductor materials 532-1A, 532-2A, …, 532-NA and the second semiconductor materials 532-1B, 532-2B, …, 532-NB by flowing a high-energy gas-phase dopant (e.g., phosphorus (P) for n-type transistors) into the vertical and horizontal openings 551 and 579 to dope the dopants at the end of the first horizontal opening 579 away from the vertical opening 551, thereby forming the second and fourth source / drain regions 523-1A and 523-1B, 523-2A and 523-2B, …, 523-NA and 523-NB.

[0056] As Figure 5C shown, the vertical direction 511 is illustrated as the third direction (D3), e.g., the z-direction in an x-y-z coordinate system, similar to Figure 1 the third direction (D3) 111 among the first, second, and third directions shown in FIG. 3. The drawing plane extending left and right is on the second direction (D2) 505 along the orientation axis of the horizontal access device and the horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory. In Figure 5C the example embodiment, the materials within the vertical stack (e.g., the repetitive iteration of alternating layers of the first dielectric materials 530-1, 530-2, …, 530-N, the second dielectric materials 533-1A, 533-2A, …, 533-NA, the first semiconductor materials 532-1A, 532-2A, …, 532-NA, the third dielectric materials 529-1, 529-2, …, 529-N, the second semiconductor materials 532-1B, 532-2B, …, 532-NB, and the fourth dielectric materials 533-1B, 533-2B, …, 533-NB) extend in and out of the drawing plane in the first direction (D1).

[0057] Figure 5D Illustrates a cross-sectional view taken along the Figure 5A cutting line A-A' in FIG., which shows another view of the semiconductor structure at this point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 5DThe cross-sectional view shown is illustrated as extending left and right in the drawing plane along a second horizontal direction (D2) 505, along repeating iterations of alternating layers of a first dielectric material 530-1, 530-2, …, 530-N, a second dielectric material 533-1A, 533-2A, …, 533-NA, a first semiconductor material 532-1A, 532-2A, …, 532-NA, a third dielectric material 529-1, 529-2, …, 529-N, a second semiconductor material 532-1B, 532-2B, …, 532-NB, and a fourth dielectric material 533-1B, 533-2B, …, 533-NB, the alternating layers extending in and out of the drawing plane in a first direction (D1) and in which horizontally oriented access devices and horizontally oriented storage nodes (such as capacitor cells) may be formed within the layers of the first semiconductor material 532-1A, 532-2A, …, 532-NA and the second semiconductor material 532-1B, 532-2B, …, 532-NB.

[0058] In Figure 5D an example embodiment of, vertical openings 551 and horizontal openings 579 are shown to be formed by the mask, patterning, and etching processes described in conjunction with Figure 5B . As Figure 5D shown, the first semiconductor material 532-1A, 532-2A, …, 532-NA and the second semiconductor material 532-1B, 532-2B, …, 532-NB in the storage node region have been selectively removed to form the horizontal openings 579.

[0059] As Figure 5D further shown in an embodiment of, the second dielectric material 533-1A, 533-2A, …, 533-NA and the fourth dielectric material 533-1B, 533-2B, …, 533-NB may be selectively removed a first horizontal distance (L1) from the first vertical opening 551 to expand the first horizontal opening 579. In one example, an atomic layer etching (ALE) process may be used to selectively remove the second dielectric material 533-1A, 533-2A, …, 533-NA and the fourth dielectric material 533-1B, 533-2B, …, 533-NB a first horizontal distance (L1) from the first vertical opening 551 to selectively etch the second dielectric material 533-1A, 533-2A, …, 533-NA and the fourth dielectric material 533-1B, 533-2B, …, 533-NB a first horizontal distance (L1) from the first vertical opening 551.

[0060] As Figure 5DAs shown in the embodiments, the first electrode 561 (e.g., the bottom electrode) may then be deposited in the first vertical opening 551 and the first horizontal opening, in direct electrical contact with the source / drain regions 523-1A and 523-1B, 523-2A and 523-2B, …, 523-NA and 523-NB (e.g., the second and fourth source / drain regions) of the first semiconductor materials 532-1A, 532-2A, …, 532-NA and the second semiconductor materials 532-1B, 532-2B, …, 532-NB formed at the distal ends of the first horizontal opening 579. In one example embodiment, atomic layer deposition (ALD) may be used to conformally deposit the first electrode 561. However, the embodiments are not limited to this example.

[0061] It should be noted that the source / drain region references enumerated herein to denote two separate and distinct source / drain regions, the source / drain regions referred to as “first,” “second,” “third,” and / or “fourth” source / drain regions are not intended to have any particular meaning. It is only desired to illustrate that the source / drain regions on one side of the channel region may be connected to a digital line (e.g., 107-2) and the other source / drain regions on the other side of the channel may be connected to a storage node.

[0062] Figure 5D Further illustrate filling the first vertical opening 551 and the first horizontal opening 579 with a fifth dielectric 538. In one example embodiment, the fifth dielectric material 538 may be an oxide or other suitable spin-on dielectric (SOD). In some embodiments, the fifth dielectric material 538 may be the same type of dielectric material as that used for the first dielectric material 530. However, the embodiments are not limited thereto. In another embodiment, the fifth dielectric material 538 may include a nitride material. In another embodiment, the fifth dielectric material 538 may include a silicon nitride (Si3N4) material (also referred to herein as “SiN”). In another embodiment, the fifth dielectric material 538 may comprise a silicon dioxide (SiO2) material. In another embodiment, the fifth dielectric material 538 may include a silicon oxycarbide (SiO x C y ) material and / or a combination thereof. The embodiments are not limited to these examples.

[0063] Figures 6A to 6D Illustrate an example method for forming a vertically stacked memory cell array of dual-channel access devices for vertical three-dimensional (3D) memories, such as those described in FIGS. Figure 1 1 to 3, in another stage of a semiconductor manufacturing process.

[0064] Figure 6A Illustrate a top view of a semiconductor structure at a particular point in time during a semiconductor manufacturing process. In Figure 6AIn an example embodiment, the method includes using a lithography process to pattern a lithography mask 636. Figure 6A The method in [reference] further illustrates using one or more etchant processes to form a plurality of vertical openings 600-1, 600-2, …, 600-N, such as a second vertical opening, through a vertical stack (shown in [reference]) in first (D1) 609 and second (D2) 605 directions. The second vertical opening 600 is illustrated as extending primarily in the second horizontal direction (D2) 605. Figure 4 As shown in [reference], one or more etchant processes form vertical openings 600 in a vertical stack rising in a third vertical direction (D3) 611 in a repeating iteration of alternating layers of a first dielectric material 630-1, 630-2, …, 630-N, a second dielectric material 633-1A, 633-2A, …, 633-NA, a first semiconductor material 632-1A, 632-2A, …, 632-NA, a third dielectric material 629-1, 629-2, …, 629-N, a second semiconductor material 632-1B, 632-2B, …, 632-NB, and a fourth dielectric material 633-1B, 633-2B, …, 633-NB to fill with a sixth dielectric 639 to separate a first electrode 661 in a first horizontal opening in a first horizontal direction (D1) 609.

[0065] As Figure 6A shown in [reference].

[0066] Figure 6B Illustrates a structure in an example embodiment at this particular point in a semiconductor manufacturing process taken along cut line A-A' in [reference]. Figure 6A Illustrates a structure in an example embodiment at this particular point in a semiconductor manufacturing process taken along cut line B-B' in [reference]. Figure 6C Illustrates along Figure 6A Illustrates a structure in an example embodiment at this particular point in a semiconductor manufacturing process taken along cut line C-C' in [reference]. Figure 6D Illustrates along Figure 6A Illustrates a structure in an example embodiment at this particular point in a semiconductor manufacturing process taken along cut line D-D' in [reference]. Figure 6E Illustrates along Figure 6A Illustrates a structure in an example embodiment at this particular point in a semiconductor manufacturing process taken along cut line D-D' in [reference].

[0067] Figures 7A to 7C Illustrates an example method for forming a vertical stack memory cell array for a dual-channel access device for vertical three-dimensional (3D) memory, such as those illustrated in [reference] to [reference], in another stage of a semiconductor manufacturing process in accordance with several embodiments of the present disclosure. Figure 1 to [reference] for a vertical three-dimensional (3D) memory.

[0068] Figure 7AShows a top view of a semiconductor structure at a specific point in a semiconductor manufacturing process according to one or more embodiments. In Figure 7A In an example embodiment, the method includes using a lithography process to pattern a lithography mask 735. Figure 7A The method in Figure 7B further illustrates using one or more etchant processes to selectively remove a fifth dielectric 538 (FIG. 5) from an original first vertical opening 751 extending in a first direction (D1) 1205 and a first horizontal opening (

[0069] Figure 7B Illustrates a structure in an example embodiment at this specific point in a semiconductor manufacturing process taken along a Figure 7A cutting line A-A' in Figure 7C Illustrates a structure in an example embodiment at this specific point in a semiconductor manufacturing process taken along a Figure 7A cutting line B-B' showing the separation of a first electrode 761 in

[0070] As shown taken along the Figure 7A cutting line A-A' in Figure 7B shown in Figure 5A a selective etch process with masking reopens a first vertical opening ( Figure 5B 551 in

[0071] Figures 8A to 8B Illustrates an example method for forming a vertical stacked memory cell array having, for example, a dual-channel access device for a vertical three-dimensional (3D) memory as described in Figure 1 to 3 at another stage of a semiconductor manufacturing process according to several embodiments of the present disclosure.

[0072] Figure 8A Illustrates a cross-sectional view taken along a Figure 7A cutting line A-A' at a specific point in a semiconductor manufacturing process according to one or more embodiments. In Figure 8A an example embodiment, the method includes depositing a second electrode 856 separated by a cell dielectric 863. Figure 8BIllustrate along Figure 7A a cross-sectional view taken along the cutting line B-B' in

[0073] In one embodiment, the cell dielectric 863 can be conformally deposited on the first electrode 861 (also referred to as the bottom electrode (BE)) in the first vertical opening, the first horizontal opening, and other exposed surfaces. In one embodiment, the cell dielectric 863 can be a high-K dielectric, as described herein, which is conformally deposited to a thickness (t1) in the range of about 2 to 10 nanometers (nm). However, the embodiments are not limited to this example thickness. Other suitable thicknesses can be achieved.

[0074] In one embodiment, the second electrode 856 can be deposited on the cell dielectric 863 in the first vertical opening, the first horizontal opening, and other exposed surfaces by chemical vapor deposition (CVD) or other suitable techniques to fill the first vertical opening. In some embodiments, the second electrode 856 can also be referred to as the top electrode (TE), the common electrode (CE), and / or the top plate electrode. However, the embodiments are not limited to these examples. Other suitable semiconductor manufacturing techniques and / or memory node structures can be used, such as ferroelectric cells.

[0075] Figures 9A to 9B Illustrate an example method for forming a vertically stacked memory cell array of dual-channel access devices for vertical three-dimensional (3D) memories such as those described in Figure 1 to 3 in another stage of a semiconductor manufacturing process.

[0076] Figure 9A Illustrate a top view of a semiconductor structure at a specific point in time in a semiconductor manufacturing process. In Figure 9A an example embodiment of, the method includes using a lithography process to pattern a lithography mask 936. Figure 9A The method in

[0077] Figure 9B Illustrate along Figure 9A a cross-sectional view taken along the cutting line A-A' in Figure 9B As illustrated in Figures 6A to 6D the etchant process can also selectively remove the sixth dielectric (from

[0078] Figures 10A to 10B Illustrate a structure in an example embodiment at the next specific point in a semiconductor manufacturing process. Figure 10A is a cross-sectional view taken along Figure 9A the cutting line A-A' inFigure 10A In an example embodiment, a selective etching process can be used to horizontally recess the first, second, and third dielectric materials 1033-1A, 1029-1 and 1033-1B, 1033-2A, 1029-2 and 1033-2B, 1033-NA, 1029-N and 1033-NB to form openings above and below the first and second semiconductor materials 1032-1A and 1032-1B, 1032-2A and 1032-2B, …, 1032-NA and 1032NB that are a second distance (L2) from the third vertical opening 1070. Figure 10B Illustrates a cross-sectional view taken along Figure 9A the cut line C-C' in

[0079] In Figures 10A to 10B an example embodiment, the method can include flowing a selective etchant into the third vertical opening 1070 to selectively etch portions of the first and third dielectric materials 1033-A and 1033-B and the second dielectric material 1029. For example, the etchant can flow into the second vertical opening 1070 to selectively etch the nitride materials 1033-A and 1033-B and selectively etch the oxide material 1029. The etchant can be for all iterations of the first and third dielectric materials 1033-A and 1033-B and the second dielectric material 1029 within the stack. Thus, the etchant can be for the first and third nitride materials 1033-A and 1003-B and the second oxide material 1029 within the stack.

[0080] The selective etchant process can consist of one or more etch chemistries selected from aqueous etch chemistries, semi-aqueous etch chemistries, vapor etch chemistries, or plasma etch chemistries and other possible selective etch chemistries. For example, a dry etch chemistry of oxygen (O2) or O2 and sulfur dioxide (SO2) (O2 / SO2) can be utilized. As another example, a dry etch chemistry of O2 or O2 and nitrogen (N2) (O2 / N2) can be used to selectively etch the first and third dielectric materials 1033-A and 1033-B and the second dielectric material 1029. Alternatively or additionally, the selective etching for removing the first and third dielectric materials 1033-A and 1033-B and the second dielectric material 1029 can include the selective etch chemistries phosphoric acid (H3PO4) or hydrogen fluoride (HF) and / or the use of selective solvents (such as NH4OH or HF) and other possible etch chemistries or solvents to dissolve the first and third dielectric materials 1033-A and 1033-B and the second dielectric material 1029. The embodiments are not limited to these examples.

[0081] The selective etchant process can etch nitride material and / or oxide materials 1033 and 1029 to form a second horizontal opening 1073. The selective etchant process can be performed such that the second horizontal opening 1073 has a length or depth (L2) that is a second distance 1076 from the second vertical opening 1070. The first and third dielectric materials 1033-A and 1033-B and the second dielectric material 1029 can be etched back a second distance (L2) 1076 in the range of about fifty (50) to one hundred and fifty (150) nanometers (nm) from the second vertical opening 1070. The second distance (L2) 1076 can be controlled by controlling the time, the composition of the etchant gas, and the etch rate of the reactive gas flowing into the second vertical opening 1070, such as rate, concentration, temperature, pressure, and time parameters. The selective etch can be isotropic, but is selective with respect to the first and third dielectric materials 1033-A and 1033-B and the second dielectric material 1029. In this example, the second horizontal opening 1073 will have a height (H1) that is substantially equal to the thickness to which the first and third dielectric layers 1033-A and 1033-B and the second dielectric material 1029 (e.g., nitride and / or oxide materials) are deposited and is controlled by that thickness. However, the embodiments are not limited to this example.

[0082] Figures 11A to 11C Illustrates an example method for forming a vertically stacked memory cell array of a dual-channel access device for a vertical three-dimensional (3D) memory, such as that described in FIGS. Figure 1 to 3, in another stage of a semiconductor manufacturing process.

[0083] Figure 11A Illustrates a top view of a semiconductor structure at a particular point in time in a semiconductor manufacturing process for depositing a conductive gate material on a gate dielectric, according to one or more embodiments.

[0084] Figure 11B Illustrates a cross-sectional view taken along Figure 11A the cut line A-A' in FIGS. In Figure 11BIn the illustrated example embodiment, the gate dielectric material 1138 may be deposited in the plurality of second horizontal openings 1173 created by etching the first, third, and second dielectric materials 1133-A, 1133-B, and 1129. The gate dielectric material 1138 may be conformally deposited around the first and second semiconductor materials 1132-1A and 1132-1B, 1132-2A and 1132-2B, …, 1132-NA and 1132NB. The gate dielectric material 1138 may be conformally deposited in the plurality of second horizontal openings 1173 using a chemical vapor deposition (CVD) process, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition process to cover the first and second semiconductor materials 1132-1A and 1132-1B, 1132-2A and 1132-2B, …, 1132-NA and 1132NB. By way of example and not limitation, the gate dielectric 1138 may include a silicon dioxide (SiO2) material, an aluminum oxide (Al2O3) material, a high dielectric constant (k) (e.g., high-k) dielectric material, and / or combinations thereof.

[0085] As Figure 11B illustrated in the example embodiment of, the first conductive materials 1177-1, 1177-2, …, 1177-N (collectively the first conductive material 1177) may be deposited on the gate dielectric material 1138 around the first and second semiconductor materials 1132-1A and 1132-1B, 1132-2A and 1132-2B, …, 1132-NA and 1132NB. The first conductive material 1177 may be deposited completely around each surface of the semiconductor material to form a gate-all-around (GAA) gate structure at the channel regions of the first and second semiconductor materials 1132-1A and 1132-1B, 1132-2A and 1132-2B, …, 1132-NA and 1132NB.

[0086] The first conductive material 1177 may be conformally deposited into a portion of the second vertical opening 1170 using a chemical vapor deposition (CVD) process, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition process such that the first conductive material 1177 is deposited completely into the second horizontal opening 1173.

[0087] In some embodiments, the first conductive material 1177 may include one or more of a doped semiconductor (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.) and / or some other combination thereof, as also described in FIG. 3. The first conductive material 1177 with the gate dielectric material 1138 may form a horizontally oriented access line opposite to the channel region of the semiconductor material, e.g., as shown as access lines 103-1, 103-2, …, 103-Q (which may also be referred to as word lines) in Figure 1 FIG. 3. Figure 11C Illustrates a cross-sectional view taken along Figure 11A cutting line B-B' in FIG.

[0088] Figures 12A to 12D Illustrates an example method for forming a vertically stacked memory cell array of dual-channel access devices for a vertical three-dimensional (3D) memory as illustrated in FIGS. Figure 1 3 in another stage of a semiconductor manufacturing process.

[0089] Figure 12A Illustrates a cross-sectional view taken along Figure 11A cutting line A-A' in FIG. Figure 12A The cross-sectional view shown in FIG. illustrates that the first conductive material 1277 may be recessed in the second horizontal opening 1273, e.g., etched from the third vertical opening 1270 using atomic layer etching (ALE) or other suitable techniques. In some instances, the first conductive material 1277 may be etched back a third distance (L3) 1283 in the horizontal opening 1273 into the successive second horizontal opening 1273. In some embodiments, the first conductive material 1277 may be etched back a third distance 1283 in the horizontal opening 1273 from the third vertical opening 1270 in the range of twenty (20) to fifty (50) nanometers (nm). The first conductive material 1277 may be selectively etched to keep the gate dielectric material 1238 intact.

[0090] Figure 12B Illustrates an example embodiment of the structure at another point in time in a semiconductor manufacturing process. Figure 12B is a cross-sectional view taken along Figure 11A cutting line A-A' in FIG. As shown in the embodiment of Figure 12B FIG., another dielectric material 1284 may be deposited to fill the second horizontal opening 1273 from the recessed first conductive material 1277 and conformally fill at least the vertical sidewalls of the third vertical opening 1270.

[0091] In some embodiments, the "another dielectric material" (e.g., 1284) may be the same or different material as the first, second, and third dielectric materials 1233 and 1229. For example, the dielectric material may be Si3N4. In another example, the dielectric material may include silicon dioxide (SiO2) material. In another example, the dielectric material may include silicon oxycarbide (SiO x C y ) material. In another example, the dielectric material may comprise silicon oxynitride (SiO x N y ) and / or combinations thereof. The embodiments are not limited to these examples.

[0092] Figure 12C is a cross-sectional view taken along the Figure 11A cutting line A-A' in Figure 12C illustrates that the dielectric 1284 can be etched to be removed from the vertical sidewalls of the third vertical opening 1270. Selective etching can also be performed to remove the gate dielectric from the vertical sidewalls of the third vertical opening 1270.

[0093] Figure 12D is also a cross-sectional view taken along the Figure 11A cutting line A-A' in for forming a vertical stacked memory cell array having a dual-channel access device for vertical three-dimensional (3D) memory in another stage of a semiconductor manufacturing process. As shown in the example embodiment of Figure 12D , a gas-phase doping process can then be used to form first source / drain regions 1221-1A and 1221-1B, 1221-2A and 1221-2B,..., 1221-NA and 1221NB in the exposed vertical surfaces of the first and second semiconductor materials 1232-1A and 1232-1B, 1232-2A and 1232-2B,..., 1232-NA and 1232-NB. The third vertical opening can then be refilled with another dielectric (e.g., 1284) as described above.

[0094] Figures 13A to 13B illustrates several views of an example method for forming a vertical stacked memory cell array having a dual-channel access device for vertical three-dimensional (3D) memory, such as that illustrated in Figure 1 to 3, in another stage of a semiconductor manufacturing process according to several embodiments of the present disclosure.

[0095] Figure 13A illustrates a top view of a semiconductor structure at a particular point in time during a semiconductor manufacturing process according to one or more embodiments. In Figure 13AIn an example embodiment, the method includes using a lithography process to pattern a lithography mask 1336 to form a plurality of patterned third vertical openings that pass through a vertical stack and are adjacent to a first source / drain region 1321, and depositing a second conductive material 1341 in the first source / drain region 1321 to form vertically oriented digital lines 1341 and 1371.

[0096] Figure 13B Illustrates a cross-sectional view taken along Figure 13A cutting line A-A' in. As Figure 13B illustrated in, the method further illustrates using one or more etchant processes to form a plurality of patterned third vertical openings that pass through a vertical stack and are adjacent to first source / drain regions 1321-1A and 1321-1B, 1321-2A and 1321-2B, …, 1321-NA and 1321-NB. As Figure 13B shown in, in some example embodiments, a highly doped semiconductor material as the second conductive material 1341 can be vertically formed in the third vertical opening 1370. The second conductive material 1341 can be in direct electrical contact with the first source / drain regions 1321-1A and 1321-1B, 1321-2A and 1321-2B, …, 1321-NA and 1321-NB. The second conductive material 1341 can be a high-concentration n-type doped polysilicon material. For example, a high-concentration n-type dopant can be formed by depositing a high-phosphorus (P)-doped (n+-type) polysilicon germanium (SiGe) material as the second conductive material 1341.

[0097] In some embodiments, the first source / drain regions 1321-1A and 1321-1B, 1321-2A and 1321-2B, …, 1321-NA and 1321-NB can be formed by diffusing an n-type (n+) dopant outward into the first and second semiconductor materials 1332-1A and 1332-1B, 1332-2A and 1332-2B, …, 1332-NA and 1332-NB. For example, the plurality of patterned third vertical openings can be adjacent to the first source / drain regions 1321-1A and 1321-1B, 1321-2A and 1321-2B, …, 1321-NA and 1321-NB, and an annealing process can be used to diffuse the high-concentration n-type dopant outward into the lightly doped first and second semiconductor materials 1332-1A and 1332-1B, 1332-2A and 1332-2B, …, 1332-NA and 1332-NB to form the first source / drain regions 1321-1A and 1321-1B, 1321-2A and 1321-2B, …, 1321-NA and 1321-NB.

[0098] In some embodiments, the second conductive material 1341 may include a titanium / nitride titanium (TiN) second conductive material 1341. The TiN second conductive material 1341 may be annealed to form titanium silicide having first source / drain regions 1321-1A and 1321-1B, 1321-2A and 1321-2B, …, 1321-NA and 1321-NB for a dual-channel access device of a vertical three-dimensional (3D) memory.

[0099] As Figure 13B shown in the example embodiment of, the method may further include depositing a third conductive material 1371 (e.g., a metal layer) on the titanium / nitride titanium (TiN) second conductive material 1341, which forms titanium silicide having first source / drain regions 1321-1A and 1321-1B, 1321-2A and 1321-2B, …, 1321-NA and 1321-NB in a plurality of patterned third vertical openings 1370 to fill and form a bilayer vertically oriented digital line 1341 and 1371. In some embodiments, depositing the metal layer 1371 may include depositing a cobalt (Co) material layer 1371 on the titanium / nitride titanium (TiN) second conductive material 1341, which forms titanium silicide having first source / drain regions 1321-1A and 1321-1B, 1321-2A and 1321-2B, …, 1321-NA and 1321-NB for a dual-channel access device of a vertical three-dimensional (3D) memory.

[0100] In some embodiments, depositing the metal layer 1371 on the second conductive material 1341 may include depositing a ruthenium (Ru) material 1371. In some embodiments, depositing the metal layer 1371 on the second conductive material 1341 may include depositing a tungsten (W) material 1371. Depositing the metal layer 1371 may include chemical vapor deposition or other suitable deposition techniques. However, the embodiments are not limited to these examples.

[0101] Figure 14 Illustrates another cross-sectional view taken along Figure 13A cutting line A-A' in, which shows a complete dual-channel access device for a vertical three-dimensional (3D) memory having a horizontally oriented access device and a horizontally oriented storage node. As Figure 14 shown in the example embodiment of, the dual-channel access device for a vertical three-dimensional (3D) includes a horizontally oriented access line 1477 and vertically oriented digital lines 1441 and 1471.

[0102] Figure 15 is a block diagram of a device according to several embodiments of the present disclosure. Figure 15FIG. 0 is a block diagram of an apparatus in the form of a computing system 1507 that includes a memory device 1508, according to several embodiments of the present disclosure. As used herein, for example, the memory device 1508, the memory array 1510, and / or the host 1501 may also be individually regarded as an “apparatus”. According to an embodiment, the memory device 1501 may include at least one memory array 1510 having memory cells formed with dual-channel access devices for vertical three-dimensional (3D), the dual-channel access devices including a horizontally oriented access device coupled to a horizontally oriented storage node and including a horizontally oriented access line and a vertically oriented digital line.

[0103] In this example, the system 1507 includes a host 1501 coupled to the memory device 1508 via an interface 1513. The computing system 1507 may be a personal laptop computer, a desktop computer, a digital camera, a mobile phone, a memory card reader, or an Internet of Things (IoT)-enabled device, as well as various other types of systems. The host 1501 may include several processing resources capable of accessing the memory 1508, such as one or more processors, microprocessors, or some other type of control circuitry. The system 1507 may include a separate integrated circuit, or both the host 1501 and the memory device 1508 may be on the same integrated circuit. For example, the host 1501 may be a system controller of a memory system that includes multiple memory devices 1508, where the system controller 1509 provides access to the corresponding memory devices 1508 through another processing resource such as a central processing unit (CPU).

[0104] In the example shown in FIG. 8, the host 1501 is responsible for executing an operating system (OS) and / or various application programs (e.g., processes) that may be loaded into it from the memory device 1508 (e.g., via the controller 1509). The OS and / or various application programs may be loaded from the memory device 1508 by providing access commands from the host 1501 to the memory device 1508 to access data including the OS and / or various application programs. The host 1501 may also access data utilized by the OS and / or various application programs by providing access commands to the memory device 1508 to retrieve the data utilized in the execution of the OS and / or various application programs.

[0105] For clarity, system 1507 has been simplified to focus on features particularly relevant to the present disclosure. Memory array 1510 can be a DRAM array, which includes at least one memory cell having digital lines and body contacts formed according to the techniques described herein. For example, memory array 1510 can be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 1510 can include memory cells arranged in rows coupled by word lines (which can be referred to herein as access lines or select lines) and columns coupled by digital lines (which can be referred to herein as sense lines or data lines). Although a single array 1510 is shown in FIG. 8, embodiments are not limited thereto. For example, memory device 1508 can include several arrays 1510, such as several banks of DRAM cells.

[0106] Memory device 1501 includes address circuitry 1503 to latch address signals provided through interface 1513. The interface can include, for example, a physical interface employing a suitable protocol, such as a data bus, an address bus, and a command bus or a combined data / address / command bus. This protocol can be custom or proprietary, or interface 1513 can employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, or the like. The address signals are received and decoded by row decoder 1506 and column decoder 1504 to access memory array 1510. Data can be read from memory array 1510 by sensing voltage and / or current changes on the sense lines using sensing circuitry 1511. For example, sensing circuitry 1511 can include sense amplifiers, which can read and latch a page (e.g., a row) of data from memory array 1510. I / O circuitry 1512 can be used to perform two-way data communication with host 1501 through interface 1513. Read / write circuitry 1505 is used to write data to memory array 1510 or read data from memory array 1510. As an example, circuitry 1505 can include various drivers, latch circuitry, and the like.

[0107] Control circuitry 1509 decodes signals provided by host 1501. The signals can be commands provided by host 1501. These signals can include chip enable signals, write enable signals, and address latch signals for controlling operations performed on memory array 1510, including data read operations, data write operations, and data erase operations. In various embodiments, control circuitry 1509 is responsible for executing instructions from host 1501. Control circuitry 1509 can include a state machine, a sequencer, and / or some other type of control circuitry, which can be implemented in the form of hardware, firmware, software, or any combination of the three. In some instances, host 1501 can be a controller external to memory device 1508. For example, host 1501 can be a memory controller coupled to the processing resources of a computing device.

[0108] The term "semiconductor" may refer to, for example, a material, a wafer, or a substrate and includes any underlying semiconductor structure. The "semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by an underlying semiconductor structure, and other semiconductor structures. In addition, when referring to a semiconductor in a previous description, previous process steps may have been used to form regions / junctions in the underlying semiconductor structure, and the term "semiconductor" may include the underlying material containing such regions / junctions.

[0109] As used herein, "a number of" or "a certain number of" something may refer to one or more such things. For example, a number of or a certain number of memory cells may refer to one or more memory cells. "A plurality of" something means two or more. As used herein, performing a plurality of actions simultaneously refers to the actions at least partially overlapping within a particular time period. As used herein, the term "coupled" may include electrical coupling without an intervening element, direct coupling and / or direct connection (e.g., by direct physical contact), indirect coupling and / or connection with an intervening element, or wireless coupling. The term "coupled" may further include two or more elements that cooperate or interact with each other, such as in a causal relationship. An element coupled between two elements may be between the two elements and coupled to each of the two elements.

[0110] It should be recognized that the term "vertical" takes into account variations relative to "perfectly" vertical due to routine manufacturing, measurement, and / or assembly variations, and one of ordinary skill in the art should know the meaning of the term "perpendicular". For example, vertical may correspond to the z direction. As used herein, when a particular element is "adjacent to" another element, the particular element may cover the other element, may be above or lateral to the other element and / or may be in direct physical contact with the other element. For example, "lateral to" may refer to a horizontal direction (e.g., the y direction or the x direction) that may be perpendicular to the z direction.

[0111] Although specific embodiments have been illustrated and described herein, one of ordinary skill in the art should understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of this disclosure. It should be understood that the above description has been presented in an illustrative rather than a restrictive manner. Those skilled in the art will appreciate combinations of the above-described embodiments and other embodiments not expressly described herein after reviewing the above description. The scope of various embodiments of this disclosure includes other applications in which the above structures and methods are used. Accordingly, the scope of various embodiments of this disclosure should be determined with reference to the appended claims and the full scope of equivalents authorized by this claim.

Claims

1. A memory device, comprising: A dual-channel horizontally-oriented access device having: A first source / drain region and a second source / drain region separated by a first channel region, the first channel region being operatively controlled by a first gate separated from the first channel region by a first gate dielectric; And A third source / drain region and a fourth source / drain region separated by a second channel region, the second channel region being operatively controlled by a second gate separated from the second channel region by a second gate dielectric; A first horizontally-oriented storage node coupled to the second source / drain region of the dual-channel access device; and A second horizontally-oriented storage node coupled to the fourth source / drain region of the dual-channel access device.

2. The memory device according to claim 1, wherein the first and the second gates are electrically connected and the first and the second gates are horizontally-oriented gates.

3. The memory device according to any one of claims 1 to 2, wherein the first source / drain region of the dual-channel access device and the third source / drain region of the dual-channel access device are coupled to a vertically-oriented digital line.

4. The memory device according to any one of claims 1 to 2, wherein: The first gate is a horizontally-oriented dual-gate structure having a top gate portion vertically located above the first channel region and a bottom gate portion vertically located below the first channel region; and The second gate is a horizontally-oriented dual-gate structure having a top gate portion vertically located above the second channel region and a bottom gate portion vertically located below the second channel region.

5. The memory device according to claim 4, wherein the bottom gate portion of the first gate and the top gate portion of the second gate are a shared gate portion between the first channel region and the second channel region.

6. The memory device according to any one of claims 1 to 2, wherein: The first and the second channel regions have a first horizontal length; and The first and the second horizontal storage nodes have a second horizontal length; Wherein the second horizontal length is at least twenty-five percent (25%) shorter than a storage node length for maintaining an equal storage capacitance value with respect to the same horizontal memory device layout architecture having only a single-channel horizontally-oriented access device using the same set of operating parameters.

7. The memory device according to any one of claims 1 to 2, wherein the first and the second channel regions have a cumulative channel width that doubles an on-current ("Ion") value with respect to the same horizontal memory device layout architecture having only a single-channel horizontally-oriented access device using the same set of operating parameters.

8. The memory device according to any one of claims 1 to 2, wherein the memory device includes a vertically-oriented three-dimensional (3D) multi-level memory array, wherein each level has a dual-channel horizontally-oriented access device and first and second horizontally-oriented storage nodes.

9. A memory device, comprising: A horizontal directional access device having a vertical stacked structure, comprising: A first horizontal gate portion; A first horizontal channel that horizontally separates a first source / drain region and a second source / drain region and is separated from the first horizontal gate by a dielectric material; A second horizontal gate portion that is separated from the first horizontal channel by the dielectric material; A second horizontal channel that horizontally separates a third source / drain region and a fourth source / drain region and is separated from the second horizontal gate by the dielectric material; and A third horizontal gate portion that is separated from the second horizontal channel by the dielectric; A first horizontally oriented storage node coupled to the second source / drain region; and A second horizontally oriented storage node coupled to the fourth source / drain region.

10. The memory device according to claim 9, wherein the first, second, and third horizontal gate portions are electrically coupled together to form a double-sided gate (G2S) structure on opposite sides of the first and second horizontal channel regions, respectively.

11. The memory device according to any one of claims 9 to 10, wherein the second horizontal gate has a vertical height (h2) that is less than the vertical height (h1) of the first horizontal gate and less than the vertical height (h3) of the third horizontal gate.

12. The memory device according to any one of claims 9 to 10, wherein when actuated, the second horizontal gate reverses the conduction paths in two opposite sides of the first and second horizontal channel regions to double the width of the conduction paths in the first and second horizontal channel regions.

13. The memory device according to any one of claims 9 to 10, wherein the horizontal directional access device is a thin film transistor (TFT), and the first and second horizontally oriented storage nodes are horizontally oriented capacitors located in the same horizontal layer for forming a dual transistor dual capacitor (2T2C) memory cell.

14. The memory device according to claim 13, wherein the memory device includes a vertically oriented three-dimensional (3D) multi-level memory array, and each level has a dual transistor dual capacitor (2T2C) memory cell.

15. The memory device according to any one of claims 9 to 10, wherein the first source / drain region of the first horizontal channel and the third source / drain region of the second horizontal channel are electrically coupled to a vertically oriented digital line.

16. The memory device according to claim 15, wherein: The second source / drain region of the first horizontal channel is coupled to the bottom electrode of the first horizontally oriented storage node; and The fourth source / drain region of the second horizontal channel is coupled to the bottom electrode of the second horizontally oriented storage node.

17. The memory device according to any one of claims 9 to 10, wherein: The first and second horizontal gates are electrically coupled together and form a gate-all-around (GAA) structure opposite to the first and second horizontal channels; and When actuated, the GAA structure reverses conduction paths in opposite sides of the first and second horizontal channels to double widths of the conduction paths in the first and second horizontal channels together with the first and third horizontal gates.

18. A method of forming a multi-level vertical three-dimensional (3D) memory, comprising: forming horizontally oriented access devices in a first horizontal level of the multi-level vertical 3D memory, the access devices having vertically stacked first horizontal gates; a first horizontal channel that horizontally separates a first source / drain region from a second source / drain region and is separated from the first horizontal gate by a first gate dielectric; a second horizontal gate that is separated from the first horizontal channel by a second gate dielectric; a second horizontal channel that horizontally separates a third source / drain region from a fourth source / drain region and is separated from the second horizontal gate by a third gate dielectric; and a third horizontal gate that is separated from the second horizontal channel by a fourth gate dielectric, forming a first horizontally oriented storage node coupled to the second source / drain region of the first horizontal channel and forming a second horizontally oriented storage node coupled to the fourth source / drain region of the second horizontal channel.

19. The method of claim 18, further comprising forming a vertical digital line coupled to the first source / drain region of the first horizontal channel and coupled to the third source / drain region of the second horizontal channel.

20. The method of any one of claims 18 to 19, further comprising coupling the first, second, and third horizontal gates together.

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