Three-dimensional memory device containing silicon

Abstract

A method of manufacturing a memory device includes forming an alternating stack of insulating layers and sacrificial material layers with a silicon oxycarbide liner interposed between a first sacrificial material layer and a first insulating layer and the first sacrificial material layer in direct contact with a second insulating layer or a dielectric material layer composed of a silicon oxide material; forming a memory opening through the alternating stack; forming a memory opening filling structure in the memory opening; forming a backside recess by selectively removing the sacrificial material layer relative to the silicon oxycarbide liner; and forming a conductive layer in the backside recess.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority of the following patent applications: U.S. Provisional Patent Application No. 63 / 481,622, filed on January 26, 2023; U.S. Provisional Patent Application No. 63 / 488,243, filed on March 3, 2023; U.S. Non-Provisional Patent Application No. 18 / 356,896, filed on July 21, 2023; and U.S. Non-Provisional Patent Application No. 18 / 356,919, filed on July 21, 2023, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three-dimensional memory devices containing silicon oxycarbide pads and methods of forming the same. Background Art

[0004] A three-dimensional vertical NAND string having one bit per cell is disclosed in the article by T. Endoh et al., titled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the Invention

[0005] According to one aspect of the present disclosure, there is provided a memory device including: an alternating stack of insulating layers and conductive layers, wherein a first conductive layer of the conductive layers has a first major horizontal surface in contact with a silicon oxycarbide pad and an opposite second major horizontal surface in contact with one of the insulating layers of the insulating layers or with a dielectric material layer composed of silicon oxide material; a memory opening extending vertically through the alternating stack; and a memory opening filling structure located in the memory opening and including a vertical semiconductor channel and a memory film.

[0006] According to another aspect of the present disclosure, a memory device is provided that includes: an alternating stack of an insulating layer and a conductive layer, wherein each conductive layer in the conductive layer is vertically spaced apart from a corresponding overlying insulating layer and a corresponding underlying insulating layer by a corresponding backside dielectric metal oxide barrier dielectric layer, and wherein a first backside dielectric metal oxide barrier dielectric layer in the backside dielectric metal oxide barrier dielectric layer includes a first horizontal surface in direct contact with a silicon carbon oxide liner and a second horizontal surface in direct contact with one of the insulating layers or a dielectric material layer composed of a silicon oxide material; a memory opening that extends vertically through the alternating stack; and a memory opening fill structure that is located in the memory opening and includes a vertical semiconductor channel and a memory film.

[0007] According to yet another aspect of the present disclosure, a method of forming a memory device is provided that includes: forming an alternating stack of an insulating layer and a sacrificial material layer, wherein a silicon carbon oxide liner is interposed between a first sacrificial material layer in the sacrificial material layer and a first insulating layer in the insulating layer, and the first sacrificial material layer is in direct contact with a second insulating layer in the insulating layer or a dielectric material layer composed of a silicon oxide material; forming a memory opening through the alternating stack; forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure includes a memory film that includes, from outside to inside, a silicon oxide barrier dielectric layer, a continuous memory material layer, and a tunneling dielectric layer, and the memory opening fill structure further includes a vertical semiconductor channel formed on the memory film; forming a backside groove by selectively removing the sacrificial material layer relative to the silicon carbon oxide liner; and forming a conductive layer in the backside groove. Description of the Drawings

[0008] Figure 1 is a schematic vertical cross-sectional view of a first exemplary structure after vertical repetition of a plurality of instances of a repeating unit of an optional semiconductor device, an optional lower-level metal interconnect structure, a semiconductor material layer, and an insulating layer, a first silicon carbon oxide liner, a sacrificial material layer, and a second silicon carbon oxide liner according to a first embodiment of the present disclosure.

[0009] Figure 2 is a schematic vertical cross-sectional view of a first exemplary structure after forming a stepped platform according to a first embodiment of the present disclosure.

[0010] Figure 3 is a schematic vertical cross-sectional view of a first exemplary structure after forming an inverse stepped dielectric material portion according to a first embodiment of the present disclosure.

[0011] Figure 4AIs a schematic vertical cross - sectional view of a first exemplary structure after forming a memory opening and a support opening according to a first embodiment of the present disclosure.

[0012] Figure 4B Is Figure 4A A top - view of the first exemplary structure of. The vertical plane A - A' is Figure 4A The plane of the cross - section of.

[0013] Figures 5A to 5F Is a sequential schematic vertical cross - sectional view of a memory opening within a first exemplary structure during the formation of a memory opening filling structure according to a first embodiment of the present disclosure.

[0014] Figure 6 Is a schematic vertical cross - sectional view of a first exemplary structure after forming a memory opening filling structure and a support pillar structure according to a first embodiment of the present disclosure.

[0015] Figure 7A Is a schematic vertical cross - sectional view of a first exemplary structure after forming a contact - level dielectric layer, a back - side trench, and a source region according to a first embodiment of the present disclosure.

[0016] Figure 7B Is Figure 7A A partial perspective top - view of the first exemplary structure of. The vertical plane A - A' is Figure 7A The plane of the schematic vertical cross - sectional view of.

[0017] Figure 8 Is a schematic vertical cross - sectional view of a first exemplary structure after forming a back - side groove according to a first embodiment of the present disclosure.

[0018] Figures 9A to 9C Is a sequential vertical cross - sectional view of a region around a memory opening filling structure in a first configuration of a first exemplary structure during the formation of a conductive layer according to a first embodiment of the present disclosure.

[0019] Figures 10A to 10E Is a sequential vertical cross - sectional view of a region around a memory opening filling structure in a second configuration of a first exemplary structure during the formation of a conductive layer according to a first embodiment of the present disclosure.

[0020] Figure 11 Is a schematic vertical cross - sectional view of a first exemplary structure after forming a conductive layer according to a first embodiment of the present disclosure.

[0021] Figure 12A Is a schematic vertical cross - sectional view of a first exemplary structure after forming a back - side trench filling structure according to a first embodiment of the present disclosure.

[0022] Figure 12BIs Figure 12A A top view of the first exemplary structure of Figure 12A . The vertical plane A-A' is the plane of the

[0023] Figure 13A A schematic vertical cross-sectional view of the first exemplary structure after forming an additional contact via structure according to a first embodiment of the present disclosure.

[0024] Figure 13B Is Figure 13A A top view of the first exemplary structure of Figure 13A . The vertical plane A-A' is the plane of the

[0025] Figures 14A to 14F A sequential schematic vertical cross-sectional view of memory openings within a second exemplary structure during formation of a memory opening fill structure according to a second embodiment of the present disclosure.

[0026] Figures 15A to 15C A sequential vertical cross-sectional view of an area around a memory opening fill structure within a second exemplary structure during formation of a conductive layer according to a second embodiment of the present disclosure.

[0027] Figure 16 A vertical cross-sectional view of a third exemplary structure after a first vertical repetition of multiple instances of a repeating unit of a first insulating layer, a first silicon oxycarbide liner, a first sacrificial material layer, and a second silicon oxycarbide liner according to a third embodiment of the present disclosure, with the topmost silicon oxynitride liner omitted.

[0028] Figure 17 A vertical cross-sectional view of a third exemplary structure after forming a first stepped surface, a first inverse stepped dielectric material portion, and an interlayer dielectric layer according to a third embodiment of the present disclosure.

[0029] Figure 18A A vertical cross-sectional view of a third exemplary structure after forming a first layer of memory openings and a first layer of support openings according to a third embodiment of the present disclosure.

[0030] Figure 18B Is Figure 18A A top view of the third exemplary structure of Figure 18A . The articulated vertical plane A-A' is the plane of the

[0031] Figure 19 A vertical cross-sectional view of a third exemplary structure after forming a first layer of sacrificial fill material portion and extending upper regions of the first layer of memory openings and the first layer of support openings according to a third embodiment of the present disclosure.

[0032] Figure 20 is a vertical cross-sectional view of a third exemplary structure after forming an interlayer sacrificial fill material portion according to a third embodiment of the present disclosure.

[0033] Figure 21 is a vertical cross-sectional view of a third exemplary structure after a second vertical repetition of a plurality of instances of a repeating unit of a second insulating layer, a first silicon oxycarbide liner, a second sacrificial material layer, and a second silicon oxycarbide liner according to a third embodiment of the present disclosure, wherein the bottommost silicon oxynitride liner is omitted.

[0034] Figure 22 is a vertical cross-sectional view of a third exemplary structure after forming a second stepped surface and a second inverse stepped dielectric material portion according to a third embodiment of the present disclosure.

[0035] Figure 23 is a vertical cross-sectional view of a third exemplary structure after forming a second layer memory opening and a second layer support opening according to a third embodiment of the present disclosure.

[0036] Figure 24 is a vertical cross-sectional view of a third exemplary structure after forming an interlayer memory opening and an interlayer support opening according to a third embodiment of the present disclosure.

[0037] Figure 25A is a vertical cross-sectional view of a third exemplary structure after forming a memory opening fill structure and a support pillar structure according to a third embodiment of the present disclosure.

[0038] Figure 25B is a vertical cross-sectional view of a region of the third exemplary structure surrounding Figure 25A the memory opening fill structure in

[0039] Figure 25C is a vertical cross-sectional view of a region of an alternative embodiment of the third exemplary structure surrounding Figure 25A the memory opening fill structure in

[0040] Figure 26A is a vertical cross-sectional view of a third exemplary structure after forming a contact level dielectric layer and isolation trenches according to a third embodiment of the present disclosure.

[0041] Figure 26B is Figure 26A a top view of the third exemplary structure of Figure 26A The articulated vertical plane A-A' is the plane of the vertical cross-sectional view of

[0042] Figure 27 is a vertical cross-sectional view of a third exemplary structure after forming a backside recess according to a third embodiment of the present disclosure.

[0043] Figures 28A to 28E A sequential vertical cross-sectional view of a region around a memory opening filling structure of a third exemplary structure during formation of a conductive layer, according to a third embodiment of the present disclosure.

[0044] Figures 29A to 29E A sequential vertical cross-sectional view of a region around a memory opening filling structure of an alternative configuration of a third exemplary structure during formation of a conductive layer, according to a third embodiment of the present disclosure.

[0045] Figure 30 A vertical cross-sectional view of a third exemplary structure after formation of a conductive layer, according to a third embodiment of the present disclosure.

[0046] Figure 31A A vertical cross-sectional view of a third exemplary structure after formation of an isolation trench filling structure, according to a third embodiment of the present disclosure.

[0047] Figure 31B is Figure 31A A top view of a third exemplary structure. The articulated vertical plane A-A' is Figure 31A the plane of the vertical cross-sectional view of

[0048] Figure 32A A vertical cross-sectional view of a third exemplary structure after formation of various contact via structures, according to a third embodiment of the present disclosure.

[0049] Figure 32B is Figure 32A A top view of a third exemplary structure. The articulated vertical plane A-A' is Figure 32A the plane of the vertical cross-sectional view of DETAILED DESCRIPTION

[0050] As discussed above, embodiments of the present disclosure relate to three-dimensional memory devices containing silicon oxycarbide liners and methods of forming the same, aspects of which are described below. The embodiments provide an enhanced word line edge shape with reduced corner rounding, which reduces short channel effects.

[0051] The drawings are not drawn to scale. Multiple instances of an element may be replicated where a single instance of the element is shown, unless explicitly described or otherwise clearly indicated to be free of replication of elements. Ordinal numbers such as "first", "second", and "third" are used only to identify similar elements, and different ordinal numbers may be used in the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0052] Like reference numerals designate like or similar elements. Unless otherwise specified, elements having the same reference numeral are considered to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing shared edges or surfaces. If two or more elements do not contact each other directly or do not contact each other directly, the two elements are "separated" from each other or "separated from" each other. As used herein, a first element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly located on" the second element. As used herein, if there is an electrical conduction path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or an "in-process" structure refers to a transient structure in which the shape or composition of at least one component is subsequently changed.

[0053] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a scope less than that of the underlying or overlying structure. In addition, the layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between any pair of horizontal planes between and / or at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below it.

[0054] As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm. As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm in the absence of electrical dopants, and capable of producing a doped material having a conductivity in the range of 1.0 S / cm to 1.0×10 5 S / cm upon appropriate doping with electrical dopants. As used herein, an "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, a "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / cm. As used herein, an "insulating material" or a "dielectric material" refers to a material having a conductivity less than 1.0×10 -6 S / cm.

[0055] As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrical dopant at an atomic concentration high enough to become a conductive material (i.e., having a conductivity greater than 1.0×10 5 S / cm) when formed as a crystalline material or when converted to a crystalline material by an annealing process (e.g., from an initial amorphous state). A "doped semiconductor material" can be a heavily doped semiconductor material or can be a semiconductor material containing an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) at a concentration providing a conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semi-conductive or conductive and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semi-conductive or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material that contains at least one metallic element. All conductivity measurements are made under standard conditions.

[0056] Generally speaking, a semiconductor die or a semiconductor package can include a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit that can independently execute commands or report status. Each die contains one or more planes (usually one or two). The same, concurrent operations can be performed on each plane, but there are some limitations. Each plane contains a plurality of blocks, which are the smallest units that can be erased in a single erase operation. Each block contains a plurality of pages, which are the smallest units that are programmable, i.e., the smallest units on which a read operation can be performed.

[0057] See Figure 1, showing a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a substrate 8, which may be a semiconductor substrate, an insulating substrate, a conductive substrate, or a combination thereof. The substrate 8 includes a substrate material layer 9, which may or may not be a semiconductor material layer. In one embodiment, the substrate 8 may include a semiconductor substrate substantially composed of single-crystalline semiconductor material or polycrystalline semiconductor material. In one embodiment, the substrate 8 may be a commercially available silicon wafer on which a plurality of semiconductor dies, such as a two-dimensional array of semiconductor dies, may be subsequently formed. In this case, the substrate material layer 9 may include doped wells in the silicon wafer or an epitaxial silicon layer located on the silicon wafer. In the case where the substrate 8 includes a semiconductor substrate, the semiconductor device 620 may optionally be formed on top of the substrate 8. Generally speaking, the semiconductor device 620 may include any type of semiconductor device known in the art. In one embodiment, the semiconductor device 620 may include complementary metal-oxide-semiconductor (CMOS) field-effect transistors of a peripheral circuit for controlling the operation of a three-dimensional memory device subsequently formed thereon.

[0058] Optionally, a metal interconnect structure 680 embedded within a dielectric material layer 660 may be formed above the substrate 8. The metal interconnect structure 680 is also referred to as a lower-level metal interconnect structure 680, and the dielectric material layer 660 is also referred to as a lower-level dielectric material layer 660. In the presence of the semiconductor device 620, the lower-level metal interconnect structure 680 may provide an electrical connection to the semiconductor device 620. In one embodiment, the metal interconnect structure 680 may include a metal pad 682, which may be used as a contact pad for a subsequently formed connection via structure. Alternatively, the formation of the semiconductor device 620, the metal interconnect structure 680, and the dielectric material layer 660 on the substrate 8 may be omitted. Instead, the semiconductor device 620 may be formed on a separate substrate and then bonded to the three-dimensional memory device.

[0059] In the presence of a lower-level dielectric material layer 660, a semiconductor material layer (e.g., a polysilicon layer) 10 may be formed on the lower-level dielectric material layer 660. The semiconductor material layer 10 may include a single semiconductor material layer or may include a vertical stack of multiple semiconductor material sub-layers. In one embodiment, the semiconductor material layer 10 may be doped with a first conductivity type, which may be p-type or n-type. In one embodiment, an in-process source-level material layer may be formed in place of the semiconductor material layer 10. In this case, the in-process source-level material layer may include a vertical stack that includes a lower source semiconductor layer, a source-level sacrificial layer that is subsequently replaced by a source contact layer, and an upper source semiconductor layer. In the absence of the lower-level dielectric material layer 660, the semiconductor material layer 10 may be omitted. Although embodiments in which the semiconductor material layer 10 is employed are described, embodiments in which the semiconductor material layer is replaced by an in-process source-level material layer or omitted are clearly contemplated herein.

[0060] A plurality of instances of a vertical repetition of a repeating unit of an insulating layer 32, a first carbon oxide silicon liner 332, a sacrificial material layer, and a second carbon oxide silicon liner 332 may be formed on a substrate. The insulating layer 32 contains an insulating material, such as a silicon oxide material. The sacrificial material layer 42 contains a sacrificial material that can be selectively removed relative to the insulating material of the insulating layer 32. As used herein, if a removal process removes a first material at a rate that is at least twice the rate of removal of a second material, the removal of the first material is "selective" relative to the second material. The first carbon oxide silicon liner 332 and the second carbon oxide silicon liner 332 contain a carbon oxide silicon material containing at least 10 atomic % of each of silicon, oxygen, and carbon.

[0061] The bottommost insulating layer 32 is referred to herein as the bottommost insulating layer 32B. The topmost insulating layer 32 is referred to herein as the topmost insulating layer 32T. In one embodiment, the insulating layer 32 contains a silicon oxide material, such as undoped silicate glass or doped silicate glass.

[0062] The sacrificial material layer 42 may contain an insulating material, a semiconductor material, or a conductive material. Non-limiting examples of the sacrificial material in the sacrificial material layer 42 include silicon nitride, amorphous semiconductor materials (such as amorphous silicon), and polycrystalline semiconductor materials (such as polysilicon). In one embodiment, the sacrificial material layer 42 may be a spacer material layer containing silicon nitride or a spacer material layer containing a semiconductor material of at least one of silicon and germanium.

[0063] The carbon oxide material of the first carbon oxide silicon liner 332 and the second carbon oxide silicon liner 332 may have SiC x O 2(1-x)The material composition, where x is greater than 0.1 and less than 0.9, and / or greater than 0.2 and less than 0.8, and / or greater than 0.3 and less than 0.7.

[0064] The insulating layer 32 can be deposited, for example, by chemical vapor deposition (CVD). The sacrificial material layer 42 can be formed, for example, by CVD or atomic layer deposition (ALD). The first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 can be deposited by CVD or ALD. In an illustrative example, the insulating layer 32 can comprise undoped silicate glass deposited by plasma-assisted decomposition of tetraethyl orthosilicate (TEOS). The sacrificial material layer 42 can comprise silicon nitride deposited by plasma-enhanced chemical vapor deposition, and the first and second silicon oxycarbide liners 322 can be deposited by a plasma-assisted chemical vapor deposition process using silane and carbon dioxide as precursor gases.

[0065] In one embodiment, the silicon oxycarbide liner 332 is thinner than the insulating layer 32 and the sacrificial material layer 42. The thickness of the insulating layer 32 and the sacrificial material layer 42 can be in the range of 20 nm to 50 nm, but smaller and larger thicknesses can be employed for each insulating layer 32 and each sacrificial material layer 42. The thickness of each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 can be in the range of 0.5 nm to 4 nm and / or 1.0 nm to 2.5 nm, but smaller and larger thicknesses can also be employed. The number of repetitions of the insulating layer 32 and sacrificial material layer 42 pairs can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but larger numbers of repetitions can also be employed.

[0066] The first exemplary structure can include a memory array region 100 and a contact region 300, in which a memory stack structure will be subsequently formed in the memory array region and a stepped surface and contact via structure will be subsequently formed in the contact region.

[0067] See Figure 2 , a stepped surface is formed at the peripheral portion of the vertical repeat (32, 42, 332), which is referred to herein as the stepped region. As used herein, a "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped chamber is formed within the volume of the vertical repeat (32, 42, 332) removed by forming the stepped surface. A "stepped chamber" refers to a chamber having a stepped surface.

[0068] A stepped region is formed in the contact region 300. The stepped chamber may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped chamber changes gradually according to the vertical distance from the top surface of the semiconductor material layer 10. In one embodiment, the stepped chamber may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the depth of the chamber by one or more levels, and the second type of etching process laterally expanding the region vertically etched in the subsequent first type of etching process. As used herein, a "level" including a plurality of alternating structures is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

[0069] Each sacrificial material layer 42 except the topmost sacrificial material layer 42 within the vertical repeat (32, 42, 332) extends laterally further than any overlying sacrificial material layer 42 within the vertical repeat (32, 42, 332) in the stepped region. The stepped region includes the stepped surface of the vertical repeat (32, 42, 332), which continuously extends from the bottommost layer within the vertical repeat (32, 42, 332) to the topmost layer within the vertical repeat (32, 42, 332).

[0070] Each vertical step of the stepped surface may have the height of one or more pairs of the insulating layer 32 and the sacrificial material layer. In one embodiment, each vertical step may have the height of a single pair of the insulating layer 32 and the sacrificial material layer 42. In another embodiment, multiple "columns" of steps may be formed along a first horizontal direction hd1 such that each vertical step has the height of multiple pairs of the insulating layer 32 and the sacrificial material layer 42, and the number of columns may be at least the number of the multiple pairs. The steps of each column may be vertically offset from each other such that each sacrificial material layer 42 has a physically exposed top surface in the steps of the corresponding column. In an illustrative example, two columns of steps are formed for each block of the memory stack structure to be formed subsequently, such that one column of steps provides a physically exposed top surface of the odd-numbered sacrificial material layers 42 (counting from the bottom), and the other column of steps provides a physically exposed top surface of the even-numbered sacrificial material layers (counting from the bottom). Configurations using three columns, four columns, or more columns of steps may also be used, with corresponding sets of vertical offsets between the physically exposed surfaces of the sacrificial material layers 42. Each sacrificial material layer 42 has a greater lateral extent than any overlying sacrificial material layer 42 in at least one direction such that each physically exposed surface of any sacrificial material layer 42 does not have an overhang. In one embodiment, the vertical steps within each column of steps may be arranged along the first horizontal direction hd1, and the columns of steps may be arranged along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1 may be perpendicular to the boundary between the memory array region 100 and the contact region 300.

[0071] See Figure 3 , a reverse stepped dielectric material portion 65 (i.e., an insulating fill material portion) can be formed in the stepped chamber by depositing a dielectric material in the stepped chamber. For example, a dielectric material such as silicon oxide can be deposited in the stepped chamber. An excess portion of the deposited dielectric material can be removed, for example, by chemical mechanical planarization (CMP) above the top surface of the topmost insulating layer 32T. The remaining portion of the deposited dielectric material that fills the stepped chamber constitutes the reverse stepped dielectric material portion 65. As used herein, a "reverse stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases as a function of the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the reverse stepped dielectric material portion 65, the silicon oxide of the reverse stepped dielectric material portion 65 may or may not be doped with dopants such as B, P, and / or F.

[0072] Optionally, a drain select level isolation structure 72 can be formed through the topmost insulating layer 32T and a subset of the sacrificial material layers 42 at the drain select level. The drain select level isolation structure 72 can be formed, for example, by forming a drain select level isolation trench and filling the drain select level isolation trench with a dielectric material such as silicon oxide. An excess portion of the dielectric material can be removed above the top surface of the topmost insulating layer 32T.

[0073] See Figure 4A and Figure 4B , a photolithography material stack (not shown) including at least a photoresist layer can be formed on the topmost insulating layer 32T and the reverse stepped dielectric material portion 65 and can be photolithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region 100 and a second set of openings formed over the contact region 300. The pattern in the photolithography material stack can be transferred through the topmost insulating layer 32T or the reverse stepped dielectric material portion 65 and through the vertical repeat (32, 42, 332) by at least one anisotropic etch using the patterned photolithography material stack as an etch mask. The portion of the vertical repeat (32, 42, 332) located below the openings in the patterned photolithography material stack is etched to form memory openings 49 and support openings 19. As used herein, a "memory opening" refers to a structure in which a memory element such as a memory stack structure is subsequently formed. As used herein, a "support opening" refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The memory openings 49 are formed through the topmost insulating layer 32T and the entire vertical repeat (32, 42, 332) in the memory array region 100. The support openings 19 are formed through the reverse stepped dielectric material portion 65 and the portion of the vertical repeat (32, 42, 332) below the stepped surface in the contact region 300.

[0074] Memory opening 49 extends through the entire vertical repeat (32, 42, 332). Support opening 19 extends through a subset of the layers within the vertical repeat (32, 42, 332). The chemistry of the anisotropic etching process for etching through the materials of the vertical repeat (32, 42, 332) can be adjusted (i.e., changed periodically) to optimize the etching of the various materials within the vertical repeat (32, 42, 332). The anisotropic etching can be, for example, a series of reactive ion etches. The sidewalls of the memory opening 49 and the support opening 19 can be substantially vertical or can be tapered. The patterned photoresist stack can then be removed, for example, by ashing.

[0075] Memory opening 49 and support opening 19 can extend from the top surface of the vertical repeat (32, 42, 332) to a horizontal plane that includes at least the topmost surface of the semiconductor material layer 10. In one embodiment, after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each memory opening 49 and each support opening 19, an over-etch in the semiconductor material layer 10 can be optionally performed. The over-etch can be performed before or after removing the photoresist stack. In other words, the recessed surface of the semiconductor material layer 10 can be vertically offset from the non-recessed top surface of the semiconductor material layer 10 by a recess depth. The recess depth can be, for example, in the range of 1 nm to 50 nm, but smaller and larger recess depths can also be employed. The over-etch is optional and can be omitted. If the over-etch is not performed, the bottom surfaces of the memory opening 49 and the support opening 19 can be coplanar with the topmost surface of the semiconductor material layer 10.

[0076] Each of the memory opening 49 and the support opening 19 can include sidewalls (or a sidewall) that extend substantially perpendicular to the topmost surface of the semiconductor material layer 10. A two-dimensional array of memory openings 49 can be formed in the memory array region 100. A two-dimensional array of support openings 19 can be formed in the contact region 300.

[0077] Figures 5A to 5F is a sequential schematic vertical cross-sectional view of the memory opening 49 within the first exemplary structure during the formation of the memory opening filling structure 58 according to a first embodiment of the present disclosure.

[0078] Figure 5A Shows the memory opening after Figure 4A and Figure 4B processing steps.

[0079] See Figure 5B, the optional base channel portion 11 can be formed, for example, at the bottom portions of each memory opening 49 and each support opening 19 by a selective semiconductor deposition process. In one embodiment, the base channel portion 11 can be doped with an electrical dopant of the same conductivity type as the semiconductor material layer 10, which is the first conductivity type. In one embodiment, the top surface of each base channel portion 11 can be formed below the horizontal plane including the top surface of the bottommost insulating layer 32B. The base channel portion 11 can be a part of the transistor channel that extends between a source region that will subsequently be formed in the semiconductor material layer 10 and a drain region that will subsequently be formed in the upper portion of the memory opening 49. A memory chamber 49' exists in the unfilled portion of the memory opening 49 above the base channel portion 11. If the semiconductor material layer 10 comprises a single-crystalline semiconductor material, the base channel portion 11 can comprise a single-crystalline semiconductor material that is epitaxially aligned with the single-crystalline semiconductor material of the semiconductor material layer 10. In one embodiment, the base channel portion 11 can comprise single-crystalline silicon.

[0080] See Figure 5C , the memory film 50 can be formed by a series of conformal deposition processes. The memory film 50 can include, from bottom to top above the topmost insulating layer 32T or from outside to inside within each memory opening 49, a silicon oxide liner 51, a dielectric metal oxide barrier dielectric layer 52, a silicon oxide barrier dielectric layer 53, a memory material layer 54, and a tunneling dielectric layer 56.

[0081] The silicon oxide liner 51 comprises a silicon oxide material such as undoped silicate glass and / or consists essentially of a silicon oxide material. In one embodiment, the silicon oxide liner 51 can be formed by a low-pressure chemical vapor deposition (LPCVD) process employing the thermal decomposition of tetraethyl orthosilicate (TEOS). The thickness of the silicon oxide liner 51 can be in the range of 1 nm to 12 nm, such as 3 nm to 8 nm, but smaller or larger thicknesses can also be employed.

[0082] The dielectric metal oxide barrier dielectric layer 52 comprises a dielectric metal oxide material having a dielectric constant greater than 7.9. Exemplary dielectric metal oxide materials that can be used for the dielectric metal oxide barrier dielectric layer 52 include, but are not limited to, aluminum oxide, hafnium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, dielectric oxides of other transition metals, or alloys or layer stacks thereof. The dielectric metal oxide barrier dielectric layer 52 can be deposited by a conformal deposition process such as an atomic layer deposition (ALD) process. The thickness of the dielectric metal oxide barrier dielectric layer 52 can be in the range of 1 nm to 12 nm, such as 3 nm to 8 nm, but smaller and larger thicknesses can also be employed.

[0083] The memory material layer 54 may comprise any memory material, such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store data bits in the form of the presence or absence of charge, the direction of ferroelectric polarization, resistivity, or other measurable physical parameters. In one embodiment, the memory material layer 54 may be a continuous silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically coincident sidewalls, and the memory material layer 54 may be formed as a single continuous layer. Generally speaking, the memory material layer 54 may include a vertical stack of memory elements located at the level of the sacrificial material layer 42. For example, the vertical stack of memory elements may include an annular portion of the memory material layer 54 located at the level of the sacrificial material layer 42.

[0084] The tunneling dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, their alloys, and / or their combinations. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a silicon oxide layer substantially free of carbon or a silicon oxynitride layer substantially free of carbon. The thickness of the tunneling dielectric layer 56 may be in the range of 2 nm to 20 nm, but smaller or larger thicknesses may also be employed.

[0085] Optionally, a sacrificial capping layer (not shown) may be formed on the memory film 50.

[0086] See Figure 5D , an optional sacrificial capping material layer (not shown), the tunneling dielectric layer 56, the memory material layer 54, the silicon oxide barrier dielectric layer 53, the dielectric metal oxide barrier dielectric layer 52, and the silicon oxide liner 51 are sequentially anisotropically etched using at least one anisotropic etching process. The portions of the sacrificial capping material layer, the tunneling dielectric layer 56, the memory material layer 54, the silicon oxide barrier dielectric layer 53, the dielectric metal oxide barrier dielectric layer 52, and the silicon oxide liner 51 that are located above the top surface of the topmost insulating layer 32T may be removed by at least one anisotropic etching process. Additionally, the horizontal portions of the sacrificial capping material layer, the tunneling dielectric layer 56, the memory material layer 54, the silicon oxide barrier dielectric layer 53, the dielectric metal oxide barrier dielectric layer 52, and the silicon oxide liner 51 at the bottom of each memory chamber 49' may be removed to form openings in their remaining portions. Each of the sacrificial capping material layer, the tunneling dielectric layer 56, the memory material layer 54, the silicon oxide barrier dielectric layer 53, the dielectric metal oxide barrier dielectric layer 52, and the silicon oxide liner 51 may be etched by a corresponding anisotropic etching process using a corresponding etching chemical, which may or may not be the same for the various material layers.

[0087] Each remaining portion of the sacrificial capping material layer (if present) may have a tubular configuration. The surface of the base channel portion 11 (or, in the case where the base channel portion 11 is not employed, the surface of the semiconductor material layer 10) may be physically exposed below the opening that passes through the sacrificial capping material layer, the tunneling dielectric layer 56, the memory material layer 54, the silicon oxide barrier dielectric layer 53, the dielectric metal oxide barrier dielectric layer 52, and the silicon oxide liner 51 at the bottom of each memory chamber 49'. Optionally, the physically exposed semiconductor surface at the bottom of each memory chamber 49' may be vertically recessed such that the recessed semiconductor surface below the memory chamber 49' is vertically offset by a recess distance from the topmost surface of the base channel portion 11 (or, in the case where the base channel portion 11 is not employed, from the semiconductor material layer 10). The sacrificial capping material layer may then be selectively removed relative to the material of the tunneling dielectric layer 56. In the case where the sacrificial capping material layer comprises a semiconductor material, a wet etching process employing hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) may be performed to remove the sacrificial capping material layer. Alternatively, if the sacrificial capping material layer comprises a semiconductor material, the sacrificial capping material layer may be retained in the final device.

[0088] See Figure 5E The semiconductor channel layer 60L may be directly deposited on the semiconductor surface of the base channel portion 11 (or, if the base channel portion 11 is omitted, on the semiconductor material layer 10), and directly deposited on the memory film 50. The semiconductor channel layer 60L comprises a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer 60L comprises amorphous silicon or polycrystalline silicon. The semiconductor channel layer 60L may be doped with a first conductivity type that is the same as the conductivity type of the semiconductor material layer 10 and the base channel portion 11. The semiconductor channel layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer 60L may be in the range of 2 nm to 10 nm, although smaller and larger thicknesses may also be employed. The semiconductor channel layer 60L may partially fill the memory chamber 49' in each memory opening, or may completely fill the chamber in each memory opening.

[0089] A dielectric core layer can be deposited to fill any remaining portion of the memory chamber 49' within each memory opening 49. The dielectric core layer comprises a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD) or by a self-planarizing deposition process such as spin coating. The horizontal portion of the dielectric core layer can be removed, for example, by a recess etching process such that each remaining portion of the dielectric core layer is located within a corresponding memory opening 49 and has a corresponding top surface below the horizontal plane of the top surface including the topmost insulating layer 32T. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0090] See Figure 5F , a doped semiconductor material having a second conductivity type can be deposited within each recessed region above the dielectric core 62. The deposited semiconductor material can be doped with a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 , but smaller or larger dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

[0091] An excess portion of the deposited semiconductor material doped with the second conductivity type and the horizontal portion of the semiconductor channel layer 60L can be removed, for example, by chemical mechanical planarization (CMP) or a recess etching process from above the horizontal plane of the top surface including the topmost insulating layer 32T. Each remaining portion of the doped semiconductor material doped with the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel layer 60L (which is doped with the first conductivity type) constitutes a vertical semiconductor channel 60.

[0092] Each combination of a memory film 50 within a memory opening 49 and a vertical semiconductor channel 60 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a vertical semiconductor channel 60, a tunneling dielectric layer 56, a plurality of memory elements (including the portion of the memory material layer 54 at the level of the sacrificial material layer 42), a silicon oxide barrier dielectric layer 53, a dielectric metal oxide barrier dielectric layer 52, and a silicon oxide liner 51. Each adjacent combination of a base channel portion 11 (if present), the memory stack structure 55, a dielectric core 62, and a drain region 63 filling the corresponding memory opening 49 is herein referred to as a memory opening fill structure 58. Each adjacent combination of a base channel portion 11 (if present), a memory film 50, a vertical semiconductor channel 60, a dielectric core 62, and a drain region 63 filling the corresponding support opening 19 is herein referred to as a support pillar structure.

[0093] Generally, a vertical semiconductor channel 60 is formed on each memory film 50. Each memory film 50 includes, from outside to inside, a silicon oxide liner 51, a dielectric metal oxide barrier dielectric layer 52, a silicon oxide barrier dielectric layer 53, a memory material layer 54, and a tunneling dielectric layer 56. The silicon oxide liner 51 laterally surrounds and contacts the dielectric metal oxide barrier dielectric layer 52.

[0094] See Figure 6 , which shows an exemplary structure after forming a memory opening fill structure 58 and a support pillar structure 20 within a memory opening 49 and a support opening 19, respectively. Examples of the memory opening fill structure 58 can be formed in each memory opening 49 of the structure of Figure 4A and Figure 4B . Examples of the support pillar structure 20 can be formed in each support opening 19 of the structure of Figure 4A and Figure 4B .

[0095] See Figure 7A and Figure 7B , a contact-level dielectric layer 80 can be formed above the vertical repeats (32, 42, 332) of the insulating layer 32 and the sacrificial material layer 42 and above the memory opening fill structure 58 and the support pillar structure 20. The contact-level dielectric layer 80 includes a dielectric material different from the dielectric material of the sacrificial material layer 42. For example, the contact-level dielectric layer 80 can include silicon oxide. The contact-level dielectric layer 80 can have a thickness in the range of 50 nm to 500 nm, but smaller and larger thicknesses can also be employed.

[0096] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and patterned lithographically to form openings in regions between clusters of the memory stack structure 55. The pattern in the photoresist layer may be transferred through the contact-level dielectric layer 80, the vertical repeats (32, 42, 332), and / or the inverse stepped dielectric material portions 65 using anisotropic etching to form backside trenches 79 that extend at least vertically from the top surface of the contact-level dielectric layer 80 to the top surface of the semiconductor material layer 10 and laterally through the memory array region 100 and the contact region 300.

[0097] In one embodiment, the backside trenches 79 may extend laterally along a first horizontal direction hd1 (which may be the word line direction), and may be laterally spaced from each other along a second horizontal direction hd2 (which may be the bit line direction) perpendicular to the first horizontal direction hd1. The memory stack structures 55 may be arranged in rows extending along the first horizontal direction hd1. The drain select-level isolation structures 72 may extend laterally along the first horizontal direction hd1. Each backside trench 79 may have a uniform width that is invariant along its length direction (i.e., along the first horizontal direction hd1). Each drain select-level isolation structure 72 may have a uniform vertical profile along a vertical plane perpendicular to the first horizontal direction hd1 that does not vary with translation along the first horizontal direction hd1. Multiple rows of memory opening fill structures 58 may be located between a pair of adjacent backside trenches 79 and drain select-level isolation structures 72, or between a pair of adjacent drain select-level isolation structures 72. In one embodiment, the backside trenches 79 may include source contact openings, in which source contact via structures may be subsequently formed. For example, the photoresist layer may be removed by ashing. Generally, the backside trenches 79 extending laterally along the first horizontal direction hd1 may be formed through the contact-level dielectric layer 80 and the vertical repeats (32, 42, 332). As the vertical repeats (32, 42, 332) formed at the processing step in Figure 2 are divided into multiple alternating stacks (32, 42) that are laterally spaced by the backside trenches 79 along the second horizontal direction hd2.

[0098] Dopants of a second conductivity type may be implanted into the physically exposed surface portion (which may be a surface portion of the semiconductor material layer 10) of the semiconductor material layer 10 that is at the bottom of the backside trenches by an ion implantation process. Source regions 61 may be formed at the surface portions of the semiconductor material layer 10 that are below each backside trench 79. Each source region 61 is formed in the surface portion of the semiconductor material layer 10 that is below the corresponding backside trench 79. Due to the dispersion of the implanted dopant atoms during the implantation process and the lateral diffusion of the implanted dopant atoms during a subsequent activation annealing process, each source region 61 may have a lateral extent that is greater than the lateral extent of the overlying backside trench 79.

[0099] The upper portion of the semiconductor material layer 10 that extends between the source region 61 and the vertical semiconductor channel 60 in the memory opening filling structure 58 constitutes the horizontal semiconductor channel 59 for a plurality of field effect transistors. The horizontal semiconductor channel 59 is connected to a plurality of vertical semiconductor channels 60.

[0100] See Figure 8 , an etchant that selectively etches the sacrificial material layer 42 with respect to the first material of the insulating layer 32 and the carbon-oxidized silicon liner 332 can be introduced into the backside trench 79 (e.g., using an etching process). A backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The removal of the sacrificial material layer 42 can be selective with respect to the first material of the insulating layer 32, the material of the carbon-oxidized silicon liner 332, the material of the inverse stepped dielectric material portion 65, the semiconductor material of the semiconductor material layer 10, and the outermost layer of the memory film 50 (such as the silicon oxide liner 51). In one embodiment, the sacrificial material layer 42 can comprise silicon nitride, and the materials of the insulating layer 32 and the inverse stepped dielectric material portion 65 can be selected from silicon oxide and dielectric metal oxides.

[0101] The etching process for selectively etching the sacrificial material layer 42 with respect to the insulating layer 32, the carbon-oxidized silicon liner 322, and the outermost layer of the memory film 50 can be a wet etching process using a wet etching solution, or it can be a gas-phase (dry) etching process, where the etchant is introduced into the backside trench 79 in a gas phase. For example, if the sacrificial material layer 42 comprises silicon nitride, then the etching process can be a wet etching process, where the first exemplary structure is immersed in a wet etching bath containing phosphoric acid, which selectively etches silicon nitride with respect to silicon oxide, silicon, and various other materials used in the art. The support pillar structure 20, the inverse stepped dielectric material portion 65, and the memory stack structure 55 provide structural support, while the backside recess 43 is present in the volume previously occupied by the sacrificial material layer 42.

[0102] Each backside recess 43 can be a laterally extending chamber, the lateral dimension of which is greater than the vertical extent of the chamber. In other words, the lateral dimension of each backside recess 43 can be greater than the height of the backside recess 43. A plurality of backside recesses 43 can be formed in the volume from which the sacrificial material layer 42 is removed. The memory opening in which the memory stack structure 55 is formed is referred to herein as a frontside opening or a frontside chamber as compared to the backside recess 43. Each of the plurality of backside recesses 43 can extend substantially parallel to the top surface of the semiconductor material layer 10. The backside recess 43 can be vertically bounded by the top surface of the underlying carbon-oxidized silicon liner 322 (such as the first carbon-oxidized silicon liner) and the bottom surface of the overlying carbon-oxidized silicon liner 322 (such as the second carbon-oxidized silicon liner). In one embodiment, each backside recess 43 can have a uniform height overall.

[0103] Figures 9A to 9C A sequential vertical cross - section of the region of the fill structure 58 around the memory opening in the first configuration of the first exemplary structure during the formation of the conductive layer 46 according to the first embodiment of the present disclosure.

[0104] See Figure 9A , which shows the region of the fill structure 58 around the memory opening in the first configuration of the first exemplary structure after the processing steps of Figure 8 . The isotropic etching process for etching the sacrificial material layer 42 can be selective with respect to the materials of the insulating layer 32, the silicon carbon oxide liner 332, and the silicon oxide liner 51.

[0105] See Figure 9B , and an isotropic etching process for etching the material of the silicon oxide liner 51 is performed. The etching chemistry of the isotropic etching process is selected such that the isotropic etching process etches the material of the silicon oxide liner 51 (i.e., the silicon oxide material) at a higher etching rate than the material of the silicon carbon oxide liner 332. In other words, the isotropic etching process etches the material of the silicon oxide liner at a higher etching rate than the materials of the first silicon carbon oxide liner 332 and the second silicon carbon oxide liner 332.

[0106] In one illustrative example, the silicon oxide liner 51 may comprise silicon dioxide, and the isotropic etching process may include diluted hydrofluoric acid or buffered hydrofluoric acid. The etching rate of the silicon carbon oxide material formed by chemical vapor deposition with silane and carbon dioxide as precursor gases in 500:1 diluted hydrofluoric acid is about 2.2 nm / min. The etching rate of the silicon dioxide formed by the decomposition of tetraethyl orthosilicate glass in 500:1 diluted hydrofluoric acid is about 11.8 nm / min. In this case, the ratio of the etching rate of the silicon carbon oxide material to the etching rate of the silicon oxide material is about 0.18. Using buffered hydrofluoric acid as the etching liquid provides a ratio of about 0.48 between the etching rate of the silicon carbon oxide material and the etching rate of the silicon oxide material.

[0107] Generally speaking, the etching rate of the silicon carbon oxide liner 322 can be significantly less than the etching rate of the silicon oxide material of the silicon oxide liner 51. In one embodiment, the etching rate of the silicon carbon oxide liner 322 is less than 50% of the etching rate of the silicon oxide material of the silicon oxide liner 51. In one embodiment, the etching rate of the silicon carbon oxide liner 322 is less than 20% of the etching rate of the silicon oxide material of the silicon oxide liner 51.

[0108] In one embodiment, the thickness of the silicon oxide liner 51, the thickness of the silicon oxycarbide liner 332, and the chemistry and duration of the isotropic etch process can be selected such that a cylindrical portion of the silicon oxide liner 51 is removed at each level of the backside recess 43 without completely removing the silicon oxycarbide liner 332. Cylindrical segments of the outer sidewalls of the dielectric metal oxide barrier dielectric layer 52 can be physically exposed to the backside recess 43 surrounding each memory opening fill structure 58. The silicon oxide liner 51 of each memory opening fill structure 58 can be divided into a plurality of discrete silicon oxide portions having corresponding tubular configurations, which are herein referred to as a vertical stack of tubular silicon oxide spacers 51'.

[0109] Each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 can be thinned. In one embodiment, the thickness of each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 prior to the isotropic etch process can be in the range of 0.5 nm to 4 nm and / or 1.0 nm to 2.5 nm, and the thickness of each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 after the isotropic etch process can be in the range of 0.25 nm to 2 nm and / or 0.5 nm to 1.2 nm. Generally, the thickness reduction of each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 can be in the range of 25% to 75% of the initial thickness of the corresponding silicon oxycarbide liner 332.

[0110] Generally, portions of the silicon oxide liner 51 can be removed from around the backside recess 43 by performing an isotropic etch process. Outer cylindrical surface segments of the dielectric metal oxide barrier dielectric layer 52 are exposed after the isotropic etch process. The remaining portion of the silicon oxide liner 51 includes a vertical stack of tubular silicon oxide spacers 51'. The memory film 50 includes a vertical stack of tubular silicon oxide spacers 51' in contact with the corresponding insulating layer 32.

[0111] The isotropic etch process etches the silicon oxide liner 51 isotropically. Thus, a concave annular surface is formed on each tubular silicon oxide spacer 51'. An annular pit 43D is formed between the dielectric metal oxide barrier dielectric layer 52 and the first and second silicon oxycarbide liners 332 by the isotropic etch process. In one embodiment, the plurality of tubular silicon oxide spacers 51' can include corresponding upper concave annular surfaces and corresponding lower concave annular surfaces, each having a radius of curvature equal to or greater than the thickness of each tubular silicon oxide spacer 51' (i.e., the lateral distance between the inner cylindrical sidewall and the outer cylindrical sidewall).

[0112] See Figure 9C and Figure 11, at least one conductive material can be deposited in the backside recess 43 and the pit 43D by supplying at least one reactive gas into the backside recess 43 via the backside trench 79. The metal barrier layer 46A can be deposited in the backside recess 43. The metal barrier layer 46A comprises a conductive metal material, which can be used as a diffusion barrier layer and / or an adhesion promoting layer for a subsequently deposited metal filling material. The metal barrier layer 46A can comprise a conductive metal nitride material, such as TiN, TaN, WN, or a stack thereof, or can comprise a conductive metal carbide material, such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer 46A can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer 46A can be in the range of 2 nm to 8 nm, such as 3 nm to 6 nm, although smaller and larger thicknesses can also be employed. In one embodiment, the metal barrier layer 46A can consist essentially of a conductive metal nitride such as TiN.

[0113] The metal filling material is deposited in the plurality of backside recesses 43, on the sidewalls of at least one backside trench 79, and above the top surface of the contact-level dielectric layer 80 to form the metal filling material layer 46B. The metal filling material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal filling material layer 46B can consist essentially of at least one elemental metal. The at least one elemental metal of the metal filling material layer 46B can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal filling material layer 46B can consist essentially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas such as WF6 can be used to deposit the metal filling material layer 46B. In one embodiment, the metal filling material layer 46B can be a tungsten layer containing a residual level of fluorine atoms as impurities. The metal filling material layer 46B is spaced apart from the insulating layer 32 and the memory stack structure 55 by the metal barrier layer 46A, which is a metal barrier layer that blocks the diffusion of fluorine atoms therethrough.

[0114] A plurality of conductive layers 46 can be formed in the plurality of backside recesses 43, and a continuous metal material layer can be formed on the sidewalls of each backside trench 79 and above the contact-level dielectric layer 80. Each conductive layer 46 includes a portion of the metal barrier layer 46A and a portion of the metal filling material layer 46B, which are located between a pair of vertically adjacent dielectric material layers (such as a pair of insulating layers 32). The continuous metal material layer includes a continuous portion of the metal barrier layer 46A and a continuous portion of the metal filling material layer 46B, which are located in the backside trench 79 or above the contact-level dielectric layer 80.

[0115] By performing an isotropic etching process that etches at least one conductive material of the continuous conductive material layer, the deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each backside trench 79 and from above the contact-level dielectric layer 80. Each remaining portion of the deposited metal material in the backside recess 43 constitutes the conductive layer 46. Each conductive layer 46 can be a wire structure. Thus, the sacrificial material layer 42 is replaced with the conductive layer 46.

[0116] Each conductive layer 46 can be used as a combination of a plurality of control gate electrodes located at the same level and a word line that electrically interconnects (i.e., electrically shorts) the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each conductive layer 46 are control gate electrodes for a vertical memory device including the memory stack structure 55. In other words, each intermediate conductive layer 46 can be a word line that serves as a common control gate electrode for a plurality of vertical memory devices. At least one topmost conductive layer 46 can be a drain-side select gate electrode. At least one bottommost conductive layer 46 can be a source-side select gate electrode.

[0117] The conductive layer 46 is directly formed on the outer cylindrical surface section of the dielectric metal oxide barrier dielectric layer 52 of each memory opening filling structure 58. As Figure 9C shown in the illustration in, in one embodiment, the tubular silicon oxide spacer 51' includes a corresponding upper concave annular surface UCAS and a corresponding lower concave annular surface LCAS, and the conductive layer 46 is formed on the upper concave annular surface UCAS and the lower concave annular surface LCAS of the tubular silicon oxide spacer 51'.

[0118] The conductive layer 46 has a hammer shape. At least one of the conductive layers in the conductive layer 46 includes an upper annular protruding portion UAPP and a lower annular protruding portion LAPP, the upper annular protruding portion UAPP protruding into the pit 43D above a first horizontal plane HP1 including the interface between the conductive layer 46 and the overlying carbon silicon oxide liner 332, and the lower annular protruding portion LAPP protruding into another pit 43D below a second horizontal plane HP2 including the interface between the conductive layer 46 and the underlying carbon silicon oxide liner 332.

[0119] In one embodiment, an upper annular protruding portion UAPP contacts a sidewall SW1 of an opening in an overlying silicon oxide liner 332; a lower annular protruding portion LAPP contacts a sidewall of an opening in an underlying silicon oxide liner 332; and a memory opening fill structure 58 extends vertically through the opening in the overlying silicon oxide liner 332 and through the opening in the underlying silicon oxide liner 332. In one embodiment, the upper annular protruding portion UAPP includes a first inner annular convex surface IACS1 and a first outer cylindrical surface OCS1; and the lower annular protruding portion LAPP includes a second inner annular convex surface IACS2 and a second outer cylindrical surface OCS2.

[0120] In one embodiment, a memory film 50 in each memory opening fill structure 58 includes a vertical stack of tubular silicon oxide spacers 51' that contact corresponding insulating layers in an insulating layer 32. In one embodiment, the plurality of tubular silicon oxide spacers 51' includes an upper concave annular surface UCAS that contacts a first conductive layer 46 and also includes a lower concave annular surface LCAS that contacts a second conductive layer 46.

[0121] The memory film 50 includes a continuous memory material layer (e.g., a charge storage layer) 54 that extends continuously through all of the conductive layers 46. Since the insulating layer 32 is not replaced after formation, no seams or air gaps are embedded therein.

[0122] Figures 10A to 10E is a sequential vertical cross-sectional view of a region around a memory opening fill structure 58 in a second configuration of a first exemplary structure during formation of the conductive layer 46 according to a first embodiment of the present disclosure.

[0123] See Figure 10A , which shows a region around a memory opening fill structure 58 in a second configuration of a first exemplary structure after the processing steps of Figure 8 . Figure 10A The region shown in Figure 9A may be the same as the region shown in

[0124] See Figure 10B , and perform an isotropic etching process for etching the material of the silicon oxide liner 51 in the same manner as described with reference to Figure 9B . Figure 10B The region shown in Figure 9B may be the same as the region shown in

[0125] See Figure 10C, a conformal dielectric liner 432L is deposited in an annular pit 43D surrounding the memory opening fill structure 58, on the physically exposed surfaces of the silicon oxycarbide spacer 332, and on the physically exposed surfaces of the insulating layer 32 and the contact-level dielectric layer 80. The conformal dielectric liner 432L can comprise any insulating material, such as silicon oxide. The thickness of the conformal dielectric liner 432L can be greater than half the thickness of the tubular silicon oxide spacer 51', such that the conformal dielectric liner 432L fills the annular pit 43D. For example, the thickness of the conformal dielectric liner 432L can be in the range of 2 nm to 4 nm. In one embodiment, the conformal dielectric liner 432L comprises undoped silicate glass (e.g., silicon dioxide) or doped silicate glass.

[0126] See Figure 10D , an isotropic recess etching process can be performed to etch back portions of the conformal dielectric liner 432L from outside the volume of the annular pit 43D. The horizontally extending surfaces of the silicon oxycarbide liner 332 can be physically exposed around each backside groove 43. The duration of the isotropic etching process can be selected to minimize collateral etching of the silicon oxycarbide liner 332 that serves as an etch stop layer. Each remaining portion of the conformal dielectric liner 432L filling the corresponding annular pit 43D has an annular shape and is referred to herein as a pit-fill annular dielectric spacer 432.

[0127] In one embodiment, each memory opening fill structure 58 includes a pit-fill annular dielectric spacer 432. Each tubular silicon oxide spacer 51' contacts a corresponding overlying spacer in the pit-fill annular dielectric spacer 432 and contacts a corresponding underlying spacer in the pit-fill annular dielectric spacer 432. In one embodiment, the plurality of tubular silicon oxide spacers 51' includes corresponding upper concave annular surfaces and corresponding lower concave annular surfaces.

[0128] See Figure 10E and Figure 11 , the processing steps described with reference to Figure 9C and Figure 11 can be performed to form a conductive layer 46 in the backside groove. In this configuration, the conductive layer 46 can also have a hammer shape. In a second configuration of the first exemplary structure, the conductive layer 46 is formed on the concave annular surfaces SCAS of a pair of pit-fill annular dielectric spacers 432.

[0129] The conductive layer 46 is formed directly on the outer cylindrical surface segments of the dielectric metal oxide barrier dielectric layer 52 of each memory opening fill structure 58. In one embodiment, the tubular silicon oxide spacer 51' includes a corresponding upper concave annular surface UCAS and a corresponding lower concave annular surface LCAS.

[0130] At least one of the conductive layers 46 includes an upper annular protruding portion UAPP and a lower annular protruding portion LAPP. The upper annular protruding portion UAPP protrudes above a first horizontal plane HP1 including the interface between the conductive layer 46 and the overlying silicon oxycarbide liner 332, and the lower annular protruding portion LAPP protrudes below a second horizontal plane HP2 including the interface between the conductive layer 46 and the underlying silicon oxycarbide liner 332.

[0131] In one embodiment, the upper annular protruding portion UAPP contacts the sidewall SW1 of the opening in the overlying silicon oxycarbide liner 332; the lower annular protruding portion LAPP contacts the sidewall of the opening in the underlying silicon oxycarbide liner 332; and the memory opening fill structure 58 extends vertically through the opening in the overlying silicon oxycarbide liner 332 and through the opening in the underlying silicon oxycarbide liner 332. In one embodiment, the upper annular protruding portion UAPP includes a first inner annular convex surface IACS1 and a first outer cylindrical surface OCS1; and the lower annular protruding portion LAPP includes a second inner annular convex surface IACS2 and a second outer cylindrical surface OCS2.

[0132] In one embodiment, the memory film 50 in each memory opening fill structure 58 includes a vertical stack of tubular silicon oxide spacers 51' in contact with the corresponding insulating layer in the insulating layer 32. In one embodiment, the plurality of tubular silicon oxide spacers 51' includes an upper concave annular surface UCAS in contact with the first pit-fill annular dielectric spacer 432, and also includes a lower concave annular surface LCAS in contact with the pit-fill annular dielectric spacer 432.

[0133] See Figure 12A and Figure 12B An insulating material layer can be formed in the backside trenches 79 and over the alternating stacks of the contact-level dielectric layer 80 and the insulating layer 32 and the conductive layer 46 by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer contains an insulating material such as silicon oxide, silicon nitride, dielectric metal oxide, organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can contain silicon oxide. The insulating material layer can be formed, for example, by low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in the range of 1.5 nm to 60 nm, but smaller or larger thicknesses can also be employed.

[0134] Anisotropic etching is performed to remove the horizontal portions of the insulating material layer from above the contact-level dielectric layer 80 and from the bottom of each backside trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A backside cavity exists within the volume surrounded by each insulating spacer 74.

[0135] The top surface of the source region 61 may be physically exposed at the bottom of each dorsal trench 79. The bottommost conductive layer 46 provided when forming the conductive layer 46 within the alternating stack (32, 46) may include a select gate electrode for a field effect transistor. Each source region 61 is formed in an upper portion of the semiconductor material layer 10. The semiconductor channels (59, 60) extend between each source region 61 and a corresponding set of drain regions 63. The semiconductor channels (59, 60) include the vertical semiconductor channel 60 of the memory stack structure 55.

[0136] A dorsal contact via structure 76 may be formed within each dorsal chamber. Each contact via structure 76 may fill the corresponding chamber. The contact via structure 76 may be formed by depositing at least one conductive material within the remaining unfilled volume (i.e., the dorsal chamber) of the dorsal trench 79. For example, the at least one conductive material may include a conductive liner 76A and a conductive fill material portion 76B. The conductive liner 76A may include a conductive metal liner such as TiN, TaN, WN, TiC, TaC, WC, their alloys, or their stacks. The thickness of the conductive liner 76A may range from 3 nm to 30 nm, although smaller or larger thicknesses may also be employed. The conductive fill material portion 76B may comprise a metal or a metal alloy. For example, the conductive fill material portion 76B may comprise W, Cu, Al, Co, Ru, Ni, their alloys, or their stacks.

[0137] The at least one conductive material may be planarized using a contact-level dielectric layer 80 covering the alternating stack (32, 46) as a barrier layer. If a chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer 80 may be used as the CMP barrier layer. Each remaining continuous portion of the at least one conductive material within the dorsal trench 79 constitutes a dorsal contact via structure 76. Each dorsal contact via structure 76 extends through the alternating stack (32, 46) and contacts the top surface of the corresponding source region 61.

[0138] Generally, a dorsal contact via structure 76 may be formed within each dorsal trench of the dorsal trenches 79 by depositing and planarizing at least one conductive material within the volume of the dorsal trench 79 not filled with the insulating spacer 74 after forming the insulating spacer 74.

[0139] Alternatively, the above-mentioned insulating material layer may be formed within the dorsal trench 79 to completely fill the entire volume of the dorsal trench 79 and may consist essentially of at least one dielectric material. In this alternative embodiment, the source region 61 and the dorsal trench via structure 76 may be omitted, and a horizontal source line (e.g., a direct strip contact) may contact one side of the lower portion of the semiconductor channel 60.

[0140] See Figure 13A andFigure 13B Additional contact via structures (88, 86, 386) can be formed through the contact-level dielectric layer 80 and optionally through the inverse-stepped dielectric material portion 65. For example, the drain contact via structure 88 can be formed through the contact-level dielectric layer 80 over each drain region 63. The layer contact via structure 86 can be formed through the contact-level dielectric layer 80 and through the inverse-stepped dielectric material portion 65 over the conductive layer 46. The through-memory-level connection via structure 386 can be formed directly over the corresponding metal pad 682 through the inverse-stepped dielectric material portion 65 and through the semiconductor material layer 10. Insulating spacers 384 can be formed around each through-memory-level connection via structure 386 to electrically isolate the through-memory-level connection via structure 386 from the semiconductor material layer 10.

[0141] Figures 14A to 14F is a sequential schematic vertical cross-sectional view of a memory opening 49 within a second exemplary structure during formation of a memory opening fill structure 58 according to a second embodiment of the present disclosure.

[0142] See Figure 14A , which shows a region around the memory opening 49 in a second exemplary structure according to a second embodiment of the present disclosure. The second exemplary structure in this processing step can be the same as the first exemplary structure after the processing steps of Figure 4A and Figure 4B . The sacrificial material layer 42 comprises silicon nitride.

[0143] See Figure 14B , the processing steps described with reference to Figure 5B can optionally be performed to form optional pedestal trench portions 11 at the bottom of each of the memory opening 49 and the support opening 19. An oxidation process is performed to convert the physically exposed surface portions of the sacrificial material layer 42 around each memory opening 49 and around each support opening 19 into tubular silicon oxide portions 41. The surface portions of each sacrificial material layer 42 are oxidized into tubular silicon oxide portions 41. The oxidation process can include a thermal oxidation process or a plasma oxidation process. In one embodiment, the sacrificial material layer 42 comprises a silicon nitride layer, and the tubular silicon oxide portions 41 are nitrogen-free or contain a residual amount of nitrogen atoms (e.g., portion 41 can comprise silicon oxynitride). If the silicon oxide portions 41 contain a residual amount of nitrogen atoms, each silicon oxide portion in the silicon oxide portions 41 can have a compositional variation where the atomic concentration of nitrogen atoms increases with the lateral distance from the memory opening 49. In other words, the atomic concentration of the residual nitrogen atoms within the tubular silicon oxide portions 41 can increase with the lateral distance from the clearance with the corresponding memory opening 49 or the clearance with the corresponding support opening 19.

[0144] Each tubular silicon oxide portion 41 may have a uniform thickness except for the top portion and the bottom portion. The top portion and the bottom portion of the tubular silicon oxide portion 41 may have a greater thickness near the interface with the corresponding silicon oxycarbide liner 332 because the silicon oxycarbide material of the silicon oxycarbide liner 332 and the silicon oxide material of the insulating layer 32 allow oxygen atoms to diffuse during oxidation. The thickness of the middle portion of each tubular silicon oxide portion 42 may be in the range of 1 nm to 12 nm, for example, 3 nm to 8 nm, but smaller and larger thicknesses may also be employed.

[0145] If the optional base channel portion 11 is formed in the memory opening 49, an optional planar semiconductor oxide plate 111 is formed at the bottom of each of the memory opening 49 and the support opening 19 by oxidation of the physically exposed surface portion of the base channel portion 11. The planar semiconductor oxide plate (e.g., silicon oxide plate) 111 is located on the top surface of the base channel portion 11.

[0146] See also Figure 14C , executable reference Figure 5C The processing steps described omit the silicon oxide liner 51 to form a memory film 50, which includes a dielectric metal oxide blocking dielectric layer 52, a silicon oxide blocking dielectric layer 53, a memory material layer 54 and a tunneling dielectric layer 56 from bottom to top above the topmost insulating layer 32T and from outside to inside within each memory opening 49.

[0147] See also Figure 14D , executable reference Figure 5D The processing steps are described to remove the horizontally extending portion of the memory film 50 and to physically expose the surface of the base channel portion 11 or the semiconductor material layer 10 at the bottom of each of the memory opening 49 and the support opening 19 .

[0148] See also Figure 14E , executable reference Figure 5E The processing steps are described to form a semiconductor channel layer 60L and a dielectric core 62 within each of the memory opening 49 and the support opening 19 .

[0149] See also Figure 14F , executable reference Figure 5FThe described processing steps form a vertical semiconductor channel 60 and a drain region 63 in each of the memory opening 49 and the support opening 19. A memory opening fill structure 58 is formed in each memory opening 49, and a support pillar structure 20 is formed in each support opening 19. Each memory opening fill structure 58 includes a memory film 50 and further includes a vertical semiconductor channel 60 formed on the memory film 50, and the memory film includes, from outside to inside, a dielectric metal oxide barrier dielectric layer 52, a silicon oxide barrier dielectric layer 53, a memory material layer 54, and a tunneling dielectric layer 56.

[0150] Subsequently, the processing steps described with reference to Figure 7A and Figure 7B can be performed to form a contact level dielectric layer 80, a back trench 79, and a source region 61.

[0151] The processing steps described with reference to Figure 8 and Figure 9A can be performed to remove the sacrificial material layer 42 and form a back groove 43.

[0152] Figures 15A to 15C is a sequential vertical cross-sectional view of a region around the memory opening fill structure 58 in a second exemplary structure during the formation of the conductive layer 46 according to a second embodiment of the present disclosure.

[0153] See Figure 15A , which shows a region around the memory opening fill structure 58 in a first configuration of a first exemplary structure after the formation of the back groove 43. The isotropic etching process for etching the sacrificial material layer 42 can be selective with respect to the materials of the insulating layer 32, the carbon silicon oxide liner 332, and the tubular silicon oxide portion 41. The back groove 43 can be formed by selectively removing the sacrificial material layer 42 with respect to the carbon silicon oxide liner 332 and the tubular silicon oxide portion 41.

[0154] See Figure 15B , and an isotropic etching process for etching the material of the tubular silicon oxide portion 41 is performed. The tubular silicon oxide portion 41 can be etched selectively with respect to the dielectric metal oxide barrier dielectric layer 52. The etching chemistry of the isotropic etching process is selected such that the isotropic etching process etches the material of the tubular silicon oxide portion 41 (i.e., silicon oxide material) at a higher etching rate than the material of the carbon silicon oxide liner 332.

[0155] In an illustrative example, the tubular silicon oxide portion 41 may include silicon oxide, and the isotropic etching process may include dilute hydrofluoric acid or buffered hydrofluoric acid. The etching rate of the silicon oxide carbide liner 322 may be significantly less than the etching rate of the silicon oxide material of the tubular silicon oxide portion 41. In one embodiment, the etching rate of the silicon oxide carbide liner 322 is less than 50% of the etching rate of the silicon oxide material of the tubular silicon oxide portion 41. In one embodiment, the etching rate of the silicon oxide carbide liner 322 is less than 20% of the etching rate of the silicon oxide material of the tubular silicon oxide portion 41.

[0156] The entire tubular silicon oxide portion 41 may be removed without completely removing the silicon oxycarbide liner 332. A cylindrical section of the outer sidewall of the dielectric metal oxide blocking dielectric layer 52 may be physically exposed to the backside recess 43 surrounding each memory opening filling structure 58. Each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 may be thinned. In one embodiment, the thickness of each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 may be in the range of 0.5 nm to 4 nm and / or 1.0 nm to 2.5 nm before the isotropic etching process, and the thickness of each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 may be in the range of 0.25 nm to 2 nm and / or 0.5 nm to 1.2 nm after the isotropic etching process. Generally, the reduction in thickness of each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 may be in a range of 25% to 75% of the initial thickness of the corresponding silicon oxycarbide liner 332 .

[0157] See also Figure 15C , executable reference Figure 9C The processing steps described are to form a conductive layer 46 in the backside recess 43. In the second exemplary structure, the conductive layer 46 can be formed directly on the horizontally extending surface of the silicon oxycarbide liner 332. In one embodiment, the conductive layer 46 is formed directly on the cylindrical outer surface segment of the dielectric metal oxide blocking dielectric layer 52. In one embodiment, each conductive layer 46 has a corresponding uniform vertical thickness throughout. Each cylindrical surface of the conductive layer 46 that contacts the corresponding dielectric metal oxide blocking dielectric layer 52 can have an upper perimeter adjacent to the horizontally extending top surface of the conductive layer 46 and a lower perimeter adjacent to the horizontally extending bottom surface of the conductive layer 46.

[0158] Then, you can execute the reference Figure 12A and Figure 12B The processing steps described and reference Figure 13A and Figure 13B The processing steps described.

[0159] Referring to all the figures and in accordance with various embodiments of the present disclosure, a memory device includes: an alternating stack (32, 46) of an insulating layer 32 and a conductive layer 46, wherein a first conductive layer 46 in the conductive layer 46 contacts an underlying silicon oxycarbide liner 332 and an overlying silicon oxycarbide liner 332; a memory opening 49 that extends vertically through the alternating stack (32, 46); and a memory opening fill structure 58 that is located in the memory opening 49 and includes a vertical semiconductor channel 60 and a memory film that includes a continuous memory material layer 54 that extends continuously through the entire alternating stack.

[0160] In one embodiment, the memory film 50 includes, from the outside to the inside, a dielectric metal oxide barrier dielectric layer 52, a silicon oxide barrier dielectric layer 53, a continuous memory material layer 54, and a tunneling dielectric layer 56.

[0161] In one embodiment, the first conductive layer 46 includes: an upper annular protruding portion UAPP that protrudes above a first horizontal plane HP1 that includes an interface between the first conductive layer 46 and the overlying silicon oxycarbide liner 332; and a lower annular protruding portion LAPP that protrudes below a second horizontal plane HP2 that includes an interface between the first conductive layer 46 and the underlying silicon oxycarbide liner 332. In one embodiment, the upper annular protruding portion UAPP contacts a sidewall SW1 of an opening in the overlying silicon oxycarbide liner 332; the lower annular protruding portion LAPP contacts a sidewall of an opening in the underlying silicon oxycarbide liner 332; and the memory opening fill structure 58 extends vertically through the opening in the overlying silicon oxycarbide liner 332 and through the opening in the underlying silicon oxycarbide liner 332. In one embodiment, the upper annular protruding portion UAPP includes a first inner annular convex surface IACS1 and a first outer cylindrical surface OCS1; and the lower annular protruding portion LAPP includes a second inner annular convex surface IACS2 and a second outer cylindrical surface OCS2.

[0162] In one embodiment, the memory film 50 includes a vertical stack of tubular silicon oxide spacers 51' that contact corresponding insulating layers in the insulating layer 32. In one embodiment, one tubular silicon oxide spacer 51' includes an upper concave annular surface UCAS that contacts the first conductive layer 46 and also includes a lower concave annular surface LCAS that contacts a second conductive layer 46 in the conductive layer 46. In one embodiment, the memory opening fill structure 58 includes a pit-fill annular dielectric spacer 432; and each tubular silicon oxide spacer 51' contacts a corresponding overlying spacer in the pit-fill annular dielectric spacer 432 and contacts a corresponding underlying spacer in the pit-fill annular dielectric spacer 432.

[0163] In one embodiment, the overlying silicon oxycarbide liner 332 contacts the bottom surface of the overlying insulating layer 32 in the insulating layer 32; and the underlying silicon oxycarbide liner 332 contacts the top surface of the underlying insulating layer 32 in the insulating layer 32.

[0164] In one embodiment, the insulating layer 32 does not have seams or air gaps embedded therein. In one embodiment, each conductive layer 46 has a corresponding uniform vertical thickness overall.

[0165] Various embodiments of the present disclosure provide a conductive layer 46 with less or no corner rounding around the memory opening filling structure 58. The conductive layer 46 may include a pair of corresponding annular protrusions or right-angle corners at the interface with the dielectric metal oxide blocking dielectric layer 52. Reduced or eliminated corner rounding reduces the short-channel effect and improves the controllability of the control gate electrode and the length of the control gate electrode adjacent to the memory film 50.

[0166] See Figure 16 , by omitting Figure 1 the formation of at least one instance of the silicon oxycarbide liner 332 in the first exemplary structure of Figure 1 shown, the third exemplary structure according to the third embodiment of the present disclosure can be obtained from Figure 21 shown. An additional vertical repetition of multiple instances of the first repeating unit (shown in Figure 16 ) is then formed above the structure shown in Figure 1 . Thus, Figure 16 the insulating layer 32 in the first exemplary structure of Figure 1 is referred to as the first insulating layer 132 in the third exemplary structure of Figure 16 , the sacrificial material layer 42 in the first exemplary structure of Figure 1 is referred to as the first sacrificial material layer 142 in the third exemplary structure of

[0167] According to a third implementation of the present disclosure, at least one instance of the silicon oxycarbide liner 332 in the third exemplary structure is omitted such that at least one (e.g., the topmost) first layer of sacrificial material layer 142 is in direct contact with one of the first layer of insulating layers 132 and in direct contact with one of the silicon oxycarbide liners 332. In other words, at least one first layer of sacrificial material layer 142 is provided such that the silicon oxycarbide liner 332 is interposed between each such first layer of sacrificial material layer 142 and the corresponding first adjacent first layer of insulating layer 132, and each such first layer of sacrificial material layer 142 is in direct contact with the second first layer of insulating layer 132.

[0168] In Figure 16 the illustrated example, the silicon oxycarbide liner 332 is interposed between the topmost first layer of sacrificial material layer 142 and the second topmost first layer of insulating layer 132, while the topmost first layer of sacrificial material layer 142 is in direct contact with the topmost first layer of insulating layer 132. Accordingly, the topmost first layer of sacrificial material layer 142 has a first (e.g., bottom) major horizontal surface that contacts the corresponding silicon oxycarbide liner 332, and a second (e.g., top) major horizontal surface that contacts the corresponding (e.g., topmost) first layer of insulating layer (e.g., silicon oxide layer) 132. Specifically, the silicon oxycarbide liner 332 can be omitted directly below and directly above the bonding region between the first device layer and the second device layer, as will be described in more detail with respect to Figure 21 below.

[0169] A first alternating stack of the first layer of insulating layer 132 and the first layer of sacrificial material layer 142 is formed in the first layer such that the silicon oxycarbide liner 332 is interposed between most adjacent pairs of the first layer of insulating layer 132 and the first layer of sacrificial material layer 142 and is absent from a few adjacent pairs of the first layer of insulating layer 132 and the first layer of sacrificial material layer 142. The set of all layers covering the semiconductor material layer 10 is referred to herein as the first layer of material layers (132, 142, 332).

[0170] Although an implementation has been described in which only one first layer of sacrificial material layer 142 is in direct contact with one first layer of insulating layer 132 and one silicon oxycarbide layer 332, implementations in which multiple first layers of sacrificial material layer 142 are in direct contact with corresponding first layers of insulating layer 132 and corresponding silicon oxycarbide layers 332 are explicitly contemplated herein.

[0171] See Figure 17 and the processing steps described with reference to Figure 2 can be performed to form a stepped surface in the contact region 300. The stepped surface formed on the first layer of material layers (132, 142, 332) is referred to herein as the first stepped surface. Then, the processing steps described with reference to Figure 3The described processing steps are performed to form an inverse stepped dielectric material portion, which is referred to herein as the first inverse stepped dielectric material portion 165.

[0172] Subsequently, a dielectric material layer composed of and / or substantially consisting of silicon oxide (e.g., silicon dioxide) may be formed over the first layer of material layers (132, 142, 332) and the first inverse stepped dielectric material portion 165. The dielectric material layer is referred to herein as the interlayer dielectric layer 170. The thickness of the interlayer dielectric layer 170 may be in the range of 50 nm to 250 nm, although smaller and larger thicknesses may also be employed.

[0173] See Figure 18A and Figure 18B , a lithographic material stack (not shown) including at least a photoresist layer may be formed over the interlayer dielectric layer 170 and may be lithographically patterned to form openings therein. The openings include a first set of openings formed in the memory array region 100 and a second set of openings formed in the contact region 300. The pattern in the lithographic material stack may be transferred through the interlayer dielectric layer 170, the first layer of material layers (132, 142, 332), and the first inverse stepped dielectric material portion 165 by at least one anisotropic etch using the patterned lithographic material stack as an etch mask. The portions of the interlayer dielectric layer 170, the first layer of material layers (132, 142, 332), and the first inverse stepped dielectric material portion 165 located below the openings in the patterned lithographic material stack are etched to form first layer memory openings 149 and first layer support openings 119. The first layer memory openings 149 are formed through each layer of the interlayer dielectric layer 170 and the first layer of material layers (132, 142, 332) in the memory array region 100. The first layer support openings 119 are formed through each layer of the interlayer dielectric layer 170 and the first layer of material layers (132, 142, 332) in the contact region 300. The patterned lithographic material stack may then be removed, for example, by ashing.

[0174] The first layer memory openings 149 and the first layer support openings 119 may extend from the top surface of the interlayer dielectric layer 170 to a horizontal plane including at least the topmost surface of the semiconductor material layer 10. In one embodiment, an over-etch in the semiconductor material layer 10 may optionally be performed after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each of the first layer memory openings 149 and each of the first layer support openings 119. Each of the first layer memory openings 149 and the first layer support openings 119 may include sidewalls (or a sidewall) extending substantially perpendicular to the topmost surface of the semiconductor material layer 10. A two-dimensional array of the first layer memory openings 149 may be formed in the first layer memory array region 100. A two-dimensional array of the first layer support openings 119 may be formed in the contact region 300.

[0175] See Figure 19 , a first sacrificial fill material may be deposited in the first layer memory opening 49 and the first layer support opening 19. The first sacrificial fill material may include a carbon-based material (such as amorphous carbon or diamond-like carbon), a polymer material, a semiconductor material, or any other suitable material that can be selectively removed relative to the semiconductor material layer 10 and the materials of the first layer material layers (132, 142, 332). Portions of the first sacrificial fill material may be removed by performing a recess etch process from above a horizontal plane located at or around the bottom surface of the interlayer dielectric layer 170. Each remaining portion of the first sacrificial fill material filling the first layer memory opening 149 constitutes a first layer sacrificial memory opening fill structure 148. Each remaining portion of the first sacrificial fill material filling the first layer support opening 119 constitutes a first layer sacrificial support opening fill structure 118.

[0176] An isotropic etch process may be performed to isotropically recess the physically exposed surface of the interlayer dielectric layer 170. The upper portions of the first layer memory opening 149 and the first layer support opening 119 that are not filled with the first layer sacrificial memory opening fill structure 148 or the first layer sacrificial support opening fill structure 118 may be laterally expanded by the isotropic etch process. Additionally, the top surface of the interlayer dielectric layer 170 may be vertically recessed by the isotropic etch process. In one illustrative example, a wet etch process using diluted hydrofluoric acid may be performed to isotropically recess the physically exposed surface of the interlayer dielectric layer 170. The lateral recess distance of the isotropic etch process may be in the range of 10% to 80% (such as 25% to 50%) of the thickness of the interlayer dielectric layer 170. For example, the lateral recess distance of the isotropic etch process may be in the range of 10 nm to 50 nm, but smaller and larger lateral recess distances may also be employed.

[0177] See Figure 20 , a second sacrificial fill material may be deposited in the unfilled volumes in the upper portions of the first layer memory opening 149 and the first layer support opening 119 at the level of the interlayer dielectric layer 170. The second sacrificial fill material may include the same material as the first sacrificial fill material. Portions of the second sacrificial fill material may be removed from above a horizontal plane including the top surface of the interlayer dielectric layer 170 by performing a planarization process, which may include a recess etch process and / or a chemical mechanical polishing (CMP) process. Each remaining portion of the second sacrificial fill material filling the upper portion of the first layer memory opening 149 constitutes an interlayer sacrificial memory opening fill structure 448. Each remaining portion of the second sacrificial fill material filling the upper portion of the first layer support opening 119 constitutes an interlayer sacrificial support opening fill structure 418.

[0178] See Figure 21 , Refer toFigure 1 The described processing steps may be performed again with appropriate modifications to form a second vertical repetition of multiple instances of the second repeating unit without forming at least one instance of the silicon oxycarbide liner 332. Each instance of the second repeating unit in the third exemplary structure includes a second insulating layer 232, a first silicon oxycarbide liner 332, a first sacrificial material layer 242, and a second silicon oxycarbide liner 332. In one embodiment, the silicon oxynitride liner 332 may be omitted from one or more instances of the second repeating unit. In the illustrated example, the bottommost first silicon oxycarbide liner 332 is omitted such that the bottommost second sacrificial material layer 242 is formed directly on the top surface of the interlayer dielectric layer 170.

[0179] In one embodiment, at least one second sacrificial material layer 242 is provided that is in direct contact with one of the insulating layers in the second insulating layer 232 and in direct contact with one of the silicon oxycarbide liners 332. In other words, at least one second sacrificial material layer 242 is provided such that a silicon oxycarbide liner 332 is interposed between each such second sacrificial material layer 242 and the corresponding adjacent second insulating layer 232, and each such second sacrificial material layer 242 is in direct contact with another second insulating layer 232 or the interlayer dielectric layer 170. In Figure 21 the illustrated example, a silicon oxycarbide liner 332 is interposed between the bottommost second sacrificial material layer 242 and the overlying (i.e., bottommost) second insulating layer 232, and the bottommost second sacrificial material layer 242 is in direct contact with the interlayer dielectric layer 170, which is a dielectric layer composed of a silicon oxide (e.g., silicon dioxide) material.

[0180] Accordingly, a second alternating stack of the second insulating layer 232 and the second sacrificial material layer 242 is formed such that a silicon oxycarbide liner 332 is interposed between most adjacent pairs of the second insulating layer 232 and the second sacrificial material layer 242 and is absent from a minority of adjacent pairs of the second insulating layer 232 and the second sacrificial material layer 242. The set of all layers covering the interlayer dielectric layer 170 is referred to herein as the second material layer (232, 242, 332).

[0181] Although embodiments are described in which only one second sacrificial material layer 242 is in direct contact with the silicon oxide material layer and one silicon oxycarbide layer 332, embodiments are expressly contemplated herein in which multiple second sacrificial material layers 242 are in direct contact with respective silicon oxide layers (such as the second insulating layer 232 or the interlayer dielectric layer 170) and respective silicon oxycarbide layers 332. In one embodiment, a second vertical repetition of multiple instances of a repeating unit of the second insulating layer 232, the first silicon oxycarbide liner 332, the second sacrificial material layer 242, and the second silicon oxycarbide liner 332 may be formed on the interlayer dielectric layer 170, wherein the bottommost silicon oxynitride liner 332 is omitted.

[0182] Generally speaking, an alternating stack {(132, 142), (232, 242)} of insulating layers (132, 232) and sacrificial material layers (142, 242) can be formed such that a silicon oxycarbide liner 332 is interposed between a first sacrificial material layer (142 or 242) and a first insulating layer (132 or 232), and the first sacrificial material layer (142 or 242) is in direct contact with the second insulating layer (132 or 232) or with a dielectric material layer (such as an interlayer dielectric layer 170) composed of a silicon oxide material (i.e., it is not a silicon oxycarbide layer).

[0183] See also Figure 22 , executable reference Figure 2 The processing steps are described to form a second stepped surface by patterning the second material layer (232, 242, 332). Subsequently, a dielectric fill material such as silicon oxide may be deposited on the second stepped surface and may be planarized to form a second inverse stepped dielectric material portion 265. The top surface of the second inverse stepped dielectric material portion 265 may be formed in a horizontal plane including the topmost surface of the second material layer (232, 242, 332) (such as the top surface of the topmost second insulating layer 232).

[0184] The first insulating layer 132 and the second insulating layer 232 are collectively referred to as insulating layers 32. The first sacrificial material layer 142 and the second sacrificial material layer 242 are collectively referred to as sacrificial material layers 42.

[0185] See also Figure 23 A photolithographic material stack (not shown) including at least a photoresist layer may be formed on the second material layer (232, 242, 332) and may be photolithographically patterned to form openings therein. The openings include a first group of openings formed in the memory array region 100 and a second group of openings formed in the contact region 300. The first group of openings has an area overlap with the first layer of sacrificial memory opening filling structure 148, and the second group of openings has an area overlap with the first layer of sacrificial support opening filling structure 118.

[0186] Patterns in the photolithographic material stack can be transferred through the second layer of material layers (232, 242, 332) and the second inverse stepped dielectric material portion 265 by at least one anisotropic etching using the patterned photolithographic material stack as an etch mask. Portions of the second layer of material layers (232, 242, 332) and the second inverse stepped dielectric material portion 265 that are located below the openings in the patterned photolithographic material stack are etched to form second layer memory openings 249 and second layer support openings 219. The second layer memory openings 249 are formed through each of the second layer of material layers (132, 242, 332) in the memory array region 100. The second layer support openings 219 are formed through each of the second layer of material layers (132, 242, 332) in the contact region 300. The patterned photolithographic material stack can then be removed, for example, by ashing. The top surface of the interlayer sacrificial memory opening fill structure 448 is physically exposed at the bottom of each second layer memory opening 249. The top surface of the interlayer sacrificial support opening fill structure 418 is physically exposed at the bottom of each second layer support opening 219.

[0187] See Figure 24 , the interlayer sacrificial memory opening fill structure 448, the interlayer sacrificial support opening fill structure 418, the first layer sacrificial memory opening fill structure 148, and the first layer sacrificial support opening fill structure 118 can be selectively removed relative to the materials of the second layer of material layers (232, 242, 332), the first layer of material layers (132, 142, 332), the interlayer material layer 170, and the semiconductor material layer 10. For example, if the interlayer sacrificial memory opening fill structure 448, the interlayer sacrificial support opening fill structure 418, the first layer sacrificial memory opening fill structure 148, and the first layer sacrificial support opening fill structure 118 comprise carbon-based materials, an ashing process can be performed to remove the interlayer sacrificial memory opening fill structure 448, the interlayer sacrificial support opening fill structure 418, the first layer sacrificial memory opening fill structure 148, and the first layer sacrificial support opening fill structure 118.

[0188] Each continuous void including the volume from which the first-layer sacrificial memory opening filling structure 148 and the inter-layer sacrificial memory opening filling structure 448 are removed, and the volume of the second-layer memory opening 249 constitutes an inter-layer memory opening 49, which is also referred to as a memory opening 49. Each continuous void including the volume from which the first-layer sacrificial support opening filling structure 118 and the inter-layer sacrificial support opening filling structure 418 are removed, and the volume of the second-layer support opening 219 constitutes an inter-layer support opening 19, which is also referred to as a support opening 19. The memory opening 49 and the support opening 19 have a wider width (e.g., a larger diameter) at the level of the inter-layer dielectric layer 170 (i.e., in the bonding area between the first layer and the second layer) than at the level of the first layer and the second layer (i.e., at the level of the first material layer (132, 142, 332) and the second material layer (232, 242, 332)).

[0189] See also Figures 25A to 25C , executable reference Figures 5A to 5F The processing steps are described to form a memory opening filling structure 58 in each memory opening 49 and to form a support pillar structure 20 in each support opening 19. Each memory opening filling structure 58 may be formed in a corresponding memory opening 49 and may include a corresponding vertical semiconductor channel 60 and a corresponding memory film 50. Each memory film 50 may include a continuous memory material layer 54 extending continuously through the entire alternating stack {(132, 142), (232, 242)}. A drain select level isolation structure 72 may be formed through at least one second sacrificial material layer 242.

[0190] Figure 25B Shown around Figure 25A , wherein each memory film 50 includes, from outside to inside, a silicon oxide liner 51, a dielectric metal oxide blocking dielectric layer 52, a silicon oxide blocking dielectric layer 53, a continuous memory material layer 54, and a tunneling dielectric layer 56. The dielectric metal oxide blocking dielectric layer 52 may include an aluminum oxide layer.

[0191] Figure 25C Shown around Figure 25A An alternative embodiment of the third exemplary structure of the memory opening filling structure 58 in FIG. 5 , wherein each memory film 50 includes a silicon oxide blocking dielectric layer 53, a continuous memory material layer 54, and a tunneling dielectric layer 56 from the outside to the inside.

[0192] See also Figure 26A and Figure 26B, a contact-level dielectric layer 80 can be formed above the second material layer (232, 242, 332) and above the memory opening filling structure 58 and the support pillar structure 20. The contact-level dielectric layer 80 includes a dielectric material different from the dielectric material of the sacrificial material layer (142, 242). For example, the contact-level dielectric layer 80 can include silicon oxide. The contact-level dielectric layer 80 can have a thickness in the range of 50 nm to 500 nm, but smaller and larger thicknesses can also be used.

[0193] A photoresist layer (not shown) can be applied on the contact-level dielectric layer 80 and patterned lithographically to form openings in the regions between the clusters of the memory opening filling structure 58. The pattern in the photoresist layer can be transferred through the contact-level dielectric layer 80, the second material layer (232, 242, 332), the interlayer dielectric layer 170, the first material layer (132, 142, 332), the second inverse stepped dielectric material portion 265, and the first inverse stepped dielectric material portion 165. The backside trench 79 is formed in the volume from which the materials of the contact-level dielectric layer 80, the second material layer (232, 242, 332), the interlayer dielectric layer 170, the first material layer (132, 142, 332), the second inverse stepped dielectric material portion 265, and the first inverse stepped dielectric material portion 165 are derived. The backside trench 79 extends at least vertically from the top surface of the contact-level dielectric layer 80 to the top surface of the semiconductor material layer 10 and extends laterally through the memory array region 100 and the contact region 300.

[0194] In one embodiment, the backside trench 79 can extend laterally along a first horizontal direction hd1 (which can be the word line direction) and can be laterally spaced along a second horizontal direction hd2 (which can be the bit line direction) perpendicular to the first horizontal direction hd1. The memory opening filling structures 58 can be arranged in rows extending along the first horizontal direction hd1. The drain select-level isolation structures 72 can extend laterally along the first horizontal direction hd1. Each backside trench 79 can have a uniform width that is constant along the length direction (i.e., along the first horizontal direction hd1).

[0195] The multi - row memory opening fill structure 58 can be located between a pair of adjacent back - side trenches 79 and the drain select level isolation structure 72, or between a pair of adjacent drain select level isolation structures 72. In one embodiment, the back - side trench 79 can include a source contact opening, in which a source contact via structure can be subsequently formed. For example, the photoresist layer can be removed by ashing. Generally speaking, the back - side trench 79 can laterally extend along a first horizontal direction hd1 and can vertically extend from the top surface of the contact level dielectric layer 80 to the top surface of the semiconductor material layer 10. The stack of the first layer material layers (132, 142, 332), the inter - layer dielectric layer 170, the second layer material layers (232, 242, 332), and the contact level dielectric layer 80 is divided into a plurality of patterned layer stacks that are laterally spaced apart by the back - side trench 79 along a second horizontal direction hd2.

[0196] A dopant of the second conductivity type can be implanted into the physically exposed surface portion (which can be a surface portion of the semiconductor material layer 10) of the semiconductor material layer 10 at the bottom of the back - side trench through an ion implantation process. The source region 61 can be formed at the surface portion of the semiconductor material layer 10 below each back - side trench 79. Each source region 61 is formed in the surface portion of the semiconductor material layer 10 below the corresponding back - side trench 79. Due to the dispersion of the implanted dopant atoms during the implantation process and the lateral diffusion of the implanted dopant atoms during the subsequent activation annealing process, each source region 61 can have a lateral range greater than the lateral range of the overlying back - side trench 79.

[0197] The upper portion of the semiconductor material layer 10 that extends between the source region 61 in the memory opening fill structure 58 and the vertical semiconductor channel 60 constitutes the horizontal semiconductor channel 59 for a plurality of field - effect transistors. The horizontal semiconductor channel 59 is connected to a plurality of vertical semiconductor channels 60.

[0198] See Figure 27 and Figure 28A , which shows a first configuration of a third exemplary structure after forming the back - side recess 43 by selectively removing the sacrificial material layers (142, 242) with respect to the carbon - doped silicon oxide liner 332, the insulating layers (132, 232) (which contain silicon oxide material), the inter - layer dielectric layer 170 containing silicon oxide material, and the contact level dielectric layer 80.

[0199] Specifically, an etchant that selectively etches the sacrificial material layers (142, 242) relative to the insulating layers (132, 232) and the silicon oxycarbide liner 332 can be introduced into the backside trench 79 during the isotropic etching process. The backside recess 43 is formed in the volume from which the sacrificial material layers (142, 242) are removed. The removal of the sacrificial material layers (142, 242) can be selective with respect to the materials of the insulating layers (132, 232), the silicon oxycarbide liner 332, the inverse stepped dielectric material portions (165, 265), the interlayer dielectric layer 170, the semiconductor material of the semiconductor material layer 10, and the outermost layer of the memory film 50 (such as the silicon oxide liner 51).

[0200] The etching process can be a wet etching process using a wet etching solution, or can be a gas-phase (dry) etching process, where the etchant is introduced into the backside trench 79 in a gas phase. For example, if the sacrificial material layers (142, 242) comprise silicon nitride, then the etching process can be a wet etching process, where the first exemplary structure is immersed in a wet etching bath containing phosphoric acid, which selectively etches silicon nitride relative to silicon oxide, silicon, and various other materials used in the art. The support pillar structure 20, the inverse stepped dielectric material portion 65, and the memory stack structure 55 provide structural support, while the backside recess 43 is present in the volume previously occupied by the sacrificial material layers (142, 242).

[0201] Each backside recess 43 can be a laterally extending chamber, the lateral dimension of which is greater than the vertical extent of the chamber. In other words, the lateral dimension of each backside recess 43 can be greater than the height of the backside recess 43. A plurality of backside recesses 43 can be formed in the volume from which the sacrificial material layers (142, 242) are removed. The memory opening 49 in which the memory stack structure 55 is formed is referred to herein as the front-side opening or the front-side chamber as compared to the backside recess 43. Each of the plurality of backside recesses 43 can extend substantially parallel to the top surface of the semiconductor material layer 10.

[0202] According to one aspect of the present disclosure, the horizontal surface of the insulating layers (132, 232) is physically exposed to at least one of the backside recesses 43. In the illustrated example, the bottom horizontal surface of the topmost first insulating layer 132 and the top horizontal surface of the interlayer dielectric layer 170 can be physically exposed to the respective backside recesses 43.

[0203] See Figure 28B , an isotropic etching process for etching the material of the silicon oxide liner 51 is performed. The etching chemistry of the isotropic etching process is selected such that the isotropic etching process etches the material of the silicon oxide liner 51 (i.e., the silicon oxide material) at a higher etching rate than the material of the silicon oxycarbide liner 332.

[0204] In an exemplary example, the silica liner 51 may comprise silicon dioxide, and the isotropic etching process may include diluted hydrofluoric acid or buffered hydrofluoric acid. The etching rate of the silicon oxycarbide material formed by chemical vapor deposition using silane and carbon dioxide as precursor gases in 500:1 diluted hydrofluoric acid is about 2.2 nm / minute. The etching rate of the silicon dioxide formed by the decomposition of tetraethyl orthosilicate glass in 500:1 diluted hydrofluoric acid is about 11.8 nm / minute. In this case, the ratio of the etching rate of the silicon oxycarbide material to the etching rate of the silicon dioxide material is about 0.18. Using buffered hydrofluoric acid as the etching liquid provides a ratio of about 0.48 between the etching rate of the silicon oxycarbide material and the etching rate of the silicon dioxide material.

[0205] Generally speaking, the etching rate of the silicon oxycarbide liner 322 may be significantly less than the etching rate of the silicon dioxide material of the silica liner 51. In one embodiment, the etching rate of the silicon oxycarbide liner 322 is less than 50% of the etching rate of the silicon dioxide material of the silica liner 51. In one embodiment, the etching rate of the silicon oxycarbide liner 322 is less than 20% of the etching rate of the silicon dioxide material of the silica liner 51.

[0206] In one embodiment, the thickness of the silica liner 51, the thickness of the silicon oxycarbide liner 332, and the chemistry and duration of the isotropic etching process may be selected such that the cylindrical portion of the silica liner 51 is removed at each level of the backside recess 43 without completely removing the silicon oxycarbide liner 332. The cylindrical section of the outer sidewall of the dielectric metal oxide barrier dielectric layer 52 may be physically exposed to the backside recess 43 surrounding each memory opening fill structure 58. The silica liner 51 of each memory opening fill structure 58 may be divided into a plurality of discrete silica portions having corresponding tubular configurations, which are herein referred to as a vertical stack of tubular silica spacers 51'.

[0207] Each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 may be thinned. In one embodiment, the thickness of each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 before the isotropic etching process may be in the range of 0.5 nm to 4 nm and / or 1.0 nm to 2.5 nm, and the thickness of each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 after the isotropic etching process may be in the range of 0.25 nm to 2 nm and / or 0.5 nm to 1.2 nm. Generally speaking, the thickness reduction of each of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332 may be in the range of 25% to 75% of the initial thickness of the corresponding silicon oxycarbide liner 332.

[0208] According to one aspect of the present disclosure, the physical exposure level surfaces of at least one insulating layer (e.g., the topmost first insulating layer 132) and the interlayer dielectric layer 170 may be vertically recessed during an isotropic etching process. For example, the bottom horizontal surface of the topmost first insulating layer 132 and the top horizontal surface of the interlayer dielectric layer 170 may be vertically recessed during the isotropic etching process.

[0209] Generally, portions of the silicon oxide liner 51 may be removed from around the backside recess 43 by performing an isotropic etching process. The outer cylindrical surface section of the dielectric metal oxide barrier dielectric layer 52 is exposed after the isotropic etching process. The remaining portion of the silicon oxide liner 51 includes a tubular silicon oxide spacer 51', an optional annular silicon oxide spacer 151 on an annular surface section of the horizontally extending top surface of the dielectric metal oxide barrier dielectric layer 52 (which is at or above the horizontal plane including the top surface of the interlayer dielectric layer 170), and a vertical stack of profiled silicon oxide spacers 251 (which are laterally surrounded by and in contact with the interlayer dielectric layer 170 and the topmost first insulating layer 132). Thus, the memory film 50 includes a vertical stack of tubular silicon oxide spacers 51' in contact with the respective insulating layers 32.

[0210] The isotropic etching process etches the silicon oxide liner 51 isotropically. In this way, a concave annular surface is formed on each tubular silicon oxide spacer 51'. An annular pit 43D is formed between the dielectric metal oxide barrier dielectric layer 52 and the first and second silicon oxycarbide liners 332 by the isotropic etching process. In one embodiment, the plurality of tubular silicon oxide spacers 51' may include respective upper concave annular surfaces and respective lower concave annular surfaces, each having a radius of curvature equal to or greater than the thickness of each tubular silicon oxide spacer 51' (i.e., the lateral distance between the inner cylindrical sidewall and the outer cylindrical sidewall).

[0211] Generally, portions of the silicon oxide liner 51 may be selectively isotropically etched relative to the silicon oxycarbide liners 332 by performing an isotropic etching process after forming the backside recess 43. The isotropic etching process divides the silicon oxide liner 51 into a vertical stack of silicon oxide spacers (51', 151, 251) vertically spaced apart from each other. The silicon oxide spacers (51', 151, 251) include a tubular silicon oxide spacer 51' having a respective tubular configuration (i.e., a respective cylindrical outer sidewall and a respective cylindrical inner sidewall), an optional annular silicon oxide spacer 151, and a profiled silicon oxide spacer 251. A vertical stack of annular pits 43D may be formed between each silicon oxycarbide liner 332 and the dielectric metal oxide barrier dielectric layer 52.

[0212] See Figure 28C, an optional conformal dielectric liner may be deposited in the annular recess 43D surrounding the memory opening fill structure 58, on the physically exposed surfaces of the silicon oxycarbide spacers 332, and on the physically exposed surfaces of the insulating layer 32, the interlayer dielectric layer 170, and the contact-level dielectric layer 80. The conformal dielectric liner may comprise any insulating material, such as silicon oxide. The thickness of the conformal dielectric liner may be greater than half the thickness of the tubular silicon oxide spacer 51' such that the conformal dielectric liner fills the annular recess 43D. The thickness of the conformal dielectric liner may be less than the thickness of the tubular silicon oxide spacer 51'. For example, the thickness of the conformal dielectric liner may be in the range of 2 nm to 4 nm. In one embodiment, the conformal dielectric liner comprises undoped silicate glass (e.g., silicon dioxide) or doped silicate glass.

[0213] An isotropic recess etching process may be performed to etch back portions of the conformal dielectric liner from outside the volume of the annular recess 43D. The horizontally extending surfaces of the silicon oxycarbide liner 332 may be physically exposed around each backside groove 43. The duration of the isotropic etching process may be selected to minimize collateral etching of the silicon oxycarbide liner 332 that serves as an etch stop layer. Each remaining portion of the conformal dielectric liner filling the respective annular recess 43D has an annular shape and is referred to herein as a recess-fill annular dielectric spacer 432.

[0214] In one embodiment, each memory opening fill structure 58 includes a recess-fill annular dielectric spacer 432. A plurality of tubular silicon oxide spacers 51' may contact corresponding overlying spacers in the recess-fill annular dielectric spacer 432 and may contact corresponding underlying spacers in the recess-fill annular dielectric spacer 432. Alternatively, the steps Figure 28C shown are not performed and the recess-fill annular dielectric spacer 432 is omitted.

[0215] See Figure 28D , a metal barrier layer 46A may be deposited in the backside groove 43. The metal barrier layer 46A in the third exemplary structure may have the same material composition and the same thickness as the metal barrier layer 46A in the first exemplary structure and the second exemplary structure and may be formed by a conformal deposition process.

[0216] See Figure 28E, a metal fill material is deposited in a plurality of backside grooves 43, on sidewalls of at least one backside trench 79, and above a top surface of a contact-level dielectric layer 80 to form a metal fill material layer 46B. The metal fill material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal fill material layer 46B may consist essentially of at least one elemental metal. The at least one elemental metal of the metal fill material layer 46B may be selected from, for example, tungsten, cobalt, ruthenium, molybdenum, or tantalum. In one embodiment, the metal fill material layer 46B may consist essentially of a single elemental metal such as tungsten. The metal fill material layer 46B may be spaced apart from the insulating layer 32 and the memory stack structure 55 by an optional metal barrier layer 46A, which is a metal barrier layer that blocks the diffusion of fluorine atoms therethrough.

[0217] A plurality of conductive layers 46 may be formed in the plurality of backside grooves 43, and a continuous metal material layer may be formed on sidewalls of each backside trench 79 and above the contact-level dielectric layer 80. Each conductive layer 46 includes a portion of the optional metal barrier layer 46A and a portion of the metal fill material layer 46B, which are located between a pair of vertically adjacent dielectric material layers (such as a pair of insulating layers 32). The continuous metal material layer includes a continuous portion of the metal barrier layer 46A and a continuous portion of the metal fill material layer 46B, which are located in the backside trench 79 or above the contact-level dielectric layer 80.

[0218] By performing an isotropic etching process that etches at least one conductive material of the continuous conductive material layer, the deposited metal material of the continuous conductive material layer is etched back from sidewalls of each backside trench 79 and from above the contact-level dielectric layer 80. Each remaining portion of the deposited metal material in the backside grooves 43 constitutes a conductive layer 46. Each conductive layer 46 may be a word line or a select gate electrode. Thus, the sacrificial material layer 42 is replaced with the conductive layer 46.

[0219] An alternating stack (32, 46) of the insulating layer 32 and the conductive layer 46 may be formed. In one embodiment, a first conductive layer 461 and a second conductive layer 462 in the conductive layer 46 may be deposited on corresponding optional pit-fill annular dielectric spacers 432, corresponding silicon oxycarbide liners 332, and corresponding cylindrical surface segments on outer sidewalls of a dielectric metal oxide barrier dielectric layer 52. In one embodiment, the first conductive layer 461 and the second conductive layer 462 may be in contact with the corresponding silicon oxycarbide liners 332 and in contact with a corresponding insulating layer in the insulating layer 32 (such as in the case of the first conductive layer 461) or a dielectric material layer composed of a silicon oxide material (such as an interlayer dielectric layer 170) (such as in the case of the second conductive layer 462). Note that Figure 28EEither the first conductive layer 461 or the second conductive layer 462 shown can be referred to as the first conductive layer or the second conductive layer because, as described above, elements of the same type can be identified in any order.

[0220] In one embodiment, the memory film 50 includes, from the outside to the inside, a vertical stack of silicon oxide spacers (51', 151, 251), a dielectric metal oxide barrier dielectric layer 52, a silicon oxide barrier dielectric layer 53, a continuous memory material layer 54, and a tunneling dielectric layer 56. In one embodiment, each conductive layer 46 is in direct contact with a corresponding surface section of the outer sidewall of the dielectric metal oxide barrier dielectric layer 52.

[0221] In one embodiment, the vertical stack of tubular silicon oxide spacers 51' can be vertically spaced from each other and can laterally surround and contact the dielectric metal oxide barrier dielectric layer 52. The optional pit-fill annular dielectric spacer 432 can contact the concave conical surface of the corresponding spacer in the tubular silicon oxide spacers 51' and can contact the corresponding cylindrical surface section of the outer sidewall of the dielectric metal oxide barrier dielectric layer 52.

[0222] The annular silicon oxide spacer 151 can optionally be located within each memory opening fill structure 58. The annular silicon oxide spacer 151 can have an inner sidewall contacting the cylindrical surface section of the outer sidewall of the dielectric metal oxide barrier dielectric layer 52 and can have a concave conical outer sidewall section contacting the first convex conical annular surface section of the first conductive layer 461. In one embodiment, one of the pit-fill annular dielectric spacers 432 contacts the second convex conical annular surface section of the first conductive layer 461.

[0223] In one embodiment, the annular silicon oxide spacer 151 has a planar annular bottom surface that contacts an annular section of the top surface of a horizontally extending portion of the dielectric metal oxide barrier dielectric layer 52.

[0224] In Figure 28E In one embodiment illustrated in the inset of, one of the tubular silicon oxide spacers 51' includes a concave conical outer sidewall section CTOS that contacts the first convex conical annular surface section of the conductive layer (such that the first or second conductive layer (461, 462)). One of the pit-fill annular dielectric spacers 432 contacts the second convex conical annular surface section of the conductive layer.

[0225] In one embodiment, the sidewall surface and the peripheral portion of the horizontal planar surface of the silicon oxycarbide liner 332 can contact one of the pit-fill annular dielectric spacers 432.

[0226] In one embodiment, the first conductive layer 461 and / or the second conductive layer 462 includes a respective main horizontally extending planar surface contacting a respective silicon oxycarbide liner 332. In one embodiment, the first conductive layer 461 and / or the second conductive layer 462 includes a respective first convex conical annular surface section having a first radius of curvature RC1, and a respective second convex conical annular surface section having a second radius of curvature RC2 that is less than the first radius of curvature RC1. In one embodiment, the edge of the respective second convex conical annular surface section abuts the edge of the respective horizontally extending planar surface. The first radius of curvature RC1 may be equal to or greater than the lateral thickness of the tubular silicon oxide liner 51' (i.e., the lateral distance between the inner wall and the outer wall). The second radius of curvature RC2 may be equal to or greater than half of the lateral thickness of the tubular silicon oxide liner 51', and less than the first radius of curvature RC1.

[0227] Accordingly, the first and second conductive layers (461, 462) are formed with respective rounded corners facing the layer-to-layer bonding region (i.e., the interlayer dielectric layer 170) that have a larger radius of curvature than the opposite rounded corners facing away from the bonding region and toward the respective silicon oxycarbide liners 332. The increased word line corner rounding at the bonding region improves reverse tunneling and thus improves device erase efficiency. In contrast, the reduced word line corner rounding for the remaining word line corners reduces short channel effect degradation and improves word line controllability.

[0228] The third exemplary structure may be formed in a second configuration, instead of Figures 28A to 28E the first configuration shown. Figures 29A to 29E is a sequential vertical cross-section of a region surrounding the memory opening fill structure 58 of an alternative configuration (i.e., the second configuration) of the third exemplary structure during the formation of the conductive layer 46 according to a third embodiment of the present disclosure.

[0229] See Figure 27 and Figure 29A which show the second configuration of the third exemplary structure after forming the backside grooves 43 by selectively removing the sacrificial material layers (142, 242) relative to the silicon oxycarbide liners 332, the insulating layers (132, 232) (which comprise silicon oxide material), the interlayer dielectric layer 170 comprising silicon oxide material, and the contact level dielectric layer 80.

[0230] In the second configuration, the memory opening fill structure 58 has the Figure 25C configuration shown. Specifically, an etchant that selectively etches the sacrificial material layers (142, 242) relative to the insulating layers (132, 232) and the silicon oxycarbide liners 332 may be introduced into the backside trenches 79 during an isotropic etching process, as described above with respect to Figure 28AAs described. The dorsal groove 43 is formed in the volume from which the sacrificial material layer (142, 242) is removed. The removal of the sacrificial material layer (142, 242) can be selective with respect to the material of the insulating layer (132, 232), the material of the silicon oxycarbide liner 332, the material of the inverse-stepped dielectric material portions (165, 265), the material of the interlayer dielectric layer 170, the semiconductor material of the semiconductor material layer 10, and the outermost layer of the memory film 50 (such as the silicon oxide barrier dielectric layer 53).

[0231] See Figure 29B , and an isotropic etching process for etching the material of the silicon oxide barrier dielectric layer 53 is performed. The etching chemistry of the isotropic etching process is selected such that the isotropic etching process etches the material of the silicon oxide barrier dielectric layer 53 (i.e., the silicon oxide material) at a higher etching rate than the material of the silicon oxycarbide liner 332. In other words, the isotropic etching process etches the material of the silicon oxide liner at a higher etching rate than the material of the first silicon oxycarbide liner 332 and the second silicon oxycarbide liner 332. In Figure 29B the processing step employed may be the same as the isotropic etching process employed in Figure 28B the processing step.

[0232] The isotropic etching process selectively isotropically etches portions of the silicon oxide barrier dielectric layer 53 with respect to the silicon oxycarbide liner 332. A vertical stack of vertically spaced annular lateral depressions 53A is formed on the outer sidewalls of the silicon oxide barrier dielectric layer 53 at each level of the dorsal groove 43. The lateral etching distance of the isotropic etching process on the outer sidewalls of the silicon oxide barrier dielectric layer 53 can be in the range of 20% to 90% of the thickness of the silicon oxide barrier dielectric layer 53 formed in Figure 25C the processing step, such as 30% to 80%. A vertical stack of annular pits 43D can be formed between each silicon oxycarbide liner 332 and the silicon oxide barrier dielectric layer 53.

[0233] See Figure 29C , and the above can be performed with respect to Figure 28CThe described optional step is to deposit a conformal dielectric liner in the annular recess 43D surrounding the memory opening and filling structure 58, on the physically exposed surface of the carbon oxynitride spacer 332, and on the physically exposed surfaces of the insulating layer 32, the interlayer dielectric layer 170, and the contact level dielectric layer 80. The conformal dielectric liner can comprise any insulating material, such as silicon oxide. The thickness of the conformal dielectric liner can be greater than half of the lateral etch distance of the isotropic etch process such that the conformal dielectric liner fills the annular recess 43D. The thickness of the conformal dielectric liner can be less than the lateral etch distance of the isotropic etch process. For example, the thickness of the conformal dielectric liner can be in the range of 2 nm to 4 nm. In one embodiment, the conformal dielectric liner comprises undoped silicate glass (e.g., silicon dioxide) or doped silicate glass.

[0234] An isotropic recess etch process can be performed to etch back a portion of the conformal dielectric liner from outside the volume of the annular recess 43D. The horizontally extending surface of the carbon oxynitride liner 332 can be physically exposed around each backside groove 43. The duration of the isotropic etch process can be selected to minimize the collateral etch of the carbon oxynitride liner 332 that serves as an etch stop layer. Each remaining portion of the conformal dielectric liner filling the corresponding annular recess 43D has an annular shape and is referred to herein as a recess-fill annular dielectric spacer 432.

[0235] In one embodiment, each memory opening filling structure 58 includes a recess-fill annular dielectric spacer 432. Each annular lateral recess 53A in the outer sidewall of the silicon oxide barrier dielectric layer 53 can contact at least one recess-fill annular dielectric spacer 432. Accordingly, a plurality of annular lateral recesses 53A in the outer sidewall of the silicon oxide barrier dielectric layer 53 can contact a pair of corresponding recess-fill annular dielectric spacers 432.

[0236] Thus, generally speaking, an annular recess 43D can be formed between each carbon oxynitride liner 332 and a corresponding annular lateral recess 53A in the outer sidewall of the silicon oxide barrier dielectric layer 53. Each annular recess 43D can optionally be filled with a recess-fill annular dielectric spacer 432.

[0237] See Figure 29D , a backside barrier dielectric layer 44 can be conformally deposited in the backside grooves 43. The backside barrier dielectric layer 44 can have the same material composition and the same thickness range as the dielectric metal oxide barrier dielectric layer 52 in the first exemplary structure and the second exemplary structure, and can be formed by a conformal deposition process. The backside dielectric metal oxide barrier layer 44 can be directly deposited on the recess-fill annular dielectric spacer 432 (if present), directly deposited on the horizontal surface of the carbon oxynitride liner 332, and directly deposited on the cylindrical surface section of the annular lateral recess of the silicon oxide barrier dielectric layer 53.

[0238] See Figure 29E , and the processing steps described therein can be executed to conformally form the conductive layer 46. Each conductive layer 46 may include a corresponding metal barrier layer 46A and a metal fill material portion 46B. Figure 28D and Figure 28E An alternating stack (32, 46) of the insulating layer 32 and the conductive layer 46 can be formed. The first conductive layer 461 and the second conductive layer 462 can be in contact with the corresponding carbon oxynitride gasket 332 and in contact with the corresponding insulating layer 32 or a dielectric material layer (such as the interlayer dielectric layer 170) composed of silicon oxide material.

[0239] Each conductive layer in the conductive layer 46 is vertically spaced apart from the corresponding overlying insulating layer 32 and the corresponding underlying insulating layer 32 by a corresponding backside dielectric metal oxide barrier dielectric layer 44. The first backside dielectric metal oxide barrier dielectric layer 44 includes a first horizontal surface in direct contact with the carbon oxynitride gasket 332 and a second horizontal surface in direct contact with one of the insulating layers 32 (such as in the case of the first conductive layer 461) or a dielectric material layer (such as the interlayer dielectric layer 170) composed of silicon oxide material (such as in the case of the second conductive layer 462).

[0240] In one embodiment, the first backside dielectric metal oxide barrier dielectric layer 44 is embedded in the first conductive layer 461 or the second conductive layer 462. The second horizontal surface is vertically spaced apart from the first horizontal surface by the sum of the vertical thickness of the first conductive layer 461 or the second conductive layer 462 and twice the thickness of the first backside dielectric metal oxide barrier dielectric layer 44.

[0241] In one embodiment, the silicon oxide barrier dielectric layer 53 is in contact with each dielectric layer in the backside dielectric metal oxide barrier dielectric layer 44. In one embodiment, the silicon oxide barrier dielectric layer 53 includes an outer sidewall having a vertical stack of annular lateral depressions vertically spaced apart; and each annular lateral depression includes a cylindrical surface section and a pair of annular concave surface sections adjacent to the corresponding edges of the cylindrical surface section.

[0242] In one embodiment, the pit-filled annular dielectric spacer 432 can be in contact with the corresponding annular concave surface section of the annular lateral depression of the silicon oxide barrier dielectric layer 53. The first backside dielectric metal oxide barrier dielectric layer 44 may include a first convex conical annular surface section having a first radius of curvature RC1 and in contact with the annular concave surface section of the silicon oxide barrier dielectric layer 53, and a second convex conical annular surface section having a second radius of curvature RC2 smaller than the first radius of curvature RC1 and in contact with one of the pit-filled annular dielectric spacers 432.

[0243] In one embodiment, the pit-filled annular dielectric spacer 432 can be in contact with the corresponding annular concave surface section of the annular lateral depression of the silicon oxide barrier dielectric layer 53. The first backside dielectric metal oxide barrier dielectric layer 44 may include a first convex conical annular surface section having a first radius of curvature RC1 and in contact with the annular concave surface section of the silicon oxide barrier dielectric layer 53, and a second convex conical annular surface section having a second radius of curvature RC2 smaller than the first radius of curvature RC1 and in contact with one of the pit-filled annular dielectric spacers 432.

[0244] In one embodiment, the second horizontal surface of the first dorsal dielectric metal oxide barrier dielectric layer 44 is in direct contact with the horizontal planar surface of the silicon oxide barrier dielectric layer 53.

[0245] In one embodiment, each memory opening 49 extends vertically through an alternating stack (32, 46) of insulating layers and conductive layers 46. A memory opening fill structure 58 may be formed in each of the memory openings 49. Each memory opening fill structure 58 includes a vertical semiconductor channel 60 and a memory film 50, the memory film including a continuous memory material layer 54 that extends continuously through the entire alternating stack (32, 46).

[0246] See Figure 30 , which shows a third exemplary structure after the formation of the conductive layer 46 (i.e., after the processing steps described in reference Figures 28A to 28E or after the processing steps described in reference Figures 29A to 29E ). The conductive layer 46 that replaces the first layer of sacrificial material layer 142 is referred to herein as the first layer conductive layer 146, and the conductive layer 46 that replaces the second layer of sacrificial material layer 242 is referred to herein as the second layer conductive layer 246.

[0247] See Figure 31A and Figure 31B , and the processing steps described in reference Figure 12A and Figure 12B may be performed to form a dorsal trench fill structure within each dorsal trench 79. For example, each dorsal trench fill structure may include a combination of an insulating spacer 74 and a dorsal contact via structure 76.

[0248] See Figure 32A and Figure 32B , and the processing steps described in reference Figure 13A and 13B may be performed to form various additional contact via structures, such as a drain contact via structure 88, a layer contact via structure 86, and a through-memory-level connection via structure 386.

[0249] See in connection with Figure 28EAll the figures related to the first configuration of the third exemplary structure shown provide a memory device that includes: an alternating stack (32, 46) of an insulating layer 32 and a conductive layer 46, wherein a first conductive layer (461 or 462) in the conductive layer 46 has a first major horizontal surface in contact with a carbon oxide silicon liner 332 and an opposite second major surface in contact with one of the insulating layers in the insulating layer 32 or a dielectric material layer composed of a silicon oxide material (such as an interlayer dielectric layer 170); a memory opening 49 that vertically extends through the alternating stack (32, 46); and a memory opening fill structure 58 that is located in the memory opening 49 and includes a vertical semiconductor channel 60 and a memory film 50.

[0250] In one embodiment, the memory film 50 includes, from the outside to the inside, a dielectric metal oxide barrier dielectric layer 52, a silicon oxide barrier dielectric layer 53, a continuous memory material layer 54, and a tunneling dielectric layer 56. In one embodiment, each conductive layer 46 is in direct contact with a corresponding surface section of the outer sidewall of the dielectric metal oxide barrier dielectric layer 52.

[0251] In one embodiment, the memory device includes: a vertical stack of tubular silicon oxide spacers 51' that are vertically spaced apart from each other and laterally surround and contact the dielectric metal oxide barrier dielectric layer 52; and a pit-fill annular dielectric spacer 432 that contacts the concave conical surface of a corresponding spacer in the tubular silicon oxide spacers 51' and contacts a corresponding cylindrical surface section of the outer sidewall of the dielectric metal oxide barrier dielectric layer 52.

[0252] In one embodiment, the memory device further includes an annular silicon oxide spacer 151 that has an inner sidewall in contact with a cylindrical surface section of the outer sidewall of the dielectric metal oxide barrier dielectric layer 52 and a concave conical outer sidewall section CTOS in contact with a first convex conical annular surface section of the first conductive layer (461 or 462), wherein one of the spacers in the pit-fill annular dielectric spacer 432 contacts a second convex conical annular surface section of the first conductive layer (461 or 462). In one embodiment, the annular silicon oxide spacer 151 has a planar annular bottom surface that contacts an annular section of the top surface of a horizontally extending portion of the dielectric metal oxide barrier dielectric layer 52.

[0253] In one embodiment, one of the tubular silicon oxide spacers 51' includes a concave conical outer sidewall section CTOS that contacts a first convex conical annular surface section of the first conductive layer 462; and one of the spacers in the pit-fill annular dielectric spacer 432 contacts a second convex conical annular surface section of the first conductive layer 462.

[0254] In one embodiment, the sidewall surface of the silicon oxycarbide liner 332 and the peripheral portion of the horizontal planar surface are in contact with one of the spacer members in the recess-fill annular dielectric spacer 432.

[0255] In one embodiment, the first conductive layer (461 or 462) includes a horizontally extending planar surface that contacts the silicon oxycarbide liner 332; the first conductive layer (461 or 462) includes a first convex conical annular surface section having a first radius of curvature RC1 and a second convex conical annular surface section having a second radius of curvature RC2 that is less than the first radius of curvature RC1; and the edge of the second convex conical annular surface section abuts the edge of the horizontally extending planar surface.

[0256] In one embodiment, the alternating stack includes a first layer, a second layer, and a dielectric material layer 170 composed of a silicon oxide material located between the first layer and the second layer. The first layer includes alternating first conductive layers 146 and first insulating layers 132, a lower silicon oxycarbide liner 332 located between the lower major horizontal surface of the first conductive layer 146 and the upper major horizontal surface of the underlying first insulating layer 132, and an upper silicon oxycarbide liner 332 located between the upper major horizontal surface of a subset of the first conductive layers 146 and the lower major horizontal surface of the overlying first insulating layer 132. The upper silicon oxycarbide liner 332 is not located on the upper major horizontal surface of the topmost conductive layer of the first conductive layer 146. The second layer includes alternating second conductive layers 246 and second insulating layers 232, an upper silicon oxycarbide liner 332 located between the upper major horizontal surface of the second conductive layer 246 and the lower major horizontal surface of the overlying second insulating layer 232, and a lower silicon oxycarbide liner 332 located between the lower major horizontal surface of a subset of the second conductive layers 246 and the upper major horizontal surface of the underlying second insulating layer 232. The lower silicon oxycarbide liner 232 is not located on the lower major horizontal surface of the bottommost conductive layer in the second conductive layer 246.

[0257] See related to Figure 29EAll of the drawings associated with the second configuration of the third exemplary structure shown provide a memory device that includes: an alternating stack (32, 46) of an insulating layer 32 and a conductive layer 46, wherein each conductive layer in the conductive layer 46 is vertically spaced apart from a corresponding overlying insulating layer 32 and a corresponding underlying insulating layer 32 by a respective backside dielectric metal oxide barrier dielectric layer 44, wherein a first backside dielectric metal oxide barrier dielectric layer 44 in the backside dielectric metal oxide barrier dielectric layer 44 includes a first horizontal surface in direct contact with a carbon silicon oxide liner 332 and a second horizontal surface in direct contact with one of the insulating layers 32 or a dielectric material layer (such as an interlayer dielectric layer 170) composed of a silicon oxide material; a memory opening 49 that vertically extends through the alternating stack (32, 46); and a memory opening fill structure 58 that is located in the memory opening 49 and includes a vertical semiconductor channel 60 and a memory film 50.

[0258] In one embodiment, the first backside dielectric metal oxide barrier dielectric layer 44 is embedded in a first conductive layer (461 or 462) in the conductive layer 46; and the second horizontal surface is vertically spaced apart from the first horizontal surface by a sum of a vertical thickness of the first conductive layer (461 or 462) and twice a thickness of the first backside dielectric metal oxide barrier dielectric layer 44.

[0259] In one embodiment, the memory film 50 includes, from outside to inside, a silicon oxide barrier dielectric layer 53, a continuous memory material layer 54, and a tunneling dielectric layer 56; and the silicon oxide barrier dielectric layer 53 contacts each dielectric layer in the backside dielectric metal oxide barrier dielectric layer 44.

[0260] In one embodiment, the silicon oxide barrier dielectric layer 53 includes an outer sidewall having a vertical stack of annular lateral depressions that are vertically spaced apart; and each annular lateral depression includes a cylindrical surface section and a pair of annular concave surface sections adjacent to respective edges of the cylindrical surface section.

[0261] In one embodiment, the memory device includes a pit-fill annular dielectric spacer 432 that contacts a respective annular concave surface section of the annular lateral depression of the silicon oxide barrier dielectric layer 53, wherein: the first backside dielectric metal oxide barrier dielectric layer 44 includes a first convex conical annular surface section having a first radius of curvature RC1 and contacting the annular concave surface section of the silicon oxide barrier dielectric layer 53, and a second convex conical annular surface section having a second radius of curvature RC2 less than the first radius of curvature RC1 and contacting one of the spacers in the pit-fill annular dielectric spacer 432.

[0262] In one embodiment, a second horizontal surface of the first dorsal dielectric metal oxide barrier dielectric layer 44 is in direct contact with a horizontal planar surface of the silicon oxide barrier dielectric layer 53.

[0263] In one embodiment, an alternating stack includes a first layer, a second layer, and a dielectric material layer 170 composed of silicon oxide material disposed between the first layer and the second layer. The first layer includes alternating first conductive layers 146 and first insulating layers 132, a lower carbon silicon oxide liner 332 disposed between a lower major horizontal surface of the first conductive layer 146 and an upper major horizontal surface of the underlying first insulating layer 132, and an upper carbon silicon oxide liner 332 disposed between an upper major horizontal surface of a subset of the first conductive layers 146 and a lower major horizontal surface of the overlying first insulating layer 132. The upper carbon silicon oxide liner 332 is not disposed on the upper major horizontal surface of the topmost conductive layer of the first conductive layer 146. The second layer includes alternating second conductive layers 246 and second insulating layers 232, an upper carbon silicon oxide liner 332 disposed between an upper major horizontal surface of the second conductive layer 246 and a lower major horizontal surface of the overlying second insulating layer 232, and a lower carbon silicon oxide liner 332 disposed between a lower major horizontal surface of a subset of the second conductive layers 246 and an upper major horizontal surface of the underlying second insulating layer 232. The lower carbon silicon oxide liner 232 is not disposed on the lower major horizontal surface of the bottommost conductive layer in the second conductive layer 246.

[0264] Various embodiments related to a third exemplary structure may provide a conductive layer 46 located at an interlayer junction having an asymmetric vertical profile. Specifically, one corner of the conductive layer 46 proximate to the memory opening fill structure 58 may have a first radius of curvature, and another corner of the conductive layer 46 proximate to the memory opening fill structure 58 may have a second radius of curvature different from the first radius of curvature. The different radii of curvature of the conductive layer 46 can be advantageously used to locally modify the electric field intensity to enhance the electrical characteristics of the device. For example, a portion of the conductive layer 46 formed adjacent to the interlayer dielectric layer 170 can be formed with a larger radius of curvature to enhance the erase characteristics of the device.

[0265] Although the foregoing relates to specific preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will recognize that various modifications can be made to the disclosed embodiments, and such modifications are intended to be within the scope of the present disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. Unless expressly stated otherwise, the word "comprising" or "including" encompasses all embodiments in which the words "consisting essentially of" or "consisting of" replace the words "comprising" or "including". Where embodiments employing a specific structure and / or configuration are shown in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise known to be impossible for those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A memory device, the memory device comprising: An alternating stack of insulating layers and conductive layers, wherein a first conductive layer in the conductive layers is in contact with an underlying silicon oxycarbide liner and an overlying silicon oxycarbide liner; A memory opening that extends vertically through the alternating stack; And A memory opening fill structure that is located in the memory opening and includes a vertical semiconductor channel and a memory film, the memory film including a continuous memory material layer that extends continuously through the entire alternating stack.

2. The memory device according to claim 1, wherein the memory film includes, from outside to inside, a dielectric metal oxide blocking dielectric layer, a silicon oxide blocking dielectric layer, the continuous memory material layer, and a tunneling dielectric layer.

3. The memory device according to claim 1, wherein the first conductive layer includes: An upper annular protruding portion that protrudes above a first horizontal plane including an interface between the first conductive layer and the overlying silicon oxycarbide liner; And A lower annular protruding portion that protrudes below a second horizontal plane including an interface between the first conductive layer and the underlying silicon oxycarbide liner.

4. The memory device according to claim 3, wherein: The upper annular protruding portion contacts a sidewall of an opening in the overlying silicon oxycarbide liner; The lower annular protruding portion contacts a sidewall of an opening in the underlying silicon oxycarbide liner; And The memory opening fill structure extends vertically through the opening in the overlying silicon oxycarbide liner and through the opening in the underlying silicon oxycarbide liner.

5. The memory device according to claim 3, wherein: The upper annular protruding portion includes a first inner annular convex surface and a first outer cylindrical surface; and The lower annular protruding portion includes a second inner annular convex surface and a second outer cylindrical surface.

6. The memory device according to claim 1, wherein the memory film further includes a vertical stack of tubular silicon oxide spacers that contact corresponding insulating layers in the insulating layer.

7. The memory device according to claim 6, wherein one of the tubular silicon oxide spacers includes an upper concave annular surface that contacts the first conductive layer and further includes a lower concave annular surface that contacts a second conductive layer in the conductive layers.

8. The memory device according to claim 6, wherein: The memory opening fill structure further includes a pit-fill annular dielectric spacer; and Each tubular silicon oxide spacer contacts a corresponding overlying spacer in the pit-fill annular dielectric spacer and contacts a corresponding underlying spacer in the pit-fill annular dielectric spacer.

9. The memory device according to claim 1, wherein: The overlying silicon oxycarbide liner contacts a bottom surface of an overlying insulating layer in the insulating layer; The underlying silicon oxycarbide liner contacts a top surface of an underlying insulating layer in the insulating layer; And The insulating layer does not have seams or air gaps embedded therein.

10. The memory device according to claim 1, wherein each of the conductive layers in the conductive layer has a corresponding uniform vertical thickness as a whole.

11. A method of forming a memory device, the method comprising: forming a vertical repetition of a plurality of instances of a repeating unit on a substrate, wherein the repeating unit includes an insulating layer, a first silicon carbon oxide liner, a sacrificial material layer, and a second silicon carbon oxide liner from bottom to top; forming a memory opening through the vertical repetition; forming a memory opening filling structure in the memory opening, wherein the memory opening filling structure includes a memory film, the memory film includes a dielectric metal oxide barrier dielectric layer, a silicon oxide barrier dielectric layer, a continuous memory material layer, and a tunneling dielectric layer from outside to inside, and the memory opening filling structure further includes a vertical semiconductor channel formed on the memory film; forming a backside groove by selectively removing the sacrificial material layer with respect to the first silicon carbon oxide liner and the second silicon carbon oxide liner; and forming a conductive layer in the backside groove.

12. The method according to claim 11, the method further comprising: forming a silicon oxide liner that laterally surrounds the dielectric metal oxide barrier dielectric layer in the memory film; and removing a portion of the silicon oxide liner from around the backside groove by performing an isotropic etching process, wherein the remaining portion of the silicon oxide liner includes a vertical stack of tubular silicon oxide spacers.

13. The method according to claim 12, wherein the isotropic etching process etches the material of the silicon oxide liner at a higher etching rate than the materials of the first silicon carbon oxide liner and the second silicon carbon oxide liner.

14. The method according to claim 12, wherein: an outer cylindrical surface section of the dielectric metal oxide barrier dielectric layer is exposed after the isotropic etching process; and the conductive layer is directly formed on the outer cylindrical surface section of the dielectric metal oxide barrier dielectric layer.

15. The method according to claim 12, wherein: the first silicon carbon oxide liner and the second silicon carbon oxide liner include corresponding openings therethrough when forming the memory opening; by the isotropic etching process, an annular pit is formed between the dielectric metal oxide barrier dielectric layer and the openings through the first silicon carbon oxide liner and the second silicon carbon oxide liner; and the method further comprises forming a pit filling annular dielectric spacer in the annular pit before the step of forming the conductive layer.

16. The method according to claim 12, wherein: the tubular silicon oxide spacers include corresponding upper concave annular surfaces and corresponding lower concave annular surfaces; and the conductive layer is formed on the upper concave annular surfaces and the lower concave annular surfaces of the tubular silicon oxide spacers.

17. The method according to claim 11, the method further comprising: The surface portion of the sacrificial material layer is oxidized into a tubular silicon oxide portion, wherein during the step of forming the backside groove, the sacrificial material layer is selectively removed with respect to the first carbon silicon oxide liner and the second carbon silicon oxide liner and with respect to the tubular silicon oxide portion; and after the step of forming the backside groove and before the step of forming the conductive layer in the backside groove, the tubular silicon oxide portion is selectively removed with respect to the dielectric metal oxide blocking dielectric layer.

18. The method according to claim 17, wherein: the sacrificial material layer comprises a silicon nitride layer; and the tubular silicon oxide portion has a compositional variation, wherein the atomic concentration of nitrogen atoms increases with the lateral distance from the memory opening.

19. The method according to claim 17, wherein the conductive layer is directly formed on the horizontally extending surfaces of the first carbon silicon oxide liner and the second carbon silicon oxide liner, and is directly formed on the cylindrical outer surface section of the dielectric metal oxide blocking dielectric layer.

20. The method according to claim 11, wherein the insulating layer does not embed seams or air gaps therein.

21. A memory device, the memory device comprising: an alternating stack of an insulating layer and a conductive layer, wherein a first conductive layer in the conductive layer has a first main horizontal surface in contact with a carbon silicon oxide liner and an opposite second main surface in contact with one of the insulating layers in the insulating layer or with a dielectric material layer composed of a silicon oxide material; a memory opening that vertically extends through the alternating stack; and a memory opening filling structure that is located in the memory opening and includes a vertical semiconductor channel and a memory film.

22. The memory device according to claim 21, wherein the memory film includes, from outside to inside, a dielectric metal oxide blocking dielectric layer, a silicon oxide blocking dielectric layer, a continuous memory material layer, and a tunneling dielectric layer.

23. The memory device according to claim 22, wherein each conductive layer in the conductive layer is directly in contact with a corresponding surface section of the outer sidewall of the dielectric metal oxide blocking dielectric layer.

24. The memory device according to claim 22, the memory device further comprising: a vertical stack of tubular silicon oxide spacers that are vertically spaced apart from each other and laterally surround and contact the dielectric metal oxide blocking dielectric layer; and a pit-filling annular dielectric spacer that contacts the concave conical surface of a corresponding spacer in the tubular silicon oxide spacers and contacts a corresponding cylindrical surface section of the outer sidewall of the dielectric metal oxide blocking dielectric layer.

25. The memory device according to claim 24, the memory device further comprising an annular silicon oxide spacer having an inner sidewall that contacts a cylindrical surface section of the outer sidewall of the dielectric metal oxide blocking dielectric layer and having a concave conical outer sidewall section that contacts a first convex conical annular surface section of the first conductive layer, wherein: One of the recess-fill annular dielectric spacers contacts a second convex conical annular surface section of the first conductive layer; and The annular silicon oxide spacer has a planar annular bottom surface that contacts an annular section of the top surface of a horizontally extending portion of the dielectric metal oxide barrier dielectric layer.

26. The memory device according to claim 24, wherein: One of the tubular silicon oxide spacers includes a concave conical outer sidewall section that contacts a first convex conical annular surface section of the first conductive layer; and One of the recess-fill annular dielectric spacers contacts a second convex conical annular surface section of the first conductive layer.

27. The memory device according to claim 24, wherein a peripheral portion of a sidewall surface and a horizontal planar surface of the silicon carbon oxide liner contacts one of the recess-fill annular dielectric spacers.

28. The memory device according to claim 21, wherein: The first conductive layer includes a horizontally extending planar surface that contacts the silicon carbon oxide liner; The first conductive layer includes a first convex conical annular surface section having a first radius of curvature and a second convex conical annular surface section having a second radius of curvature that is less than the first radius of curvature; and An edge of the second convex conical annular surface section abuts an edge of the horizontally extending planar surface.

29. The memory device according to claim 21, wherein: The alternating stack includes a first layer, a second layer, and a dielectric material layer composed of the silicon oxide material is located between the first layer and the second layer; The first layer includes alternating first conductive layers and first insulating layers, a lower silicon carbon oxide liner located between a lower major horizontal surface of the first conductive layer and an upper major horizontal surface of an underlying first insulating layer, and an upper silicon carbon oxide liner located between upper major horizontal surfaces of a subset of the first conductive layers and a lower major horizontal surface of an overlying first insulating layer, wherein the upper silicon carbon oxide liner is not located on the upper major horizontal surface of the topmost conductive layer in the first conductive layer; and The second layer includes alternating second conductive layers and second insulating layers, an upper silicon carbon oxide liner located between an upper major horizontal surface of the second conductive layer and a lower major horizontal surface of an overlying second insulating layer, and a lower silicon carbon oxide liner located between lower major horizontal surfaces of a subset of the second conductive layers and an upper major horizontal surface of an underlying second insulating layer, wherein the lower silicon carbon oxide liner is not located on the lower major horizontal surface of the bottommost conductive layer in the second conductive layer.

30. A memory device, the memory device comprising: An alternating stack of an insulating layer and a conductive layer, wherein each conductive layer in the conductive layer is vertically spaced apart from a corresponding overlying insulating layer and a corresponding underlying insulating layer by a corresponding backside dielectric metal oxide barrier dielectric layer, and wherein a first backside dielectric metal oxide barrier dielectric layer in the backside dielectric metal oxide barrier dielectric layer includes a first horizontal surface in direct contact with a silicon oxycarbide liner and a second horizontal surface in direct contact with one of the insulating layers or a dielectric material layer composed of a silicon oxide material; A memory opening that extends vertically through the alternating stack; and A memory opening filling structure that is located in the memory opening and includes a vertical semiconductor channel and a memory film.

31. The memory device according to claim 30, wherein: The first backside dielectric metal oxide barrier dielectric layer is embedded in a first conductive layer in the conductive layer; and The second horizontal surface is vertically spaced apart from the first horizontal surface by the sum of the vertical thickness of the first conductive layer and twice the thickness of the first backside dielectric metal oxide barrier dielectric layer.

32. The memory device according to claim 30, wherein: The memory film includes, from the outside to the inside, a silicon oxide barrier dielectric layer, a continuous memory material layer, and a tunneling dielectric layer; and The silicon oxide barrier dielectric layer is in contact with each dielectric layer in the backside dielectric metal oxide barrier dielectric layer.

33. The memory device according to claim 32, wherein: The second horizontal surface of the first backside dielectric metal oxide barrier dielectric layer is in direct contact with a horizontal planar surface of the silicon oxide barrier dielectric layer; The silicon oxide barrier dielectric layer includes outer sidewalls having a vertical stack of annular lateral depressions spaced vertically apart; and and Each annular lateral depression in the annular lateral depressions includes a cylindrical surface section and a pair of annular concave surface sections adjacent to corresponding edges of the cylindrical surface section.

34. The memory device according to claim 33, the memory device further includes a pit-filled annular dielectric spacer that contacts a corresponding annular concave surface section of the annular lateral depression of the silicon oxide barrier dielectric layer, wherein: The first backside dielectric metal oxide barrier dielectric layer includes a first convex conical annular surface section having a first radius of curvature and contacting the annular concave surface section of the silicon oxide barrier dielectric layer, and a second convex conical annular surface section having a second radius of curvature less than the first radius of curvature and contacting one of the pit-filled annular dielectric spacers.

35. The memory device according to claim 32, wherein: The alternating stack includes a first layer, a second layer, and the dielectric material layer composed of the silicon oxide material is located between the first layer and the second layer; The first layer includes alternating first conductive layers and first insulating layers, lower silicon carbon oxide pads located between the lower major horizontal surfaces of the first conductive layers and the upper major horizontal surfaces of underlying first insulating layers, and upper silicon carbon oxide pads located between the upper major horizontal surfaces of subsets of the first conductive layers and the lower major horizontal surfaces of overlying first insulating layers, where the upper silicon carbon oxide pads are not located on the upper major horizontal surfaces of the topmost conductive layers among the first conductive layers; and The second layer includes alternating second conductive layers and second insulating layers, upper silicon carbon oxide pads located between the upper major horizontal surfaces of the second conductive layers and the lower major horizontal surfaces of overlying second insulating layers, and lower silicon carbon oxide pads located between the lower major horizontal surfaces of subsets of the second conductive layers and the upper major horizontal surfaces of underlying second insulating layers, where the lower silicon carbon oxide pads are not located on the lower major horizontal surfaces of the bottommost conductive layers among the second conductive layers.

36. A method of forming a memory device, the method comprising: Forming an alternating stack of insulating layers and sacrificial material layers, where silicon carbon oxide pads are interposed between a first sacrificial material layer among the sacrificial material layers and a first insulating layer among the insulating layers, and the first sacrificial material layer is in direct contact with a second insulating layer among the insulating layers or in direct contact with a dielectric material layer composed of silicon oxide material; Forming memory openings through the alternating stack; Forming a memory opening fill structure in the memory openings, where the memory opening fill structure includes a memory film that includes, from outside to inside, a silicon oxide blocking dielectric layer, a continuous memory material layer, and a tunneling dielectric layer, and the memory opening fill structure further includes a vertical semiconductor channel formed on the memory film; Forming a backside recess by selectively removing the sacrificial material layer relative to the silicon carbon oxide pads; And Forming a conductive layer in the backside recess.

37. The method according to claim 36, wherein: The memory film further includes a dielectric metal oxide blocking dielectric layer laterally surrounding the silicon oxide blocking dielectric layer, and a silicon oxide pad laterally surrounding the dielectric metal oxide blocking dielectric layer; and The method further includes selectively isotropically etching portions of the silicon oxide pad relative to the silicon carbon oxide pads by performing an isotropic etching process after forming the backside recess and before forming the conductive layer.

38. The method according to claim 37, wherein: The isotropic etching process divides the silicon oxide pad into a vertical stack of vertically spaced silicon oxide spacers; Forming an annular pit between the silicon carbon oxide pad and the dielectric metal oxide blocking dielectric layer; and The method further includes forming a pit fill annular dielectric spacer in the annular pit, where a first conductive layer among the conductive layers is deposited on the pit fill annular dielectric spacer, the silicon carbon oxide pad, and a cylindrical surface section of an outer sidewall of the dielectric metal oxide blocking dielectric layer.

39. The method according to claim 36, the method further comprising: selectively isotropically etching a portion of the silicon oxide barrier dielectric layer relative to the silicon carbon oxide liner by performing an isotropic etching process after forming the backside groove to form a vertically stacked annular lateral recess that is vertically spaced apart on the outer sidewalls of the silicon oxide barrier dielectric layer; and forming a backside dielectric metal oxide barrier dielectric layer in the backside groove and directly on the horizontal surface of the silicon carbon oxide liner, wherein the conductive layer is formed on the backside dielectric metal oxide barrier dielectric layer.

40. The method according to claim 39, wherein: an annular pit is formed between the silicon carbon oxide liner and one of the annular lateral recesses; and the method further comprises forming a pit-fill annular dielectric spacer in the annular pit, wherein the backside dielectric metal oxide barrier dielectric layer is deposited on the pit-fill annular dielectric spacer, the silicon carbon oxide liner, and the cylindrical surface section of the annular lateral recess of the silicon oxide barrier dielectric layer.

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