MEMORY DEVICES INCLUDING BARRIER DIELECTRIC CONTAINING Hafnium OXIDE OR ZIRCONIUM

Abstract

A three-dimensional memory device includes: an alternating stack of insulating layers and conductive layers; a memory opening, the memory opening extending vertically through the alternating stack; a memory opening filling structure in the memory opening; and a backside barrier dielectric layer comprising hafnium oxide or zirconium oxide. Each of the memory opening filling structures includes a respective vertical stack of memory elements and a vertical semiconductor channel. Each of the conductive layers includes a metal layer and a tungsten nitride-containing diffusion barrier layer. The hafnium oxide or zirconia-containing backside barrier dielectric layer is located between the tungsten nitride-containing diffusion barrier layer and the memory opening fill structure.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of the entire content of U.S. Non - provisional Application No. 18 / 229,489, filed on August 2, 2023, entitled "MEMORY DEVICE INCLUDING HAFNIUM OR ZIRCONIUM OXIDE CONTAINING BLOCKING DIELECTRIC AND TUNGSTEN NITRIDE BARRIER AND METHODS OF FORMING THE SAME", and incorporates it herein by reference for all purposes. Technical field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices and methods of manufacturing the same, which include a blocking dielectric containing Hf oxide or Zr oxide and a tungsten nitride barrier layer for word lines. Background art

[0004] A three - dimensional vertical NAND string having one bit per cell is disclosed in the article by T. Endoh et al., entitled "Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell", Proceedings of the IEDM (2001), pages 33 - 36. Summary of the invention

[0005] According to one aspect of the present disclosure, a three - dimensional memory device includes: an alternating stack of insulating layers and conductive layers; a memory opening extending vertically through the alternating stack; a memory - opening filling structure located in the memory opening; and a back - side blocking dielectric layer containing hafnium oxide or zirconium oxide. Each memory - opening filling structure in the memory - opening filling structure includes a corresponding vertical stack of memory elements and a vertical semiconductor channel. Each conductive layer in the conductive layer includes a metal layer and a diffusion barrier layer containing tungsten nitride. The back - side blocking dielectric layer containing hafnium oxide or zirconium oxide is located between the diffusion barrier layer containing tungsten nitride and the memory - opening filling structure.

[0006] According to another aspect of the present disclosure, a method of forming a three-dimensional memory device includes: forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; forming a memory opening that vertically extends through the alternating stack; forming a memory opening fill structure in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a corresponding vertical stack of memory elements and a vertical semiconductor channel; forming a laterally extending cavity by selectively removing the sacrificial material layer relative to the insulating layer and the memory opening fill structure; forming a backside blocking dielectric layer containing hafnium oxide or zirconium oxide in the laterally extending cavity; forming a diffusion barrier layer containing tungsten nitride on the backside blocking dielectric layer containing hafnium oxide or zirconium oxide in the laterally extending cavity; and forming a metal layer on the diffusion barrier layer containing tungsten nitride in the laterally extending cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a schematic vertical cross-sectional view of an exemplary structure for forming an alternating stack of an insulating layer and a sacrificial material layer, a stop insulating layer, and a source level material layer over a carrier substrate and then forming a memory die according to an embodiment of the present disclosure.

[0008] Figure 2 FIG. 2 is a schematic vertical cross-sectional view of an exemplary structure after forming a stepped surface and an inverse stepped dielectric material portion according to an embodiment of the present disclosure.

[0009] Figure 3A FIG. 3 is a schematic vertical cross-sectional view of an exemplary structure after forming a memory opening and a support opening according to an embodiment of the present disclosure.

[0010] Figure 3B FIG. 4 is Figure 3A a top-down view of the exemplary structure of FIG. 4. The vertical plane A-A' is the Figure 3A cutting plane of the vertical cross-sectional view of FIG. 4.

[0011] Figure 4 FIG. 5 is a schematic vertical cross-sectional view of an exemplary structure after forming a support pillar structure according to an embodiment of the present disclosure.

[0012] Figures 5A to 5D FIG. 6 is a sequential vertical cross-sectional view of a memory opening during the formation of a memory opening fill structure according to an embodiment of the present disclosure.

[0013] Figure 6A FIG. 7 is a vertical cross-sectional view of an exemplary structure after forming a memory opening fill structure according to an embodiment of the present disclosure.

[0014] Figure 6B FIG. 8 is Figure 6ATop-down view of an exemplary structure. Vertical plane A-A’ is Figure 6A the cutting plane of the vertical cross-sectional view of

[0015] Figure 7A Vertical cross-sectional view of an exemplary structure after forming isolation trenches according to an embodiment of the present disclosure.

[0016] Figure 7B is Figure 7A Top-down view of an exemplary structure. Vertical plane A-A’ is Figure 7A the cutting plane of the vertical cross-sectional view of

[0017] Figure 8 Vertical cross-sectional view of an exemplary structure after forming source-level cavities according to an embodiment of the present disclosure.

[0018] Figure 9 Vertical cross-sectional view of an exemplary structure after forming source contact layers according to an embodiment of the present disclosure.

[0019] Figure 10 Vertical cross-sectional view of an exemplary structure after forming laterally extending cavities according to an embodiment of the present disclosure.

[0020] Figures 11A to 11E Sequential vertical cross-sectional views of regions of an exemplary structure during the formation of alumina barrier dielectric layers, backside barrier dielectric layers, and conductive layers in each of the laterally extending cavities in a laterally extending cavity according to an embodiment of the present disclosure.

[0021] Figure 11F Vertical cross-sectional view of a region of an alternative embodiment of an exemplary structure after forming conductive layers in each of the laterally extending cavities in a laterally extending cavity according to an embodiment of the present disclosure.

[0022] Figure 12 Vertical cross-sectional view of an exemplary structure after forming conductive layers according to an embodiment of the present disclosure.

[0023] Figure 13A Vertical cross-sectional view of an exemplary structure after forming laterally isolated trench fill structures and contact via structures according to an embodiment of the present disclosure.

[0024] Figure 13B is Figure 13A Top-down view of an exemplary structure. Vertical plane A-A’ is Figure 13A the cutting plane of the vertical cross-sectional view of

[0025] Figure 14A Vertical cross-sectional view of an exemplary structure after forming bit lines and bit-line level metal lines according to an embodiment of the present disclosure.

[0026] Figure 14B is Figure 14A a top - down view of an exemplary structure of Figure 14A The vertical plane A - A’ is the cutting plane of the vertical cross - sectional view of

[0027] Figure 15 a vertical cross - sectional view of an exemplary structure after forming a memory die according to an embodiment of the present disclosure.

[0028] Figure 16 a vertical cross - sectional view of a logic die according to an embodiment of the present disclosure.

[0029] Figure 17 a vertical cross - sectional view of an exemplary structure after forming a bonding assembly of a memory die and a logic die according to an embodiment of the present disclosure.

[0030] Figure 18 a vertical cross - sectional view of an exemplary structure after optionally removing a carrier substrate from a memory die according to an embodiment of the present disclosure.

[0031] Figure 19 a vertical cross - sectional view of an alternative configuration of an exemplary structure after forming an alternating stack of an insulating layer and a sacrificial material layer according to an alternative embodiment of the present disclosure.

[0032] Figure 20 a vertical cross - sectional view of an alternative configuration of an exemplary structure after forming a memory die according to an alternative embodiment of the present disclosure.

[0033] Figure 21 a graph illustrating the dependence of the threshold voltage on the erase voltage for various configurations of a back - side blocking dielectric layer according to various embodiments. Detailed Description

[0034] As discussed above, embodiments of the present disclosure relate to three - dimensional semiconductor devices and methods of manufacturing the same, which include a blocking dielectric containing a Group IVB oxide and a tungsten nitride barrier layer for word lines. Various aspects thereof are described below. Embodiments of the present disclosure can be used to form various structures including multi - level memory structures, non - limiting examples of which include semiconductor devices such as three - dimensional memory array devices including multiple memory strings.

[0035] The accompanying drawings are not drawn to scale. Multiple instances of an element may be replicated in the case of a single instance of an illustrated element, unless otherwise explicitly described or clearly indicated that there is no replication of the element. Ordinal numbers such as "first", "second", and "third" are only used to identify similar elements, and different ordinal numbers may be used in the description and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0036] Like reference numerals represent like or similar elements. Unless otherwise specified, elements having the same reference numeral are considered to have the same composition and the same function. Unless otherwise specified, "contact" between elements means direct contact providing an edge or surface shared by the elements. If two or more elements do not directly contact each other or do not directly contact each other, these two elements are "separated" from each other or "separated" from each other. As used herein, an element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, an element is "directly" located "on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, an element is "electrically connected to" a second element if there is an electrical conduction path composed of at least one conductive material between the element and the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure whose shape or composition of at least one of its components is subsequently modified.

[0037] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer may extend over the entire underlying or overlying structure, or its extent may be less than that of the underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be between any pair of horizontal planes between the top surface and the bottom surface of a continuous structure or at the top surface and the bottom surface. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers on, above, and / or below it.

[0038] Generally speaking, a semiconductor die or a semiconductor package may include a memory chip. Each semiconductor package includes one or more dies (e.g., one, two, or four). A die is the smallest unit that can independently execute commands or report status. Each die contains one or more planes (usually one or two). Although there are some limitations, the same and concurrent operations can be performed on each plane. Each plane contains multiple blocks, which are the smallest units that can be erased in a single erase operation. Each block contains multiple pages, which are the smallest programmable units, i.e., the smallest units on which a read operation can be performed.

[0039] As used herein, "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 - 5 S / m to 1.0 S / m in the absence of electrical dopants, and which, when appropriately doped with electrical dopants, can produce a doped material having a conductivity in the range of 1.0 S / m to 1.0×10 7 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / m. As used herein, "insulating material" or "dielectric material" refers to a material having a conductivity less than 1.0×10 -5 S / m. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with electrical dopants at a high enough atomic concentration to become a conductive material, which conductive material is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a conductivity greater than 1.0×10 5 S / m. A "doped semiconductor material" can be a heavily doped semiconductor material or can be a semiconductor material including electrical dopants (i.e., p-type dopants and / or n-type dopants), the concentration of which provides a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 7 S / m. An "intrinsic semiconductor material" refers to a semiconductor material not doped with electrical dopants. Thus, a semiconductor material can be semiconducting or conductive and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopants therein. As used herein, "metal material" refers to a conductive material containing at least one metal element. All conductivity measurements are made under standard conditions.

[0040] Reference Figure 1 illustrates an exemplary structure in accordance with an embodiment of the present disclosure. The exemplary structure includes a carrier substrate 9, which can be a semiconductor substrate or a conductive substrate. For example, the carrier substrate 9 can include a commercially available silicon wafer. Alternatively, the carrier substrate 9 can include any material that can be selectively removed relative to the material of the insulating layer 32 and the subsequent dielectric material portions to be formed.

[0041] An insulating material layer may be formed on the top surface of the carrier substrate 9. The insulating material layer may then be used as an etch-stop material layer in the process of removing the carrier substrate 9, and is referred to herein as the etch-stop insulating layer 106, or the back-side pad dielectric layer. If a polishing process such as a chemical mechanical polishing process is used to subsequently remove the carrier substrate 9, the etch-stop insulating layer 106 may then be used as a polishing stop material layer. If an etching process such as a wet etching process is used to subsequently remove the carrier substrate 9, the etch-stop insulating layer 106 may then be used as an etching stop material layer. In one embodiment, the etch-stop insulating layer 106 includes a dielectric material, such as undoped silicate glass, doped silicate glass, or silicon nitride. The thickness of the etch-stop insulating layer 106 may range from 50 nm to 600 nm, such as 100 nm to 300 nm, but smaller and larger thicknesses may also be used.

[0042] During the process, a source-level material layer 110' may be formed on the etch-stop insulating layer 106. The source-level material layer 110' may include various layers that are subsequently modified to form the source-level material layer. When formed, the source-level material layer includes a source contact layer that serves as a common source region for the vertical field-effect transistors of the three-dimensional memory device. In one embodiment, the source-level material layer 110' may include, from bottom to top, a lower source-level semiconductor layer 112, an optional lower sacrificial liner (not shown), a source-level sacrificial layer 104, an optional upper sacrificial liner (not shown), and an upper source-level semiconductor layer 116.

[0043] The lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon. The conductivity type of the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a doping of a first conductivity type, the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 have a doping of a second conductivity type opposite to the first conductivity type. The thickness of each of the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may range from 10 nm to 300 nm, such as 20 nm to 150 nm, but smaller and larger thicknesses may also be used.

[0044] The source-level sacrificial layer 104 comprises a sacrificial material that can be selectively removed relative to a lower sacrificial liner (or relative to the lower source-level semiconductor layer 112) and an upper sacrificial liner (or relative to the upper source-level semiconductor layer 116). In one embodiment, the source-level sacrificial layer 104 may comprise a semiconductor material such as undoped amorphous silicon or a silicon-germanium alloy with a germanium atom concentration greater than 20%. The thickness of the source-level sacrificial layer 104 may range from 30 nm to 400 nm, such as 60 nm to 200 nm, although smaller and larger thicknesses may also be used. The lower sacrificial liner (if present) and the upper sacrificial liner (if present) comprise materials that can be used as an etch-stop material during the removal of the source-level sacrificial layer 104. For example, the lower sacrificial liner and the upper sacrificial liner may comprise silicon oxide, silicon nitride, and / or dielectric metal oxides. In one embodiment, each of the lower sacrificial liner and the upper sacrificial liner may comprise a silicon oxide layer having a thickness in the range of 2 nm to 30 nm, although smaller and larger thicknesses may also be used.

[0045] An alternating stack of a first material layer and a second material layer may be formed over the in-process source-level material layer 110'. In an alternative embodiment, the in-process source-level material layer 110' and the blocking insulating layer 106 may be omitted, and the alternating stack may be formed directly on the surface of the semiconductor substrate 9. In another alternative embodiment described below Figure 20 peripheral circuits are formed on the same substrate as the alternating stack. For example, the peripheral circuits may include a word-line driver region, a bit-line driver region, a sense amplifier region, an input / output buffer region, etc. In this alternative embodiment, a separate logic die comprising the peripheral circuits described below Figure 16 may be omitted. In this alternative embodiment, the alternating stack may be deposited on the in-process source-level material layer 110', or the in-process source-level material layer 110' may be omitted, and the alternating stack may be deposited on the blocking insulating layer 106.

[0046] In an alternating stack, the first material layer can be an insulating layer and the second material layer can be a spacer material layer. In one embodiment, the spacer material layer can include a sacrificial material layer 42. In this case, an alternating stack (32, 42) of the insulating layer 32 and the sacrificial material layer 42 can be formed over the in-process source-level material layer 110'. The insulating layer 32 includes an insulating material such as undoped silicate glass or doped silicate glass, and the sacrificial material layer 42 includes a sacrificial material such as silicon nitride or a silicon-germanium alloy. In one embodiment, the insulating layer 32 (i.e., the first material layer) can include a silicon oxide layer, and the sacrificial material layer 42 (i.e., the second material layer) can include a silicon nitride layer. The alternating stack (32, 42) can include multiple repetitions of a unit layer stack including the insulating layer 32 and the sacrificial material layer 42. The total number of repetitions of the unit layer stack within the alternating stack (32, 42) can be, for example, in the range of 8 to 1,024, such as 32 to 256, although smaller and larger numbers of repetitions can also be employed. Hereinafter, the topmost insulating layer in the insulating layer 32 is referred to as the topmost insulating layer 32T. The bottommost insulating layer in the insulating layer 32 is the insulating layer 32 closest to the carrier substrate 9, which is referred to herein as the bottommost insulating layer 32B.

[0047] Each insulating layer in the insulating layer 32 other than the topmost insulating layer 32 can have a thickness in the range of 20 nm to 100 nm (such as 30 nm to 60 nm), although smaller and larger thicknesses can also be employed. Each sacrificial material layer in the sacrificial material layer 42 can have a thickness in the range of 20 nm to 100 nm (such as 30 nm to 60 nm), although smaller and larger thicknesses can also be employed. In one embodiment, the topmost insulating layer 32 can have a thickness that is about half the thickness of the other insulating layers 32.

[0048] Exemplary structures include a memory array region 100 and a contact region 300, in which a three-dimensional array of memory elements will be subsequently formed in the memory array region and a layer contact via structure for contacting a contact word line will be subsequently formed in the contact region.

[0049] Reference Figure 2 , a stepped surface is formed in the contact region 300. As used herein, a "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and is adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume, and a portion of the alternating stack (32, 42) is removed from the volume by forming the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0050] The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the top surface of the source electrode layer 110' in the process. In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process. The first type of etching process vertically increases the depth of the cavity by one or more levels, and the second type of etching process laterally expands the area vertically etched in the subsequent first type of etching process. As used herein, a "level" of a structure including multiple alternating layers is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

[0051] Each sacrificial material layer 42 within the alternating stack (32, 42) except for the topmost sacrificial material layer 42 extends further laterally than any overlying sacrificial material layer 42 within the alternating stack (32, 42) in the mesa region. The stepped surface of the alternating stack (32, 42) continuously extends from the bottommost layer (such as the bottommost insulating layer 32B) within the alternating stack (32, 42) to the topmost layer (such as the topmost insulating layer 32T) within the alternating stack (32, 42).

[0052] An inverse-stepped dielectric material portion 65 (i.e., an insulating fill material portion) may be formed in the stepped cavity by depositing a dielectric material in the stepped cavity. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. The excess portion of the deposited dielectric material may be removed, for example, by chemical mechanical planarization (CMP) above the top surface of the topmost insulating layer 32T. The remaining portion of the stepped cavity filled with the deposited dielectric material constitutes the inverse-stepped dielectric material portion 65. As used herein, an "inverse-stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases according to the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the inverse-stepped dielectric material portion 65, the silicon oxide of the inverse-stepped dielectric material portion 65 may or may not be doped with dopants such as B, P, and / or F.

[0053] Optionally, a drain select level isolation structure (not shown) may be formed through the topmost insulating layer 32T and a subset of the sacrificial material layers 42 located at the drain select level. For example, the drain select level isolation structure may be formed by forming a drain select level lateral isolation trench and filling the drain select level lateral isolation trench with a dielectric material such as silicon oxide. The excess portion of the dielectric material may be removed above the top surface of the topmost insulating layer 32T.

[0054] Reference Figure 3AUp to FIG. 3C, an etch mask layer (not shown) can be formed over the alternating stack (32, 42), and the etch mask layer can be lithographically patterned to form various openings therein. An anisotropic etch process can be performed to transfer the pattern of the openings in the etch mask layer through the alternating stack (32, 42). Various openings can be formed through the alternating stack (32, 42). The various openings can include memory openings 49 formed in the memory array region 100 and support openings 19 formed in the contact region 300. Each of the memory openings 49 and the support openings 19 can extend vertically through the alternating stack (32, 42) and into the in-process source level material layer 110'. In one embodiment, the bottom surfaces of the memory openings 49 and the support openings 19 can be formed within the lower source level semiconductor layer 112 or at the interface between the lower source level semiconductor layer and the blocking insulating layer 106.

[0055] The support openings 19 can have a diameter in the range of 60 nm to 400 nm (such as 120 nm to 300 nm), but smaller and larger thicknesses can be employed. The memory openings 49 can have a diameter in the range of 60 nm to 400 nm (such as 120 nm to 300 nm), but smaller and larger thicknesses can be employed.

[0056] In one embodiment, the memory array region 100 can be laterally spaced from the contact region 300 along a first horizontal direction hd1. The memory openings 49 can include multiple rows of memory openings 49 arranged along the first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd2. Multiple clusters of the memory openings 49 can be formed in the memory array region 100, each cluster containing a corresponding two-dimensional periodic array of the memory openings 49. The clusters of the memory openings 49 can be laterally spaced apart along the second horizontal direction hd2.

[0057] Reference Figure 4, an optional etch stop liner (not shown) and a sacrificial fill material (not shown) can be deposited in the memory opening 49 and the support opening. The optional etch stop liner (if present) includes a thin dielectric material layer, which includes silicon oxide, silicon nitride, or dielectric metal oxide and has a thickness in the range of 1 nm to 6 nm. The sacrificial fill material can include a carbon-based material (such as amorphous carbon or diamond-like carbon), a semiconductor material (such as amorphous silicon or polysilicon), a dielectric fill material (such as borosilicate glass or organosilicate glass), or a polymer material. The excess portion of the sacrificial fill material can be removed from above the horizontal plane of the topmost layer of the alternating stack (32, 42) through a planarization process (such as an etch-back process). The remaining portions of the sacrificial fill material that fill the memory opening 49 and the support opening 19 constitute a sacrificial memory opening fill structure (not shown) and a sacrificial support opening fill structure (not shown).

[0058] A photoresist layer (not shown) can be applied over the alternating stack (32, 42) and the inverse stepped dielectric material portion 65, and can be lithographically patterned to cover the memory array region 100 without covering the contact region 300. Each portion of the optional etch stop liner in the contact region 300 and the sacrificial support opening fill structure can be selectively removed relative to the materials of the inverse stepped dielectric material portion 65 and the alternating stack (32, 42). For example, an etch process or an ashing process can be employed to remove each portion of the optional etch stop liner in the contact region 300 and the sacrificial support opening fill structure. Subsequently, the photoresist layer can be removed.

[0059] A dielectric fill material (such as silicon oxide) can be deposited in the support opening 19 through a conformal deposition process. The excess portion of the dielectric fill material can be removed from above the top surface of the topmost insulating layer 32T, for example, through a recess etching process. Each portion of the dielectric fill material that fills the corresponding support opening 19 constitutes a support pillar structure 20, which can be used to provide structural support to the insulating layer 32 and the inverse stepped dielectric material portion 65 during the replacement of the sacrificial material layer 42 with a conductive layer.

[0060] Subsequently, each portion of the optional etch stop liner in the memory array region 100 and the sacrificial memory opening fill structure can be selectively removed with respect to the materials of the inverse stepped dielectric material portion 65 and the alternating stack (32, 42). For example, an etch process or an ashing process can be employed to remove each portion of the optional etch stop liner in the memory array region 100 and the sacrificial memory opening fill structure. A void is formed in the volume of the memory opening 49.

[0061] Figures 5A to 5Dis a sequential vertical cross-sectional view of a memory opening 49 during the formation of a NAND string (e.g., a dummy NAND string or a data storage NAND string), which is hereinafter referred to as a "memory opening fill structure" 58.

[0062] Reference Figure 5A , illustrates the memory opening 49 after the processing steps of Figure 4 .

[0063] Reference Figure 5B , a layer stack including a memory material layer 54 can be conformally deposited. In an illustrative example, the layer stack can include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. The memory material layer 54 includes a memory material, i.e., a material in which data bits can be stored. The memory material layer 54 can include a charge storage material (such as silicon nitride). In the case where the memory material layer 54 includes a charge storage material, the optional dielectric liner 56 can include a tunneling dielectric layer.

[0064] A semiconductor channel material layer 60L can be deposited on the layer stack (52, 54, 56) by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, the semiconductor channel material layer 60L can have a doping of a first conduction type, which can be p-type or n-type. In one embodiment, the first semiconductor material includes a first doped silicon material having a doping of a first conduction type. In an illustrative example, the atomic concentration of the dopant of the first conduction type in the semiconductor channel material layer 60L can be in the range of 1.0×10 13 / cm 3 to 3.0×10 17 / cm 3 , such as 1.0×10 14 / cm 3 to 3.0×10 16 / cm 3 , but smaller and larger atomic concentrations can also be employed. A dielectric core layer 62L including a dielectric fill material can be deposited in the remaining volume of the memory opening 49 and on the alternating stack (32, 42).

[0065] Reference Figure 5C , the dielectric core layer 62L can be vertically recessed such that each remaining portion of the dielectric core layer 62L has a top surface at or near a horizontal plane of the bottom surface including the topmost insulating layer 32T. Each remaining portion of the dielectric core layer 62L constitutes a dielectric core 62.

[0066] Reference Figure 5D, a doped semiconductor material of a second conductivity type can be deposited within each of the recessed regions above the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 , but smaller or larger dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

[0067] The excess portions of the deposited semiconductor material doped with the second conductivity type and the horizontal portions of the semiconductor channel material layer 60L can be removed, for example, by chemical mechanical planarization (CMP) or recess etching processes above the horizontal plane of the top surface including the topmost insulating layer 32T. Each remaining portion of the doped semiconductor material of the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel material layer 60L (which is doped with the first conductivity type) constitutes a vertical semiconductor channel 60.

[0068] Each portion of the layer stack including the memory material layer 54 retained within the respective memory opening 49 constitutes a memory film 50. In one embodiment, the memory film 50 can include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. Each successive combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Each memory opening fill structure 58 includes a respective vertical stack of memory elements, which can include portions of the memory material layer 54 at the level of the sacrificial material layer 42.

[0069] Reference Figure 6A and Figure 6B , illustrates an exemplary structure after forming the memory opening fill structure 58 within the memory opening 49. Each memory opening fill structure within the memory opening fill structure 58 can include a memory film 50 and a vertical semiconductor channel 60. Generally speaking, a combination of an alternating stack (32, 42) of the insulating layer 32 and the sacrificial material layer 42, memory openings 49 extending vertically through the alternating stack (32, 42), and the memory opening fill structures 58 located within the memory openings 49 can be formed. Each memory opening fill structure within the memory opening fill structure 58 includes a respective vertical stack of memory elements, such as portions of the memory material layer 54 at the level of the sacrificial material layer 42.

[0070] ReferenceFigure 7A and Figure 7B a dielectric material such as undoped silicate glass or doped silicate glass may be deposited over the alternating stack (32, 42) to form a contact-level dielectric layer 80. The thickness of the contact-level dielectric layer 80 may be in the range of 100 nm to 600 nm, such as 200 nm to 400 nm, although smaller and larger thicknesses may also be employed.

[0071] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be lithographically patterned to form elongated openings that extend laterally between adjacent clusters of the memory opening fill structure 58 along a first horizontal direction hd1. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stack (32, 42), the inverse-stepped dielectric material portion 65, and the in-process source-level material layer 110'. Lateral isolation trenches 79 that extend laterally along the first horizontal direction hd1 may be formed to pass through the alternating stack (32, 42), the inverse-stepped dielectric material portion 65, the contact-level dielectric layer 80, and the in-process source-level material layer 110'. Each of the lateral isolation trenches 79 may include a respective pair of longitudinal sidewalls that are parallel to the first horizontal direction hd1 and extend vertically from the blocking insulating layer 106 to the top surface of the contact-level dielectric layer 80. The top surface of the blocking insulating layer 106 may be physically exposed below each of the lateral isolation trenches 79. The lateral isolation trenches 79 isolate adjacent memory blocks from each other along a second horizontal direction hd2. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0072] Referring Figure 8 to, an etchant may be introduced into the lateral isolation trenches 79 by performing an isotropic etching process that selectively etches the material of the source-level sacrificial layer 104 relative to the materials of the alternating stack (32, 42), the contact-level dielectric layer 80, the inverse-stepped dielectric material portion 65, the lower source-level semiconductor layer 112, the upper source-level semiconductor layer 116, the upper sacrificial liner 105 (if present), and the lower sacrificial liner 103 (if present). For example, if the source-level sacrificial layer 104 comprises undoped amorphous silicon or a silicon-germanium alloy, a wet etching process using hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) may be used to selectively remove the source-level sacrificial layer 104 relative to the alternating stack (32, 42), the contact-level dielectric layer 80, the inverse-stepped dielectric material portion 65, the lower source-level semiconductor layer 112, and the upper source-level semiconductor layer 116. A source cavity 109 is formed in the volume from which the source-level sacrificial layer 104 is removed.

[0073] Wet etching chemicals such as hot TMY and TMAH are selective to doped semiconductor materials such as p-doped semiconductor materials and / or n-doped semiconductor materials of the upper source-level semiconductor layer 116 and the lower source-level semiconductor layer 112. Thus, the use of selective wet etching chemicals (such as hot TMY and TMAH) for the wet etching process of forming the source cavity 109 provides a large process window for resisting etching depth variations during the formation of the lateral isolation trench 79. Specifically, even if the sidewalls of the upper source-level semiconductor layer 116 are physically exposed or even if the surface of the lower source-level semiconductor layer 112 is physically exposed when forming the source cavity 109, the incidental etching of the upper source-level semiconductor layer 116 and / or the lower source-level semiconductor layer 112 is minimal, and structural changes to the exemplary structure caused by accidental physical exposure of the surface of the upper source-level semiconductor layer 116 and / or the lower source-level semiconductor layer 112 during the manufacturing steps do not result in device failure. Each memory opening fill structure in the memory opening fill structure 58 is physically exposed to the source cavity 109. Specifically, each memory opening fill structure in the memory opening fill structure 58 includes sidewalls and is physically exposed to the source cavity 109.

[0074] A series of isotropic etchants (such as wet etchants) can be applied to the physically exposed portions of the memory film 50 to sequentially etch the various sets of layers of the memory film 50 from the outside in, and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the level of the source cavity 109. The upper sacrificial liner 105 (if present) and the lower sacrificial liner 103 (if present) can be incidentally etched during the removal of the portion of the memory film 50 located at the level of the source cavity 109. The volume of the source cavity 109 can be enlarged by removing the portions of the memory film 50 at the levels of the source cavity 109 and the upper and lower sacrificial liners. The top surface of the lower source-level semiconductor layer 112 and the bottom surface of the upper source-level semiconductor layer 116 can be physically exposed to the source cavity 109. The source cavity 109 is formed by selectively isotropically etching the source-level sacrificial layer 104 and the bottom portion of each memory film in the memory film 50 with respect to at least one source-level semiconductor layer (such as the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116) and the vertical semiconductor channel 60.

[0075] Reference Figure 9, a doped semiconductor material of a second conductivity type can be deposited on the physically exposed semiconductor surface surrounding the source cavity 109. The physically exposed semiconductor surface includes the bottom portion of the outer sidewall of the vertical semiconductor channel 60 and the horizontal surfaces of at least one source-level semiconductor layer (such as the bottom surface of the upper source-level semiconductor layer 116 and / or the top surface of the lower source-level semiconductor layer 112). For example, the physically exposed semiconductor surface can include the bottom portion of the outer sidewall of the vertical semiconductor channel 60, the top horizontal surface of the lower source-level semiconductor layer 112, and the bottom surface of the upper source-level semiconductor layer 116.

[0076] In one embodiment, the doped semiconductor material of the second conductivity type can be deposited on the physically exposed semiconductor surface surrounding the source cavity 109 by a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant, and a dopant gas can be simultaneously introduced into the process chamber including the exemplary structure. For example, the semiconductor precursor gas can include silane, disilane, or dichlorosilane, the etchant gas can include gaseous hydrogen chloride, and the dopant gas can include hydrides of dopant atoms such as phosphine, arsine, stibine, or diborane. In this case, the selective semiconductor deposition process grows a doped semiconductor material of the second conductivity type from the physically exposed semiconductor surface surrounding the source cavity 109. The deposited doped semiconductor material forms the source contact layer 114, which can contact the sidewall of the vertical semiconductor channel 60. The atomic concentration of the dopant of the second conductivity type in the deposited semiconductor material can be in the range of 1.0×10 20 / cm 3 to 2.0×10 21 / cm 3 , such as 2.0×10 20 / cm 3 to 8.0×10 20 / cm 3 . The initially formed source contact layer 114 can consist essentially of semiconductor atoms and dopant atoms of the second conductivity type. Alternatively, at least one non-selective doped semiconductor material deposition process can be used to form the source contact layer 114. Optionally, one or more etch-back processes can be used in combination with multiple selective or non-selective deposition processes to provide a seamless and / or void-free source contact layer 114.

[0077] The duration of the selective semiconductor deposition process can be selected such that the source cavity 109 is filled with the source contact layer 114. In one embodiment, the source contact layer 114 can be formed by selectively depositing a doped semiconductor material having a second conductivity type from the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material can include doped polysilicon. Thus, the source level sacrificial layer 104 can be replaced with the source contact layer 114. The layer stack including the lower source level semiconductor layer 112, the source contact layer 114, and the upper source level semiconductor layer 116 constitutes the source layer 110, which replaces the source level material layer 110' in the process. The source layer 110 contacts the end portions of each of the vertical semiconductor channels in the vertical semiconductor channel 60.

[0078] Reference Figure 10 , an isotropic etching process can be performed to selectively remove the sacrificial material layer 42 relative to the insulating layer 32, the stop insulating layer 106, the memory opening fill structure 58, the sacrificial etch stop liner 71, and the source layer 110. A laterally extending cavity 43 can be formed in the volume where the sacrificial material layer 42 is removed. The sidewall surface segments of the memory opening fill structure 58 can be physically exposed to the laterally extending cavity 43. In an illustrative example, if the sacrificial material layer 42 comprises silicon nitride, the isotropic etching process can include a wet etching process using hot phosphoric acid, which is a process in which the exemplary structure is immersed in phosphoric acid at or near the boiling point of phosphoric acid. A suitable cleaning process can be performed as needed. Generally speaking, the laterally extending cavity 43 can be formed by selectively removing the sacrificial material layer 42 relative to the insulating layer 32 and the memory opening fill structure 58.

[0079] Figures 11A to 11E is a sequential vertical cross-sectional view of a region of an exemplary structure during the formation of an optional alumina barrier dielectric layer 44, a backside barrier dielectric layer 45, and a conductive layer 46 in each of the laterally extending cavities 43 according to an embodiment of the present disclosure.

[0080] Reference Figure 11A , illustrates the region of an exemplary structure after the processing step of Figure 10 . The cylindrical outer surface segments of each memory opening fill structure 58 and the horizontally extending surface of the insulating layer 32 can be exposed to the laterally extending cavity 43.

[0081] Reference Figure 11B, an aluminum oxide barrier dielectric layer 44 can be optionally directly deposited on the physically exposed cylindrical outer surface section of the memory opening filling structure 58 and the physically exposed surface of the insulating layer 32 through a conformal deposition process. For example, an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process can be used to deposit the aluminum oxide barrier dielectric layer 44. The aluminum oxide barrier dielectric layer 44 can consist essentially of aluminum oxide and can have a uniform thickness in the range of 0.5 nm to 4 nm (such as 1 nm to 2.5 nm), but smaller or larger thicknesses can also be used. In one embodiment, the aluminum oxide barrier dielectric layer 44 contacts the entire physically exposed surface of the insulating layer 32 and the physically exposed sidewall section of the memory opening filling structure 58.

[0082] Reference Figure 11C , a backside barrier dielectric layer 45 is deposited on the aluminum oxide barrier dielectric layer 44 in the laterally extending cavity 43. The backside barrier dielectric layer 45 comprises a dielectric metal oxide material and / or consists essentially of a dielectric metal oxide material that comprises at least one of hafnium or zirconium. In one embodiment, the backside barrier dielectric layer 45 consists essentially of stoichiometric or non-stoichiometric hafnium oxide, zirconium oxide, or hafnium zirconium oxide. The stoichiometric oxide has the formula MO2, where M is at least one of Hf or Zr.

[0083] In another embodiment, the backside barrier dielectric layer 45 comprises another element in addition to hafnium, zirconium, and oxygen. For example, the backside barrier dielectric layer 45 comprises silicon in an atomic percentage in the range of 1% to 25% (such as 10% to 17%). In one embodiment, the backside barrier dielectric layer 45 consists essentially of at least one of hafnium or zirconium and silicon and oxygen. In this case, the backside barrier dielectric layer 45 can comprise stoichiometric or non-stoichiometric metal silicates, such as hafnium silicate, zirconium silicate, or hafnium zirconium silicate. These stoichiometric silicates have the formula MSiO4, where M is at least one of Hf or Zr.

[0084] The backside barrier dielectric layer 45 can be deposited through a conformal deposition process and can always have a uniform thickness. In one embodiment, an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process can be used to deposit the backside barrier dielectric layer 45. The backside barrier dielectric layer 45 can have a thickness in the range of 1 nm to 10 nm (such as 2 nm to 5 nm), but smaller or larger thicknesses can also be used. The backside barrier dielectric layer 45 is spaced apart from the memory opening filling structure 58 and the insulating layer 32 by the aluminum oxide barrier dielectric layer 44.

[0085] Reference Figure 11D, a diffusion barrier layer 46A containing conductive tungsten nitride can be conformally deposited on the physically exposed surface of the dielectric layer 45 on the back side. The tungsten nitride-containing diffusion barrier layer 46A can consist essentially of tungsten nitride or can contain doped tungsten nitride, such as boron-doped tungsten nitride (e.g., boron tungsten nitride).

[0086] In one embodiment, the tungsten nitride-containing diffusion barrier layer 46A can contain stoichiometric tungsten nitride and / or can consist essentially of stoichiometric tungsten nitride, where the atomic ratio between tungsten atoms and nitrogen atoms is 1:1. Alternatively, the tungsten nitride-containing diffusion barrier layer 46A can contain other atoms, such as boron atoms in the range of 1% to 40% (such as 5% to 33%) atomic percentage, although smaller and larger atomic percentages can also be employed. The tungsten nitride-containing diffusion barrier layer 46A can be deposited by a conformal deposition process, such as atomic layer deposition process or chemical vapor deposition process. The thickness of the tungsten nitride-containing diffusion barrier layer 46A can be in the range of 1 nm to 8 nm, such as 2 nm to 5 nm, although smaller or larger thicknesses can also be used.

[0087] Reference Figure 11E , a metal layer 46B can be deposited in the remaining volume of the laterally extending cavity 43, and the metal layer contains a metal with an atomic percentage greater than 95%, and / or greater than 99%, and / or greater than 99.8%. In one embodiment, the metal can include tungsten, molybdenum, ruthenium, or cobalt. The metal layer 46B can be deposited by a conformal deposition process, such as chemical vapor deposition process, and can fill the remaining volume of the laterally extending cavity 43. In one embodiment, the metal layer 46B contains tungsten deposited on the tungsten nitride-containing diffusion barrier layer 46A by a two-step process, which includes a pretreatment step using a first B2H6 or silane (SiH4) gas to form a silicon- or boron-containing nucleation layer, and subsequently depositing a tungsten layer using tungsten hexafluoride or another suitable tungsten precursor in a second step. The tungsten precursor gas can also optionally be provided during the first step.

[0088] An anisotropic etching process can be performed to remove the metal layer 46B, the tungsten nitride-containing diffusion barrier layer 46A, and optionally portions of the backside barrier dielectric layer 45 and / or the alumina barrier dielectric layer 44 from within the volume of the lateral isolation trench 79 and above the contact-level dielectric layer 80. Each successive remaining portion of the combination of the metal layer 46B and the tungsten nitride-containing diffusion barrier layer 46A that is located within the volume of the corresponding laterally-extending cavity 43 constitutes a conductive layer 46. Each conductive layer 46 can be laterally spaced from the memory opening fill structure 58, the corresponding overlying dielectric layer in the dielectric layer 32, and the corresponding underlying dielectric layer in the dielectric layer 32 by a hafnium oxide- or zirconium oxide-containing backside barrier dielectric layer 45. Thereby, an alternating stack (32, 46) of the dielectric layer 32 and the conductive layer 46 is formed. The alternating stack (32, 46) of the dielectric layer 32 and the conductive layer 46 can be laterally spaced from each other by the lateral isolation trench 79 in a second horizontal direction hd2.

[0089] Reference Figure 11F , an alternative embodiment of the exemplary structure can be derived from the exemplary structure by omitting Figure 11B the step of forming the alumina barrier dielectric layer 44 as shown. In this case, the backside barrier dielectric layer 45 can be deposited directly on the memory opening fill structure 58 and on the horizontally-extending surface of the dielectric layer 32. After performing the processing steps described in Reference Figures 11C to 11E , each backside barrier dielectric layer 45 is in direct contact with the memory opening fill structure 58, the overlying dielectric layer in the dielectric layer 32, and the underlying dielectric layer in the dielectric layer 32.

[0090] At the processing step described in Reference Figure 11C , the backside barrier dielectric layer 45 formed can be divided into a plurality of backside barrier dielectric layers 45 located within a corresponding one of the laterally-extending cavities 43 in the laterally-extending cavity 43 during an etch-back process that removes the portion of the combination of the metal layer 46B and the tungsten nitride-containing diffusion barrier layer 46A that is located in the lateral isolation trench 79, or can remain as a single continuous backside barrier dielectric layer 45. Similarly, at the processing step described in Reference Figure 11B , the alumina barrier dielectric layer 44 formed can be divided into a plurality of alumina barrier dielectric layers 44 located within a corresponding one of the laterally-extending cavities 43 in the laterally-extending cavity 43 during an etch-back process that removes the portion of the combination of the metal layer 46B and the tungsten nitride-containing diffusion barrier layer 46A that is located in the lateral isolation trench 79, or can remain as a single continuous alumina barrier dielectric layer 44.

[0091] Reference Figure 12 , illustrates an exemplary structure after the processing steps of Figure 11E or after the processing steps of Figure 11F . Although for clarity, in Figure 12The optional alumina blocking dielectric layer 44 and the backside blocking dielectric layer 45 are not explicitly illustrated, but it should be understood that the optional alumina blocking dielectric layer 44 and the backside blocking dielectric layer 45 are present in the exemplary structure, such as Figure 11E and Figure 11F as shown.

[0092] Referring Figure 13A and Figure 13B , an insulating fill material can be conformally deposited in the lateral isolation trenches 79. The excess of the insulating fill material can be removed, for example, by a recess etching process from above the contact-level dielectric layer 80. Each remaining portion of the insulating fill material that fills the corresponding lateral isolation trench 79 constitutes an isolation trench fill structure 76. Alternatively, each isolation trench fill structure 76 can include a combination of a tubular insulating spacer (not explicitly shown) and a conductive connection via structure (not explicitly shown) laterally surrounded by the tubular insulating spacer. Generally speaking, the isolation trench fill structure 76 having insulating sidewalls extends vertically from the bottommost surface of the alternating stack (32, 46) to the topmost surface of the alternating stack (32, 46).

[0093] A photoresist layer (not shown) can be applied above the contact-level dielectric layer 80, and the photoresist layer can be lithographically patterned to form openings above each memory opening fill structure in the memory opening fill structure 58 above the horizontal extending surface of the stepped surface in the contact region. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80 and the inverse stepped dielectric material portion 65. A drain contact via cavity can be formed above the memory opening fill structure 58 through the contact-level dielectric layer 80. The layer contact via structure can be formed through the contact-level dielectric layer 80 and the inverse stepped dielectric material portion 65 on the top surface of a corresponding one of the conductive layers in the conductive layer 46. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0094] At least one conductive material (such as a combination of a metal barrier material and a metal fill material) can be deposited in the drain contact via cavity and the layer contact via cavity. The excess of at least one conductive material can be removed from above the horizontal plane including the top surface of the contact-level dielectric layer 80 by a planarization process, which can employ a recess etching process and / or a chemical mechanical polishing process. The remaining portion of at least one conductive material that fills the drain contact via cavity constitutes a drain contact via structure 88 on the top surface of a corresponding one of the drain regions in the contact drain region 63. The remaining portion of at least one conductive material that fills the layer contact via cavity constitutes a layer contact via structure 86 on the top surface of a corresponding one of the conductive layers of the contact conductive layer 46.

[0095] Referring Figure 14A and Figure 14B, a connection-level dielectric layer 90 may be formed over the contact-level dielectric layer 80. A connection via cavity may be formed through the connection-level dielectric layer 90 and may be filled with at least one conductive material (which may include at least one metal material) to form a connection-level via structure (98, 96). The connection-level via structure (98, 96) includes a drain connection via structure 98 of a corresponding one of the drain contact via structures in the contact drain contact via structure 88, and a layer connection via structure 96 of a corresponding one of the layer contact via structures in the contact layer contact via structure 86.

[0096] A bit-line-level dielectric layer 120 may be formed over the connection-level dielectric layer 90. A bit-line-level line cavity may be formed through the bit-line-level dielectric layer 120 and may be filled with at least one conductive material (which may include at least one metal material) to form a bit-line-level metal line (128, 126). The bit-line-level metal line may include a bit line 128 that extends laterally along a second horizontal direction hd2 and a bit-line-level interconnect metal line 126 (not shown separately) that may be used to provide an electrical connection to the layer connection via structure 96.

[0097] Reference Figure 15 , an additional dielectric material layer and an additional metal interconnect structure may be formed over the contact-level dielectric layer 80. The additional dielectric material layer may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line and via-level dielectric layer. The additional metal interconnect structure may include a metal via structure, a metal line structure, and / or an integrated metal line and via structure. The additional dielectric material layer formed over the contact-level dielectric layer 80 is referred to herein as a memory-side dielectric material layer 960. The additional metal interconnect structure is collectively referred to as the memory-side dielectric material layer 960. The memory-side dielectric material layer 960 includes a bit-line-level dielectric material layer that embeds the bit lines 128, and these bit lines are a subset of the memory-side metal interconnect structure 980.

[0098] A metal bonding pad (which is referred to herein as an upper bonding pad 988) may be formed at the topmost level of the memory-side dielectric material layer 960. The upper bonding pad 988 may be electrically connected to the memory-side metal interconnect structure 980 and various nodes of the three-dimensional memory array, which includes an alternating stack of an insulating layer 32 and a conductive layer 46 and a memory opening fill structure 58. Thus, a memory die 900 may be provided.

[0099] A memory - side dielectric material layer 960 is formed over the alternating stack (32, 46). A memory - side metal interconnect structure 980 is embedded in the memory - side dielectric material layer 960. A memory - side bonding pad 988 may be embedded within the memory - side dielectric material layer 960 and, in particular, within the top - most layer of the memory - side dielectric material layer 960. The memory - side bonding pad 988 may be electrically connected to the memory - side metal interconnect structure 980.

[0100] In one embodiment, the memory die 900 may include: a three - dimensional memory array including an alternating stack (32, 46) of insulating layers 32 and conductive layers 46; a two - dimensional array of memory openings 49 that vertically extend through the alternating stack (32, 46); and a two - dimensional array of memory - opening fill structures 58 located in the two - dimensional array of memory openings 49 and including corresponding vertical stacks of memory elements and corresponding vertical semiconductor channels 60; a two - dimensional array of drain - contact via structures 88 electrically connected to a respective one of the vertical semiconductor channels in the vertical semiconductor channels 60; and a two - dimensional array of layer - contact via structures 86 electrically connected to a respective one of the conductive layers 46, with a subset of the conductive layers serving as word lines of the three - dimensional memory array.

[0101] Generally speaking, the memory die 900 includes a memory array, a memory - side metal interconnect structure 980, and a memory - side bonding pad 988 embedded within the memory - side dielectric material layer 960. The memory die 900 includes memory devices that may include a three - dimensional memory array comprising an alternating stack of insulating layer 32 and conductive layer 46, and also includes a two - dimensional array of NAND strings (e.g., memory - opening fill structures 58) that vertically extend through the alternating stack (32, 46). In one embodiment, the conductive layer 46 includes word lines of the two - dimensional array of NAND strings. In one embodiment, the memory - side metal interconnect structure 980 includes bit lines 128 of the two - dimensional array of NAND strings.

[0102] Reference Figure 16 , a logic die 700 is provided. The logic die 700 includes peripheral circuits 720 formed on a logic - side substrate 709. According to one aspect of the present disclosure, the peripheral circuits 720 may be configured to control the operation of the memory array within the memory die 900. For example, the peripheral circuits 720 may include a word - line driver region, a bit - line driver region, a sense - amplifier region, an input / output buffer region, etc. A logic - side metal interconnect structure 780 embedded within the logic - side dielectric material layer 760 may be formed over the peripheral circuits 720. The logic die 700 includes a logic - side bonding pad 788 embedded within the logic - side dielectric material layer 760.

[0103] ReferenceFigure 17 , a bonded component can be formed by bonding the logic die 700 to the memory die 900. The logic die 700 can be attached to the memory die 900, for example, by bonding the logic-side bonding pads 788 to the memory-side bonding pads 988. The bonding between the memory die 900 and the logic die 700 can be performed using a wafer-to-wafer bonding process (in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700), by a die-to-bonding process, or by a die-to-die bonding process. The logic-side bonding pads 788 within each logic die 700 can be bonded to the memory-side bonding pads 988 within the corresponding memory die 900.

[0104] The logic die 700 can be attached to the memory die 900, for example, by bonding the logic-side bonding pads 788 to the memory-side bonding pads 988. The bonding between the memory die 900 and the logic die 700 can be performed using a wafer-to-wafer bonding process (in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700), by a die-to-bonding process, or by a die-to-die bonding process. The logic-side bonding pads 788 within each logic die 700 can be bonded to the memory-side bonding pads 988 within the corresponding memory die 900.

[0105] Reference Figure 18 , the carrier substrate 9 can be optionally removed, for example, by grinding, polishing, cleaving, an isotropic etching process, and / or an anisotropic etching process. If a polishing process such as a chemical mechanical polishing process is used to remove the carrier substrate 9, then the stop insulating layer 106 can be subsequently used as a polishing stop material layer. If an etching process such as a wet etching process is used to remove the carrier substrate 9, then the stop insulating layer 106 can be subsequently used as an etching stop material layer. Optional electrical contacts can be formed on the bottom side of the bonded component of the memory die 900 and the logic die 700.

[0106] Figure 19 An alternative configuration of an exemplary structure according to an alternative embodiment is illustrated. The alternative configuration of the exemplary structure can be provided by: forming a semiconductor device 620 on a semiconductor substrate 609, the semiconductor device including peripheral circuits for controlling the operation of a three-dimensional memory device; forming a metal interconnect structure 680 embedded in a dielectric material layer 660 on the semiconductor device 620, and then forming the structural elements described with reference to FIG. 7. In other words, a combination of the semiconductor substrate 609, the semiconductor device 620, the dielectric material layer 660, and the metal interconnect structure 680 can be used instead of the carrier substrate 9 and the stop insulating layer 106.

[0107] Reference Figure 20 , reference can be made toFigures 2 to 15 The described processing steps provide a memory die that may or may not be bonded to the logic die 700. In Figure 20 the case where the memory die is bonded to the logic die 700, the semiconductor device 620 may include a first subset of peripheral circuits for controlling the operation of the 3D memory device, and the logic die 700 may include a second subset of peripheral circuits for controlling the operation of the 3D memory device.

[0108] The tungsten nitride-containing diffusion barrier layer 46A is an excellent diffusion barrier and has a relatively low resistivity. For example, compared to a titanium nitride barrier layer, the tungsten nitride barrier layer and the tungsten boron nitride barrier layer provide excellent fluorine barrier capabilities. Specifically, if the metal layer 46B contains tungsten deposited using a tungsten hexafluoride precursor containing fluorine, the number of voids caused by fluorine in the dielectric layer of the memory device can be reduced by about 50% by using a tungsten nitride diffusion barrier layer compared to using a titanium nitride diffusion barrier layer. In addition, tungsten nitride has a lower resistivity than titanium nitride, which reduces the total resistivity of the conductive layer 46. However, compared to a titanium nitride diffusion barrier, the tungsten nitride diffusion barrier reduces the erase saturation of the memory device.

[0109] The inventors have recognized that using a high dielectric constant backside barrier dielectric layer 45 having a higher dielectric constant than alumina (such as a layer containing Hf oxide or Zr oxide) improves the erase saturation of the memory device.

[0110] Figure 21 is a graph illustrating the dependence of the threshold voltage on the erase voltage for various configurations of the backside barrier dielectric layer according to various embodiments. Compared to a first comparison device including a molybdenum conductive layer used with a TiN diffusion barrier and an alumina barrier dielectric, and compared to a second comparison device including a tungsten conductive layer used with a TiN diffusion barrier and an alumina barrier dielectric, the presence of a hafnium oxide backside barrier dielectric layer 45 (either alone or in combination with an alumina layer) between the molybdenum conductive layer 46 and the memory film 50 significantly improves the device erase saturation characteristics. Without wishing to be bound by a particular theory, it is believed that a high dielectric constant backside barrier dielectric (such as hafnium oxide or hafnium silicate, or zirconium oxide or zirconium silicate) improves charge carrier back tunneling suppression, which results in improved erase saturation.

[0111] Accordingly, the combination of the backside barrier dielectric layer 45 containing hafnium oxide or zirconium oxide and the tungsten nitride-containing diffusion barrier layer 46A has an unexpected synergistic effect. The tungsten nitride-containing diffusion barrier layer 46A improves fluorine diffusion barrier and reduces the resistivity of the conductive layer 46, but deteriorates the erase saturation of the memory device. In contrast, the backside barrier dielectric layer 45 containing hafnium oxide or zirconium oxide improves the erase saturation of the memory device and thus at least partially offsets the deterioration of the erase saturation caused by the tungsten nitride-containing diffusion barrier layer 46A. Accordingly, a memory device with low fluorine void-related faults, low conductive layer resistivity, and improved erase saturation is obtained.

[0112] Referring to all the drawings and according to various embodiments of the present disclosure, a three-dimensional memory device includes: an alternating stack of an insulating layer 32 and a conductive layer 46; a memory opening 49 that vertically extends through the alternating stack (32, 46); a memory opening filling structure 58 that is located in the memory opening 49; and a backside barrier dielectric layer 45 containing hafnium oxide or zirconium oxide. Each memory opening filling structure in the memory opening filling structure 58 includes a corresponding vertical stack of memory elements (e.g., a portion of the memory film 50) and a vertical semiconductor channel 60. Each conductive layer in the conductive layer 46 includes a metal layer 46B and a tungsten nitride-containing diffusion barrier layer 46A. The backside barrier dielectric layer 45 containing hafnium oxide or zirconium oxide is located between the tungsten nitride-containing diffusion barrier layer 46A and the memory opening filling structure 58.

[0113] In one embodiment, the tungsten nitride-containing diffusion barrier layer 46A contains tungsten nitride or boron nitride tungsten; the metal layer 46B contains tungsten, molybdenum, ruthenium, or cobalt; and the backside barrier dielectric layer 45 containing hafnium oxide or zirconium oxide contains hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium silicate, zirconium silicate, or hafnium zirconium silicate.

[0114] In one embodiment, each conductive layer in the conductive layer 46 is laterally spaced apart from the memory opening filling structure 58, the overlying insulating layer in the insulating layer 32, and the underlying insulating layer in the insulating layer 32 by a barrier dielectric layer 45 containing hafnium oxide or zirconium oxide.

[0115] In Figure 11E the illustrated embodiment, the backside barrier dielectric layer 45 containing hafnium oxide or zirconium oxide is spaced apart from the memory opening filling structure 58, the overlying insulating layer in the insulating layer 32, and the underlying insulating layer in the insulating layer 32 by an alumina backside barrier dielectric layer 44.

[0116] In Figure 11F the illustrated embodiment, the backside barrier dielectric layer 45 containing hafnium oxide or zirconium oxide is in direct contact with the memory opening filling structure 58, the overlying insulating layer in the insulating layer 32, and the underlying insulating layer in the insulating layer 32.

[0117] In one embodiment, the vertical stack of memory elements includes portions of the memory film 50, the memory film including a charge storage layer 54 located between a tunneling dielectric layer 56 and a front side blocking dielectric layer 52; and the memory element is configured to store data by electron storage in the charge storage layer 54, and the three-dimensional memory device does not store data by changing the ferroelectric polarization direction of the memory film.

[0118] Although the foregoing relates to specific preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art can envision that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the word "comprising" or "including" contemplates all embodiments in which the word "consisting essentially of" or the word "consisting of" replaces the word "comprising" or "including". Whenever two or more elements are listed as alternatives in the same paragraph or different paragraphs, a Markush group including the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb "able to" is used in the present disclosure to describe the formation of an element or the performance of a processing step, an embodiment in which such element or such processing step is not performed is also clearly contemplated, provided that the resulting device or apparatus is able to provide an equivalent result. Thus, whenever the formation of such element or such processing step is omitted and able to provide the same result or an equivalent result, the auxiliary verb "able to" as applied to the formation of an element or the performance of a processing step should also be construed as "may" or "may, or may not", these equivalent results including slightly superior results and slightly inferior results. In cases where embodiments employing a specific structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise known to be impossible to those of ordinary skill in the art. If publications, patent applications, and / or patents are cited herein, each such document is incorporated herein by reference in its entirety.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: An alternating stack of insulating layers and conductive layers; Memory openings that vertically extend through the alternating stack; Memory opening fill structures located in the memory openings: and A backside barrier dielectric layer containing hafnium oxide or zirconium oxide; Wherein: Each memory opening fill structure in the memory opening fill structures includes a corresponding vertical stack of memory elements and a vertical semiconductor channel; Each conductive layer in the conductive layers includes a metal layer and a diffusion barrier layer containing tungsten nitride; and The backside barrier dielectric layer containing hafnium oxide or zirconium oxide is located between the diffusion barrier layer containing tungsten nitride and the memory opening fill structures.

2. The three-dimensional memory device according to claim 1, wherein each conductive layer in the conductive layers is laterally spaced apart from the memory opening fill structures, the overlying insulating layer in the insulating layers, and the underlying insulating layer in the insulating layers by the barrier dielectric layer containing hafnium oxide or zirconium oxide.

3. The three-dimensional memory device according to claim 1, wherein the diffusion barrier layer containing tungsten nitride comprises tungsten nitride.

4. The three-dimensional memory device according to claim 1, wherein the diffusion barrier layer containing tungsten nitride comprises boron tungsten nitride.

5. The three-dimensional memory device according to claim 1, wherein the metal layer comprises tungsten, molybdenum, ruthenium, or cobalt.

6. The three-dimensional memory device according to claim 5, wherein the metal layer consists essentially of tungsten.

7. The three-dimensional memory device according to claim 1, wherein the backside barrier dielectric layer containing hafnium oxide or zirconium oxide comprises hafnium oxide.

8. The three-dimensional memory device according to claim 1, wherein the backside barrier dielectric layer containing hafnium oxide or zirconium oxide comprises zirconium oxide.

9. The three-dimensional memory device according to claim 1, wherein the backside barrier dielectric layer containing hafnium oxide or zirconium oxide comprises hafnium zirconium oxide.

10. The three-dimensional memory device according to claim 1, wherein the backside barrier dielectric layer containing hafnium oxide or zirconium oxide comprises hafnium silicate.

11. The three-dimensional memory device according to claim 1, wherein the backside barrier dielectric layer containing hafnium oxide or zirconium oxide comprises zirconium silicate.

12. The three-dimensional memory device according to claim 1, wherein the backside barrier dielectric layer containing hafnium oxide or zirconium oxide comprises hafnium zirconium silicate.

13. The three-dimensional memory device according to claim 1, the three-dimensional memory device further comprising an alumina backside barrier dielectric, wherein the backside barrier dielectric layer containing hafnium oxide or zirconium oxide is spaced apart from the memory opening fill structures, the overlying insulating layer in the insulating layers, and the underlying insulating layer in the insulating layers by the alumina backside barrier dielectric layer.

14. The three-dimensional memory device according to claim 1, wherein the backside barrier dielectric layer containing hafnium oxide or zirconium oxide is in direct contact with the memory opening fill structures, the overlying insulating layer in the insulating layers, and the underlying insulating layer in the insulating layers.

15. The three-dimensional memory device according to claim 1, wherein: The vertical stack of memory elements includes portions of a memory film that includes a charge storage layer located between a tunneling dielectric layer and a front-side blocking dielectric layer; And The memory elements are configured to store data by electron storage in the charge storage layer, and the three-dimensional memory device does not store data by changing the ferroelectric polarization direction of the memory film.

16. A method of forming a three-dimensional memory device, the method comprising: Forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate; Forming a memory opening that vertically extends through the alternating stack; Forming a memory opening fill structure in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a corresponding vertical stack of memory elements and a vertical semiconductor channel; Forming a laterally extending cavity by selectively removing the sacrificial material layer relative to the insulating layer and the memory opening fill structure; Forming a back-side blocking dielectric layer containing hafnium oxide or zirconium oxide in the laterally extending cavity; Forming a diffusion barrier layer containing tungsten nitride on the back-side blocking dielectric layer containing hafnium oxide or zirconium oxide in the laterally extending cavity; And Forming a metal layer on the diffusion barrier layer containing tungsten nitride in the laterally extending cavity.

17. The method according to claim 16, wherein: The diffusion barrier layer containing tungsten nitride contains tungsten nitride or boron nitride tungsten; The metal layer contains tungsten, molybdenum, ruthenium, or cobalt; and The back-side blocking dielectric layer containing hafnium oxide or zirconium oxide contains hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium silicate, zirconium silicate, or hafnium zirconium silicate.

18. The method according to claim 16, wherein: The vertical stack of memory elements includes portions of a memory film that includes a charge storage layer located between a tunneling dielectric and a front-side blocking dielectric layer; And The memory elements are configured to store data by electron storage in the charge storage layer, and the memory device does not store data by changing the ferroelectric polarization direction of the memory film.

19. The method according to claim 16, the method further comprising depositing an alumina back-side blocking dielectric layer in the laterally extending cavity, wherein the back-side blocking dielectric layer containing hafnium oxide or zirconium oxide is deposited on the alumina blocking dielectric layer exposed to the laterally extending cavity.

20. The method according to claim 16, wherein the back-side blocking dielectric layer containing hafnium oxide or zirconium oxide is directly deposited on the memory opening fill structure and on a horizontally extending surface of the insulating layer exposed to the laterally extending cavity.

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