Semiconductor device and production method

Abstract

In one embodiment, a semiconductor device (1) comprises:-a gate electrode (33); -a first semiconductor region (21) of a first conductivity type at a top side (20) of the semiconductor body (2); a plug region (24) of the second conductivity type; a first electrode (31) in electrical contact with the first semiconductor region (21) and the plug region (24); a well region (23) of the second conductivity type; and-at least one barrier region (41, 42) comprising a first barrier region (41) in the semiconductor body (2), wherein-the well region (23) is located between the first barrier region (41) and the first semiconductor region (21); -the first barrier region (41) is a barrier for charge carriers of the second conductivity type; -the first electrode (31) extends deeper or as deep as the first semiconductor region (21) into the semiconductor body (2) in the direction towards the first barrier region (41).

Description

Technical Field

[0001] A semiconductor device is provided. Further, a method of manufacturing such a semiconductor device is also provided. Background Art

[0002] The literature "Dielectric Barrier IGBT with Extreme Injection Enhancement" by M. Takei et al. (see the 22nd International Symposium on Power Semiconductor Devices and ICs (ISPSD) 2010, 2010, pp. 383 - 386) mentions injection enhancement. Summary of the Invention

[0003] The problem to be solved is to provide a semiconductor device having improved electrical performance.

[0004] This object is achieved in particular by the semiconductor device and method defined in the independent patent claims. Exemplary further improvements form the subject matter of the dependent claims.

[0005] For example, the semiconductor device described herein includes a first blocking region in a semiconductor body. At least a part of a well region is located between the first blocking region and a first semiconductor region, and the first blocking region is a blocking portion for carriers of at least one conductivity type. At least one plug region or a first electrode extends deeper into the semiconductor body in a direction towards the first blocking region than the first semiconductor region. With such a first blocking layer, a relatively low production cost can be maintained while achieving an improvement in the saturation voltage V between the collector and the emitter or between the source and the drain ce-sat and also enabling better long - term device reliability.

[0006] For example, the semiconductor body is made of silicon (Si). However, the semiconductor body can alternatively be made of a wide - bandgap semiconductor material such as SiC, Ga2O3, or GaN.

[0007] For example, the semiconductor device is a metal - insulator - semiconductor field - effect transistor (MISFET), a metal - oxide - semiconductor field - effect transistor (MOSFET), an insulated - gate bipolar transistor (IGBT), a reverse - conducting insulated - gate bipolar transistor (RC - IGBT), a bipolar junction transistor (BJT), a thyristor, a gate - turn - off thyristor (GTO), a gate - commutated thyristor (GCT), or a junction - gate field - effect transistor (JFET).

[0008] For example, a semiconductor device is a power device. For example, the semiconductor device is configured such that the maximum voltage between the source or emitter electrode and the drain or collector is at least 0.2 kV or at least 0.6 kV or at least 1.2 kV. Alternatively or additionally, the semiconductor device is configured such that the current between the source or emitter and the drain or collector is at least 0.01 kA or at least 0.1 kA or at least 1 kA and / or at most 100 kA or at most 10 kA. That is, by means of the gate electrode and by having a corresponding voltage between the first electrode and the second electrode, the flow of current through the semiconductor device can be controlled. In particular, the flow of current can be conducted or interrupted by turning on or off the voltage at the gate electrode.

[0009] Therefore, it is feasible that the semiconductor device is a semiconductor chip or a semiconductor wafer, and can be any type of IGBT or MISFET.

[0010] The semiconductor device is, for example, a power module for converting direct current from a battery into alternating current for an electric motor, which is, for example, in a vehicle such as a hybrid vehicle or a plug-in electric vehicle or in rail traffic such as a commuter train.

[0011] In at least one embodiment, the semiconductor device comprises:

[0012] - a gate electrode at the top side of the semiconductor body;

[0013] - a first semiconductor region of a first conductivity type at the top side, which is a source region or an emitter region;

[0014] - optionally, a plug region of a second conductivity type;

[0015] - a first electrode in electrical contact with the first semiconductor region and the plug region, and can thus be an emitter electrode or a source electrode;

[0016] - a well region of a second conductivity type, in which the first semiconductor region is at least partially embedded; and

[0017] - at least one blocking region comprising a first blocking region that is at least partially within the semiconductor body,

[0018] wherein

[0019] - at least a part of the well region is located between the first blocking region and the first semiconductor region;

[0020] - the first blocking region is a blocking portion for carriers of at least the second conductivity type; and

[0021] - at least one plug region or the first electrode extends deeper or equally deep into the semiconductor body in the direction of the first blocking region than the first semiconductor region.

[0022] The fact that the plug region and / or the first electrode extend into the semiconductor body means that, for example, the plug region and / or the first electrode extend deeper into the semiconductor body in a direction away from the top side. In other words, the plug region and / or the first electrode extend from the top side of the semiconductor body to the back side, and for example, a second electrode is applied to the back side portion, which can be a drain electrode or a collector electrode. That is to say, the plug region and / or the first electrode partially penetrate the semiconductor body. Therefore, the depth of the plug region and / or the first electrode is greater than the depth of the first semiconductor region.

[0023] For example, the present device relates to planar IGBT technology. Specifically, a planar IGBT design is described in which the vertical path of holes at the emitter contact (emitter contact) existing in the reference IGBT design is blocked by at least one blocking region. The at least one blocking region can be or include a dielectric or a highly doped n-layer, forcing the holes to flow parallel to the electron channel formed at the gate oxide interface and leave the device at the side emitter contact, thereby increasing the plasma concentration in this region and generating a strong injection enhancement effect, and finally obtaining a significantly improved technical curve. This design can be regarded as a functional equivalent of a finely patterned trench IGBT rotated 90° (in a cross-sectional view).

[0024] Recently, trench IGBTs have been considered a more preferred design choice compared to planar IGBTs to a large extent due to their excellent conduction performance and improved trade-off between the turn-off energy E off and V ce-sat in the technical curve. The trench IGBT design benefits from its excellent plasma profile, which results from the closely spaced vertical flow of electrons and holes near the emitter, generating an injection enhancement effect. By shortening the length L pcont of the emitter contact, or in other words, by reducing the distance between adjacent trenches, the plasma profile of the IGBT in the trench structure and thus its conduction performance can be further improved.

[0025] In contrast, in a conventional planar IGBT structure, electrons injected from the planar channel force holes to enter laterally near the edge of the emitter contact. Therefore, in a conventional planar IGBT design, the plasma profile and V ce-sat cannot be improved as simply as in a trench device by shortening the emitter contact length. However, planar IGBTs offer other advantages, such as better long-term reliability (i.e., device lifetime) and strong service-oriented architecture performance compared to trench designs, as well as a less complex and thus cheaper production process.

[0026] Accordingly, it is desirable to design electron and hole flow in a planar design in a way that achieves the same or even improved on-state performance while retaining the original advantages of the planar design. In short, a new IGBT design that combines the advantages of both (i.e., trench design and planar design) is desired.

[0027] Previously, the dielectric barrier (DB)-IGBT proposed by Takei et al. partially achieved this goal by introducing a dielectric layer as a barrier for the hole path towards the emitter contact. However, in their design, holes are extracted three-dimensionally from the p + region between the n-source regions. This has two drawbacks with respect to the semiconductor device described herein: (i) it fundamentally reduces the injection enhancement effect; and (ii) the minimum achievable emitter contact width required to maximize the injection enhancement effect is limited by lithography technology.

[0028] In the semiconductor device described herein (referred to herein as a trench-like planar insulated gate bipolar transistor, TLP-IGBT), it is also proposed to use a blocking layer to block the vertical path of holes and instead redirect the holes to flow parallel to the electron channel, but the holes will leave via, for example, a lateral emitter contact. This feature allows for further improvement of the injection enhancement effect by reducing the lateral emitter contact size (such as L pcont ) and achieving enhanced on-state performance and characteristics similar to those of a device designed according to the trench design.

[0029] Furthermore, different from in a device designed according to a reference trench design, the design described herein enables the realization of a true point-contact emitter device by reducing the vertical dimension L pcont without being limited by any lithography technology. In addition, it is proposed to stack multiple such units along the vertical dimension, similar to the lateral stacking of trench units, to further improve performance. Furthermore, at least one blocking layer is not limited to a dielectric material and can also be a semiconductor layer, such as n + Si.

[0030] In short, compared with the reference planar technology platform, the introduction of the above features brings significantly improved on-state losses and characteristics, making it a potential candidate for the next-generation new planar IGBT technology applicable to both low-voltage platforms and high-voltage platforms.

[0031] According to at least one embodiment, the semiconductor device includes a plug region of a second conductivity type. With the aid of the plug region, electrical contact can be made with the well region, in particular via a first electrode.

[0032] If there is no dedicated plug region, the well region itself can also serve the function of the plug region, i.e., making electrical contact with the first semiconductor region. That is to say, the plug region can be integrated in the well region.

[0033] According to at least one embodiment, for example, as visible in a top view, the plug region extends entirely along the first semiconductor region and / or the gate electrode. For example, the plug region extends entirely along the first semiconductor region and partially or completely overlaps the first semiconductor region. In other words, the first semiconductor region may partially or completely cover the plug region such that the first semiconductor region is directly between the plug region and the top side. Alternatively or additionally, in the top view, the plug region may extend along the first semiconductor region on a side away from the gate electrode. In other words, as visible in the top view of the top side, at least a portion of the plug region is located beside the first semiconductor region, and the first semiconductor region is located between the gate electrode and the plug region. In such a configuration, the top side may be partially formed by the plug region.

[0034] According to at least one embodiment, the first electrode is in direct contact with the first blocking region. That is, the first electrode extends into the semiconductor body up to the first blocking region, or into the first blocking region, or even through the first blocking region. In addition, the first electrode may terminate away from the first blocking region. For example, in a direction perpendicular to the top side, the distance between the first blocking region and the first electrode is at least 0.1 μm and / or at most 0.5 μm.

[0035] It is feasible that the first blocking region extends parallel to the top side. For example, in a cross-sectional view, the length of the first blocking region exceeds the thickness of the first blocking region by at least five times, or at least ten times, and / or at most 50 times. This may apply starting from the symmetry plane of the first electrode contact region.

[0036] According to at least one embodiment, the plug region is in direct contact with the first blocking region. That is, the plug region extends into the semiconductor body up to the first blocking region, or into the first blocking region, or even through the first blocking region. In addition, the plug region may terminate away from the first blocking region. For example, in a direction perpendicular to the top side, the distance between the first blocking region and the plug region is at least 0.1 μm, or at least 0.5 μm, and / or at most 2 μm.

[0037] According to at least one embodiment, the first blocking region is completely covered by the semiconductor body on a side of the first blocking region facing the first semiconductor region. This applies, for example, in at least one cross-section perpendicular to the top side through the semiconductor body. For example, between adjacent first semiconductor regions, the first blocking region is completely covered by the well region and / or the plug region. That is, the first electrode may cover the top surface of the plug region exposed from the source region such that the area ratio of the plug region extending obliquely to the top side and being contacted by the first electrode is non-existent or insignificant.

[0038] According to at least one embodiment, the first blocking region is constituted by or includes one or more doped blocking layers. For example, at least one of the doped blocking layers is of the first conductivity type.

[0039] According to at least one embodiment, the first blocking region is constituted by or includes one or more dielectric layers. It is feasible that different dielectric materials are combined to form the first blocking region.

[0040] For example, at least one of the dielectric layers is made of at least one of the following materials: SiO2, Si3N4, Al2O3, Y2O3, ZrO2, HfO2, La2O3, Ta2O5, TiO2. Thus, the gate insulation can also be referred to as an oxide layer. The same material can be selected for all other electrical insulation layers in the semiconductor device.

[0041] According to at least one embodiment, the semiconductor body further includes a drift region of the first conductivity type. For example, the drift region is directly adjacent to the well region and / or the first blocking region. The drift region can be directly located at the gate insulation layer.

[0042] According to at least one embodiment, in a direction parallel to the top side, the first blocking region extends into the drift region. For example, the first blocking region terminates in the drift region, especially outside the well region.

[0043] According to at least one embodiment, the first blocking region protrudes into the drift region from the well region by a protrusion length. The drift region can protrude from the well region along a direction parallel to the top side and / or away from the first electrode, and thus also from the first semiconductor region. For example, the protrusion length is at least 10% or 30% or 50% of the width of the well region and / or the source region along the same direction. Alternatively or additionally, the protrusion length is at most 300% or 200% or 150% of the width of the well region and / or the source region along the same direction.

[0044] According to at least one embodiment, the first blocking region separates the drift region from the well region and / or the plug region in a direction perpendicular to the top side. Thus, there may be no direct connection between the drift region and the well region and / or the plug region along said direction.

[0045] According to at least one embodiment, the first blocking region includes one or more openings. The at least one opening can extend completely through the first blocking region. Thus, in the at least one opening, the semiconductor body, such as the drift region, can be exposed from the first blocking region.

[0046] According to at least one embodiment, in a top view of the top side, the at least one opening is located beside the first semiconductor region and / or the well region and / or the plug region. Thus, in the top view of the top side, the at least one opening can be away from the first semiconductor region and / or the well region and / or the plug region.

[0047] According to at least one embodiment, the semiconductor device further includes one or more second blocking regions. At least one second blocking region is located in the semiconductor body between the first blocking region and the first semiconductor region. For example, at least one second blocking region is remote from the first blocking region and the first semiconductor region. At least one second blocking region is a blocking portion through the semiconductor body for carriers of at least a second conductivity type.

[0048] According to at least one embodiment, at least one of the plug region or the first electrode extends along at least one second blocking region toward the first blocking region. Thus, the plug region or the first electrode can extend entirely along at least one second blocking region in a direction perpendicular to the top side, starting from the top side for example.

[0049] According to at least one embodiment, at least one second blocking region includes a conductive layer that is electrically insulated from the semiconductor body by an additional dielectric layer. Thus, at least one second blocking region can adopt a multilayer design.

[0050] According to at least one embodiment, the number of the second blocking regions is at least one and at most ten. For example, the number of the second blocking regions is at least two and at most eight, or the number of the second blocking regions is at least two and at most five.

[0051] According to at least one embodiment, the conductive layer is in electrical contact with the gate electrode or the first electrode. Thus, at least one second blocking region can correspondingly correspond to an active MOS cell or a dummy MOS cell in a trench design device.

[0052] According to at least one embodiment, at least one additional first semiconductor region of at least a first conductivity type is in direct contact with at least one second blocking region on at least one main side of the second blocking layer. The at least one additional first semiconductor region and the corresponding main side can be oriented parallel to the top side. It is feasible that such an additional first semiconductor region is directly on two main sides of the corresponding second blocking region.

[0053] It is feasible that there is at least one second blocking region having at least one additional first semiconductor region, and there can be at least one second blocking region that does not have any designated additional first semiconductor region, or has only one designated additional first semiconductor region. For example, a second blocking region that does not have any designated additional first semiconductor region or has only one designated additional first semiconductor region is the lowermost second blocking region, i.e., the second blocking region farthest from the top side, or an intermediate second blocking region located between the first blocking region and another second blocking region closer to the top side.

[0054] According to at least one embodiment, the semiconductor body further includes, for example, a second semiconductor region at a bottom side portion opposite to the top side. The second semiconductor region can be a drain region of a first conductivity type or can be a collector region of a second conductivity type. Accordingly, the semiconductor device can be a field effect transistor or an insulated gate bipolar transistor, respectively.

[0055] A method of manufacturing a semiconductor device is also provided. By means of this method, a semiconductor device as described in at least one of the above embodiments can be produced. Accordingly, the features of the semiconductor device are also disclosed for this method and vice versa.

[0056] In at least one embodiment, the method is for manufacturing a semiconductor device. The method includes the following steps, for example, in the order stated:

[0057] A) Providing at least a portion of a semiconductor body;

[0058] B) Forming a first blocking region on at least a portion of the semiconductor body; and

[0059] C) Applying a first electrode and a gate electrode to the semiconductor body.

[0060] Between method steps B) and C), additional method steps can exist, such as overgrowing the first blocking region. Further optional steps can be forming at least a second blocking region and an electrically insulating layer before applying the electrodes.

[0061] According to at least one embodiment, the method further includes one or some or all of the following steps, for example, between steps B) and C), where only a first portion of the semiconductor body is provided in step A):

[0062] B1) Forming a second portion of the semiconductor body above the first blocking region, for example, by using selective silicon epitaxy, and / or

[0063] B2) Creating a first semiconductor region and a plug region in the second portion, for example, by ion implantation or in-situ doping during the growth of the second portion, and / or

[0064] B3) Forming a gate insulating layer (53) on top of the second portion, and / or

[0065] B4) Etching through the second portion down to the first blocking region, for example, by using a mask layer on the semiconductor body.

[0066] It is feasible to perform steps B1 to B4 in the order stated. Description of the Drawings

[0067] The semiconductor devices and methods described herein will be explained in more detail below with reference to the accompanying drawings. Identical elements in the various figures are denoted by the same reference numerals. However, the relationships between the elements are not shown to scale, and individual elements may be exaggerated for ease of understanding.

[0068] In the figures:

[0069] Figure 1 is a schematic cross-sectional view of an embodiment of the semiconductor device described herein;

[0070] Figure 2 and Figure 3 is a schematic cross-sectional view of a reference device;

[0071] Figures 4 to 11 is a comparison of the electrical performance between an embodiment of the semiconductor device described herein and the reference device;

[0072] Figure 12 is a schematic perspective view of an embodiment of the semiconductor device described herein;

[0073] Figure 13 is a schematic top view of a semiconductor body for an embodiment of the semiconductor device described herein;

[0074] Figure 14 and Figure 15 is a schematic cross-sectional view of an embodiment of the semiconductor device described herein;

[0075] Figure 16 is a comparison of the electrical performance between an embodiment of the semiconductor device described herein and the reference device;

[0076] Figures 17 to 21 is a schematic cross-sectional view of an embodiment of the semiconductor device described herein;

[0077] Figure 22 and Figure 23 is a schematic block diagram of an embodiment of a method for manufacturing the semiconductor device described herein;

[0078] Figures 24 to 35 is a schematic cross-sectional view of a method step for manufacturing the semiconductor device described herein;

[0079] Figure 36 is a schematic sectional view of an embodiment of the semiconductor device described herein. Detailed Description

[0080] In Figure 1In the figure, an embodiment of a semiconductor device 1 is shown. The semiconductor device 1 includes a semiconductor body 2, which is based on, for example, Si or SiC. In the semiconductor body 2, there is a drift region 25, which is, for example, weakly n-type doped. Embedded in the drift region 25 is a well region 23, which is, for example, moderately p-type doped. Next to the well region 23, there may be a plug region 24, which is, for example, heavily p-type doped. On the top side 20 of the semiconductor body 2 and also embedded in the well region 23 is a first semiconductor region 21. For example, the first semiconductor region 21 is heavily n-type doped.

[0081] For example, the semiconductor device 1 is an IGBT. Thus, at the bottom side of the semiconductor body 2 opposite to the top side 20, that is, at the bottom of the drift region 25, there is a second semiconductor region 22, which is a collector region and is, for example, heavily p-type doped; thus, the first semiconductor region 21 is an emitter region. Additionally, as an option, there may be a buffer region 28, which has the same conductivity type as the emitter region but is less heavily doped than the collector region and may have a doping concentration higher than that of the drift region 25. The buffer region 28 may be directly located between the second semiconductor region 22 and the drift region 25, for example, as a continuous, uninterrupted layer with a constant thickness, like the second semiconductor region 22 itself.

[0082] Conversely, if the semiconductor device 1 is not an IGBT but a MISFET or MOSFET, then the first semiconductor region 21 is a source region, and thus the second semiconductor region 22 is a drain region with the same conductivity type as the source region.

[0083] For example, the maximum doping concentration of the first semiconductor region 21, the second semiconductor region 22, and at least one plug region 24 is at least 1x10 18 cm -3 or at least 5x10 18 cm -3 or at least 1x10 19 cm -3 and / or at most 5x10 20 cm -3 or at most 2x10 20 cm -3 or at most 1x10 20 cm -3 . Further, the maximum doping concentration of the well region 23 and / or the buffer region 28 may be at least 5x10 15 cm -3 or at least 1x10 17 cm -3 and / or at most 5x10 19 cm -3 or at most 5x1018 cm -3 。

[0084] Depending on the voltage level of the semiconductor device 1, the maximum doping concentration of the drift region 25 can be at least 1×10 11 cm -3 or at least 1×10 12 cm -3 or at least 1×10 13 cm -3 and / or at most 1×10 17 cm -3 or at most 5×10 16 cm -3 or at most 1×10 16 cm -3 。

[0085] Furthermore, the semiconductor device 1 includes a first blocking region 41. In the intended use of the semiconductor device 1, the first blocking region 41 cannot be penetrated by holes at least.

[0086] At the top side 20, there is a gate insulating layer 53 (similar to a gate oxide) and a gate electrode 33. The gate electrode 33 is located at the flat top side 20 and is mainly located on top of the drift region 25. Next to the well region 23, the thickness of the gate insulating layer 53 is, for example, between 50 nm and 250 nm or between 80 nm and 150 nm. On top of the gate electrode 33, there is a first electrode insulating layer 51 that separates the gate electrode 33 from the first electrode 31.

[0087] It is feasible that the first electrode 31 directly contacts the first semiconductor region 21 and the lateral sides of the well region 23 or the plug region 24. The contact length between the first electrode 31 and the well region 23 and / or the plug region 24 is referred to as L pcont 。For example, L pcont is at least 50 nm and / or at most 10 μm or at most 0.5 μm or at most 0.2 μm. The first electrode 31 also contacts the first semiconductor region 21. The thickness of the first semiconductor region 21 is, for example, at least 50 nm and / or at most 0.5 μm. For example, the first electrode 31 only contacts the semiconductor body 2 at the lateral sides of the regions 21, 23, 24 and does not contact or has an insignificant contact at the top side 20. The lateral sides can extend perpendicular to the top side 20 and, for example, have a tolerance of at most 30° or at least 15°.

[0088] In Figure 1 only a part of the semiconductor device 1 is shown. Therefore, there can be a symmetry plane S, and this part of the semiconductor device 1 is mirrored on the symmetry plane S and extends correspondingly. There can be multiple such mirror elements in the semiconductor device 1, such that in Figure 1In the drawings, it is possible that only half of a unit cell is shown in cross section.

[0089] For example, the first barrier region 41 extends parallel to the top side 20. The length L of the first barrier region 41 of half of the element unit is shown. B In the x-direction, for example, the thickness T of the first barrier region 41 is at least 2 μm or at least 5 μm, and / or at most 20 μm or at most 12 μm. Alternatively or additionally, the thickness T of the first barrier region 41 in the y-direction is B At least 0.1 μm or at least 0.3 μm, and / or at most 5 μm or at most 2 μm, or at most 1 μm. Possibly 0.2 T B ≤L pcont ≤T B or 0.5T B ≤L pcont ≤2T B or 0.8T B ≤L pcont ≤1.2T B .

[0090] In the x-direction, the first barrier region 41 protrudes from the well region 23 into the drift region 25, and the protrusion length is P. For example, the protrusion length P is at least 25% or 50% of the length of the well region 23 and the plug region 24 in the x-direction. Additionally or alternatively, the protrusion length P is at most 300% or 150% of the length of the well region 23 and the plug region 24 in the x-direction.

[0091] By virtue of the first barrier region 41 , the main flow Fe of electrons is antiparallel to the main flow Fh of holes passing by the gate electrode 33 of the well region 23 .

[0092] exist Figure 2 In FIG. 1 , a reference device 91 of planar design is shown. The reference device 91 corresponds largely to Figure 1 The semiconductor device 1 of FIG. 1 is a semiconductor device 1 having a first barrier region, but without the first barrier region. Therefore, the first electrode 31 does not extend significantly into the semiconductor body 2 towards the drift region 25, but is only applied on the top side 20 or extends only slightly into the semiconductor body 2, for example, at most to 1.5 times the thickness of the first semiconductor region 21. Therefore, L pcont Greater than Figure 1 The semiconductor device 1 in FIG. 1 is a semiconductor device 1 in FIG. 1 , and each half element unit reaches about 3 μm.

[0093] exist Figure 3 , a trench design reference device 92 is shown. Thus, the gate electrode 33 is accommodated in the trench and once again the first electrode 31 is located on the top side 20 or extends only slightly into the semiconductor body 2.

[0094] As described above, the trench IGBT design 92 benefits from its excellent plasma distribution. By reducing L pcont , the IGBT plasma distribution and its conduction performance in the trench structure can be improved. In the planar IGBT structure 91, the injected electrons and holes follow different paths, as Figure 2 very schematically illustrated. Therefore, the plasma distribution and V ce-sat cannot be simply improved by reducing L pcont as in the trench device 92. Figure 4 This is illustrated, where the effect of the scaling of L pcont on V ce-sat is shown.

[0095] As Figure 2 shown, different from the trench device 62, it is not feasible to achieve a strong injection enhancement effect in the planar design 91 only by reducing the emitter contact length L pcont . To achieve this, it is important to have a device structure in which most of the holes enter the emitter contact vertically. In the planar design, this can be achieved by blocking the main vertical path of the holes by the first blocking region 41 (which can be a dielectric layer or a highly doped n + layer), and thus redirecting the holes to flow laterally along the electron channel and leave the emitter vertically via the side contact 31, as Figure 1 shown.

[0096] In such a way, a strong injection enhancement effect can be generated, which can be further enhanced by reducing the thickness L pcont towards the point contact emitter device. This design can be regarded as a functionally equivalent design of a finely patterned trench IGBT rotated 90°, which can be actually implemented with almost no lithography limitations.

[0097] The proposed TLP-IGBT design 1 was explored by means of TCAD simulation to understand its operation and further compare its performance advantages relative to the reference planar IGBT cell 91. Figure 1 A schematic cross-section of the TLP-IGBT cell used for 2D-TCAD simulation is shown, and Figure 2 the corresponding reference planar IGBT cell 91 is shown. As Figure 1 indicated exemplary, the hole current flows in a reverse parallel direction to the electron current and leaves the device 1 at the small side emitter contact region, thus generating the desired strong injection enhancement effect.

[0098] Therefore, in Figure 5 and Figure 6 shown Figure 1Output characteristics I of the TLP-IGBT 1 ce versus V ce and its comparison with the reference planar IGBT design 91, where Figure 5 V in ce ranges from 0 V to 3 V, Figure 6 V in ce ranges from 0 V to 25 V. Thus, Figure 5 and Figure 6 compare the on-state performance of the TLP-IGBT 1 with that of the reference device 91. As expected, at the nominal current level I nom of 62.5 A, compared with the V ce-sa t of the reference IGBT design 91, the V pcont of the TLP-IGBT 1 with L ce-sat = 750 nm shows a significant improvement (about 580 mV improvement). When L pcont is scaled down to 110 nm, the gain in V ce-sat increases by ~830 mV. This confirms that a strong injection enhancement is achieved in the TLP-IGBT structure 1 compared with the reference planar IGBT 91.

[0099] See Figure 7 and Figure 8 , it is also noted from the transfer characteristics that the threshold voltage V th and the sub-threshold characteristics of the TLP-IGBT cell 1 are hardly affected compared with the reference device 91.

[0100] In addition, Figure 9 shows the blocking voltage characteristics I ge of the TLP-IGBT 1 using an oxide as the first blocking region and the reference design 91 at 398 K, V c versus V ce .

[0101] Figure 10 shows the turn-off switching waveform of the TLP-IGBT device 1 at 298 K and its comparison with the reference device 91. The turn-off switching mode of the TLP-IGBT 1 is similar to that of the planar reference device 91. However, its trade-off relationship between E off and V ce-sat is significantly improved, as shown in the technical curve graph in Figure 11 . For the same turn-off loss E off , the TLP-IGBT 1 shows an increase in the on-state by about 400 mV (about 16%); alternatively, for the same V ce-sat , E off is reduced by about 90 mJ (about 32%). When L pcontWhen scaled down to 110 nm, the technology curve further shifts to the left, that is, towards the point emitter contact IGBT.

[0102] The improvement of these process curves is mainly observed because for a given V ce-sat improvement, the increase ratio of E off is relatively small. This is attributed to the achievement of a good plasma distribution in TLP-IGBT 1, with an enhanced plasma concentration near the emitter, where the high electric field results in the effective and timely removal of holes during the turn-off transient.

[0103] In Figure 12 Another embodiment of the semiconductor device 1 is shown in perspective view. The first semiconductor region 21 and regions 23, 24 extend entirely along the z direction perpendicular to the xy plane without intended variations. It should be noted that the first electrode 31 is shown in a simplified manner to better illustrate regions 21, 23, 24, but in reality it covers the sides of these regions 21, 23, 24, as shown for example in Figure 1 or Figure 14 as shown.

[0104] The first blocking region 41 is constituted by the dielectric layer 44. However, a multi-layer design of the first blocking region 41 is also alternatively feasible.

[0105] As an option, the first semiconductor region 21 can be segmented along the z direction, see Figure 13 . That is, parallel to the gate electrode 33 not shown in Figure 13 , the blocks of the first semiconductor region 21 can alternate with the blocks of the well region 23 and / or the plug region 24.

[0106] In addition to this, the same content as that of the device 1 in Figure 1 can also be applied to Figure 12 and Figure 13 , and vice versa.

[0107] According to Figure 14 , along the lateral x direction and away from the drain region 25, the optional plug region 24 and / or well region 23 protrude from the first semiconductor region 21. That is, the optional plug region 24 and / or well region 23 can be electrically contacted from the top side 20, not only from the lateral sides like the first semiconductor region 21.

[0108] With this design, an improved coverage of the emitter metal of the first electrode 31 above the p-base region / plug regions 23, 24 can be achieved, resulting in a reduced contact resistance compared to a design with only side contacts, especially during the turn-off transient. In the latter case, L pcont is determined by the thickness of the p-base regions 23, 24, and thus can still be reduced by scaling down Lpcont to achieve injection enhancement.

[0109] In addition to Figure 14 as shown, the optional plug region 24 and / or well region 23 may completely cover the first barrier region 41. This is shown Figure 36 in

[0110] For example, Figure 36 the device shown is produced by removing the first semiconductor region 21 from the partial plug region 24 such that the plug region 24 is exposed on top of the first barrier region, rather than etching completely through the semiconductor body 2 until the first barrier region 41. Thus, the plug region 24 and / or well region 23 may completely cover the region of the first barrier region 41, visible in the top view, where the first electrode 31 is in electrical contact with the semiconductor body 2. Accordingly, the first electrode 31 is separated from the first barrier region 41 by the plug region 24 and / or well region 23. That is, the first semiconductor region 21 and the first electrode 31 may have the same depth of entry into the semiconductor body 2.

[0111] Contrary to Figure 36 as shown, when the first semiconductor region 21 is removed, etching may slightly penetrate into the plug region 24 and / or well region 23. Thus, due to manufacturing issues, the first electrode 31 may have a depth of entry into the semiconductor body slightly greater than that of the first semiconductor region 21, but the first electrode 31 is still separated from the first barrier region 41 by the plug region 24 and / or well region 23.

[0112] In addition to this, the same content as the device 1 in Figure 1 and Figure 13 may also be applied to Figure 14 and Figure 36 , and vice versa.

[0113] In Figure 15 , it is shown that the first barrier region 41 consists of a doped barrier layer 45. For example, the maximum doping concentration of the n-type doped layer 45 is at least 1x10 16 cm -3 , or at least 5x10 16 cm- 3 , or at least 1x10 17 cm -3 , and / or at most 1x10 20 cm -3 , or at most 5x10 19 cm -3 , or at most 1x10 19 cm -3 . In this case, the maximum doping concentration of the drift region 25 may be between 1x10 12 cm -3 and 1x1013 cm -3 between

[0114] In addition, the same content as that of Device 1 in Figure 1 , Figure 12 , Figure 13 , Figure 14 and Figure 36 can also be applied to Figure 15 , and vice versa.

[0115] In Figure 16 , the output characteristics of the TLP-IGBT 1 with the n + blocking layer 45 are compared with those of the TLP-IGBT 1 with the oxide blocking layer 44 and Figure 2 's reference plane design 91. It can be seen that the performance advantage brought by the n + blocking layer 45 in on-state conduction is similar to that of the oxide blocking layer 44 and is an effective block for hole flow. However, the doping of the n + blocking layer 45 may need to be optimized in a way that does not adversly affect the blocking ability of Device 1.

[0116] According to Figure 17 , the first blocking region 41 includes a plurality of openings 46 that completely extend through the first blocking region 41, exposing the drift region 25. This allows for an additional path for hole extraction during the turn-off transient. This will result in improved reverse-biased safe operating area (RBSOA) capability with some compromise in on-state loss.

[0117] In addition, the same content as that of Device 1 in Figure 1 , Figure 12 , Figure 13 , Figure 14 , Figure 36 and Figure 15 can also be applied to Figure 17 , and vice versa.

[0118] In the device of Figure 18 , the first electrode 31 is restricted or substantially restricted to the top side 20 and thus does not or does not significantly extend into the first blocking region 41. However, the plug region 24 extends from the first electrode 31 at the top side 20 down to the first blocking region 41.

[0119] In addition, the same content as that of Device 1 in Figure 1 , Figure 12 , Figure 13 , Figure 14 , Figure 36 , Figure 15 and Figure 17 can also be applied to Figure 18 , and vice versa.

[0120] The performance of the TLP-IGBT 1 can be further optimized, for example, by introducing a second blocking region 42, which similarly corresponds to an active trench or a virtual trench in a trench IGBT device. See Figures 19 to 21 . In these figures, by way of example, there are two second blocking regions 42, but this is not a limitation on the number of second blocking regions 42. For example, there is at least one and at most five second blocking regions 42.

[0121] Each of the second blocking regions 42 includes a core portion composed of a conductive layer 47, such as a polysilicon layer. Around this core portion, there is also an additional dielectric layer 48, which electrically insulates the conductive layer 47 from the semiconductor body 2. The conductive layer 47 can be selectively connected to one of the electrodes 31, 33, such that the corresponding conductive layer 47 can be at the same potential as the designated electrode 31, 33.

[0122] For example, starting from the lateral side of the semiconductor body 2 provided with the first electrode 31, the second blocking region 42 extends into the semiconductor body 2 until the first blocking region 41. However, in principle, it is also feasible for the second blocking region 42 to protrude from the first blocking region 41, or alternatively, the first blocking region 41 to protrude from the second blocking region 42, or the second blocking region 42 to extend into the drift region 25 to a different extent, which is contrary to Figures 18 to 20 that shown. The second blocking region 42 can extend parallel to the top side 20.

[0123] The second blocking regions 42 can be arranged at equal intervals. That is, the spacing between adjacent second blocking regions 42 and the spacing towards the top side 20 and / or towards the first blocking region 41 can all correspond to L pcont , for example, with a tolerance factor of 1.5 times.

[0124] As Figure 19 shown, two additional first semiconductor regions 27 are applied to each of the second blocking regions 42, where one of the additional first semiconductor regions 27 is directly located on each main side of the second blocking region 42, parallel to the top side 20. Similar to the first blocking region 41, the second blocking region 42 protrudes into the drift region 25 from these additional first semiconductor regions 27 and the associated well regions 23 and / or plug regions 24.

[0125] Regarding the geometry and doping of the additional first semiconductor regions 27, these additional first semiconductor regions 27 can be configured like the first semiconductor regions 21.

[0126] Therefore, a plurality of vertically stacked cells can be provided, where each cell includes one of the second blocking regions 42 and the associated additional first semiconductor regions 27 and / or well regions 23 and / or plug regions 24.

[0127] In addition, the same content as the device 1 in Figure 1 , Figure 12 , Figure 13 , Figure 14 , Figure 36 , Figure 15 , Figure 17 and Figure 18 can also be applied to Figure 19 , and vice versa.

[0128] In Figure 20 , it is shown that the topmost second blocking region 42 beside the top side 20 is in electrical contact with the first electrode 31, so it corresponds to a virtual MOS unit similar to the trench design IGBT 92. The bottommost second blocking region 42 beside the first blocking region 41 is in electrical contact with the gate electrode 33, so it corresponds to an active MOS unit similar to the trench design IGBT 92.

[0129] In addition, the same content as the device 1 in Figure 19 can also be applied to Figure 20 , and vice versa.

[0130] According to Figure 21 , all the second blocking regions 42 are electrically connected to the gate electrode 33.

[0131] In addition, in Figure 21 it is also shown that not all the second blocking regions 42 need to be provided with an additional first semiconductor region 27. For example, the topmost second blocking region 42 has no additional first semiconductor region.

[0132] In addition, for example, in order to improve the RBSOA performance, the additional first semiconductor region 27 can be removed from the bottommost second blocking region 42 and only retained in at least one top unit. In this way, when electrons are injected from the top unit, the parasitic NPN transistor responsible for latching can be completely eliminated from the hole extraction path. This allows electrons and / or holes to be separated and / or filtered near the contact (region) with the first electrode 31. Therefore, the bottom unit can be used as a hole extractor, while the top unit can still be responsible for electron injection.

[0133] Therefore, the additional first semiconductor region 27 can be added to the second blocking region 42 where needed. For example, as shown in Figure 19 and Figure 20 , each of the second blocking regions 42 has two additional first semiconductor regions 27, while in Figure 21 the topmost second blocking region 42 has no additional first semiconductor region 27, or as in Figure 21As described for the variants, the lowermost second blocking region 42 next to the first blocking region may alternatively not have an additional first semiconductor region 27. The additional first semiconductor region 27 may also be applied only on one main side of the respective second blocking region 42.

[0134] In addition, the same content as that of the device 1 in Figure 19 and Figure 20 can also be applied to Figure 21 , and vice versa.

[0135] As shown in Figures 19 to 21 , stacking n vertical units on top of each other, for example, brings the following technical advantages: First, stacking n units in the vertical direction will only increase the MOS unit density in a given chip. The additional electron injection from the n vertical units will result in an increase in plasma density and thus a reduction in the on-state loss for a given chip area, similar to a fine-pattern trench design densely arranged in the vertical dimension.

[0136] Second, by selectively arranging the source regions 27 in the vertical units, that is, removing / adding source regions 27 in some units, it is feasible to separate or filter the paths for electron injection and hole extraction. For example, the top unit including such a source region 27 can be used for electron injection, while the bottom unit without such a source region 27 can only be used for hole extraction during the off-state. Removing the source region 27 from the path of hole extraction will make it difficult for the parasitic thyristor to conduct, thus improving the RBSOA capability.

[0137] In Figure 22 and Figure 23 , the manufacturing method for the semiconductor device 1 is schematically shown as a block diagram.

[0138] In method step M1, at least part of the semiconductor body 2 is provided, for example, all of the semiconductor body up to the first blocking region 41.

[0139] In method steps M20, M21, M22, the first blocking region 41 is formed.

[0140] According to step M20 (see Figure 22 ), the dielectric material for the first blocking region 41 is applied to the semiconductor body 2 that was previously only partially provided, and then in step M3, the first blocking region 41 overgrows such that a complete semiconductor body 2 is produced. In addition, a doping blocking layer 45 can be formed in method step M20 such that step M3 can be optional.

[0141] According to Figure 23, in step M1, a complete semiconductor body 2 can be provided, and etching is performed in step M21. Then, in step M22, the material for the first blocking region 41 is filled into the etched-out grooves. Thus, method step M3 (i.e., overgrowth) can be optional.

[0142] In step M4, electrodes 31, 33 and all the additional required components are applied.

[0143] At least one second blocking region 42 can be produced similarly to the first blocking region 41.

[0144] In addition, the same content as Figures 1 to 21 and Figure 36 can also be applied to Figure 22 and Figure 23 , and vice versa.

[0145] In Figures 24 to 31 an exemplary method for producing a semiconductor device is shown. According to Figure 24 , a first part 81 of the semiconductor body is provided. For example, the first part 81 includes most of the drift region 25. Optionally, the first part 81 includes a buffer region 28 that can be n + -type doped and a second semiconductor region 22 that can be p + -type doped.

[0146] In the next step, referring to Figure 25 , a continuous starting material layer 4 is applied on the first part 81. For example, the starting material layer 4 is a layer of grown oxide, such as silicon oxide.

[0147] Next, referring to Figure 26 , the starting material layer 4 is structured, for example by means of dry etching, to form the first blocking region 41, which is correspondingly composed of the material from the starting material layer 4.

[0148] Then, referring to Figure 27 , overgrowth is performed such that a second part 82 of the semiconductor body 2 is created. The second part 82 completely covers the first blocking region 41. For example, the second part 82 has a height corresponding to or approximately corresponding to that of the first blocking region 41. It is feasible that Figure 27 the step (e.g., using Si) is completed by selective epitaxial overgrowth.

[0149] In Figure 28 it is shown that the second part 82 is planarized such that a planar top side 20 is formed.

[0150] In Figure 29In the method steps shown, a well region 23, a plug region 24, and a first semiconductor region 21 are created. This can be achieved, for example, by ion implantation or doping during the growth of the second part 82. Then, as also shown in Figure 29 a gate insulating layer 53 is provided on the top side 20.

[0151] According to Figure 30 , the semiconductor body 2 is etched starting from the top side 20 until the first barrier region 41, such that a trench is formed. Subsequently, referring to Figure 31 , a first electrode 31 is applied in the trench, such that the lateral sides of the first semiconductor region 21 and the plug region 24 are electrically connected by the first electrode 31. As shown by the dashed line in Figure 31 , the trench belongs to two device cells. That is, Figure 31 the dashed line in Figure 1 , Figure 14 , Figure 15 and Figures 18 to 21 the dashed line in

[0152] In addition, the same content as in Figure 22 and Figure 23 can also be applied to Figures 24 to 31 , and vice versa.

[0153] In Figures 32 to 35 , another method is shown by means of which, for example, the semiconductor device 1 in Figures 19 to 21 can be produced. The first step of the method can correspond to the method steps in Figures 24 to 29 . However, after applying the gate insulating layer 53, referring to Figure 32 , instead of etching the trench, a conductive layer 47 for the first of the second barrier regions 42 is applied. For example, the conductive layer 47 is made of polysilicon.

[0154] According to Figure 33 , the conductive layer 47 is structured to correspond to the second barrier region 42. Then, referring to Figure 34 , a second part of the dielectric layer 48 is similarly applied to the gate insulating layer 53 (e.g., by oxidation). Thus, the conductive layer 47 is surrounded by the dielectric layer 48. The optional wire between the conductive layer 47 and one of the electrodes 31, 33 is not shown.

[0155] Subsequently, referring to Figure 35 , a third part 83 of the semiconductor body 2 is applied. This can be achieved, for example, by epitaxial growth of Si. Then, semiconductor regions according to Figures 19 to 21 can be formed in the third part 83 as required.

[0156] If, as in Figures 19 to 21If multiple second blocking regions 42 are desired as in Figure 28 and Figure 29 and Figures 32 to 35 the steps of Figure 30 and 31 shown in

[0157] will be correspondingly repeated before applying the first electrode 31. Figure 35 Otherwise, if only one second blocking region 42 is to be formed, the step of Figures 28 to 31 can be directly followed by the step of

[0158] Unless otherwise indicated, the components shown in the figures are exemplarily stacked on top of each other in the specified order. Components that do not touch in the figures are exemplarily spaced apart from each other. If the lines drawn are parallel to each other, the corresponding surfaces may be oriented parallel to each other. Similarly, unless otherwise stated, the relative positions of the components drawn are correctly reproduced in the drawings.

[0159] The invention described herein is not limited by the description based on the exemplary embodiments. On the contrary, the invention encompasses any new features and any combination of features, which particularly includes any combination of features in the patent claims, even if such features or combinations themselves are not explicitly stated in the patent claims or the exemplary embodiments.

[0160] List of Reference Numerals

[0161] 1 Semiconductor device

[0162] 2 Semiconductor body

[0163] 20 Top side

[0164] 21 First semiconductor region (source / emitter region)

[0165] 22 Second semiconductor region (drain / collector region)

[0166] 23 Well region

[0167] 24 Plug region

[0168] 25 Drift region

[0169] 27 Additional first semiconductor region

[0170] 28 Buffer region

[0171] 31 First electrode (source / emitter electrode)

[0172] 32 Second electrode (drain / collector electrode)

[0173] 33 Gate electrode

[0174] 4 Starting material layer

[0175] 41 First blocking region

[0176] 42 Second blocking region

[0177] 44 Dielectric layer

[0178] 45 Doping blocking layer

[0179] 46 Opening

[0180] 47 Conductive layer

[0181] 48 Additional dielectric layer

[0182] 51 First electrode insulating layer

[0183] 53 Gate insulating layer

[0184] 81 First part of the semiconductor body

[0185] 82 Second part of the semiconductor body

[0186] 83 Third part of the semiconductor body

[0187] 91 Planar design reference device

[0188] 92 Trench design reference device

[0189] E off Energy loss during turn-off

[0190] Main current of the Fe electrode

[0191] Main current of the Fh holes

[0192] I c Current at the second electrode (collector)

[0193] I on Ion current at the second electrode in the on-state

[0194] L B Length of the first blocking region of a cell

[0195] L pcont Length of the first electrical contact (emitter contact)

[0196] M.. Method step

[0197] P Protrusion length

[0198] S Symmetry plane

[0199] T Time

[0200] T Temperature (in K)

[0201] T B Thickness of the first blocking region

[0202] V ce Voltage between the second electrode and the first electrode (collector and emitter electrodes)

[0203] V ce-sat Saturation voltage between the second electrode and the first electrode (collector and emitter electrodes)

[0204] V ge Voltage between the gate electrode and the first electrode (emitter electrode)

[0205] Lateral coordinate x (in μm)

[0206] Vertical coordinate y (in μm)

[0207] Third dimension z

Claims

1. A semiconductor device (1), comprising: - a gate electrode (33) at a top side (20) of a semiconductor body (2), - a first semiconductor region (21) of a first conductivity type at the top side (20), the first semiconductor region (21) being a source region or an emitter region, - a plug region (24) of a second conductivity type, - a first electrode (31) in electrical contact with the first semiconductor region (21) and the plug region (24), - a well region (23) of the second conductivity type, the first semiconductor region (21) being at least partially embedded in the well region (23), and - at least one blocking region (41, 42) including a first blocking region (41) in the semiconductor body (2), wherein - at least a part of the well region (23) is located between the first blocking region (41) and the first semiconductor region (21), - the first blocking region (41) is a blocking portion for carriers of at least the second conductivity type, and - the first electrode (31) extends deeper or equally deep into the semiconductor body (2) in a direction towards the first blocking region (41) than the first semiconductor region (21).

2. The semiconductor device (1) according to the preceding claim, comprising at least one second blocking region (42) in the semiconductor body (2) between the first blocking region (41) and the first semiconductor region (21), the at least one second blocking region (42) being a blocking portion for carriers of at least the second conductivity type, Among them, at least one of the first electrode (31) or the plug region (24) extends along the at least one second blocking region (42) towards the first blocking region (41).

3. The semiconductor device (1) according to the previous claim, Among them, the at least one second blocking region (42) includes a conductive layer (47), the conductive layer (47) being electrically insulated from the semiconductor body (2) by an additional dielectric layer (48).

4. The semiconductor device (1) according to the previous claim, Among them, the conductive layer (47) is in electrical contact with the gate electrode (33) or the first electrode (31), and wherein at least one additional first semiconductor region (27) of the first conductivity type is in direct contact with the at least one second blocking region (42) at least on one main side of the second blocking layer (42) and is oriented parallel to the top side (20).

5. The semiconductor device (1) according to the previous claim, including a plurality of the second blocking regions (42), wherein, a main side of the lowermost one of the second blocking regions (42) located next to the first blocking region (41) is in direct contact with the plug region (24) and / or the well region (23).

6. The semiconductor device (1) according to any one of the two preceding claims, Among them, at least one of the second blocking regions (42) does not have any additional first semiconductor regions (27) on at least one main side.

7. The semiconductor device (1) according to any one of the preceding claims, Among them, In a top view of the top side (20), the plug region (24) extends completely along the first semiconductor region (21), and / or the first semiconductor region (21) is completely and directly covered by the electrical insulation layers (51, 53) such that the first semiconductor region (21) is in electrical contact with the first electrode (31) only at its side surfaces that are inclined and oriented towards the top side (20).

8. The semiconductor device (1) according to any one of the preceding claims, Among them, The first electrode (31) is in direct contact with the first blocking region (41).

9. The semiconductor device (1) according to any one of claims 1 to 7, Among them, The first blocking region (41) is completely covered by the semiconductor body (2) on its side facing the first semiconductor region (21).

10. The semiconductor device (1) according to any one of the preceding claims, Among them, The plug region (24) extends deeper into the semiconductor body (2) in the direction towards the first blocking region (41) than the first semiconductor region (21) and is in direct contact with the first blocking region (41).

11. The semiconductor device (1) according to any one of the preceding claims, Among them, The first blocking region (41) is constituted by or includes a doping blocking layer (45) of the first conductivity type.

12. The semiconductor device (1) according to any one of the preceding claims, Among them, The first blocking region (41) is constituted by or includes a dielectric layer (44).

13. The semiconductor device (1) according to any one of the two preceding claims, Among them, The first blocking region (41) extends parallel to the top side (20) and away from the top side (20).

14. The semiconductor device (1) according to any one of the preceding claims, Among them, The semiconductor body (2) includes a drift region (25) of the first conductivity type adjacent to the well region (23), wherein, in a direction parallel to the top side (20), the first blocking region (41) extends into the drift region (25).

15. The semiconductor device (1) according to the preceding claim, Among them, The first blocking region (41) protrudes into the drift region (25) from the well region (23) by a protrusion length (P), and the protrusion length (P) is 30% to 300% of the width of the well region (23) in the same direction.

16. The semiconductor device (1) according to any one of the two preceding claims, Among them, The first blocking region (41) separates the drift region (25) from the well region (23) along a direction (z) perpendicular to the top side (20).

17. The semiconductor device (1) according to any one of the preceding claims, Among them, The first blocking region (41) includes at least one opening (46) that extends completely through the first blocking region (41), wherein, in a top view of the top side (20), the at least one opening (46) is located beside the first semiconductor region (21) and the gate electrode (33).

18. The semiconductor device (1) according to any one of the preceding claims, Among them, wherein the semiconductor body (2) comprises a second semiconductor region (22) at a bottom side opposite to the top side (20), and the second semiconductor region (22) is a drain region of the first conductivity type or a collector region of the second conductivity type, such that the semiconductor device (1) is a field effect transistor or an insulated gate bipolar transistor.

19. A method for manufacturing a semiconductor device (1) according to any one of the preceding claims, the method comprising the following steps in the given order: A) providing at least a part of the semiconductor body (2), B) forming the first blocking region (41), and C) applying the first electrode (31) and the gate electrode (33) to the semiconductor body.

20. The method according to the preceding claim, It further includes the following step between steps B) and C), wherein, wherein in step A) only a first part of the semiconductor body (2) is provided: B1) forming a second part of the semiconductor body (2) above the first blocking region (41), B2) creating the first semiconductor region (21) and the plug region (24) in the second part, B3) forming a gate insulating layer (53) on top of the second part, and B4) etching through the second part down to the first blocking region (41).

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