A reference circuit applied to large substrate working in deep N well in negative voltage environment

Abstract

The application provides a reference circuit applied to a large substrate working in a negative voltage environment in a deep N well, comprising a bias circuit, a reference voltage generation and output module, the bias circuit comprises first to third output ends, the bias circuit and the reference voltage generation and output module comprise first to third input ends, the first to third output ends are connected with the corresponding first to third input ends; the deep N well of NMOS tubes in the bias circuit and the reference voltage generation and output module are connected with a power voltage, and the wafer substrate ring of all MOS tubes in the bias circuit and the reference voltage generation and output module is connected with a negative voltage vsn. The application can be applied to a working voltage of +6V to -6V, has better temperature stability, stronger power supply anti-interference, higher precision, faster response speed, is more chip area-saving, and reduces cost.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and particularly relates to a reference circuit used in a deep N-well with a large substrate operating in a negative pressure environment. Background Technology

[0002] In integrated circuits, reference voltage sources typically provide a reliable reference voltage and current for the entire integrated circuit system. Their accuracy and stability directly affect the performance of the entire integrated circuit system. As the most classic reference voltage circuit, the bandgap reference voltage circuit utilizes the difference in base-emitter voltage VBE (ΔVBE) of different bipolar transistors under different current densities and the opposite temperature coefficient to obtain a reference voltage that is insensitive to both power supply voltage and temperature. The output voltage reference value is approximately 1.2V. It is a stable and reliable reference voltage that does not change with temperature. In practical circuit design, the bandgap reference voltage is often further divided or multiplied by a resistor network to obtain various different reference voltages. The bandgap reference voltage can be used as a voltage reference and forms key IC components such as bias circuits, operational amplifiers, phase-locked loops, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs), and is widely used in various fields.

[0003] In existing technologies, when circuits operating in deep N-wells and large substrates operate in a special environment of negative pressure, high-performance charge pumps and supporting switching control circuits, clock circuits, etc. are required. This will occupy a large area of ​​the chip, and the implementation cost will be high. It will also increase the complexity of the circuit and bring inconvenience to integration. Summary of the Invention

[0004] Purpose of the invention: In order to solve the problems existing in the prior art, the present invention provides a reference circuit that operates in a negative pressure environment on a large substrate in a deep N-well.

[0005] Technical Solution: This invention discloses a reference circuit operating in a negative voltage environment on a large substrate in a deep N-well. The circuit includes a bias circuit and a reference voltage generation and output module. The bias circuit includes first to third output terminals, and the bias circuit and the reference voltage generation and output module include first to third input terminals. The first to third output terminals are connected to their respective first to third input terminals. The deep N-wells of the NMOS transistors in the bias circuit and the reference voltage generation and output module are connected to a power supply voltage. The wafer substrate of all the MOS transistors in the bias circuit and the reference voltage generation and output module is connected to a negative voltage vsn.

[0006] Furthermore, the bias circuit employs a cascode bias circuit, including six PMOS transistors and four NMOS transistors; the gate of the first PMOS transistor is connected to the gate of the third PMOS transistor and the drain of the second PMOS transistor; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; the source and substrate of the first PMOS transistor are connected to the power supply voltage; the gate of the second PMOS transistor is connected to the gate of the fifth PMOS transistor, the gate and drain of the sixth PMOS transistor, and the drain of the first NMOS transistor; the substrate of the second PMOS transistor is connected to the power supply voltage; the source and substrate of the third PMOS transistor are connected to the power supply voltage, and its drain is connected to the source of the fourth PMOS transistor; the gate of the fourth PMOS transistor is connected to the gate of the second PMOS transistor; the drain of the fourth PMOS transistor serves as the first output terminal of the bias circuit, connected to the reference circuit to generate and output the reference voltage mode. The first input terminal of the block is connected to the power supply voltage via the substrate of the fourth PMOS transistor; the source and substrate of the fifth PMOS transistor are connected to the power supply voltage, and the drain is connected to the source of the sixth PMOS transistor; the gate of the first NMOS transistor serves as the second output terminal of the bias circuit, connected to the gate of the second NMOS transistor and the second input terminal of the reference circuit generating and outputting the reference voltage module; the source of the first NMOS transistor is connected to the substrate of the first NMOS transistor and the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor; the source and substrate of the third NMOS transistor are grounded; the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor and the substrate of the second NMOS transistor; the gate of the fourth NMOS transistor serves as the third output terminal of the bias circuit, connected to the third input terminal of the reference circuit generating and outputting the reference voltage module; the source and substrate of the fourth NMOS transistor are grounded.

[0007] Furthermore, the reference circuit generating and outputting reference voltage module includes fifth to seventh MOSFETs, first to sixth resistors, and first and second transistors; the gate of the fifth MOSFET serves as the first input terminal of the reference circuit generating and outputting reference voltage module and is connected to the first output terminal of the bias circuit. The gate of the fifth MOSFET is also connected to the drain of the sixth MOSFET. The drain of the fifth MOSFET is connected to the power supply voltage, and the source is connected to the gate of the sixth MOSFET. The substrate of the fifth MOSFET is connected to one end of the fifth resistor; the substrate of the sixth MOSFET is connected to the source of the sixth MOSFET; one end of the fifth resistor serves as the reference for the reference circuit generating and outputting reference voltage. The second input terminal of the voltage module is connected to the bias circuit. The other end of the fifth resistor serves as the output terminal of the reference circuit generating and outputting the reference voltage module, and is connected to one end of the third and fourth resistors. The other end of the fourth resistor serves as the third input terminal of the reference circuit generating and outputting the reference voltage module, and is connected to one end of the second resistor. The other end of the second resistor is connected to one end of the emitter of the first transistor. The other end of the first resistor is connected to one end of the sixth resistor. The other end of the sixth resistor is connected to the gate of the seventh MOS transistor and the other end of the third resistor. The source and substrate of the seventh MOS transistor are grounded, and the drain is connected to the source of the sixth MOS transistor.

[0008] Furthermore, the fifth to seventh MOS transistors are NMOS transistors. Beneficial effects

[0009] 1. The present invention adds a deep N-well layer between the P-well and the P-type substrate, which significantly improves the isolation between the MOS device and the substrate.

[0010] 2. By biasing the P-well, deep N-well, and P-substrate under a reasonable DC voltage, the parasitic PN junction can be reverse biased, thereby reducing signal coupling leakage.

[0011] 3. It can be used with a working voltage of +6V to -6V (providing a 12V working voltage for industrial control applications), with better temperature stability, stronger power supply anti-interference, higher accuracy, faster response speed, and more chip area saving, reducing costs. Attached Figure Description

[0012] Figure 1 This is an overall structural diagram of the present invention.

[0013] Figure 2 This is the traditional PNP connection method for reference circuits. Detailed Implementation

[0014] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0015] like Figure 1 The present invention provides a reference circuit for use in a large substrate in a deep N-well operating in a negative voltage environment, comprising: a cascode bias circuit, a reference circuit generation and output reference voltage module, a deep N-well potential (Vdd), and a negative voltage potential.

[0016] The cascode bias circuit consists of PMOS transistors P1~P6 and isolated NMOS transistors N1, N2, N3, and N4. The gate of P1 is connected to the drains of P2 and N2 and the gate of P3; its source is connected to the power supply voltage; its drain is connected to the source of P2; the substrate is connected to the power supply voltage; and the PSUB ring is connected to a negative voltage potential (vsn). The gate of P2 is connected to the gates of P4, P5, and P6 and the drains of P6 and N1; its source is connected to the drain of P1; its drain is connected to the gates of P1, P3, and N2; the substrate is connected to the power supply voltage; and the PSUB ring is connected to a negative voltage potential (vsn). The gate of P3 is connected to the gate of P1 and the drains of P2 and N2; its source is connected to the power supply voltage; its drain is connected to the source of P4; the substrate is connected to the power supply voltage; and the PSUB ring... The P4 gate is connected to the gates of P2, P5, and P6, and the drains of P6 and N1. Its source is connected to the drain of P3, and its drain is connected to the gates of N3 and N4. The substrate is connected to the power supply voltage. The PSUB ring is connected to a negative voltage (vsn). The P5 gate is connected to the gates of P2, P4, and P6, and the drains of P6 and N1. Its source is connected to the power supply voltage, and its drain is connected to the source of P6. The substrate is connected to the power supply voltage, and the PSUB ring is connected to a negative voltage (vsn). The P6 gate is connected to the gates of P2, P4, and P5, and the drains of P6 and N1. Its source is connected to the drain of P5, and its drain is connected to the gates of P2, P4, and P6. 5. The gate of P6 and the drain of N1 are connected to the power supply voltage via the substrate, and the PSUB ring is connected to a negative voltage potential (vsn). The gate of N1 is connected to the gates of N2 and N4, the source of N3, and the PLUS terminal of R5. The source is connected to the substrate of N1 and the drain of N3. The drain is connected to the gates of P2, P4, P5, and P6, and the drains of P6 and N1. The substrate is connected to the source of N1 and the drain of N3. The PSUB ring is connected to a negative voltage potential (vsn), and the deep N-well is connected to the power supply voltage. The gate of N2 is connected to the gates of N1 and N4, the source of N3, and the PLUS terminal of R5. The source is connected to the substrate of N2 and the drain of N4. The drain is connected to the drain of P2 and... The gates of P1 and P3 are connected to the substrates of N2 (source) and N4 (drain), the PSUB ring is connected to a negative voltage potential (vsn), and the deep N-well is connected to the power supply voltage. The gate of N3 is connected to the gate of N4, the MINUS terminal of R4, and the PLUS terminal of R2. The source is grounded. The drain is connected to the substrate and source of N1. The substrate is grounded. The PSUB ring is connected to a negative voltage potential (vsn), and the deep N-well is connected to the power supply voltage. The gate of N4 is connected to the gate of N3, the MINUS terminal of R4, and the PLUS terminal of R2. The source is grounded. The drain is connected to the substrate and source of N2. The substrate is grounded. The MINUS terminal of R4 and the PLUS terminal of R2 are also connected to the power supply voltage.

[0017] The reference circuit generates and outputs a reference voltage module consisting of isolated NMOS transistors N5, N6, N7, resistors R1 to R6, and PNP1 and PNP2. N5's gate is connected to the drains of P4 and N6, its source is connected to the gates of N1, N2, and N6, the PLUS terminal of R5, and the N5 substrate, its drain is connected to the power supply voltage, and its substrate is connected to the gates of N1, N2, and N6, the PLUS terminal of R5, and the N5 source. The PSUB ring is connected to a negative voltage potential (vsn), and the deep N-well is connected to the power supply voltage. N6's gate is connected to the gates of N1 and N2, the PLUS terminal of R5, the N5 source, and the N5 substrate. Its source is connected to the N6 substrate and the N7 drain, its drain is connected to the gate of N5 and the drain of P4, and its substrate is connected to the N6 source and the N7 drain. The PSUB ring is connected to a negative voltage potential (vsn), and the deep N-well is connected to the power supply voltage. N7's gate is connected to the MINUS terminal of R3 and the PLUS terminal of R0, its source is grounded, its drain is connected to the N6 substrate and source, and its substrate is connected to the N7 source. The PLUS terminal of R5 is connected to the gates of N1, N2, and N6, and the N5 substrate, and its MINUS terminal is connected to R3. The PLUS terminal of R4 and the VOUT output port are connected; the PLUS terminal of R4 is connected to the MINUS terminal of R5 and the PLUS terminal of R3 and the VOUT output port, and the MINUS terminal is connected to the gates of N3 and N4 and the PLUS terminal of R2; the PLUS terminal of R2 is connected to the gates of N3 and N4 and the MINUS terminal of R4, and the MINUS terminal is connected to the emitter of PNP1; the PLUS terminal of R6 is connected to the MINUS terminal of R3 and the gate of N7, and the MINUS terminal is connected to the PLUS terminal of R1; the PLUS terminal of R1 is connected to the MINUS terminal of R6, and the MINUS terminal is connected to the emitter of PNP2; the emitter of PNP1 is connected to the MINUS terminal of R2, the base is grounded and the base of PNP2, and the collector is connected to a negative voltage potential (vsn); the emitter of PNP2 is connected to the MINUS terminal of R1, the base is grounded and the base of PNP1, and the collector is connected to a negative voltage potential (vsn).

[0018] Traditional PNP connection methods, such as Figure 2 As shown, VEC=VEB no longer meets the requirements of the circuit. Therefore, in this invention, the bases of PNP1 and PNP2 are grounded and the collectors are connected to a negative voltage potential (vsn) VEC≥VEB, and PNP1:PNP2=1:8. This invention will not generate a large current that will affect the circuit function.

[0019] This invention provides a stable current to the entire circuit through a cascode bias circuit. The gate connection of N4 can be considered as the non-inverting input of the op-amp, while N7 is the inverting input. The connection of N2, N6, N4, and N7 reflects the virtual short characteristic of the op-amp, so I = ΔVBE / R1. Taking R1 = R2, it is clear that the voltage across the resistors is equal. Due to the virtual open characteristic, there is no current at the gates of N4 and N7, so the currents in R2 and R1 are equal. Because the resistances are equal, the currents in the two branches R1 and R2 are equal. Then, by adjusting the resistance ratio of the R2 and R1 branches, the reference voltage can be obtained and output from the VOUT terminal. Since this circuit will operate under the special condition of negative voltage, the entire circuit is built in a deep N-well. Even when operating under negative voltage, the reference output voltage of this circuit remains unaffected.

[0020] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

Claims

1. A reference circuit used in a deep N-well with a large substrate operating in a negative pressure environment, characterized in that, It includes a bias circuit, a reference circuit, and a reference voltage generation and output module. The bias circuit includes first to third output terminals, and the bias circuit and the reference circuit generate and output reference voltage module include first to third input terminals. The first to third output terminals are connected to the corresponding first to third input terminals. The deep N-well of the NMOS transistors in the bias circuit and reference circuit generating and outputting reference voltage module is connected to the power supply voltage. The wafer substrate of all MOS transistors in the bias circuit and reference circuit generating and outputting reference voltage module is ring-connected to a negative voltage vsn. The bias circuit adopts a cascode bias circuit, including first to sixth PMOS transistors and first to fourth NMOS transistors. The gate of the first PMOS transistor is connected to the gate of the third PMOS transistor and the drain of the second PMOS transistor. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The source and substrate of the first PMOS transistor are connected to the power supply voltage. The gate of the second PMOS transistor is connected to the gate of the fifth PMOS transistor, the gate and drain of the sixth PMOS transistor, and the drain of the first NMOS transistor. The substrate of the second PMOS transistor is connected to the power supply voltage. The source and substrate of the third PMOS transistor are connected to the power supply voltage, and the drain is connected to the source of the fourth PMOS transistor. The gate of the fourth PMOS transistor is connected to the gate of the second PMOS transistor. The drain of the fourth PMOS transistor serves as the first output terminal of the bias circuit and is connected to the first input terminal of the reference circuit generating and outputting reference voltage module. The substrate of the fourth PMOS transistor is connected to the power supply voltage. The source and substrate of the fifth PMOS transistor are connected to the power supply voltage, and the drain is connected to the source of the sixth PMOS transistor. The gate of the first NMOS transistor serves as the second output terminal of the bias circuit and is connected to the gate of the second NMOS transistor and the second input terminal of the reference circuit generating and outputting the reference voltage module. The source of the first NMOS transistor is connected to the substrate of the first NMOS transistor and the drain of the third NMOS transistor. The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor. The source and substrate of the third NMOS transistor are grounded. The source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor and the substrate of the second NMOS transistor. The gate of the fourth NMOS transistor serves as the third output terminal of the bias circuit and is connected to the third input terminal of the reference circuit generating and outputting the reference voltage module. The source and substrate of the fourth NMOS transistor are grounded.

2. The reference circuit according to claim 1, which operates in a negative voltage environment on a large substrate in a deep N-well, is characterized in that... The reference circuit generating and outputting reference voltage module includes fifth to seventh MOSFETs, first to sixth resistors, and first and second transistors. The gate of the fifth MOSFET serves as the first input terminal of the reference circuit generating and outputting reference voltage module and is connected to the first output terminal of the bias circuit. The gate of the fifth MOSFET is also connected to the drain of the sixth MOSFET. The drain of the fifth MOSFET is connected to the power supply voltage, and the source is connected to the gate of the sixth MOSFET. The substrate of the fifth MOSFET is connected to one end of the fifth resistor. The substrate of the sixth MOSFET is connected to the source of the sixth MOSFET. One end of the fifth resistor serves as the second input terminal of the reference circuit generating and outputting the reference voltage module, which is connected to the bias circuit. The other end of the fifth resistor serves as the output terminal of the reference circuit generating and outputting the reference voltage module, and is connected to one end of the third and fourth resistors. The other end of the fourth resistor serves as the third input terminal of the reference circuit generating and outputting the reference voltage module, and is connected to one end of the second resistor; the other end of the second resistor is connected to one end of the emitter of the first transistor, the other end of the third resistor is connected to one end of the sixth resistor and the gate of the seventh MOSFET, the other end of the sixth resistor is connected to one end of the first resistor, the other end of the first resistor is connected to the emitter of the second transistor, the bases of the first and second transistors are connected to each other and then grounded, and the collectors of the first and second transistors are connected to each other; the source and substrate of the seventh MOSFET are grounded, and the drain is connected to the source of the sixth MOSFET.

3. A reference circuit for use in a deep N-well with a large substrate operating in a negative voltage environment, as described in claim 2, is characterized in that... The fifth to seventh MOSFETs are NMOS transistors.

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