Method and device for controlling back bias output zero temperature coefficient current

Abstract

The invention discloses a method and equipment for controlling back bias output zero temperature coefficient current, relates to the technical field of integrated circuits, and is used for solving the problem that the current temperature coefficient of a target transistor cannot be flexibly regulated and controlled in the prior art. Comprising the following steps: configuring a band-gap reference circuit; simulating a target transistor in the band-gap reference circuit, and determining the size and bias voltage of the transistor meeting a preset condition; performing voltage division processing on the band-gap reference circuit to determine a target back gate voltage; and applying the target back gate voltage to the back gate end of the target transistor, iteratively updating the transistor size and the target back gate voltage, and outputting a current meeting the zero temperature coefficient requirement. According to the technical scheme provided by the invention, better temperature performance can be realized, and the complexity of circuit design is reduced; flexible back bias voltage is provided, and more choices are provided for circuit design.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular, to a method and device for controlling a zero temperature coefficient current output by body biasing. Background Art

[0002] In modern integrated circuit applications, the influence of temperature on circuit performance is extremely significant. As electronic devices continue to develop towards high integration and high performance, the heat generated by internal circuit components during operation is more likely to accumulate, resulting in an increase in the operating temperature. With the large influx of new energy vehicles into the market, in order to ensure the safety of driving, it is particularly important to research chips that meet the working conditions of a wide temperature change range for automotive applications. The AEC-Q100 standard grade1 stipulates that the operating temperature range of automotive electronics is -40 to 150 °C. Therefore, it is of great significance to study the variation law of the performance of electronic devices in a wide temperature range and regulate the temperature coefficient of the circuit to the expected level.

[0003] For 22nm FDSOI process MOS devices, when the temperature changes in a wide range, the Id-Vg transfer characteristic curve of a single transistor shows that there is a zero temperature coefficient (ZTC) point for the drain current Id. This point has a constant Vg bias. Since the threshold voltage decreases with increasing temperature, Id increases with temperature at Vg below Id-ZTC, and the carrier mobility decreases with increasing temperature, while Id decreases with temperature at Vg above Id-ZTC. At the point where these two mechanisms balance each other, an Id that is invariant with temperature appears. In addition, based on the body biasing characteristics of this process, applying a body bias voltage to the device can change device characteristics such as the threshold voltage of the device. Therefore, after applying the body bias voltage, the temperature characteristics of the device can also be changed accordingly, and the position of the zero temperature coefficient point of the device can be adjusted.

[0004] Therefore, there is an urgent need to provide a more reliable solution for controlling the zero temperature coefficient current output by body biasing. Summary of the Invention

[0005] The purpose of the present invention is to provide a method and device for controlling a zero temperature coefficient current output by body biasing, which are used to solve the problem that the current temperature coefficient of a target transistor cannot be flexibly regulated in the prior art.

[0006] To achieve the above purpose, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a method for controlling a zero temperature coefficient current output by body biasing, the method comprising:

[0008] Configuring a bandgap reference circuit;

[0009] Simulating a target transistor in the bandgap reference circuit to determine a transistor size and a bias voltage that meet a preset condition;

[0010] Perform voltage division on the bandgap reference circuit to determine the target back-gate voltage;

[0011] Apply the target back-gate voltage to the back-gate terminal of the target transistor, iteratively update the transistor size and the target back-gate voltage, and output a current that meets the zero temperature coefficient requirement.

[0012] Compared with the prior art, the present invention provides a method for controlling the back-bias to output a zero temperature coefficient current. By configuring a bandgap reference circuit; simulating the target transistor in the bandgap reference circuit to determine the transistor size and the bias voltage that meet the preset conditions; performing voltage division on the bandgap reference circuit to determine the target back-gate voltage; applying the target back-gate voltage to the back-gate terminal of the target transistor, iteratively updating the transistor size and the target back-gate voltage, and outputting a current that meets the zero temperature coefficient requirement. The present invention adds a positive temperature coefficient current and a negative temperature coefficient current generated by a single transistor and a resistor with a zero temperature coefficient output voltage, and matches the temperature coefficients of the two types of output currents to achieve a zero temperature coefficient current. There is no need to design an additional compensation circuit, which can achieve better temperature performance and reduce the complexity of circuit design; provides a flexible back-bias voltage and offers more choices for circuit design.

[0013] Optionally, the simulating the target transistor in the bandgap reference circuit to determine the transistor size and the bias voltage that meet the preset conditions includes:

[0014] Perform a wide temperature range simulation on the target transistor, fix the gate-source voltage and the drain-source voltage, and obtain the regulation data of the back-bias voltage on the drain current corresponding to transistors of different sizes;

[0015] Collect and analyze the regulation data to determine the transistor size and the bias voltage that meet the preset conditions; the preset conditions include at least the target current magnitude and the target temperature coefficient.

[0016] Optionally, the performing voltage division on the bandgap reference circuit to determine the target back-gate voltage includes:

[0017] Perform voltage division on the zero temperature coefficient voltage through a resistor network to determine the target back-gate voltage for regulating the back-gate of the target transistor.

[0018] Optionally, the applying the target back-gate voltage to the back-gate terminal of the target transistor, iteratively updating the transistor size and the target back-gate voltage, and outputting a current that meets the zero temperature coefficient requirement includes:

[0019] Apply the voltage-divided zero temperature coefficient voltage to the back-gate port of the target transistor in the bandgap reference circuit;

[0020] Monitor the output current of the target transistor. By iteratively optimizing the size of the transistor and the target back-gate voltage, make the output current reach a preset magnitude and the temperature coefficient approach zero, and determine that the sum of the two output currents is a constant current with a zero temperature coefficient.

[0021] Optionally, the configured bandgap reference circuit at least includes:

[0022] A first current generation circuit, a reference voltage generation circuit, a zero temperature coefficient current generation circuit, and a second current generation circuit;

[0023] The first current generation circuit is used to generate a positive temperature coefficient current, and the second current generation circuit is used to generate a negative temperature coefficient current;

[0024] Determine the zero temperature coefficient current by using the positive temperature coefficient current, the zero temperature coefficient voltage output by the reference voltage generation circuit, and the negative temperature coefficient current.

[0025] Optionally, before simulating the target transistor in the bandgap reference circuit to determine the transistor size and bias voltage that meet the preset conditions, it further includes:

[0026] According to the circuit structure of the bandgap reference circuit, the NMOS transistor in the bandgap reference circuit uses a flipped well structure, and the PMOS transistor in the bandgap reference circuit uses a conventional well structure.

[0027] Optionally, convert the zero temperature coefficient voltage into a negative temperature coefficient current through a resistor and a single-transistor circuit;

[0028] Add the positive temperature coefficient current and the negative temperature coefficient current to form a synthetic current.

[0029] Optionally, applying the target back-gate voltage to the back-gate terminal of the target transistor, iteratively updating the transistor size and the target back-gate voltage, and outputting a current that meets the zero temperature coefficient requirement, includes:

[0030] Apply the divided zero temperature coefficient voltage to the back-gate port of the target transistor in the bandgap reference circuit, construct a feedback loop to iteratively optimize the back-gate voltage value, so that the synthetic current maintains the zero temperature coefficient characteristic in a wide temperature range.

[0031] Optionally, the regulation data at least includes the regulation effect of different back-bias voltages on the output characteristic curve of the target transistor;

[0032] Collect and analyze the regulation data to determine the transistor size and bias voltage that meet the preset conditions, including:

[0033] Based on the regulation effect of different back bias voltages on the output characteristic curve of the target transistor, establish the mapping relationship between the back bias voltage and the negative temperature coefficient current;

[0034] According to the mapping relationship, determine the back bias voltage value that makes the temperature coefficients of the positive temperature coefficient current and the negative temperature coefficient current match.

[0035] In a second aspect, the present invention provides a device for controlling a back bias output zero temperature coefficient current, and uses the above method for controlling a back bias output zero temperature coefficient current to output a zero temperature coefficient current.

[0036] The technical effects achieved by the device type solution provided in the second aspect are the same as those of the method type solution provided in the first aspect, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0038] Figure 1 is a schematic flow chart of a method for controlling a back bias output zero temperature coefficient current provided by the present invention;

[0039] Figure 2 is a schematic diagram of a configured bandgap reference circuit provided by the present invention;

[0040] Figure 3 is a schematic diagram of the output characteristic curve of a MOS transistor with a wide temperature range provided by the present invention;

[0041] Figure 4 is a schematic diagram of the regulation effect curve of the back bias voltage on the output characteristic curve of a MOS transistor with a wide temperature range provided by the present invention;

[0042] Figure 5 is a schematic diagram of a bandgap self - biased back bias output zero temperature coefficient current provided by the present invention.

[0043] REFERENCE NUMERALS:

[0044] 1 - First current generation circuit, 2 - Reference voltage generation circuit, 3 - Zero temperature coefficient current generation circuit, 4 - Second current generation circuit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] For the convenience of clearly describing the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit their sequence. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity and execution order, and terms such as "first" and "second" do not necessarily limit being different.

[0046] It should be noted that in the present invention, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present invention should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplary" or "for example" aims to present relevant concepts in a specific manner.

[0047] In the present invention, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0048] As an important part of the circuit, the bandgap reference circuit combines VBE with a negative temperature coefficient and ΔVBE with a positive temperature coefficient in a certain proportion to obtain a zero-temperature coefficient voltage, and the accuracy of its output voltage and temperature stability affect the performance of the subsequent circuit.

[0049] The present invention proposes to use the zero-temperature coefficient voltage of the bandgap reference circuit to obtain the required back-bias voltage by voltage division, and regulate the current temperature coefficient of the target transistor. According to this characteristic, an output current with an arbitrary temperature coefficient can be flexibly obtained.

[0050] Specifically, the solution proposed by the present invention is a method of using the zero-temperature coefficient voltage of a bandgap circuit as a back-bias voltage to self-bias the bandgap circuit to output a zero-temperature coefficient current. The bandgap circuit combines the VBE with a negative temperature coefficient and the ΔVBE with a positive temperature coefficient in a certain proportion to obtain a zero-temperature coefficient voltage. This reference voltage is divided by a voltage divider to obtain reference voltages of different magnitudes, and the divided reference voltage is led out as the back-bias voltage of the MOS transistor for the bandgap output current. Referring to the single-transistor simulation results, continuously iterate and adjust the transistor size, back-bias state, etc., and finally achieve the target current magnitude and current temperature coefficient in the circuit. In addition, the method of using the stable voltage output by the bandgap circuit as the back-bias voltage to bias the circuit proposed by the present invention is not only applicable to the bandgap to generate a zero-temperature coefficient current, but also can be extended to other analog circuits that need to control the current temperature coefficient.

[0051] Next, a method for controlling the back-bias output of a zero-temperature coefficient current provided in the embodiments of the present specification will be described with reference to the accompanying drawings:

[0052] As Figure 1 shown, the process may include the following steps:

[0053] Step 110: Configure a bandgap reference circuit.

[0054] The bandgap reference circuit (Bandgap circuit) is the core circuit in analog integrated circuits for providing a high-precision, low-temperature coefficient reference voltage or current.

[0055] Step 120: Simulate the target transistor in the bandgap reference circuit to determine the transistor size and bias voltage that meet the preset conditions.

[0056] The target transistor can be a transistor that selects a suitable bipolar transistor type according to the circuit design requirements and sets initial size parameters.

[0057] Step 130: Perform voltage division processing on the bandgap reference circuit to determine the target back-gate voltage.

[0058] When implementing this step, a voltage division network can be constructed first, and then the target back-gate voltage can be determined. When constructing the voltage division network, appropriate components such as resistors and capacitors can be selected according to the circuit requirements to construct the voltage division network. Set the initial parameters, set the initial resistance values and ratios for the voltage division network to initially determine the range of the back-gate voltage. It is simple and easy to adjust.

[0059] Step 140: Apply the target back-gate voltage to the back-gate terminal of the target transistor, iteratively update the transistor size and the target back-gate voltage, and output a current that meets the zero-temperature coefficient requirement.

[0060] Figure 1 The method in [reference] configures a bandgap reference circuit, simulates the target transistors in the bandgap reference circuit to determine the transistor size and bias voltage that meet the preset conditions, performs voltage division processing on the bandgap reference circuit to determine the target backgate voltage, applies the target backgate voltage to the backgate terminal of the target transistor, iteratively updates the transistor size and the target backgate voltage, and outputs a current that meets the zero temperature coefficient requirement. The present invention adds a positive temperature coefficient current and a negative temperature coefficient current generated by a single transistor and a resistor through a zero temperature coefficient output voltage, and matches the temperature coefficients of the two types of output currents to achieve a zero temperature coefficient current. There is no need to design an additional compensation circuit, which can achieve better temperature performance and reduce the complexity of circuit design; it provides a flexible back-bias voltage and offers more choices for circuit design.

[0061] Based on Figure 1 the method in [reference], some specific embodiments of this method are also provided in the embodiments of this specification, which will be described below.

[0062] For Figure 1 the solution in [reference], the bandgap reference circuit in step 110 is as shown in Figure 2 and the bandgap reference circuit may at least include:

[0063] a first current generation circuit, a reference voltage generation circuit, a zero temperature coefficient current generation circuit, and a second current generation circuit;

[0064] The first current generation circuit is used to generate a positive temperature coefficient current, and the second current generation circuit is used to generate a negative temperature coefficient current;

[0065] The zero temperature coefficient current is determined by using the positive temperature coefficient current, the zero temperature coefficient voltage output by the reference voltage generation circuit, and the negative temperature coefficient current.

[0066] Among them, the zero temperature coefficient voltage regulates the negative temperature coefficient current in the current generation circuit to an appropriate value. The positive and negative summation achieves a zero temperature coefficient.

[0067] As shown in Figure 2, the source terminal of the P transistor in the figure is connected to VDD. The first current generation circuit 1 is used to generate IPTAT current. Therefore, the first current generation circuit 1 is an IPTAT current generation circuit. In the first current generation circuit 1, the PNP transistors Q1 and Q2 are of the same size, and the number of Q2 is N times that of Q1. The operational amplifier OPA1 clamps the voltages at both ends of the input terminal to be the same, generating a positive temperature coefficient voltage ΔVBE, and an IPTAT current is generated through R1. In the reference voltage generation circuit 2, Q3 is exactly the same as Q1, and the gates of P3 and P4 are connected to those of P1 and P2. P3 and P4 are used for current replication to generate a positive temperature coefficient current, and the positive temperature coefficient current flowing through R2 generates a positive temperature coefficient voltage. The negative temperature coefficient voltage of Q3 is added to the positive temperature coefficient voltage across R2 to achieve a zero temperature coefficient voltage. This voltage can output an arbitrary voltage Vref with a value lower than a certain value through the proportional voltage division of R3 and R4. The second current generation circuit 4 is used to generate ICTAT current. Therefore, the second current generation circuit 4 is an ICTAT current generation circuit. In the second current generation circuit 4, the operational amplifier OPA2 clamps the voltage at the source terminal of N1 to the zero temperature coefficient voltage Vref. The resistance of the N1 transistor has a positive temperature coefficient, so a negative temperature coefficient current is generated. The drain terminal of N1 is connected to the R5 resistor, and the resistance value determines the magnitude of the ICTAT current. In the zero temperature coefficient current generation circuit 3, the gate of P5 is connected to that of P1 to replicate the IPTAT current, and the gate of P6 is connected to that of P7 to replicate the ICTAT current. The drain terminals of the currents connected to P5 and P6 sum the output currents to achieve a zero temperature coefficient current.

[0068] The Vref voltage is led out to regulate the back-gate voltage of P6 to control the magnitude of the temperature coefficient.

[0069] According to the circuit structure of the bandgap reference circuit, the NMOS transistor in the bandgap reference circuit is selected to be of the reverse well structure, and the PMOS transistor in the bandgap reference circuit is selected to be of the conventional well structure.

[0070] In the above settings, selecting the reverse well structure for the NMOS transistor improves the transistor performance. The reverse well structure can optimize performance parameters such as the threshold voltage and mobility of the NMOS transistor, thereby improving the accuracy and stability of the bandgap reference circuit. And the NMOS transistor with the reverse well structure can more effectively control the leakage current and reduce power consumption during operation, which is particularly important for the low-power design of the bandgap reference circuit. In addition, the reverse well structure helps to reduce the parasitic capacitance and resistance of the NMOS transistor, thereby improving the response speed and overall performance of the circuit.

[0071] For the PMOS transistor, a conventional well structure is selected. The manufacturing process of the PMOS transistor with a conventional well structure is relatively mature, which can ensure the performance stability and consistency of the transistor, and this is crucial for the reliability and repeatability of the bandgap reference circuit. The PMOS transistor with a conventional well structure does not require additional complex process steps during manufacturing, which helps to reduce the production cost. Moreover, the PMOS transistor with a conventional well structure can work better with the NMOS transistor in the bandgap reference circuit to optimize the circuit performance, such as performing better in aspects such as temperature compensation and power supply rejection ratio.

[0072] Optionally, Figure 1 In step 120, in specific implementation, it may include:

[0073] Perform a wide temperature range simulation on the target transistor, fix the gate-source voltage and the drain-source voltage, and obtain the regulation data of the back bias voltage on the drain current corresponding to transistors of different sizes;

[0074] Collect and analyze the regulation data to determine the transistor size and the bias voltage that meet the preset conditions; the preset conditions at least include the target current magnitude and the target temperature coefficient.

[0075] Specifically, according to the regulation effect of different back bias voltages on the output characteristic curve of the target transistor, establish a mapping relationship between the back bias voltage and the negative temperature coefficient current;

[0076] According to the mapping relationship, determine the back bias voltage value that makes the temperature coefficients of the positive temperature coefficient current and the negative temperature coefficient current match.

[0077] In this step, a large number of simulations are performed on the MOS device to determine the regulation effect of the back bias voltage Vb on the current Id of MOS transistors of different sizes in a wide temperature range under the condition of fixed Vgs and Vds, and determine the transistor size and the bias voltage with the target current magnitude and the temperature coefficient.

[0078] Adding the positive and negative temperature coefficient voltages of the bandgap reference circuit can obtain a voltage with a zero temperature coefficient. Construct a circuit model including NMOS (reverse well structure) and PMOS (conventional well structure) transistors. In the model, the parameters of the transistors, such as the gate length (L), the gate width (W), etc., can be set in detail.

[0079] Set the basic transistor dimensions and bias voltages, and observe the output characteristics of the circuit. For example: Set different combinations of gate widths and gate lengths, and observe the changes in the output current. Adjust the bias current and voltage, and check the impact on the circuit performance. To systematically find the transistor dimensions and bias voltages that meet the conditions, perform a parameter scan. Based on the simulation results, analyze which parameter combinations can meet the preset performance metrics. If it is found that some performance metrics are not met, then the transistor dimensions or bias voltages need to be adjusted and the simulation redone. Possible adjustment strategies include: Adjusting the transistor size ratio to optimize the matching of the current mirror. Changing the bias current to adjust the operating point of the circuit. Optimizing the parameters of the temperature compensation network to improve the temperature stability. Through continuous iteration and optimization, finally determine the transistor dimensions and bias voltages that meet the conditions.

[0080] Figure 1 In step 130, when implemented, it may include:

[0081] Divide the zero temperature coefficient voltage through a resistor network to determine the target back-gate voltage for regulating the back gate of the target transistor.

[0082] In the above steps, the voltage division process of the bandgap reference circuit to determine the target back-gate voltage is achieved by adding a voltage division network in the circuit. The back-gate voltage has an important impact on the threshold voltage and leakage current of the transistor, and thus affects the performance of the bandgap reference circuit. The back-gate voltage will affect the threshold voltages of NMOS and PMOS transistors, and thus affect the output characteristics and temperature stability of the bandgap reference circuit. Through the voltage division process, the back-gate voltage can be precisely controlled to optimize the circuit performance.

[0083] The operational amplifier is used to clamp the vref voltage and generate the ICTAT current through the vref voltage. And the output of the operational amplifier serves as the gate voltage of the ICTAT current transistor.

[0084] Optionally, when step 140 is implemented, it may specifically include:

[0085] Apply the divided zero temperature coefficient voltage to the back-gate port of the target transistor in the bandgap reference circuit;

[0086] Monitor the output current of the target transistor, and through iterative optimization of the transistor dimensions and the target back-gate voltage, make the output current reach a preset magnitude and the temperature coefficient approach zero, and determine that the sum of the two output currents is a constant current with zero temperature coefficient.

[0087] When the above step 140 is implemented, the back-gate voltage needs to be applied after initializing the parameters. The initialization parameters may include:

[0088] Determine the initial dimensions of the target transistor (such as channel length, width, etc.) and the initial target back-gate voltage.

[0089] Set the step size for iterative update, that is, the change amount when updating the transistor dimensions and the target back-gate voltage each time.

[0090] Determine the iteration termination condition, for example, reaching the preset maximum number of iterations, or the temperature coefficient of the current being within a certain allowable error range.

[0091] During the specific implementation of steps 120 - 130, the transistor dimensions and the bias voltage are determined. Apply the back-gate voltage to the back-gate terminal of the target transistor.

[0092] As an alternative implementation, a circuit simulation tool (such as SPICE) can be used to simulate the characteristics of the circuit where the transistor is located at this time, so as to obtain the curve of the output current varying with temperature. From the curve of the output current varying with temperature, select the current values at different temperature points. Using the selected current values and the corresponding temperatures, calculate the temperature coefficient of the current. Compare the calculated temperature coefficient of the current with the preset error range. If the temperature coefficient is within the error range, it is considered that the zero temperature coefficient requirement is met. At this time, the current transistor dimensions, the target back-gate voltage, and the corresponding output current can be output; according to the positive or negative and magnitude of the current temperature coefficient at present, adjust the transistor dimensions and the target back-gate voltage. For example, if the temperature coefficient is positive, try to increase the ICTAT current coefficient or current, increase the dimensions of the transistor with ICTAT current output, or increase the back-bias voltage; if the temperature coefficient is negative, do the opposite. The adjustment amplitude is determined by the previously set iteration step size. Apply the updated target back-gate voltage to the back-gate terminal of the target transistor again, and repeat the above steps until the iteration termination condition is met.

[0093] Figure 1 In the method of, when specifically implemented, first simulate the single-transistor characteristics of the MOS transistor with ICTAT current output, and obtain the output characteristic curve of the MOS transistor with ICTAT current output in a wide temperature range, such as Figure 3 shown. Determine the temperature coefficient of the transistor before regulation according to the output characteristic curve of the MOS transistor with ICTAT current output in a wide temperature range.

[0094] Then scan the regulation effect of the back-bias voltage on the output characteristic curve of the MOS transistor in a wide temperature range, such as Figure 4 shown. Determine the back-bias voltage when the output transistor reaches an ICTAT current temperature coefficient that matches the IPTAT temperature coefficient.

[0095] The zero temperature coefficient voltage of the bandgap circuit is divided to derive a suitable Vref as the back gate voltage of the MOS tube. By continuously iteratively optimizing the back gate voltage of the transistor, the output current of the MOS tube reaches the required size, and the two currents and outputs have a zero temperature coefficient, that is, the current remains constant at different temperatures. The final structure is as follows Figure 5 shown.

[0096] Through the description of the above embodiments, the solution proposed by the present invention is not only applicable to the bandgap self-biased output of zero temperature coefficient current, but can also be applied to the design of other analog circuits. Under the premise that the Vgs and Vds voltages cannot be changed, the output current can reach the target temperature coefficient through the back gate voltage regulation circuit. Determine the appropriate transistor type according to the circuit structure. Since the bandgap generates a positive bias, the nmos transistor uses a flip well structure, and the pmos transistor uses a conventional well structure. Perform a large number of simulations on MOS devices to determine the fixed V gs 、V ds Under the condition of wide temperature range, the back bias voltage V of MOS tubes of different sizes b For current I d The control effect is to determine the target current size, the transistor size of the temperature coefficient, and the bias voltage. The bandgap circuit output is divided and designed to be converted into the target back-gate voltage through circuit elements such as a resistor network. The back-bias voltage generated by the bandgap is applied to the back-gate port of the MOS tube in the circuit. The output current of the MOS tube of the monitoring circuit is continuously fed back and iterated to optimize the size of the transistor and the back-gate voltage until the output current reaches the required size and target temperature coefficient. Stable current output helps to improve the performance of the entire circuit system, so that it can maintain a good operating state under various working conditions. Compared with the traditional bandgap current control method, the present invention uses the bandgap self-biased back-biased method to output zero temperature coefficient current, without the need to design an additional compensation circuit, and can achieve better temperature performance, reducing the complexity and cost of circuit design. In addition, the present invention obtains reference voltages of different sizes by dividing the reference voltage generated by the bandgap circuit, provides a flexible back-bias voltage, provides more options for circuit design, and also provides an effective solution for the design and optimization of other analog circuits.

[0097] Based on the same idea, the present invention also provides a device for controlling back bias to output zero temperature coefficient current, and the device can output zero temperature coefficient current by using the method for controlling back bias to output zero temperature coefficient current in the above embodiment.

[0098] Although the present invention has been described in connection with the various embodiments, however, in the process of implementing the claimed invention, those skilled in the art can understand and realize other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0099] Although the present invention has been described in connection with specific features and their embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of the present invention. Accordingly, the present specification and the drawings are merely exemplary illustrations of the invention defined by the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A method for controlling the output of a zero temperature coefficient current in a back bias, characterized in that, The method includes: Configuring a bandgap reference circuit; Simulating a target transistor in the bandgap reference circuit to determine a transistor size and a bias voltage that meet preset conditions; Performing voltage division processing on the bandgap reference circuit to determine a target backgate voltage; Applying the target backgate voltage to the backgate terminal of the target transistor, iteratively updating the transistor size and the target backgate voltage, and outputting a current that meets the zero temperature coefficient requirement.

2. The method for controlling the output of a zero temperature coefficient current with back bias according to claim 1, wherein The simulating a target transistor in the bandgap reference circuit to determine a transistor size and a bias voltage that meet preset conditions includes: Performing a wide temperature range simulation on the target transistor, fixing the gate-source voltage and the drain-source voltage, and obtaining regulation data of the back-bias voltage on the drain current corresponding to transistors of different sizes; Collecting and analyzing the regulation data to determine a transistor size and a bias voltage that meet preset conditions; the preset conditions at least include a target current magnitude and a target temperature coefficient.

3. The method for controlling the output of a zero temperature coefficient current with back bias according to claim 1, characterized in that The performing voltage division processing on the bandgap reference circuit to determine a target backgate voltage includes: Performing voltage division on the zero temperature coefficient voltage through a resistor network to determine a target backgate voltage for regulating the backgate of the target transistor.

4. The method for controlling the output of a zero temperature coefficient current with back bias according to claim 1, wherein The applying the target backgate voltage to the backgate terminal of the target transistor, iteratively updating the transistor size and the target backgate voltage, and outputting a current that meets the zero temperature coefficient requirement includes: Applying the voltage-divided zero temperature coefficient voltage to the backgate port of the target transistor in the bandgap reference circuit; Monitoring the output current of the target transistor, and through iterative optimization of the transistor size and the target backgate voltage, making the output current reach a preset magnitude and the temperature coefficient approach zero, and determining that the sum of the two output currents is a constant current with a zero temperature coefficient.

5. The method for controlling the output of a zero temperature coefficient current with back bias according to claim 2, wherein The configured bandgap reference circuit at least includes: A first current generation circuit, a reference voltage generation circuit, a zero temperature coefficient current generation circuit, and a second current generation circuit; The first current generation circuit is used to generate a positive temperature coefficient current, and the second current generation circuit is used to generate a negative temperature coefficient current; Determining a zero temperature coefficient current by using the positive temperature coefficient current, the zero temperature coefficient voltage output by the reference voltage generation circuit, and the negative temperature coefficient current.

6. The method for controlling the output of a zero temperature coefficient current with back bias according to claim 5, characterized in that, Before the simulating a target transistor in the bandgap reference circuit to determine a transistor size and a bias voltage that meet preset conditions, it further includes: According to the circuit structure of the bandgap reference circuit, an NMOS transistor in the bandgap reference circuit uses a flipped well structure, and a PMOS transistor in the bandgap reference circuit uses a conventional well structure.

7. The method for controlling the output of a zero temperature coefficient current in a back bias according to claim 5, characterized in that Converting the zero temperature coefficient voltage into a negative temperature coefficient current through a resistor and a single-transistor circuit; Adding the positive temperature coefficient current and the negative temperature coefficient current to form a synthesized current.

8. The method for controlling the output of a zero temperature coefficient current by back bias according to claim 7, wherein The applying the target backgate voltage to the backgate terminal of the target transistor, iteratively updating the transistor size and the target backgate voltage, and outputting a current that meets the zero temperature coefficient requirement includes: Apply the zero temperature coefficient voltage after voltage division to the back-gate port of the target transistor in the bandgap reference circuit, construct a feedback loop to iteratively optimize the back-gate voltage value, so that the synthesized current maintains the zero temperature coefficient characteristic in a wide temperature range.

9. The method for controlling the back bias to output a zero temperature coefficient current according to claim 5, wherein The regulation data at least includes the regulation effect of different back-bias voltages on the output characteristic curve of the target transistor; Collect and analyze the regulation data to determine the transistor size and bias voltage that meet the preset conditions, including: Establish a mapping relationship between the back-bias voltage and the negative temperature coefficient current according to the regulation effect of different back-bias voltages on the output characteristic curve of the target transistor; According to the mapping relationship, determine the back-bias voltage value that makes the temperature coefficients of the positive temperature coefficient current and the negative temperature coefficient current match.

10. An apparatus for controlling a back bias to output a zero temperature coefficient current, characterized in that, The device outputs a zero temperature coefficient current by using the method for controlling the back-bias to output a zero temperature coefficient current according to any one of claims 1-9.

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