circuit boards

Abstract

The present application provides a circuit board that can be applied to the field of circuit board technology. The circuit board includes: a universal substrate; a clock unit and multiple open acceleration modules, which are arranged on the universal substrate; a switching unit, which is arranged on the universal substrate and connected to the clock unit and the multiple open acceleration modules, and is configured to: receive a first clock signal from the clock unit, and based on the first clock signal, exchange data with the multiple open acceleration modules through a first port of the switching unit; when the data transmission volume of the first port of the switching unit meets a predetermined condition, send a clock control signal to the clock unit to control the clock unit to provide a second clock signal to the switching unit; and based on the first clock signal and the second clock signal, exchange data with the multiple open acceleration modules through the first port and the second port of the switching unit, respectively.

Description

Technical Field

[0001] The present application relates to the technical field of circuit boards, and in particular to a circuit board. Background Art

[0002] As a standardized acceleration module, the Open Accelerator Module (OAM) is widely used in artificial intelligence (AI) servers due to its excellent compatibility and scalability. However, in related technologies, the circuits used for data exchange between multiple OAMs are highly complex, unreliable, difficult to maintain, resource-intensive, and lack real-time performance. Summary of the Invention

[0003] In view of the above problems, the present application provides a circuit board.

[0004] According to the first aspect of the present application, a circuit board is provided, comprising: a universal substrate; a clock unit and a plurality of open acceleration modules, which are arranged on the universal substrate; a switching unit, which is arranged on the universal substrate and connected to the clock unit and the plurality of open acceleration modules, and is used to: receive a first clock signal from the clock unit, and based on the first clock signal, perform data exchange with the plurality of open acceleration modules through the first port of the switching unit; when the data transmission volume of the first port of the switching unit meets a predetermined condition, send a clock control signal to the clock unit to control the clock unit to provide a second clock signal to the switching unit; based on the first clock signal and the second clock signal, perform data exchange with the plurality of open acceleration modules through the first port and the second port of the switching unit respectively.

[0005] According to an embodiment of the present application, by electrically connecting multiple open acceleration modules to a switching unit on a universal substrate, full interconnection between multiple open acceleration modules can be achieved directly within the board via the switching unit, without relying on external devices to achieve the interconnection of multiple open acceleration modules within the board. This reduces the intermediate links in data transmission, reduces data transmission latency, improves the real-time nature of data transmission and the overall performance of the circuit board, and reduces the complexity of hardware connection links and wiring, reduces the difficulty of troubleshooting, and facilitates maintenance, thereby improving the reliability of data interaction between multiple open acceleration modules. In addition, since there is no need to deploy additional external devices to achieve interconnection between multiple open acceleration modules, the resources required to deploy and maintain external devices can be reduced.

[0006] Furthermore, when the data transmission volume of the first port of the switching unit meets a predetermined condition, the switching unit can control the clock unit to send a second clock signal to the switching unit by sending a clock control signal to the clock unit, thereby enabling the first port and the second port of the switching unit to be used together for data exchange with multiple open acceleration modules. This reduces the amount of data transmitted by the first port of the switching unit, avoids the reduction in the real-time performance of data transmission due to excessive data transmission by the first port of the switching unit, and ensures the timeliness of data exchange between multiple open acceleration modules. Furthermore, because the clock unit is controlled to provide the second clock signal to the switching unit only when the data transmission volume of the first port meets the predetermined condition, the switching unit exchanges data via the second port, reducing the resources consumed by data exchange between multiple open acceleration modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0008] Figure 1 A schematic diagram of a circuit board according to an embodiment of the present application is shown.

[0009] Figure 2 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0010] Figure 3 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0011] Figure 4 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0012] Figure 5 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0013] Figure 6 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0014] Figure 7 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0015] Figure 8 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0016] Figure 9 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0017] Figure 10 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0018] Figure 11 A schematic diagram of a circuit board according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0020] The terms used herein are only for describing specific embodiments and are not intended to limit this application. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0021] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0022] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0023] It should be noted that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like, indicating positions or relationships, are based on the positions or relationships shown in the accompanying drawings and are intended solely for ease of description and simplification of the present application. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present application. The terms "mounted," "connected," and "connected" should be interpreted broadly, and may include, for example, fixed, removable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. The terms "parallel," "perpendicular," and "equal" encompass the described conditions and conditions similar to the described conditions, provided that the range of the similar conditions is within an acceptable range of deviation, as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes both absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism may be, for example, within 5°; "perpendicular" includes both absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity may also be, for example, within 5°. "Equal" includes both absolute equality and approximate equality, where the acceptable deviation range for approximate equality may be, for example, that the difference between the two is less than or equal to 5% of either. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0024] As a mature network technology, Ethernet dominates server data communications. With the rapid growth of data volumes, the requirements for Ethernet transmission speeds and interconnection methods are becoming increasingly stringent. From the early days of 100M Ethernet to today's single-lane 112G Ethernet, technological advancements are driving the continuous improvement of AI server performance.

[0025] In AI servers, a Universal Base Board (UBB) can accommodate multiple open acceleration modules to provide powerful computing power. The open acceleration modules can be used to perform AI computing tasks, while data transmission and exchange require a network. In one implementation, an Ethernet switch can be used to interconnect the open acceleration modules. However, in this implementation, the Ethernet switch is connected to the UBB as an external device to interconnect multiple open acceleration modules. This approach increases the complexity of the system composed of open acceleration modules, the UBB, and the Ethernet switch, as well as the resource consumption caused by interconnecting the open acceleration modules.

[0026] Specifically, the need for an external Ethernet switch increases the complexity of hardware connectivity and management in the server system. Not only does it require additional space to house the switch, but it also requires connecting and configuring network cables, making wiring more difficult and troubleshooting more complex. Furthermore, purchasing and maintaining an external Ethernet switch requires additional resources, including the cost of purchasing the equipment, electricity resources, and subsequent maintenance resources. This increases the resource consumption of the entire AI server system.

[0027] Furthermore, because multiple open acceleration modules are interconnected via traces on a printed circuit board (PCB), interconnection can only be achieved using a single connector method during design. Later modifications can only be made by adding new boards or using an external switch. Furthermore, data transmission from the open acceleration module to the external Ethernet switch and then to the target open acceleration module involves multiple stages, each of which introduces latency, impacting the real-time nature of data transmission and overall system performance.

[0028] In view of this, in order to address the above-mentioned problems such as low application flexibility, data transmission delay, high system complexity and increased resource consumption, the present application provides a circuit board, in which a switching unit is set on a universal substrate to achieve full interconnection of open acceleration modules within the board, thereby solving the above-mentioned problems.

[0029] Figure 1 A schematic diagram of a circuit board according to an embodiment of the present application is shown.

[0030] like Figure 1 As shown, the circuit board of this embodiment can be an AI server, but it should be understood that the present application is not limited to this. In other embodiments of the present application, the circuit board can also be used as other devices.

[0031] In an embodiment of the present application, a circuit board may include a universal baseboard (UBB), a clock unit (TC), a switching unit (SW), and an open acceleration module (OP). The switching unit (SW) and multiple open acceleration modules (OP) are disposed on the universal baseboard (UBB) so that the universal baseboard (UBB) can support the switching unit (SW) and the open acceleration modules (OP). However, the present application is not limited to this embodiment. In another embodiment of the present application, the universal baseboard (UBB) may also be provided with other functional circuits, such as a power supply unit. The power supply unit can be used to supply power to the switching unit (SW) and the open acceleration modules (OP).

[0032] The switching unit SW can be a device for exchanging data. Multiple open acceleration modules OP can be electrically connected to the switching unit SW. For example, the links between the multiple open acceleration modules OP and the switching unit SW can be traces provided on a universal baseboard (UBB). Furthermore, the links between the multiple open acceleration modules OP and the switching unit SW can include high-speed links, for example, which can be used to transmit high-speed signals, such as high-speed Peripheral Component Interconnect Express (PCIe) signals. However, it should be understood that the embodiments of the present application are not limited to this. In another embodiment of the present application, the links between the multiple open acceleration modules OP and the switching unit SW can also include low-speed links other than the high-speed links, for example, which can be used to transmit low-speed signals that are slower than PCIe signals. In this way, the multiple open acceleration modules OP can exchange data via the switching unit SW. For example, the switching unit SW can receive data to be transmitted from a portion of the multiple open acceleration modules OP and, based on the data to be transmitted, send the data to another portion of the multiple open acceleration modules OP. It should be understood that a part of the open acceleration modules OP described therein may be one or more open acceleration modules OP, and correspondingly, another part of the open acceleration modules OP described therein may be one or more open acceleration modules OP. The same applies below and will not be repeated.

[0033] The switching unit SW may include a first port, through which the switching unit SW can exchange data with multiple open acceleration modules OP. For example, the switching unit SW may be electrically connected to a clock unit TC and receive a first clock signal from the clock unit TC. The first clock signal may be used for data exchange between the first port of the switching unit SW and the multiple open acceleration modules OP. For example, the switching unit SW may exchange data with the multiple open acceleration modules OP via the first port of the switching unit SW based on the first clock signal. Specifically, the switching unit SW may control the data transmission timing of the first port of the switching unit SW based on the first clock signal. Furthermore, the switching unit SW may also include a second port. Similar to the first port, the second port of the switching unit SW may also be used for data exchange with multiple open acceleration modules OP. Specifically, the switching unit SW may detect the data transmission volume of the first port of the switching unit SW based on a pre-determined program. If the data transmission volume of the first port of the switching unit SW is detected to meet a predetermined condition, the switching unit SW may send a clock control signal to the clock unit TC to control the clock unit TC to provide the second clock signal to the switching unit SW. The switching unit SW may receive the first clock signal and the second clock signal from the clock unit TC via two different lines, respectively. The second clock signal can be used for the second port of the switching unit SW to exchange data with multiple open acceleration modules OP. For example, the switching unit SW can exchange data with multiple open acceleration modules OP through the second port of the switching unit SW based on the second clock signal. Specifically, the switching unit SW can control the data transmission timing of the second port of the switching unit SW based on the second clock signal, etc. On this basis, the first port and the second port of the switching unit SW can respectively exchange data with multiple open acceleration modules OP. In this way, the first port and the second port of the switching unit SW are both used to exchange data with multiple open acceleration modules OP, which can reduce the amount of data transmitted by the first port of the switching unit SW and avoid the reduction in the real-time performance of data transmission due to excessive data transmitted by the first port of the switching unit SW.

[0034] Furthermore, multiple open acceleration modules OP can be located around the switching unit SW on the universal substrate UBB, thereby shortening the line length between the multiple open acceleration modules OP and the universal substrate UBB as much as possible, simplifying the complexity of the line, and facilitating maintenance.

[0035] Based on this, by placing multiple open acceleration modules OP around a switching unit SW on a universal substrate (UBB) and electrically connecting them to the switching unit SW, full interconnection between the multiple open acceleration modules OP can be achieved directly within the board via the switching unit SW, eliminating the need to rely on external devices to achieve interconnection between the multiple open acceleration modules OP within the board. This reduces the intermediate links in data transmission, reduces data transmission latency, improves the real-time nature of data transmission and the overall performance of the circuit board, and reduces the complexity of hardware connection links and wiring, making troubleshooting easier and facilitating maintenance. This can improve the reliability of data exchange between the multiple open acceleration modules OP. Furthermore, since no additional external equipment is required to achieve interconnection between the multiple open acceleration modules OP, the resources required to deploy and maintain external equipment can be reduced.

[0036] Furthermore, when the data transmission volume of the first port of the switching unit SW meets a predetermined condition, the switching unit SW can control the clock unit TC to send a second clock signal to the switching unit SW by sending a clock control signal to the clock unit TC. This allows the first and second ports of the switching unit SW to be used together for data exchange with multiple open acceleration modules OP, reducing the amount of data transmitted by the first port of the switching unit SW, avoiding a reduction in the real-time performance of data transmission due to excessive data transmission by the first port of the switching unit SW, and ensuring the timeliness of data exchange between multiple open acceleration modules OP. Furthermore, because the clock unit TC is controlled to provide the second clock signal to the switching unit SW only when the data transmission volume of the first port meets the predetermined condition, the switching unit SW performs data exchange via the second port, reducing the resources consumed by data exchange between multiple open acceleration modules OP.

[0037] Optionally, the switching unit SW can also receive data to be sent from a part of the open acceleration modules OP among the multiple open acceleration modules OP via the first port of the switching unit SW based on the first clock signal, and send the data to be sent to another part of the open acceleration modules OP among the multiple open acceleration modules OP based on the data to be sent.

[0038] Specifically, based on the predetermined procedure described above, the switching unit SW can receive data to be transmitted from an open acceleration module OP among multiple open acceleration modules OP that is used to transmit data, and then parse the received data to be transmitted to obtain address information contained in the data to be transmitted. For example, the address information can be the Media Access Control Address (MAC) address in the data frame of the data to be transmitted. The switching unit SW can then, based on the address information, determine the open acceleration module OP from the multiple open acceleration modules OP that is used to receive the data to be transmitted, and transmit the data to the open acceleration module OP. In this way, data exchange between multiple open acceleration modules OP can be achieved directly via the switching unit SW on the universal baseboard (UBB), without the need for an external Ethernet switch. For example, the switching unit SW can utilize technology with single-lane speeds exceeding 200G to meet the requirements for high-data-volume, high-speed transmission between multiple open acceleration modules OP.

[0039] Specifically, the plurality of open acceleration modules OP may include a plurality of first open acceleration modules and a plurality of second open acceleration modules. The data to be sent may include first data to be sent and second data to be sent.

[0040] The switching unit SW can monitor the data transmission volume of the first port of the switching unit SW and, if the data transmission volume of the first port of the switching unit SW is greater than or equal to a predetermined threshold, determine that the data transmission volume of the first port satisfies a predetermined condition, thereby sending a clock control signal to the clock unit TC and receiving a second clock signal from the clock unit TC. Subsequently, upon receiving the first clock signal and the second clock signal, the switching unit SW can receive first data to be transmitted from a portion of the first open acceleration modules among the plurality of first open acceleration modules via the first port of the switching unit SW based on the first clock signal, and send the first data to be transmitted to another portion of the first open acceleration modules based on the first data to be transmitted. Furthermore, based on the second clock signal, the switching unit SW can receive second data to be transmitted from a portion of the second open acceleration modules among the plurality of second open acceleration modules via the second port of the switching unit SW, and send the second data to be transmitted to another portion of the second open acceleration modules based on the second data to be transmitted. In this way, when the data transmission volume of the first port of the switching unit SW is greater than or equal to a predetermined threshold, the switching unit SW can control the clock unit TC to send a second clock signal to the switching unit by sending a clock control signal to the clock unit TC. This allows the first and second ports of the switching unit SW to be used together for data exchange with multiple open acceleration modules OP, reducing the amount of data transmitted by the first port of the switching unit SW, avoiding the reduction in the real-time performance of data transmission due to excessive data transmission by the first port of the switching unit SW, and ensuring the timeliness of data exchange between multiple open acceleration modules OP. Furthermore, because the clock unit TC is controlled to provide the second clock signal to the switching unit SW only when the data transmission volume of the first port is greater than or equal to the predetermined threshold, the switching unit SW performs data exchange via the second port, reducing the resources consumed by data exchange between multiple open acceleration modules OP.

[0041] Figure 2 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0042] exist Figure 2 In the embodiment shown, the circuit board may include a universal substrate UBB, a switching unit SW and an open acceleration module OP. The switching unit SW and a plurality of open acceleration modules OP are arranged on the universal substrate UBB, for example, Figure 2In the figure, the switching unit SW and two open acceleration modules OP are arranged on the universal substrate UBB. It should be understood that this is for illustration only. The present application does not limit the number of open acceleration modules OP provided on the universal substrate UBB, nor does it limit the number of switching units SW provided on the universal substrate UBB. In other embodiments, a larger number of switching units SW and a larger number of open acceleration modules OP may be provided on the universal substrate UBB, which will not be described in detail here. It should be noted that, for ease of illustration, some units of the present application, such as the clock unit, are not shown in some of the following figures. It should be understood that in the embodiments corresponding to the figures that do not show units such as the clock unit, the clock unit, etc. of the present application are included, and will not be described in detail below.

[0043] Multiple open acceleration modules OP can be electrically connected to the switching unit SW. In this way, multiple open acceleration modules OP can exchange data via the switching unit SW. Different from the embodiment described above, for example, in this embodiment, any open acceleration module OP can be electrically connected to the switching unit SW through multiple ports. For example, the multiple ports can include a first port and a second port. Figure 2 It can be seen that the switching unit SW is electrically connected to the open acceleration module OP located on its left side through two ports. However, it should be understood that the embodiment of the present application is not limited thereto. In other embodiments of the present application, the switching unit SW can also be electrically connected to the open acceleration module OP through one port or more than two ports. For example, continue to refer to Figure 2 As can be seen, the switching unit SW can be electrically connected to the open acceleration module OP located on its right side via three ports. In other embodiments, the switching unit SW can also be electrically connected to the open acceleration module OP via four, five, six, or other larger number of ports. Furthermore, the number of ports used by the switching unit SW to connect to different open acceleration modules OP can be the same or different, and this application does not impose any limitation on this.

[0044] Optionally, in one embodiment of the present application, the switching unit SW can parse the data to be sent to obtain the target address information. In this embodiment, the target address information can be the address identifier of the port, specifically the address identifier of the switching unit SW port to which the target open acceleration module is connected. In this way, based on the target address information, multiple first ports for connecting to the target open acceleration module can be determined from all ports for connecting to multiple open acceleration modules OP. Then, data can be transmitted to the target open acceleration module via the port connected to the target open acceleration module. On this basis, since the port can be directly and quickly determined based on the target address information in the data to be sent, data can be sent to the target open acceleration module via the port, thereby improving the timeliness of data transmission. It should be understood that the second port of the switching unit SW has a function similar to that of the first port. For details, please refer to the description of the first port, which will not be repeated here.

[0045] In an embodiment of the present application, a predetermined program can be set to control the operation of the switching unit SW. For example, the predetermined program can configure and manage the port status, data forwarding rules, etc. of the switching unit SW. Management software can be integrated into the operating system of the AI ​​server to monitor the communication status between the open acceleration modules OP and the working status of the switching unit SW. The management software can obtain the workload information, data transmission rate and other parameters of the open acceleration module OP in real time, and dynamically allocate the resources of the switching unit SW based on this information. And the embodiment of the present application is not limited to this. In another embodiment of the present application, the workload information, data transmission rate and other information of the open acceleration module OP can also be obtained in real time by a program set in the switching unit SW, and the resources of the switching unit SW can be dynamically allocated based on this information.

[0046] For example, Figure 2 The open acceleration module OP on the left is used as the open acceleration module OP for sending data. Figure 2 Taking the open acceleration module OP located on the right side of the image as the target open acceleration module for receiving data, in an embodiment of the present application, the switching unit SW can collect data transmission rate information of the target open acceleration module based on a pre-deployed program. For example, the switching unit SW can determine the data transmission volume of the port connected to the target open acceleration module per unit time, and determine the data transmission volume per unit time as the data transmission rate information. For example, the unit time can be 1 second, etc., which is not limited in this application.

[0047] The switching unit SW can then determine a target port from the multiple first ports connected to the target open acceleration module based on the data transmission rate information. For example, if the data transmission rate is higher than a predetermined rate value, a portion of the multiple first ports connected to the target open acceleration module can be determined as target ports; if the data transmission rate is lower than or equal to the predetermined rate value, a portion of the multiple first ports connected to the target open acceleration module can be determined as target ports. Specifically, if the data transmission rate is higher than the predetermined rate value, it can be determined that the data transmission rate to the target open acceleration module during that period is higher, and thus a portion of the specific ports can be determined as target ports; if the data transmission rate is lower than or equal to the predetermined rate value, it can be determined that the data transmission rate to the target open acceleration module during that period is lower, and thus another portion of the specific ports can be determined as target ports. Based on this, the switching unit SW can send data to the target open acceleration module via the target port. In this way, different ports can be used for data transmission according to the different transmission speeds of the open acceleration module OP, achieving flexible scheduling of switching unit SW resources and improving the timeliness of high-speed data transmission.

[0048] And the embodiments of the present application are not limited thereto, the switching unit SW can determine the port quantity information based on the data transmission rate information. For example, the switching unit SW can pre-store a mapping relationship between a predetermined data transmission rate and a predetermined port quantity, for example, the mapping relationship can be in the form of a mapping table. In this way, when the data transmission rate information of the target open acceleration module is collected, the port quantity information corresponding to the data transmission rate information can be queried based on the mapping relationship. Then, the switching unit SW can determine a plurality of target ports corresponding to the port quantity information from a plurality of first ports according to the port quantity information, and send the data to be sent to the target open acceleration module in parallel via the plurality of target ports. For different data transmission rates, different numbers of ports can be used for data transmission, so that a larger number of ports can be used for data transmission for high-speed data, thereby improving the timeliness of data transmission.

[0049] For another example, after a portion of the open acceleration modules OP sends data, the switching unit SW may collect workload information of another portion of the open acceleration modules OP for receiving data. For example, the workload information may be the memory occupancy rate of the open acceleration module OP, etc. For example, such information may be sent by the open acceleration module OP to the switching unit SW via a specific routing, which is not limited in this application. The switching unit SW may then determine priority information based on the workload information. For example, the switching unit SW may sort the open acceleration modules OP for receiving data according to the size of the workload information (e.g., the size of the memory occupancy rate) of the open acceleration modules OP for receiving data, obtain sequence information of the open acceleration modules OP for receiving data, and use the sequence information as priority information for sending data.

[0050] On this basis, for the other open acceleration modules OP waiting to receive data, the switching unit SW can sequentially send data to the other open acceleration modules OP according to the priority information, so that the open acceleration modules OP with relatively low memory usage receive and process data first, and the open acceleration modules OP with relatively high memory usage receive and process data later. In this way, the resources of the open acceleration modules OP with relatively low memory usage can be fully utilized, and the open acceleration modules OP with relatively high memory usage can be prevented from experiencing abnormal conditions (such as failures) due to excessive data processing load in the open acceleration modules OP with relatively high memory usage.

[0051] Figure 3 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0052] exist Figure 3 In the embodiment shown, the circuit board may include a universal substrate UBB, a switching unit SW and an open acceleration module OP. The switching unit SW and a plurality of open acceleration modules OP are arranged on the universal substrate UBB. Figure 3In this embodiment, a switching unit SW and eight open acceleration modules OP are disposed on a universal baseboard UBB. Multiple open acceleration modules OP can be electrically connected to the switching unit SW. Unlike the previously described embodiments, in this embodiment, any of the multiple open acceleration modules OP includes a first port L and a second port H. For example, the first port L and the second port H can be high-speed ports. The first port L and the second port H can be x8 ports, supporting eight differential signal pairs. However, it should be understood that the embodiments of the present application are not limited to this. Other embodiments of the present application can also support other numbers of differential signal pairs, and the present application is not limited in this regard. The first port L can be connected to the switching unit SW. The second port H can be connected to an expansion device Q. For example, the expansion device Q can be a device for connecting to other devices outside the universal baseboard UBB. For example, the expansion device Q can be an expansion connector. The other device can be a server motherboard, an external Ethernet switch, or the like. Thus, through the first port L, the open acceleration modules OP can exchange data via the switching unit SW, improving the timeliness of data exchange between the open acceleration modules OP. Furthermore, through the second port H, the open acceleration module OP can exchange data with the expansion device Q, thereby improving the scalability of the circuit board.

[0053] Further, continue to refer to Figure 3 It can be seen that the first port L and the second port H of any open acceleration module OP are respectively distributed at the edges of different sides of any open acceleration module OP. The second port H of any open acceleration module OP is located at the edge of a side away from the switching unit SW. For example, Figure 3 The second port H of the open acceleration module OP on the left side is located on the left side of the open acceleration module OP, and Figure 3 The second port H of the open acceleration module OP on the middle right side is located on the right side of the open acceleration module OP. For the first port L of any open acceleration module OP, it can be located on an edge other than one side edge. For example, the first port L of any open acceleration module OP can be located on an adjacent side adjacent to the side where the second port H is located, or can be located on an opposite side opposite to the side where the second port H is located, and this application does not limit this. In this way, the second port H that requires an external expansion device is set at a position away from the switching unit SW, so that the second port H can be electrically connected to the expansion device Q without affecting the line between the switching unit SW and the first port L, reducing the complexity of the line for data interaction, facilitating maintenance, and thus improving the reliability of the circuit board.

[0054] Figure 4 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0055] exist Figure 4In the embodiment shown, the circuit board may include a universal substrate UBB, a switching unit SW and an open acceleration module OP. The switching unit SW and a plurality of open acceleration modules OP are arranged on the universal substrate UBB. Figure 4 In the embodiment, the switching unit SW and eight open acceleration modules OP are arranged on a universal substrate UBB. Multiple open acceleration modules OP can be electrically connected to the switching unit SW. Any open acceleration module OP among the multiple open acceleration modules OP includes a first port L and a second port H. Different from the embodiment described above, in this embodiment, the second port H of the open acceleration module OP can be connected to an expansion connector. For example, the connector can be a Quad Small Form-factor Pluggable (QSFP) connector. In this way, the second port H of the open acceleration module OP can be electrically connected to other devices via the expansion connector. Based on this, by using wiring to lead the signal of the second port H of the open acceleration module OP to the expansion connector, the wiring on the universal substrate UBB can be made more flexible, thereby simplifying the complexity of the circuit board wiring and facilitating maintenance.

[0056] Figure 5 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0057] exist Figure 5 In the illustrated embodiment, the circuit board may include a universal baseboard (UBB), switching units (SW), and open acceleration modules (OP). The switching units (SW) and multiple open acceleration modules (OP) are disposed on the universal baseboard (UBB). Specifically, in this embodiment, there are multiple switching units (SW). Any switching unit (SW) can be connected to multiple open acceleration modules (OP). In one embodiment of the present application, if a portion of the multiple switching units (SW) is in an abnormal state, the multiple open acceleration modules (OP) may stop sending data to the abnormal switching units (SW) and instead send the data to be sent to another portion of the multiple switching units (SW). In this way, the other portion of the multiple switching units (SW) may receive data to be sent from the portion of the multiple open acceleration modules (OP) used to send data and, based on the data to be sent, send the data to be sent to another portion of the open acceleration modules (OP). Therefore, if a portion of the switching units (SW) fails, the multiple open acceleration modules (OP) stop sending data to the failed switching units (SW) and switch to the normally functioning switching units (SW) for data exchange, thereby ensuring the timeliness and reliability of data exchange.

[0058] For example, any switching unit SW can monitor the working status of other switching units SW, thereby determining whether other switching units SW are in an abnormal state. For example, multiple switching units SW may include a first switching unit and a second switching unit. The first switching unit belongs to a portion of switching units SW that are in an abnormal state, and the second switching unit belongs to another portion of switching units SW that are normal. When the second switching unit detects that the first switching unit is in an abnormal state, it sends a module control signal to the multiple open acceleration modules OP to control the multiple open acceleration modules OP to stop sending data to the first switching unit, that is, to control the open acceleration modules OP to stop sending data to the switching unit SW in the abnormal state and send data to the normal switching unit SW. Based on this, since, in the event of a failure of the first switching unit, the second switching unit promptly controls the multiple open acceleration modules OP to stop sending data to the failed switching unit SW and switch to the normally functioning switching unit SW for data exchange, the timeliness and reliability of data exchange are guaranteed.

[0059] Figure 6 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0060] exist Figure 6 In the illustrated embodiment, a circuit board may include a universal baseboard (UBB), a switching unit SW, and an open acceleration module OP. The switching unit SW and multiple open acceleration modules OP are disposed on the universal baseboard (UBB). One switching unit SW can be connected to multiple open acceleration modules OP. Unlike the previously described embodiment, in this embodiment, the switching unit SW and multiple open acceleration modules OP are also electrically connected to a controller. The controller may be disposed on the server motherboard. For example, the controller may be a baseboard management controller (BMC). The controller may monitor and control the operating status of the switching unit SW and multiple open acceleration modules OP. For example, the switching unit SW may send a status monitoring signal to the controller, allowing the controller to obtain information about the operating status of the switching unit SW based on the status monitoring signal. This allows the controller to take timely measures if the switching unit SW is in an abnormal state, thereby ensuring timely data exchange between the multiple open acceleration modules OP. For example, the status monitoring signal in this application may be a regularly transmitted watchdog timer (WDT) signal. In a case where the switching unit SW transmits a WDT signal within a predetermined period, it can be determined that the switching unit SW is in an abnormal state.

[0061] Figure 7 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0062] exist Figure 7 In the illustrated embodiment, the circuit board may include a universal baseboard (UBB), a first switching unit SW1, a second switching unit SW2, and a plurality of open acceleration modules OP. The first switching unit SW1, the second switching unit SW2, and the plurality of open acceleration modules OP may be connected to a controller provided on a server mainboard.

[0063] In this embodiment, the first switching unit SW1 and the second switching unit SW2 may be electrically disconnected. The first switching unit SW1 may send a first status monitoring signal to the controller so that the controller determines the working status of the first switching unit SW1 based on the first status monitoring signal. When it is determined that the first switching unit SW1 is in an abnormal state, the controller may send a module control signal to the second switching unit SW2 to send the module control signal to the multiple open acceleration modules OP via the second switching unit SW2 to control the multiple open acceleration modules OP to stop sending data to the first switching unit SW1. Based on this, since, in the event of a failure of the first switching unit SW1, the controller promptly sends a module control signal to the second switching unit SW2 to control the multiple open acceleration modules OP via the second switching unit SW2 to stop sending data to the failed switching unit SW and switch to the normally functioning switching unit SW for data interaction, the timeliness and reliability of data interaction are guaranteed.

[0064] Figure 8 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0065] exist Figure 8 In the illustrated embodiment, the circuit board may include a universal base board (UBB), a first switching unit SW1, a second switching unit SW2, and multiple open acceleration modules OP. The first switching unit SW1, the second switching unit SW2, and the multiple open acceleration modules OP may be connected to a controller provided on the server motherboard. Unlike the previously described embodiment, in this embodiment, the first switching unit SW1 and the second switching unit SW2 may be electrically connected. In this manner, the first switching unit SW1 may also transmit a second status monitoring signal to the second switching unit SW2.

[0066] The second switching unit SW2 can, upon receiving the second status monitoring signal, generate a status indication signal for indicating the working status of the first switching unit SW1 and send the status indication signal to the controller. The controller can determine the working status of the first switching unit SW1 based on the status indication signal and the first status monitoring signal. For example, the controller can determine that the first switching unit SW1 is in an abnormal state when the status indication signal indicates that the first switching unit SW1 is in an abnormal state and the first status monitoring signal indicates that the first switching unit SW1 is in an abnormal state. Since the abnormal condition of the controller itself may cause the accuracy of monitoring the working status of the first switching unit SW1 to be reduced, the accuracy of the monitored working status of the first switching unit SW1 can be ensured by using the second switching unit SW2 to simultaneously monitor the working status of the first switching unit SW1.

[0067] On this basis, if the first switching unit SW1 is determined to be in an abnormal state, the controller can send a module control signal to the multiple open acceleration modules OP via the second switching unit SW2 to control the multiple open acceleration modules OP to stop sending data to the first switching unit SW1. Based on this, the operating status of the first switching unit SW1 is simultaneously monitored by the controller and the second switching unit SW2. Therefore, if the first switching unit SW1 is in an abnormal state, the multiple open acceleration modules OP can be promptly controlled to exchange data through the second switching unit SW2, ensuring the timeliness and reliability of data exchange.

[0068] Figure 9 It should be noted that, in order to clearly illustrate the connection lines between the switching unit and the multiple open acceleration modules, different grayscale connection lines are used to illustrate the connection lines between the switching unit and the open acceleration modules.

[0069] exist Figure 9 In the illustrated embodiment, the switching unit SW also includes a switching expansion port. The switching expansion port can be electrically connected to an expansion device Q. In this way, the expansion port of the switching unit SW can be electrically connected to other devices via an expansion connector. Based on this, by using wiring to route signals from the expansion port of the switching unit SW to the expansion connector, wiring on the universal baseboard (UBB) can be made more flexible, thereby simplifying the complexity of circuit board wiring and facilitating maintenance.

[0070] In the embodiment of the present application, a plurality of open acceleration modules OP can be arranged on the first and second sides of the switch unit SW. The switch expansion port is arranged on the third and / or fourth sides of the switch unit SW. For example, referring to Figure 9 It can be seen that multiple open acceleration modules OP can be respectively set in the switching unit SW. Figure 9 The left and right sides of the switching unit SW, and the switching expansion interface is set on the upper and lower sides of the switching unit SW. Specifically, there can generally be two switching units SW, and the two switching units SW can be interconnected through a high-speed line, for example, through 8 interconnection ports, but not limited to this. In this way, redundancy can be achieved through the two switching units SW, so that when one switching unit SW fails, the data interaction of multiple open acceleration modules OP can be realized through the other switching unit SW, thereby improving the timeliness of data interaction, and avoiding the wiring on the circuit board being too complicated due to the excessive number of switching units SW. Since the switching units SW need to be electrically connected to each other in order to transmit status monitoring signals to each other to monitor each other's working status, the switching expansion port of any switching unit SW among the multiple switching units SW is set at the edge of a side away from the other switching units SW. In this way, it is possible to avoid excessive wiring complexity, ensure the scalability of the circuit board by switching the expansion port, and simultaneously monitor the working status of the other switching unit SW through the controller and one switching unit SW. Therefore, when one of the two switching units SW is in an abnormal state, the multiple open acceleration modules OP can be promptly controlled to perform data exchange through the second switching unit SW2, thereby ensuring that the communication between the multiple open acceleration modules OP is not affected, ensuring the timeliness and reliability of data exchange, and reducing the risk of system downtime due to failure of the switching unit SW.

[0071] Figure 10 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0072] exist Figure 10 In the illustrated embodiment, the circuit board may further include a power supply unit VC, a clock unit TC, and a signal processing unit PC, disposed on a universal base board (UBB). The power supply unit VC can supply power to the switching unit SW. The clock unit TC can provide a clock signal to the switching unit SW. Thus, by adding the power supply unit VC and clock unit TC for the switching unit SW to the circuit board, the stable operation of the switching unit SW can be ensured. The signal processing unit PC can send a reset signal to the switching unit SW to control the switching unit SW to reset. This is not limited to this embodiment; the signal processing unit PC may also send other signals to control the switching unit SW to ensure stable operation of the switching unit SW.

[0073] Figure 11 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0074] exist Figure 11The power supply unit VC, clock unit TC and signal processing unit PC are provided on the universal base board UBB. For example, the power supply unit VC can receive the initial power signal via the power interface and perform voltage conversion and other processing operations on the initial power signal to obtain a power signal for providing to the switching unit SW. For example, the voltage conversion process may include voltage reduction, etc., which is not limited in this application. Then, the power supply unit VC can provide the processed power signal to the switching unit SW to power the switching unit SW. It should be noted that in Figure 11 Only one power supply unit VC is shown in the figure, but it should be understood that the embodiment of the present application is not limited to this. In another embodiment of the present application, more power supply units VC can be set, and multiple power supply units VC can provide different power signals to the switching unit SW. The present application does not limit this.

[0075] The clock unit TC can be electrically connected to the switch unit SW. In this embodiment, the clock unit TC can be electrically connected to the switch unit SW via two lines. One line can be used to provide the core clock required for the operation of the switch unit SW itself, namely a 100M (megabit) clock, and the other line can be used to provide a high-precision, low-jitter network clock to the switch unit SW, namely a 156.25M clock. This application is not limited to this. In this embodiment, more lines can be used to electrically connect the clock unit TC and the switch unit SW to transmit more clock signals, which is not limited in this application.

[0076] The signal processing unit PC can be connected to the switching unit SW via an uplink connector or other device. For example, the signal processing unit PC can be electrically connected to the switching unit SW via the uplink connector to provide management signals such as a reset signal to the switching unit SW, thereby ensuring the stability of the switching unit SW. The management signals can, for example, be two-wire serial bus (Inter-Integrated Circuit, I2C) signals. Furthermore, each switching unit SW can be equipped with independent circuits such as a clock unit TC and a power supply unit VC, but this application does not limit this.

[0077] Based on the above solution, in a high-performance computing cluster, a large amount of data exchange and communication is required between multiple computing nodes. Applying the technology of this application to a high-performance computing cluster, a switching unit SW can be integrated on the mainboard of the computing node to achieve full intra-board interconnection between nodes, thereby reducing system complexity and improving data transmission efficiency.

[0078] In a data center network, by integrating a switching unit SW on a server motherboard, dependence on external devices for data interaction can be reduced, the network architecture of the data center can be optimized, resource consumption can be reduced, and network performance can be improved.

[0079] Furthermore, the hardware architecture can be appropriately adjusted to suit different application scenarios. For example, the appropriate switch unit (SW) and port number can be selected based on the scale and needs of a high-performance computing cluster or data center. Furthermore, the pre-deployed drivers and management software can be optimized to effectively manage and control different devices.

[0080] Those skilled in the art will appreciate that the features described in the various embodiments of this application may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in this application. In particular, the features described in the various embodiments of this application may be combined and / or coupled in various ways without departing from the spirit and teachings of this application. All such combinations and / or couplings fall within the scope of this application.

[0081] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A circuit board, characterized in that: include: Universal substrate; A clock unit and a plurality of open acceleration modules are arranged on the universal substrate; A switching unit is provided on the universal substrate and is connected to the clock unit and the plurality of open acceleration modules, and is used to: receiving a first clock signal from the clock unit, and performing data exchange with the plurality of open acceleration modules through the first port of the switching unit based on the first clock signal; When the data transmission volume of the first port of the switching unit meets a predetermined condition, sending a clock control signal to the clock unit to control the clock unit to provide a second clock signal to the switching unit; Based on the first clock signal and the second clock signal, data is exchanged with the multiple open acceleration modules through the first port and the second port of the switching unit respectively.

2. The circuit board according to claim 1, wherein: The switching unit is further configured to: Based on the first clock signal, data to be sent is received from a part of the multiple open acceleration modules via the first port of the switching unit, and based on the data to be sent, the data to be sent is sent to another part of the multiple open acceleration modules.

3. The circuit board according to claim 2, wherein: There are multiple switching units; any of the switching units is connected to the multiple open acceleration modules; When a part of the plurality of switching units is in an abnormal state, the plurality of open acceleration modules stop sending the to-be-sent data to the part of the switching units; Another part of the switching units among the plurality of switching units is used for: receiving the data to be sent from the part of the open acceleration modules; Based on the data to be sent, the data to be sent is sent to the other part of the open acceleration module.

4. The circuit board according to claim 3, wherein: The part of the switching units includes a first switching unit; the other part of the switching units includes a second switching unit; The second switching unit is configured to send a module control signal to the plurality of open acceleration modules when the first switching unit is in an abnormal state, so as to control the plurality of open acceleration modules to stop sending the to-be-sent data to the first switching unit.

5. The circuit board according to claim 4, characterized in that The plurality of switching units are further connected to a controller provided on a server mainboard; The first switching unit is configured to: sending a first status monitoring signal to the controller, so that the controller determines the working status of the first switching unit based on the first status monitoring signal; When it is determined that the first switching unit is in an abnormal state, the module control signal is sent to the second switching unit, so as to send the module control signal to the multiple open acceleration modules via the second switching unit, so as to control the multiple open acceleration modules to stop sending the to-be-sent data to the first switching unit.

6. The circuit board according to claim 5, characterized in that The first switching unit is further configured to send a second status monitoring signal to the second switching unit; The second switching unit is further configured to: When the second status monitoring signal is received, sending a status indication signal to the controller, so that the controller determines the working status of the first switching unit based on the status indication signal and the first status monitoring signal; When it is determined that the first switching unit is in an abnormal state, the module control signal is sent to the multiple open acceleration modules to control the multiple open acceleration modules to stop sending the to-be-sent data to the first switching unit.

7. The circuit board according to any one of claims 2 to 6, wherein: The plurality of open acceleration modules include a plurality of first open acceleration modules and a plurality of second open acceleration modules; the data to be sent include first data to be sent and second data to be sent; The switching unit is further configured to: monitoring the data transmission volume of the first port of the switching unit; When the data transmission volume of the first port of the switching unit is greater than or equal to a predetermined threshold, sending the clock control signal to the clock unit and receiving the second clock signal from the clock unit; Upon receiving the first clock signal and the second clock signal, receiving first data to be sent from a portion of the plurality of first open acceleration modules via a first port of the switching unit based on the first clock signal, and sending the first data to be sent to another portion of the plurality of first open acceleration modules based on the first data to be sent; Based on the second clock signal, second data to be sent is received from a part of the multiple second open acceleration modules via the second port of the switching unit, and based on the second data to be sent, the second data to be sent is sent to another part of the multiple second open acceleration modules.

8. The circuit board according to any one of claims 2 to 6, wherein: The target open acceleration modules in the other part of the open acceleration modules are connected to the multiple first ports of the switching unit; The switching unit is further configured to: Collecting data transmission rate information of the target open acceleration module; determining a target port from the plurality of first ports based on the data transmission rate information; The data to be sent is sent to the target open acceleration module via the target port.

9. The circuit board according to claim 8, wherein: The switching unit is further configured to: Determining port quantity information based on the data transmission rate information; determining a plurality of target ports from the plurality of first ports according to the port quantity information; The data to be sent is sent in parallel to the target open acceleration module via the multiple target ports.

10. The circuit board according to claim 8, wherein: The switching unit is further configured to: Parsing the data to be sent to obtain target address information; Based on the target address information, the plurality of first ports for connecting to the target open acceleration module are determined from the ports of the switching unit for connecting to the plurality of open acceleration modules.

11. The circuit board according to any one of claims 2 to 6, characterized in that: The switching unit is further configured to: Collecting workload information of the other part of the open acceleration modules; determining priority information based on the workload information; According to the priority information, the data to be sent is sent to the other part of the open acceleration modules in sequence.

12. The circuit board according to any one of claims 1 to 6, characterized in that: The switching unit further comprises a switching expansion port; the switching expansion port is used to connect an expansion device; The plurality of open acceleration modules are arranged on a first side and a second side opposite to the switching unit; the switching expansion port is arranged on a third side and / or a fourth side opposite to the switching unit.

13. The circuit board according to claim 12, wherein: There are multiple switching units; The switch expansion port of any switch unit among the plurality of switch units is arranged at an edge of a side away from other switch units.

14. The circuit board according to any one of claims 1 to 6, characterized in that: Any open acceleration module among the plurality of open acceleration modules comprises a first port and a second port; the first port of any open acceleration module is used to connect to the switching unit, and the second port is used to connect to the expansion device; The first port and the second port of any open acceleration module are respectively distributed on the edges of different sides of any open acceleration module; the second port of any open acceleration module is located at the edge of a side away from the switching unit; the first port of any open acceleration module is located at the edge other than the edge of the side.

15. The circuit board according to any one of claims 1 to 6, characterized in that: Also included is: a power supply unit, configured to supply power to the switching unit; The signal processing unit is used to send a reset signal to the switching unit to control the switching unit to reset.

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