Mainboard power management circuit, main and backup power supply switching method and chip

Abstract

Embodiments of the present disclosure provide a mainboard power management circuit, a main and standby power switching method and a chip. The circuit comprises a first switch tube, a second switch tube, a first NOT gate, a second NOT gate, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a main power supply and a standby power supply. The source of the first switch tube is connected to the main power supply, the drain is connected to a chip power supply input end, and the gate is connected to the first resistor. The main power supply and the first resistor are connected to the first NOT gate, one end of the second resistor is grounded, and the other end is connected to the main power supply. The source of the second switch tube is connected to the standby power supply, the drain is connected to the chip power supply input end, and the gate is connected to the fourth resistor. The fourth resistor is connected to the fifth resistor and the sixth resistor, the other end of the sixth resistor is grounded, the other end of the fifth resistor is connected to the second NOT gate, and the first NOT gate and the second NOT gate are connected to the third resistor.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of power supply technology for electronic devices, specifically to a motherboard power management circuit, a main / backup power switching method, and a chip. Background Technology

[0002] The motherboard is the basic platform that connects various hardware devices in a computer (such as CPU, memory, storage devices, graphics card, peripherals, etc.). It provides various interfaces and slots, and realizes data exchange and communication between various hardware components through its built-in bus system (such as PCIe, SATA, USB, etc.). It is also responsible for allocating and managing the computer's power supply.

[0003] Motherboards typically have two power supplies. During normal operation, the 3.3V main power supply provides power to the various peripherals on the motherboard, handling a significant current load. However, in the power-off state, some basic functions still need to be maintained, such as saving settings and maintaining communication. In this case, the 3.3V standby power supply provides power, with a smaller current requirement. For certain specific boards (such as the ZX-200 chip), although the standby power requirement is small in the power-off state, the power demand increases significantly after system startup. Therefore, when designing these boards, a higher-power power supply chip needs to be designed for the standby power supply to ensure that the demand is met after startup.

[0004] In expansion cards, according to the PCIe protocol standard, the gold fingers can only provide a single power pin. When multiple PCIe slots are connected through an expansion card, the power provided by a single power pin is insufficient to meet the power requirements of multiple PCIe slots. Currently, the common practice is to run an additional standby power cable from the motherboard to the expansion board, but this increases cost and occupies PCB area. Summary of the Invention

[0005] To provide sufficient and stable power to the motherboard and expansion cards, the embodiments described herein provide a motherboard power management circuit, a primary / backup power switching method, and a chip.

[0006] According to a first aspect of this disclosure, a motherboard power management circuit is provided, comprising: a first switching transistor, a second switching transistor, a first NOT gate, a second NOT gate, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a main power supply, and a standby power supply; the source of the first switching transistor is connected to the main power supply, the drain is connected to the chip power input terminal, and the gate is connected to the first resistor; the first NOT gate is connected between the main power supply and the first resistor, one end of the second resistor is grounded, and the other end is connected to the main power supply; the source of the second switching transistor is connected to the standby power supply, the drain is connected to the chip power input terminal, and the gate is connected to the fourth resistor; the fourth resistor is connected to the fifth resistor and the sixth resistor respectively, the other end of the sixth resistor is grounded, the other end of the fifth resistor is connected to the second NOT gate, and the third resistor is connected between the first NOT gate and the second NOT gate.

[0007] In some embodiments of this disclosure, when the motherboard is powered off, the main power supply outputs a low level, which becomes a high level after passing through the first NOT gate, turning off the first switching transistor; the high level output by the first NOT gate becomes a low level after passing through the third resistor and the second NOT gate, turning on the second switching transistor, and the standby power supply supplies power to the chip through the second switching transistor.

[0008] In some embodiments of this disclosure, when the motherboard is powered on, the main power supply outputs a high level, which becomes a low level after passing through the first NOT gate, turning on the first switching transistor, and the main power supply supplies power to the chip through the first switching transistor; the low level output by the first NOT gate becomes a high level after passing through the second NOT gate, turning off the second switching transistor.

[0009] In some embodiments of this disclosure, the fifth resistor and the sixth resistor form a voltage divider circuit to divide the high level output of the second NOT gate so that the gate voltage of the second switch is less than the turn-off threshold.

[0010] In some embodiments of this disclosure, both the first switch and the second switch are PMOS transistors.

[0011] In some embodiments of this disclosure, both the first NOT gate and the second NOT gate are Schmitt NOT gates.

[0012] In some embodiments of this disclosure, the chip power input is connected to an expansion board via gold fingers.

[0013] According to a second aspect of this disclosure, a method for switching between primary and backup power supplies is provided, executed based on the motherboard power management circuit described in the first aspect of the present disclosure, the method comprising:

[0014] When the motherboard is powered off, the low level output by the main power supply becomes a high level after passing through the first NOT gate, turning off the first switching transistor; the high level output by the first NOT gate becomes a low level after passing through the third resistor and the second NOT gate, turning on the second switching transistor, and the standby power supply powers the chip through the second switching transistor; when the motherboard is powered on, the high level output by the main power supply becomes a low level after passing through the first NOT gate, turning on the first switching transistor, and the main power supply powers the chip through the first switching transistor; the low level output by the first NOT gate becomes a high level after passing through the second NOT gate, turning off the second switching transistor.

[0015] In some embodiments of this disclosure, the fifth resistor and the sixth resistor form a voltage divider circuit to divide the high level output of the second NOT gate, so that the gate voltage of the second switch is less than the turn-off threshold.

[0016] According to a third aspect of this disclosure, a chip is provided. The chip includes a motherboard power management circuit according to a first aspect of this disclosure.

[0017] According to the embodiments of the present disclosure, the motherboard power management circuit and the main / standby power switching method utilize the simple logic control of NOT gates and the cooperation of switching transistors to smoothly achieve power switching control between power on and power off states. This simplifies the design of the motherboard power management circuit, reduces design complexity, and eliminates the need for additional high-power power chips and additional power lines, thereby saving costs and PCB space. Furthermore, the design of the voltage divider circuit significantly improves the stability and system reliability during power switching. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0019] Figure 1 This is a schematic diagram of the motherboard power management circuit according to an embodiment of the present disclosure;

[0020] Figure 2 This is a schematic flowchart of a primary / backup power switching method 200 according to an embodiment of the present disclosure.

[0021] It should be noted that the elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0024] In computers and electronic devices, the "main power supply" and "standby power supply" are responsible for different power supply tasks. The main power supply provides energy when the device is powered on, and typically has multiple different output voltages (e.g., 3.3V, 5V, 12V, etc.) to provide power according to the needs of different hardware components. The standby power supply continues to provide power even when the device is off or in standby mode, maintaining the operation of some low-power devices, such as clock chips (RTC), remote wake-up functions, and system management chips. In summary, the main power supply and standby power supply are two complementary power systems, providing the necessary power in different operating states of the device.

[0025] To meet the power requirements of the system during shutdown and power-on, embodiments of this disclosure propose a motherboard power management circuit that can automatically switch between main power and standby power during system shutdown and power-on. This circuit can meet the power requirements of the chip after startup and maintain a smooth power transition without the need for additional wiring to an expansion board, thus reducing wiring complexity and space occupation.

[0026] Figure 1 This is a schematic diagram of the motherboard power management circuit according to an embodiment of the present disclosure. (Refer to...) Figure 1As shown, the motherboard power management circuit includes: a first switching transistor Q1, a second switching transistor Q2, a first NOT gate, a second NOT gate, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a main power supply P3V3, and a standby power supply P3V3_STBY; the source S of the first switching transistor Q1 is connected to the main power supply P3V3, the drain D is connected to the chip power input terminal IN, and the gate G is connected to the first resistor R1; the first NOT gate is connected between the main power supply P3V3 and the first resistor R1; one end of the second resistor R2 is grounded, and the other end is connected to the main power supply P3V3; the source S of the second switching transistor Q2 is connected to the standby power supply P3V3_STBY, the drain D is connected to the chip power input terminal IN, and the gate G is connected to the fourth resistor R4; the fourth resistor R4 is connected to the fifth resistor R5 and the sixth resistor R6 respectively, the other end of the sixth resistor R6 is grounded, the other end of the fifth resistor R5 is connected to the second NOT gate, and the third resistor R3 is connected between the first NOT gate and the second NOT gate.

[0027] In some embodiments of this disclosure, both the first switch Q1 and the second switch Q2 are PMOS transistors. Both the first NOT gate and the second NOT gate are Schmitt NOT gates. Figure 1 In the motherboard power management circuit shown, the first and second NOT gates use Schmitt-Negative gates 74LVC1G14, and the first switching transistor Q1 and the second switching transistor Q2 use PMOS transistors CJQ4407. The resistor values ​​are set as follows: R1 = 33Ω, R2 = 2KΩ, R3 = 33Ω, R4 = 33Ω, R5 = 1KΩ, and R6 = 2KΩ. These values ​​can be adjusted according to the actual application requirements of the chip; this solution does not impose any limitations on this.

[0028] The gate of a PMOS transistor is used to control its on / off state, which is controlled by the gate-source voltage (V_GS). Specifically, when the gate-source voltage (V_GS) is lower than the source voltage, the PMOS transistor is on. When the gate-source voltage (V_GS) is greater than or equal to the source voltage, the PMOS transistor is off. Figure 1 In the motherboard power management circuit shown, the first NOT gate inverts the output signal of P3V3, thereby controlling the switching of PMOS transistor Q1. The second NOT gate inverts the output signal of the first NOT gate, thereby controlling the switching of PMOS transistor Q2. PMOS transistor Q1 controls the on / off state of the P3V3 power supply. When the system is powered on, Q1 is on, and the main power supply provides power to the chip; when the system is powered off, Q1 is off, and the main power supply is cut off. PMOS transistor Q2 controls the on / off state of the standby power supply. When the system is powered on, Q2 is off, and the standby power supply is disconnected; when the system is powered off, Q2 is on, and the standby power supply 3V3_STBY supplies power to the chip. R5 and R6 are voltage divider resistors used to smooth the turn-off process of Q2 and avoid abrupt changes during power switching.

[0029] Because the Schmitt-NOT gate combines the functions of a Schmitt trigger and a NOT gate, it exhibits hysteresis, meaning it has different response thresholds for high and low input signal levels. When the input signal changes from low to high, it triggers one threshold; when the input signal changes from high to low, another threshold controls the output change. This avoids frequent output changes when the input signal fluctuates, thus providing a more stable output.

[0030] Figure 1 The power management circuit shown is designed to handle the switching of chip power supply during motherboard power-on and power-off states. Specifically, when the motherboard is powered off, the main power supply P3V3 outputs a low level (0V), which becomes a high level after passing through the first NOT gate, turning off the first switching transistor Q1. At this time, the shutdown of Q1 disconnects the system's main power supply, thus preventing power from being supplied to the chip through P3V3. The high level output from the first NOT gate, after passing through the third resistor R3 and the second NOT gate, becomes a low level, turning on the second switching transistor Q2. The standby power supply 3V3_STBY then supplies power to the chip through the second switching transistor Q2. This ensures that the chip can continue to receive standby voltage even when the system is powered off.

[0031] When the motherboard is powered on, the main power supply P3V3 outputs a high level (3.3V), which becomes a low level after passing through the first NOT gate, turning on the first switching transistor Q1. The main power supply then supplies power to the chip through the first switching transistor Q1. The low level output from the first NOT gate becomes a high level after passing through the second NOT gate, turning off the second switching transistor Q2.

[0032] The fifth resistor R5 and the sixth resistor R6 form a voltage divider circuit to divide the high-level output of the second NOT gate, ensuring that the gate voltage of the second switch is below the turn-off threshold. Even if the high-level signal at the NOT gate output is present, the voltage divider effect of R5 and R6 prevents the gate voltage of Q2 from completely reaching its turn-off threshold, ensuring that Q2 is not completely turned off. This means that Q2 will still conduct a small amount of current, rather than completely blocking it, resulting in a "slow" turn-off process. In this way, the current will not be completely cut off in a short time, but will gradually decrease, thus avoiding a step change in voltage. In other words, the turn-off process of Q2 becomes smoother, and the change in power supply voltage becomes smoother, avoiding power supply noise or interference caused by voltage surges.

[0033] When the system shuts down again, the P3V3 output returns to a low level, Q1 turns off, Q2 turns on, and the 3V3_STBY power supply resumes powering the chip. This ensures that the standby power supply can still stably power the chip even when the system is off. This circuit effectively manages the switching between main power and standby power by using switching transistors, NOT gates, and resistor networks.

[0034] In a computer system, the connection between the motherboard and expansion boards is achieved through physical slots and bus interfaces. PCIe slots are a set of interfaces provided on the motherboard for connecting various expansion cards (such as graphics cards, network cards, sound cards, and memory controller cards). The motherboard not only provides data connectivity for the expansion cards but also provides power through the power supply system. The chip's power input terminal connects to the expansion board via gold fingers to supply power to the expansion board.

[0035] Figure 2 This is a schematic flowchart of a primary / backup power supply switching method 200 according to an embodiment of the present disclosure. The process in this embodiment is as follows: Figure 1 The motherboard power management circuit shown is in operation. The order in which the various steps execute can be adjusted according to actual conditions and is not limited here. Figure 2 In the example, the main power supply is a high or low level signal from the power supply unit, used to control the switching state of the entire system. Standby power is the power supply that continues to provide power to critical parts of the motherboard (such as chips) when the main power supply is off. This power supply can be controlled by turning a switching transistor on or off.

[0036] In step S210, when the motherboard is powered off, the low level output by the main power supply becomes a high level after passing through the first NOT gate, which turns off the first switching transistor; the high level output by the first NOT gate becomes a low level after passing through the third resistor and the second NOT gate, which turns on the second switching transistor, and the standby power supply supplies power to the chip through the second switching transistor.

[0037] Reference Figure 1 As shown, when the main power supply output level goes low, it means the main power supply no longer provides power to the system. At this time, the main power supply output directly acts on the input of the first NOT gate. Due to the logic characteristics of the NOT gate, when the input is low, the output of the first NOT gate will become high. The high-level output of the first NOT gate is connected to the input of the second NOT gate through the third resistor R3. Simultaneously, this high-level signal also directly acts on the gate of the first switching transistor Q1. Q1 is a switching transistor that controls the main power supply; when a high-level signal is input to its gate, Q1 will turn off, thus cutting off the main power supply to the chip. At this time, the chip cannot obtain power from the main power supply. When the output of the first NOT gate is high, after passing through the third resistor R3 and the input of the second NOT gate, the output of the second NOT gate will become low. The low-level signal output of the second NOT gate will act on the gate of the second switching transistor Q2, driving Q2 to conduct. When Q2 is on, Q2 establishes an electrical connection between the standby power supply and the chip's power input, allowing the standby power supply to power the chip through Q2. At this time, standby power flows into the chip's power input terminal through Q2, ensuring that the system still has power supply even in standby mode. Although the standby power supply voltage is low, it is sufficient to ensure that the chip is in standby or low-power mode.

[0038] In step S220, when the motherboard is powered on, the high level output by the main power supply becomes a low level after passing through the first NOT gate, which turns on the first switching transistor, and the main power supply supplies power to the chip through the first switching transistor; the low level output by the first NOT gate becomes a high level after passing through the second NOT gate, which turns off the second switching transistor.

[0039] When the main power supply output voltage is high, the output of the first NOT gate is low, and this low-level signal is transmitted to the gate of the first switching transistor Q1. When the gate of the first switching transistor Q1 receives the low-level signal, it turns on. In the on state, Q1 forms a low-impedance path, allowing the main power supply voltage to flow into the chip's power input terminal through Q1. At this time, the main power supply provides power to the system through Q1, starting to drive the chip and other hardware components. The low-level output signal of the first NOT gate is transmitted to the input terminal of the second NOT gate through the third resistor R3, resulting in a high-level output. The high-level output signal of the second NOT gate acts on the gate of the second switching transistor Q2, turning it off. Because the first switching transistor Q1 is on, the high-level signal provided by the main power supply can smoothly power the system through Q1, starting the chip and other devices.

[0040] When power is switched, if Q2 turns off too quickly, it may cause a step change in the power supply voltage. This sudden voltage fluctuation can affect the stability of the power supply and may even cause abnormal behavior in other sensitive circuits. To avoid step changes during the switching between main power and standby power, in some embodiments of this disclosure, when the motherboard is powered on, the fifth and sixth resistors form a voltage divider circuit to divide the high-level output of the second NOT gate, making the gate voltage of the second switching transistor less than the turn-off threshold. Through voltage division, the circuit can control the change in gate voltage, so that the turn-off of Q2 is not completely "abrupt" or "complete". This means that the gate voltage of Q2 will not be directly pulled to an extremely low voltage, thus making the turn-off state of Q2 smoother rather than sudden, which can slow down the turn-off process of Q2, avoid such sudden voltage changes, and thus ensure smooth power switching and improve the overall stability and reliability of the circuit.

[0041] Embodiments of this disclosure also provide a chip. This chip includes a motherboard power management circuit according to embodiments of this disclosure.

[0042] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, a rack-mount server device. Rack-mount servers typically support modular design, facilitating expansion as needed. For example, hardware such as hard drives, memory, and CPUs can be added to meet evolving business requirements.

[0043] In summary, the motherboard power management circuit and main / standby power switching method according to the embodiments of this disclosure utilize simple logic control of NOT gates and the cooperation of switching transistors to smoothly achieve power switching control between power on and off states. This simplifies the design of the motherboard power management circuit, reduces design complexity, eliminates the need for additional high-power power chips and additional power lines, thereby saving costs and PCB space. Furthermore, the voltage divider circuit design significantly improves the stability and system reliability during power switching.

[0044] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0045] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0046] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A motherboard power management circuit, characterized in that, include: First switching transistor, second switching transistor, first NOT gate, second NOT gate, first resistor, second resistor, third resistor, fourth resistor, fifth resistor, sixth resistor, main power supply and standby power supply; The source of the first switching transistor is connected to the main power supply, the drain is connected to the chip power input terminal, and the gate is connected to the first resistor; the main power supply and the first resistor are connected to the first NOT gate, one end of the second resistor is grounded, and the other end is connected to the main power supply; the source of the second switching transistor is connected to the standby power supply, the drain is connected to the chip power input terminal, and the gate is connected to the fourth resistor; the fourth resistor is connected to the fifth resistor and the sixth resistor respectively, the other end of the sixth resistor is grounded, the other end of the fifth resistor is connected to the second NOT gate, and the first NOT gate and the second NOT gate are connected to the third resistor.

2. The motherboard power management circuit according to claim 1, characterized in that, When the motherboard is powered off, the main power supply outputs a low level, which becomes a high level after passing through the first NOT gate, turning off the first switching transistor; the high level output by the first NOT gate becomes a low level after passing through the third resistor and the second NOT gate, turning on the second switching transistor, and the standby power supply supplies power to the chip through the second switching transistor.

3. The motherboard power management circuit according to claim 1, characterized in that, When the motherboard is powered on, the main power supply outputs a high level, which becomes a low level after passing through the first NOT gate, turning on the first switching transistor. The main power supply then supplies power to the chip through the first switching transistor. The low level output from the first NOT gate becomes a high level after passing through the second NOT gate, turning off the second switching transistor.

4. The motherboard power management circuit according to claim 3, characterized in that, The fifth and sixth resistors form a voltage divider circuit to divide the high-level output of the second NOT gate, so that the gate voltage of the second switch is less than the turn-off threshold.

5. The motherboard power management circuit according to claim 1, characterized in that, Both the first and second switching transistors are PMOS transistors.

6. The motherboard power management circuit according to claim 1, characterized in that, Both the first NOT gate and the second NOT gate are Schmitt NOT gates.

7. The motherboard power management circuit according to claim 1, characterized in that, The chip's power input terminal is connected to the expansion board via gold fingers.

8. A method for switching between primary and backup power supplies, characterized in that, The method is executed based on the motherboard power management circuit according to any one of claims 1-7, and includes: When the motherboard is powered off, the low level output by the main power supply becomes a high level after passing through the first NOT gate, which turns off the first switching transistor; the high level output by the first NOT gate becomes a low level after passing through the third resistor and the second NOT gate, which turns on the second switching transistor, and the standby power supply supplies power to the chip through the second switching transistor. When the motherboard is powered on, the high level output by the main power supply becomes a low level after passing through the first NOT gate, which turns on the first switching transistor, and the main power supply supplies power to the chip through the first switching transistor; the low level output by the first NOT gate becomes a high level after passing through the second NOT gate, which turns off the second switching transistor.

9. The motherboard main / standby power switching method according to claim 8, characterized in that, When the motherboard is powered on, the fifth and sixth resistors form a voltage divider circuit to divide the high-level output of the second NOT gate, making the gate voltage of the second switching transistor less than the turn-off threshold.

10. A chip, wherein, Includes the motherboard power management circuit as described in any one of claims 1-7.

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