Data rereading method, memory and storage medium

Abstract

The present application relates to the field of EMMC R&D performance technology, and in particular to a data rereading method, a memory and a storage medium. The method comprises: counting the number of basic storage cells corresponding to n data states in a flash memory page, obtaining n numbers, which are counted as N0, N1, ..., N n‑1 , n≥2; according to N0 to N n‑1 The voltage distribution offset state of the flash memory page is determined based on the size relationship between the two. The offset direction of the reread voltage is determined based on the voltage distribution offset state of the flash memory page, and the corresponding offset voltage value is filtered out from the reread table based on the offset direction. The reread process is executed based on the offset voltage value to correct the data or terminate the reread process after reaching a preset number of rereads. Therefore, this application can effectively solve the problems of NAND Flash traversing the retry table many times and the long reread process time when executing the reread process.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a data rereading method, a memory, and a storage medium. Background Art

[0002] Read Retry technology is used to adjust the internal read reference voltage when an uncorrectable data error occurs on a flash memory page. This adjustment is intended to correctly distinguish the data state stored in the basic storage cell. The NAND flash memory then performs a reread process, sending a read operation to the NAND flash memory to attempt to correctly read the data stored in the basic storage cell. Read Retry technology uses a retry table, which stores the voltage offset for each read operation. However, the retry table contains multiple sets of read retry values, each corresponding to the voltage adjustment range and direction required in different scenarios.

[0003] Manufacturers typically provide a retry table, but these tables often lack scenario-specific offset voltage values. This often results in the retry table being traversed repeatedly, attempting all read retry values ​​until the data is correctly read. This approach results in frequent retry table traversals, a time-consuming retry flow, and a significant degradation in read performance. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a data rereading method, a memory, and a storage medium, which can effectively solve the problems of traversing the retry table many times and taking a long time when executing the reread process of NAND Flash.

[0005] In a first aspect, an embodiment of the present application provides a data rereading method, comprising:

[0006] Count the number of basic storage units corresponding to n data states in the flash memory page, and get n numbers, which are recorded as N0, N1, ..., N n-1 , n≥2;

[0007] According to N0 to N n-1 The magnitude relationship between them is used to determine the voltage distribution offset state of the flash memory page;

[0008] determining an offset direction of a reread voltage according to a voltage distribution offset state of the flash memory page, and selecting a corresponding offset voltage value from a reread table according to the offset direction;

[0009] A reread process is executed according to the offset voltage value to correct the data or the reread process is terminated after a preset number of reread times is reached.

[0010] In some embodiments, the data states of the basic storage unit include: "0" and "1";

[0011] The counting of the numbers of basic storage units corresponding to n data states in the flash memory page to obtain n numbers includes:

[0012] The number of basic storage cells corresponding to the "0" state and the "1" state in the flash memory page is counted to obtain N0 and N1 respectively.

[0013] In some embodiments, the n-1 and determining a voltage distribution offset state of the flash memory page based on a magnitude relationship between the voltage distribution of the flash memory page and the voltage distribution of the flash memory page, including:

[0014] Compare the sizes of N0 and N1;

[0015] If N0 is equal to N1, the voltage distribution offset state of the flash memory page is unbiased;

[0016] and / or, if N0 is greater than N1, the voltage distribution offset state of the flash memory page is right-skewed;

[0017] And / or, if N0 is smaller than N1, it is determined that the voltage distribution offset state of the flash memory page is left-biased.

[0018] In some embodiments, when the flash memory page is configured in MLC mode, the data states of the basic storage unit include: "00", "01", "10" and "11";

[0019] The counting of the number of basic storage units corresponding to n data states in the flash memory page includes:

[0020] The numbers of basic storage cells corresponding to the "11" state, the "01" state, the "00" state, and the "10" state in the flash memory page are counted, and N0, N1, N2, and N3 are obtained in sequence.

[0021] In some embodiments, the n-1 The size relationship between them determines the voltage distribution offset state of the flash memory page, including:

[0022] Get the flash page type;

[0023] The voltage distribution offset state of the flash memory page is determined according to the flash memory page type and the relationship between N0, N1, N2 and N3.

[0024] In some embodiments, the flash memory page types include: a low page and an upper page;

[0025] Determining the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0, N1, N2, and N3 includes:

[0026] When the flash memory page type is a low-order page, for the threshold voltage R2', compare the magnitudes of N0 + N1 and N2 + N3:

[0027] If N0 + N1 > N2 + N3, the voltage distribution offset state of the flash memory page is left-biased;

[0028] If N0 + N1 < N2 + N3, the voltage distribution offset state of the flash memory page is right-biased;

[0029] If they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0030] When the flash memory page type is a high-order page, for the threshold voltage R1', compare the magnitudes of 3×N0 and N1 + N2 + N3:

[0031] If 3×N0 is greater than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is left-biased; <00000८1>

[0032] If 3×N0 is less than N1 + N2 + N३, the voltage distribution offset state of the flash memory page is right-biased;

[0033] If they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0034] For the threshold voltage R3', compare the magnitudes of 3×N2 and N1 + N2 + N3:

[0035] If 3×N2 is greater than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is left-biased;

[0036] If 3×N2 is less than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is right-biased;

[0037] If they are equal, the voltage distribution offset state of the flash memory page is unbiased.

[0038] In some embodiments, when the flash memory page is configured in the TLC mode, the data states of the basic memory cells include: "000", "001", "010", "011", "100", "101", "110", and "111";

[0039] Statistically counting the number of basic memory cells corresponding to n data states in the flash memory page to obtain n quantities, including:

[0040] The numbers of basic storage cells corresponding to the "111" state, "110" state, "100" state, "000" state, "010" state, "011" state, "001" state, and "101" state in the flash memory page are counted, and the corresponding numbers are N0, N1, N2, N3, N4, N5, N6, and N7.

[0041] In some embodiments, the n-1 The voltage distribution offset state of the flash memory page is determined based on the size relationship between the two, including:

[0042] Get the flash page type;

[0043] The voltage distribution offset state of the flash memory page is determined according to the type of the flash memory page and the relationship between N0 to N7.

[0044] In some embodiments, the flash memory page types include: low page, high page and super page;

[0045] The determining the voltage distribution offset state of the flash memory page according to the relationship between the flash memory page type and N0 to N7 includes:

[0046] If the flash memory page type is a low-order page, for the threshold voltage R1″, compare 7×N0 with the values ​​of N1+N2+N3+N4+N5+N6+N7:

[0047] If 7×N0 is greater than N1+N2+N3+N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is left-biased;

[0048] If 7×N0 is less than N1+N2+N3+N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is right-skewed;

[0049] If they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0050] For the threshold voltage R5, compare the size of 3×(N1+N2+N3+N4) and 5×(N5+N6+N7):

[0051] If 3×(N1+N2+N3+N4) is greater than 5×(N5+N6+N7), the offset state of the voltage distribution of the flash memory page is left-skewed;

[0052] If 3×(N1+N2+N3+N4) is less than 5×(N5+N6+N7), the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0053] If the flash memory page type is a high-order page, for the threshold voltage R2″, compare 3×(N0+N1) with N2+N3+N4+N5+N6+N7:

[0054] If 3×(N0+N1) is greater than N2+N3+N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is left-biased;

[0055] If 3×(N0+N1) is less than N2+N3+N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0056] For the threshold voltage R4, compare the sizes of N0+N1+N2+N3 and N4+N5+N6+N7:

[0057] If N0+N1+N2+N3 is greater than N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is left-biased; if N0+N1+N2+N3 is less than N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0058] For the threshold voltage R6, compare the size of N0+N1+N2+N3+N4+N5 with 3×(N6+N7):

[0059] If N0+N1+N2+N3+N4+N5 is greater than 3×(N6+N7), the voltage distribution offset state of the flash memory page is left-biased; if N0+N1+N2+N3+N4+N5 is less than 3×(N6+N7), the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0060] If the flash memory page type is a middle bit page, for the threshold voltage R3″, compare 5×(N0+N1+N2) and 3×(N3+N4+N5+N6+N7):

[0061] If 5×(N0+N1+N2) is greater than 3×(N3+N4+N5+N6+N7), the voltage distribution offset state of the flash memory page is left-biased;

[0062] If 5×(N0+N1+N2) is less than 3×(N3+N4+N5+N6+N7), the voltage distribution offset state of the flash memory page is right-skewed;

[0063] If they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0064] For the threshold voltage R7, compare the size of N1+N2+N3+N4+N5+N6 with 7×N7:

[0065] If N1+N2+N3+N4+N5+N6 is greater than 7×N7, the voltage distribution offset state of the flash memory page is left-biased; if N1+N2+N3+N4+N5+N6 is less than 7×N7, the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased.

[0066] In some embodiments, determining an offset direction of a reread voltage according to an offset state of a voltage distribution of the flash memory page, and selecting a corresponding offset voltage value from the reread table according to the offset direction comprises:

[0067] If the voltage distribution offset state of the flash memory page is right-skewed, filtering out offset voltage values ​​greater than zero from the reread table;

[0068] And or, if the voltage distribution offset state of the flash memory page is left-skewed, filtering out offset voltage values ​​less than zero from the reread table.

[0069] In a second aspect, an embodiment of the present application provides a memory, which is used to store a computer program that implements a data rereading method provided in the first aspect of the present application, and uses a data rereading method provided in the first aspect of the present application to correct data when reading data errors.

[0070] In a third aspect, an embodiment of the present application provides a readable storage medium storing a computer program. When the computer program is executed on a processor, the data rereading method provided in the first aspect of the present application is implemented.

[0071] The embodiments of the present application have the following beneficial effects:

[0072] In this application, the number of basic storage cells corresponding to n data states in the flash memory page is counted to obtain n numbers, which are recorded as N0, N1, ..., N n-1 , n≥2; according to N0 to N n-1 The voltage distribution offset state of the flash memory page is determined by the size relationship between the voltage distribution offset state of the flash memory page; the offset direction of the reread voltage is determined according to the voltage distribution offset state of the flash memory page, and the corresponding offset voltage value is filtered out from the reread table according to the offset direction; the reread process is executed according to the offset voltage value to correct the data or the reread process is terminated after the preset reread times are reached. This application adopts the Read retry technology to execute the reread process according to the precise voltage threshold determined by the voltage distribution offset state to correct the data, which can effectively solve the problems of traversing the Retry table many times and the long time spent in the reread process when NAND Flash executes the reread process. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0074] Figure 1 A schematic diagram of a flow chart of a data rereading method according to an embodiment of the present application is shown;

[0075] Figure 2 A schematic diagram of an MLC standard unbiased voltage distribution offset state in a data rereading method according to an embodiment of the present application is shown;

[0076] Figure 3 A schematic diagram of the offset state of the TLC standard unbiased voltage distribution in the data rereading method according to an embodiment of the present application is shown;

[0077] Figure 4 A schematic diagram of a flow chart of a data rereading method according to an embodiment of the present application when a flash memory page is configured as an SLC type is shown;

[0078] Figure 5 A schematic diagram of a flow chart of a data rereading method according to an embodiment of the present application when a flash memory page is configured as an MLC type is shown;

[0079] Figure 6-1 A schematic diagram of the first part of the flow chart of the data rereading method according to an embodiment of the present application when the flash memory page is configured as a TLC type is shown;

[0080] Figure 6-2 A schematic diagram of the second part of the flow chart of the data rereading method according to an embodiment of the present application when the flash memory page is configured as a TLC type is shown;

[0081] Figure 6-3 A schematic diagram of the third part of the flow chart of the data rereading method according to an embodiment of the present application when the flash memory page is configured as a TLC type is shown;

[0082] Figure 7 A structural diagram of a reread process execution device according to an embodiment of the present application is shown.

[0083] Description of main component symbols:

[0084] 710 - statistics module; 720 - offset state determination module; 730 - offset voltage value determination module; 740 - rereading module. DETAILED DESCRIPTION

[0085] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0086] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0087] Hereinafter, the terms "including", "having" and their cognates used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the aforementioned items, and should not be understood as excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the aforementioned items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the aforementioned items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and should not be understood as indicating or implying relative importance.

[0088] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0089] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0090] The Read Retry flow is the normal read process of the EMMC (Embedded Multi Media Card) embedded non-volatile memory system. It uses a page as the minimum operation unit. If a Read Page Pass result indicates that the page read process has passed, no Read Retry flow is required. If a Read Page Failure result is returned, the Read Retry flow begins. This process first sets the offset voltage value according to the Retry table and then performs another read operation. If a Pass result is returned, the data is corrected during this retry. If a Failure result is returned, the next offset voltage value in the Retry table is reset, the read voltage is adjusted, and the next read operation is performed until the Read Operation Passes or the maximum number of retry attempts is reached. In the prior art, the Read Retry flow typically traverses the Retry table, trying each voltage offset value one by one. This results in a large number of Retry table traversals, a significant time consumption, and a significant degradation in read performance. Therefore, the present application proposes a data rereading method, a memory and a storage medium, which can effectively solve the problems of traversing the retry table many times and taking a long time when executing the reread process of NAND Flash.

[0091] The main idea of ​​this application is to propose a method for classifying the Retry table according to the scenario, that is, according to the voltage distribution offset state of the flash memory page, determine whether the voltage distribution offset state of the flash memory page (also known as Vt distribution) is left-biased or right-biased, and classify it according to the left-biased or right-biased. For example, when the left offset is screened out, the offset voltage values ​​in the Retry table where the retry voltage is right-biased are skipped, and about half of the offset voltage values ​​in the Retry table are screened out, thereby reducing the number of traversals of the Retry table, thereby shortening the retry flow time and further optimizing the Read Retry flow performance. It also provides a starting solution for subsequent further subdivision of scenarios (data retention, life loss, read and write interference). In other words, this application directly compares the number of each state based on the fact that the cells in each state should be 1:1:1:1 under normal circumstances to confirm whether the overall offset of this flash memory page is left-biased or right-biased by directly comparing the number of each state.

[0092] The data rereading method is described below with reference to some specific embodiments.

[0093] Figure 1 A flow chart of a data rereading method according to an embodiment of the present application is shown. Exemplarily, the data rereading method includes the following steps:

[0094] S10, counting the number of basic storage units corresponding to n data states in the flash memory page, and obtaining n numbers, which are recorded as N0, N1, ..., N n-1 , n≥2.

[0095] The basic storage unit cell is also called the flash memory basic storage unit.

[0096] A flash memory page is a logical concept. It consists of cells (the basic storage unit of flash memory) on the same wordline. The number of pages on a wordline is determined by the cell's bit storage capacity. In SLC memory, a single cell can store 1 bit of information, while MLC can store 2 bits, TLC can store 3 bits, and QLC can store 4 bits.

[0097] NAND Flash memory chip types include SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Triple-Level Cell), and QLC (Quadrature Cell). Each memory cell in an SLC chip stores one binary bit, namely "1" and "0," and the corresponding cell has two data states. Each memory cell in an MLC chip stores two binary bits, namely "11, 01, 00, and 10," and the corresponding cell has four data states. Each memory cell in a TLC chip stores three binary bits, namely "111, 101, 100, 110, 000, 001, 010, and 011," and the corresponding cell has eight data states. The voltage threshold used to distinguish between different states increases from low to high.

[0098] Threshold voltages (R) are required when reading data within a page. Different types of NAND Flash use a different number of threshold voltages, each located at the intersection of adjacent Vt distribution curves. The threshold voltages must be known during a read operation to determine the charge level and, therefore, the data stored in the memory cell. Specifically, SLC has only one threshold voltage; MLC has three threshold voltages R: R1', R2', and R3'. TLC has seven threshold voltages: R1", R2", R3", R4, R5, R6, and R7.

[0099] Under normal circumstances, after randomization, the number of data states in SLC, MLC, and TLC cells is equal. Therefore, based on this characteristic, as long as the quantitative relationship between the various data states is obtained, the Vt of the cell can be determined to be left-skewed or right-skewed. For SLC, the determination can be made by simply counting the number of 0s and 1s. However, MLC and TLC are more complicated and require counting the number of cells corresponding to each data state.

[0100] After a Read operation fails, the process enters the Read Retry flow, where the number of cells corresponding to each data state of the page is counted and recorded separately.

[0101] S20, according to N0 to N n-1 The size relationship between them determines the voltage distribution offset state of the flash memory page.

[0102] S30, determining an offset direction of a reread voltage according to a voltage distribution offset state of the flash memory page, and selecting a corresponding offset voltage value from a reread table according to the offset direction;

[0103] In this embodiment, the Vt distribution deviation states include no deviation, left deviation and right deviation. Figure 2 The voltage distribution deviation state diagram of the MLC standard is unbiased ( Figure 2 The threshold voltage R1 is the threshold voltage R1', the threshold voltage R2 is the threshold voltage R2', and the threshold voltage R3 is the threshold voltage R3'). Figure 3 The voltage distribution offset state diagram of the TLC standard is unbiased ( Figure 3 The middle threshold voltage R1 is threshold voltage R1″, the threshold voltage R2 is threshold voltage R2″, and the threshold voltage R3 is threshold voltage R3″. If the voltage distribution offset state is left-biased, the offset voltage values ​​in the retry table whose offset voltage values ​​are right-biased are skipped; if the voltage distribution offset state is right-biased, the offset voltage values ​​in the retry table whose offset voltage values ​​are left-biased are skipped.

[0104] S40 , executing a reread process to correct data according to the offset voltage value or ending the reread process after reaching a preset reread times.

[0105] In one embodiment, when the flash memory page is configured in SLC mode, the data states of the basic storage unit include: "0" and "1".

[0106] In step S10, the number of basic storage cells corresponding to n data states in the flash memory page is counted to obtain n numbers, including:

[0107] The number of basic storage cells corresponding to the "0" state and the "1" state in the flash memory page is counted to obtain N0 and N1 respectively.

[0108] Further, in step S20, according to N0 to N n-1 The size relationship between them determines the voltage distribution offset state of the flash memory page, including:

[0109] S211, compare the sizes of N0 and N1.

[0110] S212: If N0 is equal to N1, the voltage distribution offset state of the flash memory page is unbiased.

[0111] S213 , if N0 is greater than N1 , the voltage distribution offset state of the flash memory page is right-biased.

[0112] S214: If N0 is smaller than N1, confirm that the voltage distribution offset state of the flash memory page is left-biased.

[0113] For example, Figure 4 As shown, the data rereading method for SLC in this embodiment includes:

[0114] S110 , determining whether the read page needs to be reread.

[0115] After the Read operation fails, the process enters the Read Retry flow and executes S120 to collect statistics on the status of each data.

[0116] S120 , if a reread process needs to be executed, the number of cells corresponding to the “0” state and the “1” state of the flash memory page are counted, and N0 and N1 are obtained accordingly.

[0117] That is to say, step S10 involves counting the number of cells corresponding to n data states in the page to obtain n numbers, including counting the number of cells corresponding to the "0" state and the "1" state in the page to obtain N0 and N1 respectively.

[0118] S130, determine whether N0 and N1 are equal. That is, compare N0 and N1; if N0 is equal to N1, execute step S140; if not, execute step S150.

[0119] S140 , confirming that the voltage distribution offset state of the flash memory page is unbiased.

[0120] S150, determine whether N0 is greater than N1. If N0 is greater than N1, execute step S160; if N0 is less than N1, execute step S170.

[0121] S160: Confirm that the voltage distribution offset state of the flash memory page is right-skewed. Then, it is necessary to filter the offset voltage value greater than 0 from the reread table to serve as the accurate offset voltage value.

[0122] S170 confirms that the voltage distribution offset state of the flash memory page is left-skewed. Furthermore, it is necessary to filter the retry table for offset voltage values ​​less than 0 to serve as accurate offset voltage values. In other words, after determining whether the Vt distribution (also known as the voltage distribution offset state) is left-skewed or right-skewed, the retry table can be distinguished based on two scenarios to filter out the offset voltage value for the corresponding scenario. A left-skewed Vt distribution indicates that the read voltage must also shift leftward for correct reading. Therefore, offsets (offset voltage values) greater than 0 in the retry table can be filtered out and directly skipped. Similarly, when the Vt distribution is right-skewed, offsets less than 0 in the retry table can be filtered out.

[0123] That is to say, step S20 involves the n-1 The voltage distribution offset state of the flash memory page is determined based on the size relationship between the two, including: step S130, step S140, step S150, step S160 and step S170.

[0124] S180: Perform retry flow based on the accurate offset voltage value obtained through screening.

[0125] In one embodiment, when the flash memory page is configured in MLC mode, the data states of the basic storage cells include: "00", "01", "10", and "11". MLC has three threshold voltages R, namely R1', R2', and R3'.

[0126] Count the number of basic storage cells corresponding to n data states in a flash memory page, including:

[0127] The numbers of basic storage cells corresponding to the "11" state, the "01" state, the "00" state, and the "10" state in the flash memory page are counted, and N0, N1, N2, and N3 are obtained in sequence.

[0128] In step S20, according to N0 to N n-1 The size relationship between them determines the voltage distribution offset state of the flash memory page, including:

[0129] S221, obtaining the flash memory page type.

[0130] S222 , determining a voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0 , N1 , N2 , and N3 .

[0131] Furthermore, the flash memory page types include: lower page and upper page. Different cases (scenarios) are run according to different flash memory page types. For the retry flow of the lower page and the upper page, only the corresponding threshold voltages need to be known.

[0132] According to the encoding method of the lower page, only the offset situation of the threshold voltage R2' needs to be known to confirm the offset state of the lower page, so as to screen the retry table for the retry flow.

[0133] Determine the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0, N1, N2, and N3, including:

[0134] S2221, when the flash memory page type is the lower page, for the threshold voltage R2', compare the magnitudes of N0 + N1 and N2 + N3:

[0135] If N0 + N1 > N2 + N3, the voltage distribution offset state of the flash memory page is left-biased;

[0136] If N0 + N1 < N2 + N3, the voltage distribution offset state of the flash memory page is right-biased;

[0137] If they are equal, the voltage distribution offset state of the flash memory page is unbiased, and the retry flow can be directly performed.

[0138] In other words, first determine whether Equation 1 holds, where Equation 1 is: (N0 + N1) = (N2 + N3); if Equation 1 holds, it means that the voltage distribution offset state of the flash memory page is unbiased, and the retry flow is directly performed; otherwise, further determine whether the voltage distribution offset state of the flash memory page is left-biased or right-biased. If (N0 + N1) > (N2 + N3), it means that the voltage distribution offset state of the flash memory page is left-biased, and vice versa.

[0139] However, for the upper page, the offset state needs to be confirmed according to two threshold voltages R1' and R3'.

[0140] S2222, when the flash memory page type is the upper page, for the threshold voltage R1', compare the magnitudes of 3×N0 and N1 + N2 + N3:

[0141] If 3×N0 is greater than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is left-biased;

[0142] If 3×N0 is less than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is right-biased;

[0143] If they are equal, the voltage distribution offset state of the flash memory page is unbiased, and it is confirmed that the voltage distribution offset state around the threshold voltage R1 ′ is unbiased.

[0144] Exemplarily, first determine whether Equation 2 holds true. Equation 2 is (3×N0)=(N1+N2+N3). If they are equal, it indicates that the voltage distribution offset state around the threshold voltage R1′ is unbiased. If they are greater than, it is confirmed to be left-biased. Otherwise, it is confirmed to be right-biased.

[0145] S2223, for the threshold voltage R3', compare 3×N2 with N1+N2+N3:

[0146] If 3×N2 is greater than N1+N2+N3, the voltage distribution offset state of the flash memory page is left-biased;

[0147] If 3×N2 is less than N1+N2+N3, the voltage distribution offset state of the flash memory page is right-skewed;

[0148] If they are equal, the voltage distribution offset state of the flash memory page is unbiased.

[0149] Exemplarily, first determine whether Equation 3 (3×N2)=(N1+N0+N3) holds true; if true (equal), confirm that the voltage distribution offset state around threshold voltage R3′ is unbiased; if greater than, confirm that the voltage distribution offset state around threshold voltage R3′ is left-biased; otherwise, confirm that the voltage distribution offset state around threshold voltage R3′ is right-biased.

[0150] Demonstration, such as Figure 5 ( Figure 5 As shown in FIG. 1 , where the threshold voltage R1 is the threshold voltage R1′, the threshold voltage R2 is the threshold voltage R2′, and the threshold voltage R3 is the threshold voltage R3′, when the flash memory page is configured as an MLC type, the data rereading method of the embodiment of the present application specifically includes:

[0151] S210, determine whether the read page needs to be reread. If so, execute step S220, otherwise, terminate directly.

[0152] S220 , counting the number of cells corresponding to the “11” state, the “01” state, the “00” state, and the “10” state in the flash memory page, and obtaining N0 , N1 , N2 , and N3 in sequence.

[0153] That is to say, in step S10, the number of cells corresponding to n data states in the flash memory page is counted to obtain n numbers, including: counting the number of cells corresponding to the "11" state, "01" state, "00" state and "10" state in the flash memory page, and obtaining N0, N1, N2 and N3 respectively.

[0154] Before executing step S220, the MLC encoding scheme must be determined. Different cell types may have different encoding schemes. Currently, most encoding schemes are based on voltage ranges, with the sequence from left to right being "11"-"01"-"00"-"10". Based on the read operation results, the corresponding record counts are N0, N1, N2, and N3. Specifically, after a Read operation fails, the retry flow begins. Unlike SLC, an MLC cell can have four states: "00", "01", "10", and "11". The number of each of these four cell states is counted and recorded in an array of length 4.

[0155] S230: Confirm that the flash memory page type is a low page.

[0156] S231: Determine whether Equation 1 (N0 + N1) = (N2 + N3) holds true to confirm whether there is an offset. If they are equal, proceed to the last step; if not, proceed to step S232.

[0157] S232, determine whether (N0+N1)>(N2+N3) is true. If not, proceed to step S233; if so, proceed to step S234.

[0158] S233 , confirming that the voltage distribution around the threshold voltage R2 ′ is shifted to the right.

[0159] S234 , confirming that the voltage distribution shift state around the threshold voltage R2 ′ is left-biased.

[0160] S240: Confirm that the flash memory page type is an up page.

[0161] S241: Determine whether the equation (3×N0)=(N1+N2+N3) holds true to confirm whether there is an offset. If they are equal, proceed to the last step; if not, proceed to step S242.

[0162] S242, determine whether (3×N0)>(N1+N2+N3) is true. If so, go to step S243; if not, go to step S244.

[0163] S243 confirms that the voltage distribution around threshold voltage R1' is right-skewed. The retry table is filtered for offset voltages greater than 0 to determine the accurate offset voltage value. The MLC retry table is re-screened based on the offset condition, and a suitable retry table is initially selected based on the left-skew and right-skew conditions.

[0164] S244: Confirm that the voltage distribution around the threshold voltage R1' is offset to the left. Filter the offset voltage values ​​less than 0 from the reread table to use as accurate offset voltage values.

[0165] S245: Determine whether the equation (3×N2)=(N1+N0+N3) holds. If so, proceed to the last step; otherwise, proceed to step S246.

[0166] S246: Determine whether the equation (3×N2)>(N1+N0+N3) holds. If so, proceed to S247; otherwise, proceed to S248.

[0167] S247: Confirm that the voltage distribution around the threshold voltage R3' is right-skewed. Filter the offset voltage values ​​greater than 0 from the reread table to use as accurate offset voltage values.

[0168] S248: Confirm that the voltage distribution around the threshold voltage R3' is offset to the left. Filter the offset voltage values ​​less than 0 from the reread table to use as accurate offset voltage values.

[0169] S250 , performing a read retry flow based on the screened accurate offset voltage value.

[0170] In one embodiment, when a flash memory page is configured in TLC mode, the data states of the basic storage cells include: "000," "001," "010," "011," "100," "101," "110," and "111." TLC has seven threshold voltages: R1," R2," R3," R4," R5," R6," and R7.

[0171] First, we need to understand the TLC encoding method. Different NAND flash chips may have different encoding methods. Currently, the most common encoding method is 76502314. From left to right, based on the voltage range, it is: "111"-"110"-"100"-"000"-"010"-"011"-"001"-"101". The advantage of this encoding method is that it balances the read and write times of different page types in the same cell, preventing large differences in read and write times for different page types.

[0172] Count the number of basic storage cells corresponding to n data states in the flash memory page to obtain n numbers, including:

[0173] The number of basic storage cells corresponding to the "111" state, "110" state, "100" state, "000" state, "010" state, "011" state, "001" state, and "101" states within the flash memory page is counted, and the corresponding numbers are N0, N1, N2, N3, N4, N5, N6, and N7, respectively. Specifically, after a read operation fails, the retry flow begins. A TLC cell has eight data states. Based on the read operation results, the number of cells corresponding to each of the eight data states is counted and recorded in an array of length 8.

[0174] Further, according to N0 to N n-1 The relationship between the sizes determines the voltage distribution offset state of the flash memory page, including:

[0175] Gets the flash page type.

[0176] A TLC wordline has three types of pages: lower page (LSB), upper page (MSB), and extra page (CSB). Different cases are run according to different page types.

[0177] The voltage distribution offset state of the flash memory page is determined according to the flash memory page type and the relationship between N0 to N7.

[0178] Furthermore, flash memory page types include: lower page, upper page, and extra page.

[0179] Determining a voltage distribution offset state of a flash memory page according to a flash memory page type and a relationship between N0 to N7 includes:

[0180] S2321: If the flash memory page type is a low-order page, for the threshold voltage R1″, compare 7×N0 with N1+N2+N3+N4+N5+N6+N7:

[0181] If 7×N0 is greater than N1+N2+N3+N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is left-biased;

[0182] If 7×N0 is less than N1+N2+N3+N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is right-skewed;

[0183] If they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0184] For the threshold voltage R5, compare the size of 3×(N1+N2+N3+N4) and 5×(N5+N6+N7):

[0185] If 3×(N1+N2+N3+N4) is greater than>5×(N5+N6+N7), the offset state of the voltage distribution of the flash memory page is left-skewed;

[0186] If 3×(N1+N2+N3+N4)<5×(N5+N6+N7), the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0187] S2322: If the flash memory page type is a high-order page, for the threshold voltage R2″, compare 3×(N0+N1) with N2+N3+N4+N5+N6+N7:

[0188] If 3×(N0+N1)>N2+N3+N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is left-biased;

[0189] If 3×(N0+N1)<N2+N3+N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is right-skewed; if they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0190] For the threshold voltage R4, compare the sizes of N0+N1+N2+N3 and N4+N5+N6+N7:

[0191] If N0+N1+N2+N3 is greater than N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is left-skewed; if N0+N1+N2+N3 is less than N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is right-skewed; if they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0192] For the threshold voltage R6, compare the size of N0+N1+N2+N3+N4+N5 with 3×(N6+N7):

[0193] If N0+N1+N2+N3+N4+N5 is greater than 3×(N6+N7), the voltage distribution offset state of the flash memory page is left-skewed; if N0+N1+N2+N3+N4+N5 is less than 3×(N6+N7), the voltage distribution offset state of the flash memory page is right-skewed; if they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0194] S2323: If the flash memory page type is a middle bit page, for the threshold voltage R3″, compare 5×(N0+N1+N2) with 3×(N3+N4+N5+N6+N7):

[0195] If 5×(N0+N1+N2)>3×(N3+N4+N5+N6+N7), the voltage distribution offset state of the flash memory page is left-biased;

[0196] If 5×(N0+N1+N2)<3×(N3+N4+N5+N6+N7), the voltage distribution offset state of the flash memory page is right-skewed;

[0197] If they are equal, the voltage distribution offset state of the flash memory page is unbiased;

[0198] For the threshold voltage R7, compare the size of N1+N2+N3+N4+N5+N6 with 7×N7:

[0199] If N1+N2+N3+N4+N5+N6 is greater than 7×N7, the voltage distribution offset state of the flash memory page is left-skewed; if N1+N2+N3+N4+N5+N6 is less than 7×N7, the voltage distribution offset state of the flash memory page is right-skewed; if they are equal, the voltage distribution offset state of the flash memory page is unbiased.

[0200] Furthermore, determining the offset direction of the reread voltage according to the voltage distribution offset state of the flash memory page, and filtering out the corresponding offset voltage value from the reread table according to the offset direction; including:

[0201] If the voltage distribution offset state of the flash memory page is right-skewed, an offset voltage value greater than zero is filtered out from the reread table;

[0202] If the voltage distribution offset state of the flash memory page is left-skewed, an offset voltage value less than zero is filtered out from the reread table.

[0203] When the NAND Flash page is configured in TLC mode (TLC mode), the cell data states include: "000", "001", "010", "011", "100", "101", "110", and "111".

[0204] Step S20: According to the number N0 to the number N n-1 The relationship between the sizes determines the Vt distribution offset state, including:

[0205] like Figure 6-1 ( Figure 6-1 The threshold voltage R1 is the threshold voltage R1') Figure 6-2 ( Figure 6-2 The threshold voltage R2 is the threshold voltage R2') Figure 6-3 ( Figure 6-3 As shown in FIG. 2 , when the NAND flash is of TLC type, the data rereading method of the embodiment of the present application specifically includes:

[0206] S310: Determine whether the read page needs to be reread. If so, proceed to step S320; otherwise, proceed to the last step.

[0207] S320 , summing the numbers of cells corresponding to the respective data states in the flash memory page, and obtaining N0 , N1 , N2 , N3 , N4 , N5 , N6 , and N7 in sequence.

[0208] S331, the flash memory page type is lower page. It is necessary to determine the offset of the threshold voltage R1″ and the threshold voltage R5. The offset state of the threshold voltage R1″ is determined first, and then the offset state of the threshold voltage R5 is determined.

[0209] S332, for the threshold voltage R1", determine whether the equation (N0×7)=(N1+N2+N3+N4+N5+N6+N7) holds. If so, confirm that the voltage distribution offset state around the threshold voltage R1" is unbiased, and then execute step S336 to determine the threshold voltage R5. If not, execute step S333.

[0210] According to the encoding method page type, if the flash memory page type is lower page, for the threshold voltage R1", determine whether Equation 3 is true. Equation 3 is: (N0×7)=(N1+N2+N3+N4+N5+N6+N7).

[0211] S333: Determine whether (N0×7)>(N1+N2+N3+N4+N5+N6+N7). If so, proceed to step S334; if not, proceed to step S335.

[0212] S334 , confirming that the voltage distribution around the threshold voltage R1″ is shifted to the left. Filtering the offset voltage values ​​less than 0 from the reread table as accurate offset voltage values.

[0213] S335 , confirming that the voltage distribution around the threshold voltage R1″ is right-biased. Filtering the offset voltage values ​​greater than 0 from the reread table as accurate offset voltage values.

[0214] S336 , for the threshold voltage R5 , determine whether the equation (N0 + N1 + N2 + N3 + N4)×3 = (N5 + N6 + N7)×5 holds.

[0215] If yes, execute the last step, if not, execute step S337.

[0216] For threshold voltage R5, determine whether Equation 4 holds true: (N0 + N1 + N2 + N3 + N4) × 3 = (N5 + N6 + N7) × 5. If they hold, the voltage distribution offset around threshold voltage R5 is confirmed to be unbiased.

[0217] S337: Determine whether the equation (N0 + N1 + N2 + N3 + N4) × 3 > (N5 + N6 + N7) × 5 holds. If so, proceed to step S338; if not, proceed to step S339.

[0218] S338: Confirm that the voltage distribution around the threshold voltage R5 is offset to the left. Filter the offset voltage values ​​less than 0 from the reread table to use as accurate offset voltage values.

[0219] S339: Confirm that the voltage distribution around the threshold voltage R5 is right-skewed. Filter the offset voltage values ​​greater than 0 from the reread table to use as accurate offset voltage values.

[0220] At step S340 , the flash memory page type is upper page. It is necessary to determine the offsets of the threshold voltages R2″, R4, and R6. The offset of the threshold voltage R2″ is determined first, followed by the offset of the threshold voltage R4, and finally the offset of the threshold voltage R6.

[0221] S341, for the threshold voltage R2", determine whether the equation (N0 + N1) × 3 = (N2 + N3 + N4 + N5 + N6 + N7) holds. If so, then the voltage distribution offset state around the threshold voltage R2" is unbiased, and execute step S345 to determine the offset of R4; otherwise, execute step S342.

[0222] Determine whether Equation 5 is true. Equation 5 is: (N0+ N1)×3 = (N2+ N3+ N4+ N5+ N6+ N7).

[0223] S342: Determine whether the equation (N0 + N1) × 3 > (N2 + N3 + N4 + N5 + N6 + N7) holds. If so, proceed to step S343; if not, proceed to step S344.

[0224] S343: Confirm that the voltage distribution around the threshold voltage R2″ is offset to the left. Filter the offset voltage values ​​less than 0 from the reread table to use as accurate offset voltage values.

[0225] S344: Confirm that the voltage distribution around the threshold voltage R2″ is right-biased. Filter the offset voltage values ​​greater than 0 from the reread table to use as accurate offset voltage values.

[0226] S345: For threshold voltage R4, determine whether the equation (N0 + N1 + N2 + N3) = (N4 + N5 + N6 + N7) holds. If so, the voltage distribution around threshold voltage R4 is unbiased, and step S349 is performed to determine the offset of R6. If not, step S346 is performed.

[0227] Determine whether Equation 6 is true. Equation 6 is: (N0+ N1+ N2+ N3) = (N4+ N5+ N6+ N7);

[0228] S346: Determine whether (N0 + N1 + N2 + N3) > (N4 + N5 + N6 + N7). If so, proceed to step S347; if not, proceed to step S348.

[0229] S347: Confirm that the voltage distribution around the threshold voltage R4 is offset to the left. Filter the offset voltage values ​​less than 0 from the reread table to use as accurate offset voltage values.

[0230] S348: Confirm that the voltage distribution around the threshold voltage R4 is right-skewed. Filter the offset voltage values ​​greater than 0 from the reread table to use as accurate offset voltage values.

[0231] S349: For threshold voltage R6, determine whether the equation (N0 + N1 + N2 + N3 + N4 + N5) = (N6 + N7) × 3 holds. If so, the voltage distribution around threshold voltage R6 is offset, indicating no offset, and proceed to the final step. If not, proceed to step S350.

[0232] Determine whether Equation 7 is true. Equation 7 is: (N0+ N1+ N2+ N3+ N4+ N5) = (N6+ N7)×3;

[0233] S350, determine whether the equation (N0+N1+N2+N3+N4+N5)>(N6+N7)×3 holds. If it does, execute step S351; if it does not, execute step S352.

[0234] S351: Confirm that the voltage distribution around the threshold voltage R6 is offset to the left. Filter the offset voltage values ​​less than 0 from the reread table to use as accurate offset voltage values.

[0235] S352: Confirm that the voltage distribution around the threshold voltage R6 is right-skewed. Filter the offset voltage values ​​greater than 0 from the reread table to use as accurate offset voltage values.

[0236] S360: The flash memory page type is Extra page. It is necessary to determine the offset of the threshold voltage R3″ and the threshold voltage R7. First, determine the offset of the threshold voltage R1″, and then determine the offset of the threshold voltage R5.

[0237] S371, for the threshold voltage R3", determine whether the equation (N0 + N1 + N2) × 5 = (N3 + N4 + N5 + N6 + N7) × 3 holds. If so, if it is equal, the voltage distribution offset state around the threshold voltage R3" is unbiased, and then execute step 380 to determine the offset condition of R7; if not, execute step S372.

[0238] Determine whether Equation 8 is true. Equation 8 is: (N0+ N1+ N2)×5 = (N3+ N4+ N5+ N6+ N7)×3.

[0239] S372: Determine whether the equation (N0 + N1 + N2) × 5 > (N3 + N4 + N5 + N6 + N7) × 3 holds. If so, proceed to step S373; if not, proceed to step S374.

[0240] S373: Confirm that the voltage distribution around the threshold voltage R3″ is offset to the left. Filter the offset voltage values ​​less than 0 from the reread table to use as accurate offset voltage values.

[0241] S374: Confirm that the voltage distribution around the threshold voltage R3″ is right-biased. Filter the offset voltage values ​​greater than 0 from the reread table to use as accurate offset voltage values.

[0242] At step S380, for threshold voltage R7, determine whether the equation (N0 + N1 + N2 + N3 + N4 + N5 + N6) = N7 × 7 holds. If so, the voltage distribution offset around threshold voltage R3″ is considered to be zero, and the final step is executed. If not, step S381 is executed.

[0243] Determine whether Equation 9 is true. Equation 9 is: (N0+ N1+ N2+ N3+ N4+ N5+ N6) = N7×7.

[0244] S381: Determine whether the equation (N0+N1+N2+N3+N4+N5+N6) > N7×7 holds. If so, proceed to step S382; if not, proceed to step S383.

[0245] S382: Confirm that the voltage distribution around the threshold voltage R7 is offset to the left. Filter the offset voltage values ​​less than 0 from the reread table to use as accurate offset voltage values.

[0246] S383: Confirm that the voltage distribution around the threshold voltage R7 is right-biased. Filter the offset voltage values ​​greater than 0 from the reread table to use as accurate offset voltage values.

[0247] S390: Perform retry flow based on the accurate offset voltage value obtained through screening.

[0248] After confirming the offset, re-screen the TCL retry table based on the offset. Based on the left and right offsets, preliminarily select the appropriate retry table and perform the retry flow.

[0249] In this application, the state distribution of the basic storage unit (cell) is analyzed to determine whether the threshold voltage (Vt) is left-biased or right-biased, thereby screening out the retrytable suitable for the current scenario.

[0250] Figure 7 A schematic structural diagram of a rereading process execution device according to an embodiment of the present application is shown. Exemplarily, the rereading process execution device includes: a statistics module 710 , an offset state determination module 720 , an offset voltage value determination module 730 and a rereading module 740 .

[0251] The statistics module 710 is used to count the number of basic storage units corresponding to n data states in the flash memory page, and obtain n numbers, which are recorded as N0, N1, ..., N n-1 , n≥2;

[0252] The offset state determination module 720 is configured to determine the offset state according to the values ​​of N0 to N1. n-1 The size relationship between them determines the voltage distribution offset state of the flash memory page;

[0253] An offset voltage value determining module 730 is configured to determine an offset direction of a reread voltage according to an offset state of a voltage distribution of a flash memory page, and select a corresponding offset voltage value from a reread table according to the offset direction;

[0254] The reread module 740 is configured to execute a reread process to correct data according to the offset voltage value or terminate the reread process after a preset number of reread times is reached.

[0255] It can be understood that the device of this embodiment corresponds to the data rereading method of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0256] The present application also provides a memory device. The memory device is illustratively used to store a computer program that implements the data rereading method of the present application, and uses the data rereading method of the present application to correct data read errors. The storage device comprises a main control chip and a NAND flash memory. The data rereading method of the present application is stored in a fixed location in the NAND flash memory. Upon power-up, the program is loaded into the main control chip for execution. The main control chip schedules the execution of the program to implement the functions of the data rereading method of the present application.

[0257] It can be understood that the device of this embodiment corresponds to the data rereading method of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0258] The present application also provides a terminal device. Exemplarily, the terminal device includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program to enable the terminal device to execute the above-mentioned data rereading method or the functions of each module in the above-mentioned rereading process execution device.

[0259] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, etc., and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0260] The memory may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM). The memory is used to store computer programs, and the processor can execute the computer programs accordingly after receiving an execution instruction.

[0261] The present application also provides a readable storage medium for storing the computer program used in the above-mentioned terminal device.

[0262] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or flowchart, and the combination of boxes in the structure diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0263] In addition, the functional modules or units in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0264] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a smart phone, personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0265] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A data rereading method, characterized in that: Including: Count the number of basic storage units corresponding to n data states in the flash memory page, and get n numbers, which are recorded as N0, N1, ..., N n-1 , n≥2; According to N0 to N n-1 The magnitude relationship between them is used to determine the voltage distribution offset state of the flash memory page; wherein the voltage distribution offset state includes no offset, left offset and right offset; Determine the offset direction of the reread voltage according to the voltage distribution offset state of the flash memory page, and screen out the corresponding offset voltage value from the reread table according to the offset direction, specifically including: if the voltage distribution offset state of the flash memory page is right-offset, screen out the offset voltage value greater than zero from the reread table; and / or, if the voltage distribution offset state of the flash memory page is left-offset, screen out the offset voltage value less than zero from the reread table; Execute the reread process to recover data according to the offset voltage value or end the reread process after reaching the preset reread times; When the flash memory page is configured in the MLC mode, the data states of the basic storage units include: "00", "01", "10" and "11"; The counting of the number of basic storage units corresponding to n data states in the flash memory page includes: Count the number of basic storage units corresponding to the "11" state, "01" state, "00" state and "10" state in the flash memory page respectively, and obtain N0, N1, N2 and N3 in sequence; According to N0 to N n-1 The size relationship between them determines the voltage distribution offset state of the flash memory page, including: If the flash memory page type is a low-order page, For the threshold voltage R2', compare the magnitudes of N0 + N1 and N2 + N3: If N0 + N1 > N2 + N3, the voltage distribution offset state of the flash memory page is left-offset; If N0 + N1 < N2 + N3, the voltage distribution offset state of the flash memory page is right-offset; If they are equal, the voltage distribution offset state of the flash memory page is non-offset; If the flash memory page type is a high-order page, for the threshold voltage R1', compare the magnitudes of 3×N0 and N1 + N2 + N3: If 3×N0 is greater than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is left-offset; If 3×N0 is less than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is right-offset; If they are equal, the voltage distribution offset state of the flash memory page is non-offset; For the threshold voltage R3', compare the magnitudes of 3×N2 and N1 + N2 + N3: If 3×N2 is greater than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is left-offset; If 3×N2 is less than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is right-offset; If they are equal, the voltage distribution offset state of the flash memory page is non-offset.

2. The data rereading method according to claim 1, wherein: When the flash memory page is configured in the SLC mode, the data states of the basic storage units include: "0" and "1"; The counting of the number of basic storage units corresponding to n data states in the flash memory page, obtaining n numbers, includes: Count the number of basic storage units corresponding to the "0" state and "1" state in the flash memory page respectively, and obtain N0 and N1 correspondingly.

3. The data rereading method according to claim 2, wherein: According to N0 to N n-1 and determining a voltage distribution offset state of the flash memory page based on a magnitude relationship between the voltage distribution of the flash memory page and the voltage distribution of the flash memory page, including: Compare the magnitudes of N0 and N1; If N0 is equal to N1, the voltage distribution offset state of the flash memory page is non-offset; and / or, if N0 is greater than N1, the voltage distribution offset state of the flash memory page is right-offset; and / or, if N0 is less than N1, confirm that the voltage distribution offset state of the flash memory page is left-offset.

4. The data re-reading method according to claim 1, wherein: When the flash memory page is configured in TLC mode, the data states of the basic storage unit include: "000", "001", "010", "011", "100", "101", "110" and "111"; The counting of the numbers of basic storage units corresponding to n data states in the flash memory page to obtain n numbers includes: The numbers of basic storage cells corresponding to the "111" state, "110" state, "100" state, "000" state, "010" state, "011" state, "001" state, and "101" state in the flash memory page are counted, and the corresponding numbers are N0, N1, N2, N3, N4, N5, N6, and N7.

5. The data re-reading method according to claim 4, characterized in that: According to N0 to N n-1 The voltage distribution offset state of the flash memory page is determined based on the size relationship between the two, including: Get the flash page type; The voltage distribution offset state of the flash memory page is determined according to the type of the flash memory page and the relationship between N0 to N7.

6. The data re-reading method according to claim 5, characterized in that: The flash memory page types include: low page, high page and super page; The determining the voltage distribution offset state of the flash memory page according to the relationship between the flash memory page type and N0 to N7 includes: If the flash memory page type is a low-order page, for the threshold voltage R1″, compare 7×N0 with the values ​​of N1+N2+N3+N4+N5+N6+N7: If 7×N0 is greater than N1+N2+N3+N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is left-biased; If 7×N0 is less than N1+N2+N3+N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is right-skewed; If they are equal, the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R5, compare the size of 3×(N1+N2+N3+N4) and 5×(N5+N6+N7): If 3×(N1+N2+N3+N4) is greater than 5×(N5+N6+N7), the offset state of the voltage distribution of the flash memory page is left-skewed; If 3×(N1+N2+N3+N4) is less than 5×(N5+N6+N7), the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased; If the flash memory page type is a high-order page, for the threshold voltage R2″, compare 3×(N0+N1) with N2+N3+N4+N5+N6+N7: If 3×(N0+N1) is greater than N2+N3+N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is left-biased; If 3×(N0+N1) is less than N2+N3+N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R4, compare the sizes of N0+N1+N2+N3 and N4+N5+N6+N7: If N0+N1+N2+N3 is greater than N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is left-biased; if N0+N1+N2+N3 is less than N4+N5+N6+N7, the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R6, compare the size of N0+N1+N2+N3+N4+N5 with 3×(N6+N7): If N0+N1+N2+N3+N4+N5 is greater than 3×(N6+N7), the voltage distribution offset state of the flash memory page is left-biased; if N0+N1+N2+N3+N4+N5 is less than 3×(N6+N7), the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased; If the flash memory page type is a middle bit page, for the threshold voltage R3″, compare 5×(N0+N1+N2) and 3×(N3+N4+N5+N6+N7): If 5×(N0+N1+N2) is greater than 3×(N3+N4+N5+N6+N7), the voltage distribution offset state of the flash memory page is left-biased; If 5×(N0+N1+N2) is less than 3×(N3+N4+N5+N6+N7), the voltage distribution offset state of the flash memory page is right-skewed; If they are equal, the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R7, compare the size of N1+N2+N3+N4+N5+N6 with 7×N7: If N1+N2+N3+N4+N5+N6 is greater than 7×N7, the voltage distribution offset state of the flash memory page is left-biased; if N1+N2+N3+N4+N5+N6 is less than 7×N7, the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased.

7. A memory, characterized in that: The memory is used to store a computer program for implementing the data rereading method according to any one of claims 1 to 6, and to use the data rereading method according to any one of claims 1 to 6 to correct data when reading data errors.

8. A readable storage medium, characterized in that: The device stores a computer program, which, when executed on a processor, implements the data re-reading method according to any one of claims 1 to 6.

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