System address mapping method, device, equipment and storage medium

Abstract

The embodiments of the present application disclose a system address mapping method, apparatus, device and storage medium, in which a target system address is obtained by dividing a preset reference system address into multiple address segments, and then performing segmented mapping according to the physical address corresponding to a single storage page. The storage area corresponding to the first type of address segment in the multiple address segments is used to store protection data and data check codes corresponding to the protection data, and the storage area corresponding to the second type of address segment is used to store non-protection data; therefore, when data is accessed through the target system address, the protection data and its corresponding data check code can be read for the protection data, thereby ensuring the reliability of data reading. At the same time, for non-protection data, the second type of address segment is not divided in the same manner as the first type of address segment, so the second type of address segment is a continuously accessible address, which can improve the access efficiency of non-protection data.

Description

Technical Field

[0001] The present application relates to the field of data storage and access technology, and in particular to a system address mapping method, apparatus, device and storage medium. Background Art

[0002] During the reading and writing process of DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random-access Memory), inline error-correcting code (inline ECC) is often used for important data to improve read and write reliability.

[0003] At present, in the related art, ECC codes are usually attached to the data block in a fixed ratio, for example, 8 bits of ECC code are attached to every 64 bits of data. In addition, during address mapping, the system address space is fixedly partitioned. For example, in an 8GB storage page, the first 7GB stores data and the last 1GB stores ECC codes. This fixed partitioning allows the controller to access data and its ECC code simultaneously during reading and writing. However, in most scenarios, not all data requires ECC protection. When only part of the data requires ECC protection, for non-ECC protected data, since the system address allocation method is still mapped in a fixed partitioning manner, the address of the non-ECC protected data will also be divided into two parts, resulting in poor access efficiency. Summary of the Invention

[0004] To solve the above technical problems, embodiments of the present application provide a system address mapping method, apparatus, device, and storage medium to improve the efficiency of data access.

[0005] According to one aspect of an embodiment of the present application, a system address mapping method is provided, comprising: obtaining a physical address corresponding to a single storage page in a preset memory; wherein the high bits of the column address in the physical address are used to address a data check code storage area, and the low bits of the column address in the physical address are used to address a data storage area; the data storage area stores protection data and non-protection data; dividing the preset reference system address to obtain a plurality of address segments; wherein the plurality of address segments include a first type of address segment and a second type of address segment, the storage area corresponding to the first type of address segment is used to store protection data and a data check code corresponding to the protection data, and the storage area corresponding to the second type of address segment is used to store non-protection data; performing address mapping on the plurality of address segments according to the physical address corresponding to the single storage page to obtain a target system address.

[0006] In some embodiments, the address mapping of the multiple address segments according to the physical address corresponding to the single storage page to obtain the target system address includes: mapping the high bits of the first type address segment in the multiple address segments to the high bits of the column address of the physical address, and mapping the low bits of the first type address segment in the multiple address segments to the low bits of the column address storing protection data in the physical address; and mapping the low bits of the second type address segment in the multiple address segments to the low bits of the column address storing non-protection data in the physical address.

[0007] In some embodiments, the storage area corresponding to the physical address corresponding to the single storage page is divided into eight equal parts, the first seven equal parts are used to store protection data and non-protection data, and the last equal part is used to store a data check code corresponding to the protection data.

[0008] In some embodiments, dividing the preset reference system address to obtain multiple address segments includes: obtaining the data type and data size stored in the physical address; dividing the preset reference system address according to the data type and data size to obtain multiple address segments.

[0009] In some embodiments, dividing the preset reference system address to obtain multiple address segments includes: obtaining a preset custom segmentation method; and dividing the preset reference system address according to the custom segmentation method to obtain multiple address segments.

[0010] In some embodiments, after performing address mapping on the multiple address segments according to the physical address corresponding to the single storage page to obtain a target system address, the method further includes: accessing data according to the target system address.

[0011] In some embodiments, after performing address mapping on the multiple address segments according to the physical addresses corresponding to the single storage page to obtain the target system address, the method further includes: upon receiving a preset instruction, re-dividing the reference system addresses corresponding to the multiple address segments; wherein the preset instruction includes a power-on instruction, a power-off instruction, and a reset instruction.

[0012] According to one aspect of an embodiment of the present application, a system address mapping device is provided, comprising: an acquisition module, a division module and a mapping module; wherein the acquisition module is configured to acquire a physical address corresponding to a single storage page in a preset memory; wherein the high bits of the column address in the physical address are used to address a data check code storage area, and the low bits of the column address in the physical address are used to address a data storage area; the data storage area stores protection data and non-protection data; the division module is configured to divide a preset reference system address to obtain a plurality of address segments; wherein the plurality of address segments include a first type address segment and a second type address segment, the storage area corresponding to the first type address segment is used to store protection data and a data check code corresponding to the protection data, and the storage area corresponding to the second type address segment is used to store non-protection data; the mapping module is configured to perform address mapping on the plurality of address segments according to the physical address corresponding to the single storage page to obtain a target system address.

[0013] According to one aspect of an embodiment of the present application, an electronic device is provided, comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the system address mapping method as described above.

[0014] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor of a computer, the computer executes the system address mapping method as described above.

[0015] In the technical solution provided in the embodiment of the present application, the physical address corresponding to a single storage page in the preset memory is obtained, and the preset reference system address is divided into multiple address segments, and then segmented mapping is performed according to the physical address corresponding to the single storage page to obtain the target system address. In this way, since the multiple address segments include a first-type address segment and a second-type address segment, the storage area corresponding to the first-type address segment is used to store protection data and a data check code corresponding to the protection data, and the storage area corresponding to the second-type address segment is used to store non-protection data; therefore, when data is accessed through the target system address, the protection data and its corresponding data check code can be read for the protection data, thereby ensuring the reliability of data reading. At the same time, for non-protection data, the second-type address segment is not divided in the same manner as the first-type address segment, so the second-type address segment is a continuously accessible address, which can improve the access efficiency of non-protection data.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application and, together with the specification, serving to explain the principles of the present application. It is obvious that the drawings described below are merely some embodiments of the present application, and a person of ordinary skill in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0018] Figure 1 It is a schematic diagram of an implementation environment involved in a system address mapping method shown in an exemplary embodiment of the present application;

[0019] Figure 2 This is a schematic diagram of an application of physical address mapping on the particle side shown in an exemplary embodiment of the present application;

[0020] Figure 3 This is a schematic diagram of an application of conventional system address mapping shown in an exemplary embodiment of the present application;

[0021] Figure 4 This is a schematic diagram of an application of conventional system address mapping for partial data protection, shown in an exemplary embodiment of the present application;

[0022] Figure 5 yes Figure 1 Step S130 in the illustrated embodiment is a flow chart of performing segment address mapping in an exemplary embodiment;

[0023] Figure 6 This is a schematic diagram of an application of segmented address mapping shown in an exemplary embodiment of the present application;

[0024] Figure 7 is a flowchart of a system address mapping method shown in another exemplary embodiment of the present application;

[0025] Figure 8 is a structural diagram of a system address mapping device shown in an exemplary embodiment of the present application;

[0026] Figure 9 A schematic diagram of the structure of a computer system suitable for implementing an electronic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0027] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments applicable to the present application. Rather, they are merely examples of apparatus and methods applicable to certain aspects of the present application, as detailed in the appended claims.

[0028] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. In other words, these functional entities may be implemented in the form of an application program, in one or more hardware modules or integrated circuits, or in different models and / or processor devices and / or microcontroller devices.

[0029] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0030] It should be noted that the term "plurality" used in this application refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0031] First, it should be noted that the default memory in this application is DDR (Double Data Rate) SDRAM (synchronous dynamic random-access memory). During the read and write process of DDR SDRAM, inline ECC (Error-Correcting Code) is often used for important data to improve read and write reliability. The inline ECC function allows the DDR controller to generate a corresponding ECC code based on the written data while writing data to the DDR SDRAM. The ECC code is then stored in the same DDR SDRAM page. When reading data from the DDR SDRAM, both the ECC code and the corresponding data are read out and an ECC check is performed to improve data access reliability. Therefore, the core goal of inline ECC is real-time detection, rather than post-verification after data transmission is completed. This technology is widely used in storage, communications, and hardware design to improve system reliability and efficiency.

[0032] In some embodiments, a real-time error correction module is embedded in the memory controller to generate or verify error correction codes in real time while data is being written, read, or transmitted. The error correction codes may be Hamming codes, LDPC codes, Reed-Solomon codes, etc. This enables real-time verification of data integrity and immediate correction of errors upon discovery, reducing latency and subsequent processing burden.

[0033] In related technologies, ECC codes are usually attached to data blocks in a fixed ratio, for example, 8 bits of ECC code are attached to every 64 bits of data. In addition, during address mapping, the system address space is fixedly partitioned. For example, in an 8GB storage page, the first 7GB stores data, and the last 1GB stores ECC codes. This fixed partitioning allows the controller to access data and its ECC code simultaneously during reading and writing. However, in most scenarios, not all data requires ECC protection. When only part of the data requires ECC protection, for non-ECC protected data, since the system address allocation method is still mapped in a fixed partitioning manner, the address of the non-ECC protected data will also be divided into two parts, resulting in poor access efficiency.

[0034] Based on this, the present application provides a system address mapping method, which obtains the physical address corresponding to a single storage page in a preset memory, divides the preset reference system address into multiple address segments, and then performs segmented mapping based on the physical address corresponding to the single storage page to obtain the target system address. In this way, since the multiple address segments include a first-type address segment and a second-type address segment, the storage area corresponding to the first-type address segment is used to store protection data and a data check code corresponding to the protection data, and the storage area corresponding to the second-type address segment is used to store non-protection data; therefore, when accessing data through the target system address, for protection data, the protection data and its corresponding data check code can be read, thereby ensuring the reliability of data reading. At the same time, for non-protection data, the second-type address segment is not divided in the same way as the first-type address segment, so the second-type address segment is a continuously accessible address, which can improve the access efficiency of non-protection data.

[0035] The following describes in detail the system address mapping method provided in the embodiment of the present application.

[0036] Please continue reading Figure 1 , Figure 1 FIG. 1 is a flowchart of a system address mapping method shown in an exemplary embodiment of the present application. Figure 1 As shown, in an exemplary embodiment, the system address mapping method includes at least steps S110 to S130, which are described in detail as follows:

[0037] Step S110: Obtain the physical address corresponding to a single storage page in a preset memory. The upper bits of the column address in the physical address are used to address the data check code storage area, and the lower bits of the column address in the physical address are used to address the data storage area; the data storage area stores protected data and non-protected data.

[0038] It should be understood that in the process of reading or writing data in DDR SDRAM, two addresses are involved, one is the system address and the other is the physical address of DDR SDRAM (i.e., particle address). The DDR SDRAM host will initiate data access to the DDR SDRAM according to the system address. The DDR controller converts the system address into the physical address of DDR SDRAM, and then accesses data in the DDR SDRAM according to the physical address.

[0039] In some embodiments, physical addresses are typically divided into row addresses and column addresses. When accessing memory, the row address is first activated, the data of the entire row is read into the row buffer, and then the column address is used to access specific data in the row. Therefore, the memory page in this application refers to a row opened after the row address is activated, and the physical address of the memory page refers to the granule address, that is, the address structure inside the memory granule.

[0040] Combine Figure 2 As shown, Figure 2 This is a schematic diagram of an application of physical address mapping on the particle side shown in an exemplary embodiment of the present application. Figure 2 The memory cell includes multiple memory cells such as bank 0, bank 1, ..., bank n. The horizontal axis of each memory cell is the column address and the vertical axis is the row address. Each memory cell includes multiple memory pages. The storage area corresponding to the physical address of a single memory page is divided into eight equal parts. The first seven equal parts are used to store protected data and non-protected data, and the last equal part is used to store the data check code corresponding to the protected data. It can be understood that a memory page is a row in a memory cell, such as Figure 2 As shown, the storage area corresponding to a single storage page is divided into two areas from low to high, that is, the first 7 / 8 is the data area, and the last 1 / 8 is the ECC code area, wherein the first 7 / 8 of the data area is used to store data, and the last 1 / 8 of the ECC code area is used to store the ECC code corresponding to the data.

[0041] Step S120: Divide the preset reference system address into multiple address segments, wherein the multiple address segments include first-type address segments and second-type address segments. The storage area corresponding to the first-type address segments is used to store protected data and data check codes corresponding to the protected data, and the storage area corresponding to the second-type address segments is used to store unprotected data.

[0042] In an embodiment of the present application, by dividing the preset reference system address to obtain multiple address segments of different types, the system address can be divided into multiple data protection segments and non-protection segments. This makes it easy to perform address mapping in different ways for different types of address segments, thereby ensuring the access reliability of protected data and improving the access efficiency of non-protected data.

[0043] Combine Figure 3 As shown, Figure 3 This is a schematic diagram of an application of conventional system address mapping shown in an exemplary embodiment of the present application. Figure 3 In order to ensure the continuity of host access, the upper three bits of the system address are usually mapped to the upper three bits of the column address of the physical address, that is, the upper 1 / 8 of the system address is used to store the ECC code. In some embodiments, the entire system address space is 8GB, 0-7GB is the data area for storing data, and 7GB-8GB is the ECC code area for storing the ECC code corresponding to the data. Figure 3 As shown, region0 is the data area and region1 is the ECC code area.

[0044] In a storage unit, not all data requires ECC protection. Considering costs and resources, as well as ensuring system performance and reliability, ECC is typically used to protect only critical data. For scenarios where only some data requires ECC protection, the entire storage area containing unprotected data is used to store data without ECC. However, because related technologies still divide system addresses into two areas (the ECC area and the data area), the storage area for unprotected data is still divided into two parts, resulting in non-contiguous system addresses being mapped, which can easily reduce access efficiency.

[0045] See also Figure 4 , Figure 4 This is a schematic diagram of an application of conventional system address mapping for partial data protection, shown in an exemplary embodiment of the present application. Figure 4 In comparison with Figure 3 The data area shown, Figure 4The data area in the bytecode is divided into ECC protection area and non-ECC protection area; among them, the ECC protection area includes region0 and region2, the non-ECC protection area includes region1, and region3 was originally used to store the ECC codes corresponding to all data (including ECC code0 corresponding to the protection data stored in region0, and ECC code2 corresponding to the protection data stored in region2). However, due to the existence of non-ECC protection area, some unused areas exist in region3 (i.e. Figure 4 The unused area in region 1 is originally used to store the ECC codes corresponding to the data in region 1. This unused area is scattered across region 3, hindering system data access. Furthermore, when a memory page contains only valid data, the addresses accessed by the system are split into two parts based on this mapping method: the first 7 / 8 of the memory page is accessed through the 0-7GB address space, and the last 1 / 8 of the memory page is accessed through the 7-8GB address space. This results in discontinuous data access, reducing access efficiency.

[0046] In the embodiment of the present application, by dividing the preset reference system address into multiple address segments of different types, the addresses corresponding to the protected data and the unprotected data can be segmented and mapped, thereby ensuring that each address segment is continuously accessible and improving access efficiency.

[0047] Exemplarily, dividing the preset reference system address to obtain multiple address segments includes: obtaining the data type and data size stored in the physical address; dividing the preset reference system address according to the data type and data size to obtain multiple address segments.

[0048] In the embodiment of the present application, the reference system address is divided according to the stored data type and data size, and the influence of different data types and data sizes on the address division is taken into consideration, so that the address division can be more accurate.

[0049] In some embodiments, the preset reference system address is divided according to the data type and data size to obtain multiple address segments, including: matching the address segment length and the number of address segments corresponding to the data type and data size from a preset database; dividing the preset reference system address according to the address segment length and the number of address segments to obtain multiple address segments.

[0050] For example, there are as many address segments as there are types of data, and the data size of different types of data is positively correlated with the length of the address segment. The larger the data size, the longer the corresponding address segment length.

[0051] Exemplarily, dividing a preset reference system address to obtain a plurality of address segments includes: acquiring a preset custom segmentation method; and dividing the preset reference system address according to the custom segmentation method to obtain a plurality of address segments.

[0052] In the embodiment of the present application, customized segmentation can be performed in advance, which can facilitate more flexible segmentation, so that the obtained multiple address segments are more in line with actual needs, and the flexibility and adaptability of the segmentation are improved.

[0053] Step S130 , performing address mapping on multiple address segments according to the physical address corresponding to a single storage page to obtain a target system address.

[0054] In an embodiment of the present application, after segmentation processing, address mapping in different ways can be performed for different types of address segments. For data that need to be protected, address mapping can still be performed by dividing it into protected data areas and ECC code areas from low to high. For data that do not need to be protected, mapping can be performed in address order, thereby ensuring the access reliability of protected data and improving the access efficiency of non-protected data.

[0055] In some embodiments, combined Figure 5 As shown, Figure 5 yes Figure 1 Step S130 in the illustrated embodiment is a flow chart of performing segment address mapping in an exemplary embodiment; it includes at least steps S510 to S520, which are described in detail as follows:

[0056] In step S510, the upper bits of the first type address segments in the plurality of address segments are mapped to the upper bits of the column address of the physical address, and the lower bits of the first type address segments in the plurality of address segments are mapped to the lower bits of the column address storing the protection data in the physical address.

[0057] It can be understood that the storage area corresponding to the first type of address segment in the embodiment of the present application is used to store protection data and the data check code (i.e., ECC code) corresponding to the protection data. In the first type of address segment, it is mapped from low to high in sequence to the protection data area and the ECC code area.

[0058] For example, for a first-type address segment, the upper three bits of the first-type address segment can be mapped to the upper three bits of the physical column address (all 1), thereby dividing the last 1 / 8 of the first-type address segment into an ECC code area and the first 7 / 8 into a continuously accessible protected data area. This ensures the reliability of access to the protected data.

[0059] Step S520 : Map the lower bits of the second type address segment in the plurality of address segments to the lower bits of the column address storing the non-protected data in the physical address.

[0060] The storage area corresponding to the second type of address segment in the embodiment of the present application is used to store non-protected data. In the second type of address segment, a normal address mapping method is adopted, that is, the column address in the physical address is mapped to the low bit of the system address. The target system address obtained at this time can continuously and efficiently access a storage page, solving the problem of scattered addresses in the system's accessible space and low access efficiency.

[0061] In some embodiments, combined Figure 6 As shown, Figure 6 This is a schematic diagram of the application of segmented address mapping shown in an exemplary embodiment of the present application. Figure 6 The system address in the is divided into three address segments: region 0 and region 1 form a first-type address segment, region 2 a second-type address segment, and region 3 and region 4 a third-type address segment. In a first-type address segment, the segment is divided into eight equal parts: the first 7 / 8 is the protected data area, such as region 0, and the last 1 / 8 is the ECC code area, such as region 1. In a second-type address segment, the mapped address is used to address non-protected data.

[0062] In an embodiment of the present application, by dividing the preset reference system address to obtain multiple address segments of different types, the system address can be divided into multiple data protection segments and non-protection segments. This makes it convenient to perform address mapping in different ways for different types of address segments. For the first type of address segment, it is divided into a protected data area and an ECC code area for address mapping. For the second type of address segment, the non-protected data area is address mapped according to a normal mapping method, thereby ensuring the access reliability of the protected data and improving the access efficiency of the non-protected data.

[0063] In some embodiments, after performing address mapping on multiple address segments based on the physical address corresponding to a single storage page to obtain a target system address, the method further includes: accessing data based on the target system address. In this way, accessing data based on the segmented mapped target system address can improve access efficiency of non-protected data.

[0064] Please continue reading Figure 7 , Figure 7 is a flowchart of a system address mapping method shown in another exemplary embodiment of the present application. Figure 1 After step S130 in the embodiment of the present application, the system address mapping method further includes at least step S710, which is described in detail as follows:

[0065] Step S710: upon receiving a preset instruction, re-dividing the reference system addresses corresponding to the plurality of address segments, wherein the preset instruction includes a power-on instruction, a power-off instruction, and a reset instruction.

[0066] In an embodiment of the present application, by re-dividing the reference system address at each power-on, power-off or reset, not only can resource utilization be optimized, address mapping can be adapted to different needs, and the performance of system access to data can be optimized, but also the security and adaptability of the system can be improved. In addition, re-dividing the address segments helps to organize memory, release unused space, and improve utilization.

[0067] In some embodiments, upon receiving a preset instruction, the reference system addresses corresponding to the plurality of address segments are re-divided, including: obtaining a current configuration requirement, and re-dividing the reference system addresses according to the current configuration requirement.

[0068] For example, the current configuration requirements may include the data type and data size stored in the physical address, and the reference system address is re-divided according to the data type and data size. For example, for metadata and small files, the first type of address segment is suitable for address mapping, which prioritizes data access reliability; for streaming data and large files, the second type of address segment is suitable for address mapping, which improves data throughput through continuous mapping.

[0069] Combine Figure 8 As shown, Figure 8 FIG. 1 is a structural diagram of a system address mapping device shown in an exemplary embodiment of the present application. Figure 8 As shown, the exemplary system address mapping device includes: an acquisition module 810, a division module 820 and a mapping module 830. The acquisition module 810 is configured to acquire the physical address corresponding to a single storage page in a preset memory; wherein the high bit of the column address in the physical address is used to address the data check code storage area, and the low bit of the column address in the physical address is used to address the data storage area; the data storage area stores protection data and non-protection data; the division module 820 is configured to divide the preset reference system address to obtain multiple address segments; wherein the multiple address segments include a first type address segment and a second type address segment, the storage area corresponding to the first type address segment is used to store protection data and the data check code corresponding to the protection data, and the storage area corresponding to the second type address segment is used to store non-protection data; the mapping module 830 is configured to perform address mapping on the multiple address segments according to the physical address corresponding to the single storage page to obtain the target system address.

[0070] In an embodiment of the present application, by adopting the exemplary system address mapping device, since the multiple address segments include a first type of address segment and a second type of address segment, the storage area corresponding to the first type of address segment is used to store protection data and a data check code corresponding to the protection data, and the storage area corresponding to the second type of address segment is used to store non-protection data; therefore, when data is accessed through the target system address, the protection data and its corresponding data check code can be read out for the protection data, thereby ensuring the reliability of data reading. At the same time, for non-protection data, the second type of address segment is not divided in the same manner as the first type of address segment, so the second type of address segment is a continuously accessible address, which can improve the access efficiency of non-protection data.

[0071] In another exemplary embodiment, the mapping module 830 is configured to perform address mapping on multiple address segments according to the physical address corresponding to a single storage page to obtain a target system address in the following manner, including: mapping the high bits of the first type address segments in the multiple address segments to the high bits of the column address of the physical address, and mapping the low bits of the first type address segments in the multiple address segments to the low bits of the column address storing protection data in the physical address; and mapping the low bits of the second type address segments in the multiple address segments to the low bits of the column address storing non-protection data in the physical address.

[0072] In another exemplary embodiment, the storage area corresponding to the physical address corresponding to a single storage page is divided into eight equal parts, the first seven equal parts are used to store protection data and non-protection data, and the last equal part is used to store a data check code corresponding to the protection data.

[0073] In another exemplary embodiment, the division module 820 is configured to divide the preset reference system address to obtain multiple address segments in the following manner, including: obtaining the data type and data size stored in the physical address; dividing the preset reference system address according to the data type and data size to obtain multiple address segments.

[0074] In another exemplary embodiment, the division module 820 is configured to divide the preset reference system address to obtain multiple address segments by: obtaining a preset custom segmentation method; dividing the preset reference system address according to the custom segmentation method to obtain multiple address segments.

[0075] In another exemplary embodiment, the system address mapping device further includes an access module, which is configured to perform address mapping on multiple address segments according to the physical address corresponding to a single storage page, obtain a target system address, and then perform data access according to the target system address.

[0076] In another exemplary embodiment, the system address mapping device further includes an adjustment module, and the adjustment module is configured to dynamically adjust the types of the multiple address segments.

[0077] It should be noted that the system address mapping device provided in the above embodiment and the system address mapping method provided in the above embodiment are based on the same concept. The specific manner in which each module and unit performs operations has been described in detail in the method embodiment and will not be repeated here. In actual applications, the system address mapping device provided in the above embodiment can, as needed, allocate the above functions to different functional modules, that is, divide the internal structure of the device into different functional modules to complete all or part of the functions described above. This is not limited here.

[0078] An embodiment of the present application also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the system address mapping method provided in the above-mentioned embodiments.

[0079] Figure 9 The following is a schematic diagram showing the structure of a computer system suitable for implementing an electronic device according to an embodiment of the present application. Figure 9 The computer system 900 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0080] like Figure 9 As shown, computer system 900 includes a central processing unit (CPU) 901, which can perform various appropriate actions and processes, such as the methods described in the above embodiments, based on programs stored in read-only memory (ROM) 902 or programs loaded from storage 908 into random access memory (RAM) 903. RAM 903 also stores various programs and data required for system operation. CPU 901, ROM 902, and RAM 903 are interconnected via a bus 904. An input / output (I / O) interface 905 is also connected to bus 904.

[0081] The following components are connected to the I / O interface 905: an input section 906 including a keyboard, a mouse, and the like; an output section 907 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and speakers; a storage section 908 including devices such as a hard disk; and a communication section 909 including a module interface card such as a LAN (Local Area Network) card or a modem. The communication section 909 performs communication processing via a module such as the Internet. A drive 910 is also connected to the I / O interface 905 as needed. Removable media 911, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 910 as needed, so that computer programs read from the removable media can be installed in the storage section 908 as needed.

[0082] In particular, according to embodiments of the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program including a computer program for executing the methods illustrated in the flowcharts. In such embodiments, the computer program can be downloaded and installed from the model via the communication section 909 and / or installed from removable media 911. When the computer program is executed by the central processing unit (CPU) 901, the various functions defined in the system of the present application are performed.

[0083] It should be noted that the computer-readable medium described in the embodiments of this application may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may, for example, be an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying a computer-readable computer program. This propagated data signal may take a variety of forms, including, but not limited to, an electromagnetic signal, an optical signal, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. A computer program embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0084] Another aspect of the present application provides a computer-readable storage medium having a computer program stored thereon. When executed by a processor, the computer program implements the system address mapping method described above. The computer-readable storage medium may be included in the electronic device described in the above embodiments, or may exist independently and not be incorporated into the electronic device.

[0085] Another aspect of the present application provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the system address mapping method provided in each of the above embodiments.

[0086] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation scheme of the present application. Ordinary technicians in this field can easily make corresponding changes or modifications based on the main ideas and spirit of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection required by the claims.

[0087] It should be noted that when the embodiments of the present application are applied to specific products or technologies, such as obtaining a physical address, it is inevitable to obtain the data storage address in the memory, so it is necessary to obtain the permission or consent of the relevant object, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

Claims

1. A system address mapping method, characterized in that: include: Obtaining a physical address corresponding to a single storage page in a preset memory; wherein the upper bits of the column address in the physical address are used to address a data check code storage area, and the lower bits of the column address in the physical address are used to address a data storage area; the data storage area stores protected data and unprotected data; Dividing a preset reference system address to obtain a plurality of address segments; wherein the plurality of address segments include a first type of address segment and a second type of address segment, the storage area corresponding to the first type of address segment is used to store protection data and a data check code corresponding to the protection data, and the storage area corresponding to the second type of address segment is used to store non-protection data; Performing address mapping on the multiple address segments according to the physical address corresponding to the single storage page to obtain a target system address; The address mapping of the multiple address segments according to the physical address corresponding to the single storage page to obtain the target system address includes: mapping the high bits of the first type address segment in the multiple address segments to the high bits of the column address of the physical address, and mapping the low bits of the first type address segment in the multiple address segments to the low bits of the column address storing protection data in the physical address, so as to divide the latter 1 / 8 of the storage area corresponding to the first type address segment into an ECC code area and the former 7 / 8 into a continuously accessible protection data area; and mapping the low bits of the second type address segment in the multiple address segments to the low bits of the column address storing non-protection data in the physical address.

2. The method according to claim 1, characterized in that The storage area corresponding to the physical address corresponding to the single storage page is divided into eight equal parts, the first seven equal parts are used to store protection data and non-protection data, and the last equal part is used to store a data check code corresponding to the protection data.

3. The method according to claim 1, characterized in that The preset reference system address is divided to obtain multiple address segments, including: Obtaining the data type and data size stored in the physical address; The preset reference system address is divided according to the data type and data size to obtain multiple address segments.

4. The method according to claim 1, wherein The preset reference system address is divided to obtain multiple address segments, including: Get the preset custom segmentation method; The preset reference system address is divided according to the custom segmentation method to obtain multiple address segments.

5. The method according to claim 1, wherein After performing address mapping on the multiple address segments according to the physical address corresponding to the single storage page to obtain the target system address, the method further includes: Data access is performed according to the target system address.

6. The method according to claim 1, characterized in that After performing address mapping on the multiple address segments according to the physical address corresponding to the single storage page to obtain the target system address, the method further includes: When a preset instruction is received, the reference system addresses corresponding to the multiple address segments are re-divided; wherein the preset instruction includes a power-on instruction, a power-off instruction, and a reset instruction.

7. A system address mapping device, characterized in that: include: an acquisition module configured to acquire a physical address corresponding to a single storage page in a preset memory; wherein the upper bits of the column address in the physical address are used to address a data check code storage area, and the lower bits of the column address in the physical address are used to address a data storage area; and the data storage area stores protected data and unprotected data; a partitioning module configured to partition a preset reference system address to obtain a plurality of address segments; wherein the plurality of address segments include a first type of address segment and a second type of address segment, wherein a storage area corresponding to the first type of address segment is used to store protection data and a data check code corresponding to the protection data, and a storage area corresponding to the second type of address segment is used to store non-protection data; a mapping module configured to perform address mapping on the multiple address segments according to the physical address corresponding to the single storage page to obtain a target system address; The address mapping of the multiple address segments according to the physical address corresponding to the single storage page to obtain the target system address includes: mapping the high bits of the first type address segment in the multiple address segments to the high bits of the column address of the physical address, and mapping the low bits of the first type address segment in the multiple address segments to the low bits of the column address storing protection data in the physical address, so as to divide the latter 1 / 8 of the storage area corresponding to the first type address segment into an ECC code area and the former 7 / 8 into a continuously accessible protection data area; and mapping the low bits of the second type address segment in the multiple address segments to the low bits of the column address storing non-protection data in the physical address.

8. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, which, when executed by the one or more processors, enables the electronic device to implement the system address mapping method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that Computer-readable instructions are stored thereon, and when the computer-readable instructions are executed by a processor of a computer, the computer is caused to execute the system address mapping method according to any one of claims 1 to 6.

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