FPGA configuration and readback method and system

Abstract

The present invention relates to the technical field of data configuration readback, specifically an FPGA configuration and readback method and system, comprising: constructing an FPGA structure, identifying original configuration data in an external device, processing the original configuration data using a data processing unit in a configuration module to obtain target configuration data, storing the target configuration data in an SRAM array using the configuration module, identifying target readback data in the FPGA structure, and transmitting the target readback data to an external device using the configuration module. The present invention can simplify the operational process of FPGA data configuration and readback, thereby improving the efficiency of data configuration.

Description

Technical Field

[0001] The present invention relates to the technical field of data configuration readback, and in particular to an FPGA configuration and readback method and system. Background Art

[0002] Bitstream configuration is an essential step in using FPGA chips. This step configures the bitstream generated by compiling the user's project into the FPGA, forming a circuit structure and implementing the required logical functions. In some special application scenarios or during debugging, the bitstream also needs to be read back to the local computer or CPU. An efficient configuration readback structure is also a feature of high-performance FPGAs. The configuration readback pipeline structure described in the present invention is applicable to small-scale to very large-scale FPGA chips.

[0003] The traditional method uses a two-stage pipeline configuration circuit to implement FPGA data configuration and readback. Although this method can achieve FPGA data configuration and readback to a certain extent, the circuit structure involved in this method is relatively complex and the data transmission efficiency is low. Summary of the Invention

[0004] The present invention provides an FPGA configuration and readback method and system, the main purpose of which is to simplify the operation process of FPGA data configuration and readback and improve the efficiency of data configuration.

[0005] To achieve the above objectives, the present invention provides an FPGA configuration and readback method, comprising:

[0006] Constructing an FPGA structure, wherein the FPGA structure includes: a configuration module, a shift register, a holding register, and an SRAM array, and the configuration module includes: a data processing unit, an address generation unit, a word line control unit, and a read / write control unit;

[0007] Identifying original configuration data in a pre-built external device, and processing the original configuration data using a data processing unit in a configuration module to obtain target configuration data, wherein the target configuration data includes a plurality of data frame groups, and each data frame group includes a valid data frame and a padding data frame;

[0008] The target configuration data is stored in the SRAM array using the configuration module to complete the configuration of the target configuration data, wherein the transmission path of the target configuration data is: shift register, holding register and SRAM array;

[0009] Identify target readback data in the FPGA structure, wherein the target readback data includes a plurality of readback data frame groups, and each readback data frame group includes: a readback fill frame and a readback valid frame;

[0010] The target readback data is transmitted to the external device using the configuration module to complete the readback of the target readback data, wherein the target readback data transmission path is: SRAM array, holding register, shift register and external device.

[0011] Optionally, the processing of the original configuration data by a data processing unit in the configuration module to obtain target configuration data includes:

[0012] Determining the interface bit width of the configuration module;

[0013] The original configuration data is bitstream parsed using the data processing unit and the interface bit width to obtain the target configuration data, wherein the arrangement of each data frame group in the target configuration data is:

[0014] ;

[0015] in, Represents a data frame group, Indicates the first valid data frame in the data frame group. Indicates the first Valid data frames, Indicates the number of valid data frames in the data frame group. Indicates the first filled data frame in the data frame group. Indicates the second padded data frame in the data frame group.

[0016] Optionally, each data frame in the data frame group includes N unit data, where the unit data is 32-bit wide data.

[0017] Optionally, the utilizing the configuration module to store the target configuration data in the SRAM array to complete the configuration of the target configuration data includes:

[0018] sequentially extracting data frame groups from a plurality of data frame groups of target configuration data;

[0019] Extract the first data frame from the data frame group;

[0020] Using the read-write control unit in the configuration module, the first data frame is written into the shift register to obtain a shift data frame;

[0021] In the step of writing the first data frame into the shift register using the read / write control unit in the configuration module, the address generation unit in the configuration module is used to locate the target storage location of the SRAM array where the first data frame is to be stored;

[0022] Shifting the shifted data frame into the holding register to obtain a held data frame;

[0023] Using a word line control unit, writing the retained data frame into a target storage location in the SRAM array to complete the configuration of the first data frame;

[0024] Eliminate the first data frame from the data frame group to obtain a data frame group to be configured, use the data frame group to be configured as the data frame group, and return to the step of extracting the first data frame from the data frame group until the penultimate valid data frame in the data frame group is configured;

[0025] When the penultimate valid data frame in the data frame group is configured, the last valid frame in the holding register is confirmed;

[0026] Using the first padded data frame and the second padded data frame in the data frame group, the last valid frame is pushed into the SRAM array and the configuration of the data frame group is completed;

[0027] When each of the multiple data frame groups is configured, the configuration of the target configuration data is completed.

[0028] Optionally, the step of writing the retained data frame to a target storage location in the SRAM array by using a word line control unit includes:

[0029] Based on the word line control unit, the word line corresponding to the target storage position in the SRAM array is turned on to obtain a high-level word line;

[0030] Using a high-level word line, writing the retained data frame from the retention register to a target storage location in the SRAM array;

[0031] After the data frame is written into the target storage location in the SRAM array, the high level word line is turned off.

[0032] Optionally, the utilizing the first filling data frame and the second filling data frame in the data frame group to push the last valid frame into the SRAM array and complete the configuration of the data frame group includes:

[0033] Reading the first filling data frame in the data frame group, writing the first filling data frame into the shift register to obtain a push data frame;

[0034] Pushing the last valid frame into a target storage location corresponding to the last valid frame in the SRAM array using a push data frame;

[0035] Reading a second filling data frame in the data frame group, writing the second filling data frame into the shift register to obtain a reset data frame, and using the reset data frame to update the holding register to a preset reset state;

[0036] When the holding register is updated to the reset state, the configuration of the data frame group is completed.

[0037] Optionally, the target readback data is stored in an SRAM array of an FPGA structure, and each of the multiple readback data frame groups of the target readback data is expressed as:

[0038] ;

[0039] in, Indicates reading back the data frame group. Indicates the first read-back fill frame in the read-back data frame group. Indicates the second read-back fill frame in the read-back data frame group. Indicates the first valid frame in the readback data frame group. Indicates reading back the first Read back valid frames, Indicates the number of valid frames read back in the readback data frame group.

[0040] Optionally, the utilizing the configuration module to transmit the target readback data to the external device to complete the readback of the target readback data includes:

[0041] sequentially extracting readback data frame groups from a plurality of readback data frame groups;

[0042] Reading a first readback fill frame in the readback data frame group, wherein the first readback fill frame is stored in a holding register;

[0043] Writing the first readback filling frame into the shift register, wherein after the first readback filling frame is written into the shift register, the shift register is reset;

[0044] In the step of writing the first readback filling frame into the shift register, a readback frame address is generated based on the address generating unit;

[0045] Identify the first valid readback frame corresponding to the readback frame address, and write the first valid readback frame into the holding register based on the word line control unit to obtain a readback holding data frame;

[0046] Writing the readback hold data frame into the shift register to obtain a readback shift data frame, and storing the readback shift data frame into an external device using a read-write control unit;

[0047] The first readback valid frame is removed from the readback data frame group to obtain a to-be-readback data frame group, the to-be-readback data frame group and the readback hold data frame are recorded as a readback data frame group and a first readback fill frame, respectively, and the process returns to the step of generating a readback frame address based on the address generation unit in the step of writing the first readback fill frame into the shift register, until the first readback valid frame becomes the last readback valid frame in the readback data frame group;

[0048] After the last readback valid frame is written into the shift register, the second readback filling frame in the readback data frame group is read, and the last readback valid frame and the second readback filling frame in the shift register are written into the external device to complete the readback of the readback data frame group;

[0049] When each of the plurality of readback data frame groups is read back, the readback of the target readback data is completed.

[0050] Optionally, the last valid frame read back is the first frame in the read back data frame group. Read back valid frames.

[0051] To achieve the above object, the present invention further provides an FPGA configuration and readback system, comprising:

[0052] An FPGA structure construction module is used to construct an FPGA structure, wherein the FPGA structure includes: a configuration module, a shift register, a holding register and an SRAM array, and the configuration module includes: a data processing unit, an address generation unit, a word line control unit and a read / write control unit;

[0053] an original data processing module, configured to identify original configuration data in a pre-built external device and process the original configuration data using a data processing unit in the configuration module to obtain target configuration data, wherein the target configuration data includes a plurality of data frame groups, and each data frame group includes a valid data frame and a padding data frame;

[0054] A data configuration module is used to store target configuration data into the SRAM array using the configuration module, wherein the transmission path of the target configuration data is: a shift register, a holding register and the SRAM array;

[0055] The data readback module is used to identify the target readback data in the FPGA structure and transmit the target readback data to the external device using the configuration module, wherein the target readback data includes multiple readback data frame groups, and each readback data frame group includes: a readback fill frame and a readback valid frame. The target readback data transmission path is: SRAM array, holding register, shift register and external device.

[0056] In order to solve the above problem, the present invention further provides an electronic device, comprising:

[0057] a memory storing at least one instruction; and

[0058] The processor executes the instructions stored in the memory to implement the above-mentioned FPGA configuration and readback method.

[0059] In order to solve the above problems, the present invention also provides a computer-readable storage medium, which stores at least one instruction. The at least one instruction is executed by a processor in an electronic device to implement the above-mentioned FPGA configuration and readback method.

[0060] The present invention aims to solve the problems described in the background technology. The present invention first constructs an FPGA structure, wherein the FPGA structure includes: a configuration module, a shift register, a holding register and an SRAM array, and the configuration module includes: a data processing unit, an address generation unit, a word line control unit and a read-write control unit. The FPGA structure of the present invention has both a shift register and a holding register. By sharing the shift register and the holding register, the control circuit in the data configuration and readback process is simplified, thereby reducing the operational complexity of the data configuration and readback, and ensuring high-speed and reliable FPGA configuration and readback. Furthermore, the target configuration data in the present invention includes multiple data frame groups, and each data frame group The target readback data in the present invention includes multiple readback data frame groups, and each readback data frame group includes: a readback fill frame and a readback valid frame. The present invention introduces a fill frame into the above data frame, that is, a fill frame in the configuration process and a readback fill frame in the readback process. The fill frame has the function of promoting the valid frame and resetting the register. The present invention unifies the data pipeline structure in the configuration and readback processes by introducing the fill frame, while ensuring efficient and reliable data transmission. In addition, the present invention uses the frame as the basic unit to achieve high-throughput configuration and readback, and through the generated frame address, it can achieve partial configuration readback and compressed configuration, greatly improving configuration efficiency. Therefore, the present invention can simplify the operation process of FPGA data configuration and readback, and improve the efficiency of data configuration. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 A flowchart of an FPGA configuration and readback method provided by one embodiment of the present invention;

[0062] Figure 2 A functional module diagram of an FPGA configuration and readback system provided by one embodiment of the present invention;

[0063] Figure 3 A schematic diagram of an electronic device implementing the FPGA configuration and readback method provided by an embodiment of the present invention.

[0064] Description of reference numerals:

[0065] 1. Electronic device; 10. Processor; 11. Memory; 12. Bus.

[0066] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0067] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0068] The present invention provides an FPGA configuration and readback method. The FPGA configuration and readback method may be performed by at least one electronic device, such as a server or a terminal, that can be configured to perform the method provided by the present invention. In other words, the FPGA configuration and readback method may be performed by software or hardware installed on a terminal or server device, where the software may be a blockchain platform. The server may include, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0069] Reference Figure 1 FIG. 1 is a flow chart of an FPGA configuration and readback method according to an embodiment of the present invention. In this embodiment, the FPGA configuration and readback method includes:

[0070] S1. Construct an FPGA structure, wherein the FPGA structure includes: a configuration module, a shift register, a holding register and an SRAM array, and the configuration module includes: a data processing unit, an address generation unit, a word line control unit and a read / write control unit.

[0071] It is understandable that the configuration module refers to the circuit that controls configuration and readback. In this configuration module, the data processing unit refers to the control circuit that converts the input raw configuration data into 32-bit wide data, and the address generation unit refers to the control circuit that generates the data frame address. When configuring or reading back the FPGA (Field Programmable Gate Array) chip, the chip automatically generates the address of the data frame through the address generation unit and sends the address to the corresponding frame position in the SRAM array to achieve addressing. The word line control unit refers to the control circuit that controls the opening and closing of the word line. When accessing the SRAM cell, its word line (Word Line) needs to be raised to a high level to control the node that stores data in the basic unit to connect to the bit line (Bit Line) for reading or writing operations. The word line needs to be maintained for a certain time during the reading and writing process to ensure that the data can be written or read correctly. The read and write control unit refers to the control circuit that controls data reading and writing.

[0072] Furthermore, the SRAM array is composed of a plurality of SRAM cells, and the SRAM array is supplemented with necessary pre-charging circuits, sensitive amplifier circuits, and the like.

[0073] S2. Confirm the original configuration data in the pre-built external device, and use the data processing unit in the configuration module to process the original configuration data to obtain target configuration data, wherein the target configuration data includes multiple data frame groups, and each data frame group includes a valid data frame and a padding data frame.

[0074] As you can see, the external device refers to the external CPU that configures and reads back data from the FPGA structure. As a programmable device, the SRAM-based FPGA chip needs to load data from the external device after power-up. This data is then configured into the SRAM array within the FPGA chip to enable the user program to run. When necessary, the configuration data in the SRAM array is also read back to the local or external CPU for verification.

[0075] It should be explained that the original configuration data refers to the data that needs to be configured from an external device into the FPGA structure. The target configuration data refers to the original configuration data after being processed by the data processing unit. The data frame group includes multiple data frames, wherein the data frames are divided into valid data frames and padding data frames. Valid data frames refer to data frames that need to be configured into the SRAM array during the configuration process, while padding data frames only participate in shifting and updating the holding register and shift register during the configuration process and are not configured into the SRAM array.

[0076] In detail, the data processing unit in the configuration module processes the original configuration data to obtain the target configuration data, including:

[0077] Determining the interface bit width of the configuration module;

[0078] The original configuration data is bitstream parsed using the data processing unit and the interface bit width to obtain the target configuration data, wherein the arrangement of each data frame group in the target configuration data is:

[0079] ;

[0080] in, Represents a data frame group, Indicates the first valid data frame in the data frame group. Indicates the first Valid data frames, Indicates the number of valid data frames in the data frame group. Indicates the first filled data frame in the data frame group. Indicates the second padded data frame in the data frame group.

[0081] It needs to be explained that after the FPGA chip is powered on and the reset and clear processes are completed, all registers (shift registers and holding registers) are set to the initial state, and the FPGA chip starts to read data from the external device. The configuration module parses the bit stream according to the configuration mode interface bit width to form 32-bit wide data, and then starts shift control. The 32-bit data is periodically shifted into the shift register in sequence according to a fixed timing. After N shifts (that is, the shift of a data frame is completed), the control writes all N*32 bits of data in the shift register into the holding register. Since the shift register data is constantly being updated, the data in the shift register will be written to the holding register every N shifts. After the data is kept in the holding register for a period of time, the word line control is turned on, and a frame of data is configured to the corresponding position in the SRAM array according to the generated address.

[0082] Furthermore, the step of shifting a data frame in the data configuration process is: transferring data from the external non-volatile memory (external device) to the SRAM array in the FPGA. In this process, the original data in the external device is first processed to convert the original data into 32-bit wide data, and then the 32-bit wide data is entered into the shift register. This 32-bit wide data is recorded as data N. This data N will be shifted to data N-1, data N-2... until it is shifted to data 0 as other 32-bit wide data are entered. When data N is shifted to data 0, it means that N 32-bit wide data have been entered into the shift register. These N 32-bit wide data are recorded as a frame of data, and a frame of data is written into the holding register. At the same time, the next frame of data begins to enter the shift register.

[0083] It is clear that during the data configuration process, the role of the first filling data frame is to push the last valid data frame in the same data frame group into the holding register, and the role of the first filling data frame is to update the holding register and the shift register to the reset state.

[0084] In detail, each data frame in the data frame group includes N unit data, wherein the unit data is 32-bit wide data.

[0085] S3. Utilize the configuration module to store the target configuration data into the SRAM array to complete the configuration of the target configuration data. The transmission path of the target configuration data is: shift register, holding register and SRAM array.

[0086] In detail, the configuration module is used to store the target configuration data in the SRAM array to complete the configuration of the target configuration data, including:

[0087] sequentially extracting data frame groups from a plurality of data frame groups of target configuration data;

[0088] Extract the first data frame from the data frame group;

[0089] Using the read-write control unit in the configuration module, the first data frame is written into the shift register to obtain a shift data frame;

[0090] In the step of writing the first data frame into the shift register using the read / write control unit in the configuration module, the address generation unit in the configuration module is used to locate the target storage location of the SRAM array where the first data frame is to be stored;

[0091] Shifting the shifted data frame into the holding register to obtain a held data frame;

[0092] Using a word line control unit, writing the retained data frame into a target storage location in the SRAM array to complete the configuration of the first data frame;

[0093] Eliminate the first data frame from the data frame group to obtain a data frame group to be configured, use the data frame group to be configured as the data frame group, and return to the step of extracting the first data frame from the data frame group until the penultimate valid data frame in the data frame group is configured;

[0094] When the penultimate valid data frame in the data frame group is configured, the last valid frame in the holding register is confirmed;

[0095] Using the first padded data frame and the second padded data frame in the data frame group, the last valid frame is pushed into the SRAM array and the configuration of the data frame group is completed;

[0096] When each of the multiple data frame groups is configured, the configuration of the target configuration data is completed.

[0097] It is clear that the first data frame refers to the first valid data frame in the data frame group, the shift data frame refers to the first data frame being shifted, and the hold data frame refers to the shift data frame stored in the hold register. The target storage location refers to the specific location where the first data frame needs to be written.

[0098] In detail, the step of writing the retained data frame to a target storage location in the SRAM array using a word line control unit includes:

[0099] Based on the word line control unit, the word line corresponding to the target storage position in the SRAM array is turned on to obtain a high-level word line;

[0100] Using a high-level word line, writing the retained data frame from the retention register to a target storage location in the SRAM array;

[0101] After the data frame is written into the target storage location in the SRAM array, the high level word line is turned off.

[0102] In detail, the method of utilizing the first filling data frame and the second filling data frame in the data frame group to push the last valid frame into the SRAM array and complete the configuration of the data frame group includes:

[0103] Reading the first filling data frame in the data frame group, writing the first filling data frame into the shift register to obtain a push data frame;

[0104] Pushing the last valid frame into a target storage location corresponding to the last valid frame in the SRAM array using a push data frame;

[0105] Reading a second filling data frame in the data frame group, writing the second filling data frame into the shift register to obtain a reset data frame, and using the reset data frame to update the holding register to a preset reset state;

[0106] When the holding register is updated to the reset state, the configuration of the data frame group is completed.

[0107] It can be understood that the push data frame refers to the first filling data frame being shifted, and the reset data frame refers to the second filling data frame being shifted.

[0108] S4. Confirm the target readback data in the FPGA structure, wherein the target readback data includes a plurality of readback data frame groups, and each readback data frame group includes: a readback fill frame and a readback valid frame.

[0109] It can be understood that the readback filling frame refers to the filling data frame in the data readback process, and the readback valid frame refers to the valid data frame in the data readback process.

[0110] In detail, the target readback data is stored in an SRAM array of an FPGA structure, and each of the multiple readback data frame groups of the target readback data is represented as:

[0111] ;

[0112] in, Indicates reading back the data frame group. Indicates the first read-back fill frame in the read-back data frame group. Indicates the second read-back fill frame in the read-back data frame group. Indicates the first valid frame in the readback data frame group. Indicates reading back the first Read back valid frames, Indicates the number of valid frames read back in the readback data frame group.

[0113] S5. Utilize the configuration module to transmit the target readback data to the external device to complete the readback of the target readback data, wherein the target readback data transmission path is: SRAM array, holding register, shift register and external device.

[0114] In detail, the configuration module is used to transmit the target readback data to the external device to complete the readback of the target readback data, including:

[0115] sequentially extracting readback data frame groups from a plurality of readback data frame groups;

[0116] Reading a first readback fill frame in the readback data frame group, wherein the first readback fill frame is stored in a holding register;

[0117] Writing the first readback filling frame into the shift register, wherein after the first readback filling frame is written into the shift register, the shift register is reset;

[0118] In the step of writing the first readback filling frame into the shift register, a readback frame address is generated based on the address generating unit;

[0119] Identify the first valid readback frame corresponding to the readback frame address, and write the first valid readback frame into the holding register based on the word line control unit to obtain a readback holding data frame;

[0120] Writing the readback hold data frame into the shift register to obtain a readback shift data frame, and storing the readback shift data frame into an external device using a read-write control unit;

[0121] The first readback valid frame is removed from the readback data frame group to obtain a to-be-readback data frame group, the to-be-readback data frame group and the readback hold data frame are recorded as a readback data frame group and a first readback fill frame, respectively, and the process returns to the step of generating a readback frame address based on the address generation unit in the step of writing the first readback fill frame into the shift register, until the first readback valid frame becomes the last readback valid frame in the readback data frame group;

[0122] After the last readback valid frame is written into the shift register, the second readback filling frame in the readback data frame group is read, and the last readback valid frame and the second readback filling frame in the shift register are written into the external device to complete the readback of the readback data frame group;

[0123] When each of the plurality of readback data frame groups is read back, the readback of the target readback data is completed.

[0124] It is understood that the readback frame address refers to the storage location of the first readback valid frame in the SRAM array. The first readback valid frame refers to the first readback valid frame in the readback data frame group. The readback hold data frame refers to the first readback valid frame stored in the hold register. The readback shift data frame refers to the readback hold data frame being shifted.

[0125] In detail, the last valid frame read back is the first frame in the read back data frame group. Read back valid frames.

[0126] The present invention aims to solve the problems described in the background technology. The present invention first constructs an FPGA structure, wherein the FPGA structure includes: a configuration module, a shift register, a holding register and an SRAM array, and the configuration module includes: a data processing unit, an address generation unit, a word line control unit and a read-write control unit. The FPGA structure of the present invention has both a shift register and a holding register. By sharing the shift register and the holding register, the control circuit in the data configuration and readback process is simplified, thereby reducing the operational complexity of the data configuration and readback, and ensuring high-speed and reliable FPGA configuration and readback. Furthermore, the target configuration data in the present invention includes multiple data frame groups, and each data frame group The target readback data in the present invention includes multiple readback data frame groups, and each readback data frame group includes: a readback fill frame and a readback valid frame. The present invention introduces a fill frame into the above data frame, that is, a fill frame in the configuration process and a readback fill frame in the readback process. The fill frame has the function of promoting the valid frame and resetting the register. The present invention unifies the data pipeline structure in the configuration and readback processes by introducing the fill frame, while ensuring efficient and reliable data transmission. In addition, the present invention uses the frame as the basic unit to achieve high-throughput configuration and readback, and through the generated frame address, it can achieve partial configuration readback and compressed configuration, greatly improving configuration efficiency. Therefore, the present invention can simplify the operation process of FPGA data configuration and readback, and improve the efficiency of data configuration.

[0127] like Figure 2 FIG. 1 is a functional module diagram of an FPGA configuration and readback system provided by an embodiment of the present invention.

[0128] The FPGA configuration and readback system 100 described in the present invention can be installed in an electronic device. Depending on the functionality implemented, the FPGA configuration and readback system 100 may include an FPGA structure building module 101, a raw data processing module 102, a data configuration module 103, and a data readback module 104. A module, also referred to as a unit, is a series of computer program segments that can be executed by an electronic device processor and perform a fixed function. These segments are stored in the electronic device's memory.

[0129] The FPGA structure construction module 101 is used to construct an FPGA structure, wherein the FPGA structure includes: a configuration module, a shift register, a holding register and an SRAM array, and the configuration module includes: a data processing unit, an address generation unit, a word line control unit and a read / write control unit;

[0130] The raw data processing module 102 is used to identify the raw configuration data in the pre-built external device and process the raw configuration data using the data processing unit in the configuration module to obtain target configuration data, wherein the target configuration data includes multiple data frame groups, and each data frame group includes a valid data frame and a padding data frame;

[0131] The data configuration module 103 is used to store target configuration data into the SRAM array using the configuration module, wherein the transmission path of the target configuration data is: shift register, holding register and SRAM array;

[0132] The data readback module 104 is used to identify the target readback data in the FPGA structure and transmit the target readback data to the external device using the configuration module, wherein the target readback data includes multiple readback data frame groups, and each readback data frame group includes: a readback fill frame and a readback valid frame. The target readback data transmission path is: SRAM array, holding register, shift register and external device.

[0133] In detail, each module in the FPGA configuration and readback system 100 of the embodiment of the present invention adopts the same method as above when in use. Figure 1 The FPGA configuration and readback methods described in the previous section are the same technical means and can produce the same technical effects, so they will not be repeated here.

[0134] like Figure 3 FIG. 1 is a schematic diagram of an electronic device for implementing an FPGA configuration and readback method provided by an embodiment of the present invention.

[0135] The electronic device 1 may include a processor 10 , a memory 11 and a bus 12 , and may further include a computer program stored in the memory 11 and executable on the processor 10 , such as an FPGA configuration and readback method program.

[0136] The memory 11 includes at least one type of readable storage medium, including flash memory, a removable hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory 11 may be an internal storage unit of the electronic device 1, such as a removable hard disk of the electronic device 1. In other embodiments, the memory 11 may also be an external storage device of the electronic device 1, such as a plug-in removable hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. equipped on the electronic device 1. Furthermore, the memory 11 includes both internal storage units of the electronic device 1 and external storage devices. The memory 11 can be used not only to store application software installed in the electronic device 1 and various types of data, such as code for FPGA configuration and readback method programs, but also to temporarily store data that has been output or is about to be output.

[0137] In some embodiments, the processor 10 may be comprised of an integrated circuit, such as a single packaged integrated circuit or multiple packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and a combination of various control chips. The processor 10 is the control core (control unit) of the electronic device, connecting the various components of the electronic device using various interfaces and circuits. It executes programs or modules stored in the memory 11 (e.g., FPGA configuration and readback methods) and accesses data stored in the memory 11 to perform various functions and process data.

[0138] The bus 12 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus 12 may be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to enable communication between the memory 11 and at least one processor 10, etc.

[0139] Figure 3 Only the electronic device with components is shown, and it can be understood by those skilled in the art that Figure 3The method shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown in the figure, or combine certain components, or arrange the components differently.

[0140] For example, although not shown, the electronic device 1 may further include a power source (e.g., a battery) to power various components. Preferably, the power source may be logically connected to the at least one processor 10 via a power management system, thereby enabling functions such as charge management, discharge management, and power consumption management through the power management system. The power source may further include any components such as one or more DC or AC power sources, a recharging system, a power failure detection circuit, a power converter or inverter, and a power status indicator. The electronic device 1 may further include various sensors, Bluetooth modules, Wi-Fi modules, etc., which are not further described here.

[0141] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0142] Optionally, the electronic device 1 may further include a user interface, which may be a display or an input unit (such as a keyboard). Optionally, the user interface may also be a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen. The display may also be appropriately referred to as a display screen or a display unit, and is used to display information processed by the electronic device 1 and to display a visual user interface.

[0143] The FPGA configuration and readback method program stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When executed in the processor 10, it can achieve the following:

[0144] Constructing an FPGA structure, wherein the FPGA structure includes: a configuration module, a shift register, a holding register, and an SRAM array, and the configuration module includes: a data processing unit, an address generation unit, a word line control unit, and a read / write control unit;

[0145] Identifying original configuration data in a pre-built external device, and processing the original configuration data using a data processing unit in a configuration module to obtain target configuration data, wherein the target configuration data includes a plurality of data frame groups, and each data frame group includes a valid data frame and a padding data frame;

[0146] The target configuration data is stored in the SRAM array using the configuration module to complete the configuration of the target configuration data, wherein the transmission path of the target configuration data is: shift register, holding register and SRAM array;

[0147] Identify target readback data in the FPGA structure, wherein the target readback data includes a plurality of readback data frame groups, and each readback data frame group includes: a readback fill frame and a readback valid frame;

[0148] The target readback data is transmitted to the external device using the configuration module to complete the readback of the target readback data, wherein the target readback data transmission path is: SRAM array, holding register, shift register and external device.

[0149] Specifically, the specific implementation method of the processor 10 for the above instructions can refer to Figures 1 to 3 The description of the relevant steps in the corresponding embodiments will not be repeated here.

[0150] Furthermore, if the modules / units integrated into the electronic device 1 are implemented as software functional units and sold or used as independent products, they may be stored in a computer-readable storage medium. The computer-readable storage medium may be volatile or non-volatile. For example, the computer-readable medium may include any entity or system capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0151] The present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program. When the computer program is executed by a processor of an electronic device, the computer program can implement:

[0152] Constructing an FPGA structure, wherein the FPGA structure includes: a configuration module, a shift register, a holding register, and an SRAM array, and the configuration module includes: a data processing unit, an address generation unit, a word line control unit, and a read / write control unit;

[0153] Identifying original configuration data in a pre-built external device, and processing the original configuration data using a data processing unit in a configuration module to obtain target configuration data, wherein the target configuration data includes a plurality of data frame groups, and each data frame group includes a valid data frame and a padding data frame;

[0154] The target configuration data is stored in the SRAM array using the configuration module to complete the configuration of the target configuration data, wherein the transmission path of the target configuration data is: shift register, holding register and SRAM array;

[0155] Identify target readback data in the FPGA structure, wherein the target readback data includes a plurality of readback data frame groups, and each readback data frame group includes: a readback fill frame and a readback valid frame;

[0156] The target readback data is transmitted to the external device using the configuration module to complete the readback of the target readback data, wherein the target readback data transmission path is: SRAM array, holding register, shift register and external device.

[0157] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the system embodiments described above are only exemplary, and actual implementations may have other division methods.

[0158] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network elements. Some or all of the modules may be selected to achieve the purpose of the solution of this embodiment according to actual needs.

[0159] In addition, the functional modules in various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or hardware plus software functional modules.

[0160] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A FPGA configuration and readback method, characterized in that: The method comprises: Constructing an FPGA structure, wherein the FPGA structure includes: a configuration module, a shift register, a holding register, and an SRAM array, and the configuration module includes: a data processing unit, an address generation unit, a word line control unit, and a read / write control unit; Confirming original configuration data in a pre-built external device, and processing the original configuration data using a data processing unit in a configuration module to obtain target configuration data, wherein the target configuration data includes a plurality of data frame groups, and each data frame group includes a valid data frame and a padding data frame; The target configuration data is stored in the SRAM array using the configuration module to complete the configuration of the target configuration data, wherein the transmission path of the target configuration data is: shift register, holding register and SRAM array; The configuration module is used to store the target configuration data in the SRAM array to complete the configuration of the target configuration data, including: sequentially extracting data frame groups from a plurality of data frame groups of target configuration data; Extract the first data frame from the data frame group; Using the read-write control unit in the configuration module, the first data frame is written into the shift register to obtain a shift data frame; In the step of writing the first data frame into the shift register using the read / write control unit in the configuration module, the address generation unit in the configuration module is used to locate the target storage location of the SRAM array where the first data frame is to be stored; Shifting the shifted data frame into the holding register to obtain a held data frame; Using a word line control unit, writing the retained data frame into a target storage location in the SRAM array to complete the configuration of the first data frame; Eliminate the first data frame from the data frame group to obtain the data frame group to be configured, use the data frame group to be configured as the data frame group, and return to the step of extracting the first data frame from the data frame group until the penultimate valid data frame in the data frame group is configured; When the penultimate valid data frame in the data frame group is configured, the last valid frame in the holding register is confirmed; Using the first padded data frame and the second padded data frame in the data frame group, the last valid frame is pushed into the SRAM array and the configuration of the data frame group is completed; When each of the multiple data frame groups is configured, the configuration of the target configuration data is completed; Identify target readback data in the FPGA structure, wherein the target readback data includes a plurality of readback data frame groups, and each readback data frame group includes: a readback fill frame and a readback valid frame; The target readback data is transmitted to the external device using the configuration module to complete the readback of the target readback data, wherein the target readback data transmission path is: SRAM array, holding register, shift register and external device.

2. The FPGA configuration and readback method according to claim 1, wherein: The method of processing the original configuration data by the data processing unit in the configuration module to obtain the target configuration data includes: Determining the interface bit width of the configuration module; The original configuration data is bitstream parsed using the data processing unit and the interface bit width to obtain the target configuration data, wherein the arrangement of each data frame group in the target configuration data is: ； in, Represents a data frame group, Indicates the first valid data frame in the data frame group. Indicates the first Valid data frames, Indicates the number of valid data frames in the data frame group. Indicates the first filled data frame in the data frame group. Indicates the second padded data frame in the data frame group.

3. The FPGA configuration and readback method according to claim 2, wherein: Each data frame in the data frame group includes N unit data, wherein the unit data is 32-bit wide data.

4. The FPGA configuration and readback method according to claim 3, wherein: The method of using a word line control unit to write the retained data frame to a target storage location in the SRAM array includes: Based on the word line control unit, the word line corresponding to the target storage position in the SRAM array is turned on to obtain a high-level word line; Using a high-level word line, writing the retained data frame from the retention register to a target storage location in the SRAM array; After the data frame is written into the target storage location in the SRAM array, the high level word line is turned off.

5. The FPGA configuration and readback method according to claim 3, wherein: The method of utilizing the first filling data frame and the second filling data frame in the data frame group to push the last valid frame into the SRAM array and complete the configuration of the data frame group includes: Reading the first filling data frame in the data frame group, writing the first filling data frame into the shift register to obtain a push data frame; Pushing the last valid frame into a target storage location corresponding to the last valid frame in the SRAM array using a push data frame; Reading a second filling data frame in the data frame group, writing the second filling data frame into the shift register to obtain a reset data frame, and using the reset data frame to update the holding register to a preset reset state; When the holding register is updated to the reset state, the configuration of the data frame group is completed.

6. The FPGA configuration and readback method according to claim 1, wherein: The target readback data is stored in an SRAM array of an FPGA structure, and each of the multiple readback data frame groups of the target readback data is expressed as: ； in, Indicates reading back the data frame group. Indicates the first read-back fill frame in the read-back data frame group. Indicates the second read-back fill frame in the read-back data frame group. Indicates the first valid frame in the readback data frame group. Indicates reading back the first Read back valid frames, Indicates the number of valid frames read back in the readback data frame group.

7. The FPGA configuration and readback method according to claim 6, wherein: The step of transmitting the target readback data to the external device by using the configuration module to complete the readback of the target readback data includes: sequentially extracting readback data frame groups from a plurality of readback data frame groups; Reading a first readback fill frame in the readback data frame group, wherein the first readback fill frame is stored in a holding register; Writing the first readback filling frame into the shift register, wherein after the first readback filling frame is written into the shift register, the shift register is reset; In the step of writing the first readback filling frame into the shift register, a readback frame address is generated based on the address generating unit; Identify the first valid readback frame corresponding to the readback frame address, and write the first valid readback frame into the holding register based on the word line control unit to obtain a readback holding data frame; Writing the readback hold data frame into the shift register to obtain a readback shift data frame, and storing the readback shift data frame into an external device using a read-write control unit; The first readback valid frame is removed from the readback data frame group to obtain a to-be-readback data frame group, the to-be-readback data frame group and the readback hold data frame are recorded as a readback data frame group and a first readback fill frame, respectively, and the process returns to the step of generating a readback frame address based on the address generation unit in the step of writing the first readback fill frame into the shift register, until the first readback valid frame becomes the last readback valid frame in the readback data frame group; After the last readback valid frame is written into the shift register, the second readback filling frame in the readback data frame group is read, and the last readback valid frame and the second readback filling frame in the shift register are written into the external device to complete the readback of the readback data frame group; When each of the plurality of readback data frame groups is read back, the readback of the target readback data is completed.

8. The FPGA configuration and readback method according to claim 7, wherein: The last valid frame read back is the first frame in the read back data frame group. Read back valid frames.

9. An FPGA configuration and readback system, characterized in that: The system comprises: An FPGA structure construction module is used to construct an FPGA structure, wherein the FPGA structure includes: a configuration module, a shift register, a holding register and an SRAM array, and the configuration module includes: a data processing unit, an address generation unit, a word line control unit and a read / write control unit; an original data processing module, configured to identify original configuration data in a pre-built external device and process the original configuration data using a data processing unit in the configuration module to obtain target configuration data, wherein the target configuration data includes a plurality of data frame groups, and each data frame group includes a valid data frame and a padding data frame; A data configuration module is configured to store target configuration data in an SRAM array using the configuration module, wherein the target configuration data is transmitted via a shift register, a holding register, and the SRAM array. Using the configuration module to store the target configuration data in the SRAM array includes: sequentially extracting data frame groups from a plurality of data frame groups of target configuration data; Extract the first data frame from the data frame group; Using the read-write control unit in the configuration module, the first data frame is written into the shift register to obtain a shift data frame; In the step of writing the first data frame into the shift register using the read / write control unit in the configuration module, the address generation unit in the configuration module is used to locate the target storage location of the SRAM array where the first data frame is to be stored; Shifting the shifted data frame into the holding register to obtain a held data frame; Using a word line control unit, writing the retained data frame into a target storage location in the SRAM array to complete the configuration of the first data frame; Eliminate the first data frame from the data frame group to obtain the data frame group to be configured, use the data frame group to be configured as the data frame group, and return to the step of extracting the first data frame from the data frame group until the penultimate valid data frame in the data frame group is configured; When the penultimate valid data frame in the data frame group is configured, the last valid frame in the holding register is confirmed; Using the first padded data frame and the second padded data frame in the data frame group, the last valid frame is pushed into the SRAM array and the configuration of the data frame group is completed; When each of the multiple data frame groups is configured, the configuration of the target configuration data is completed; The data readback module is used to identify the target readback data in the FPGA structure and transmit the target readback data to the external device using the configuration module, wherein the target readback data includes multiple readback data frame groups, and each readback data frame group includes: a readback fill frame and a readback valid frame. The target readback data transmission path is: SRAM array, holding register, shift register and external device.

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