Database acceleration system and database acceleration method

Abstract

The invention discloses a database acceleration system and a database acceleration method, and relates to the technical field of data processing, the database acceleration system comprises a central processing unit, an internal bus, a vector processor and a plurality of preset execution units; the central processing unit receives an operation request sent by a user side; analyzing the operation request into an operation plan; calling corresponding target data from a database according to the operation plan; sending the operation plan and the target data to an internal bus; the internal bus is used for sending the operation plan and the target data to the vector processor; the vector processor is used for controlling one or more preset execution units to process the target data according to the operation plan so as to obtain a processing result corresponding to the operation plan; a processing result is returned to the central processing unit; and the central processing unit outputs the processing result to the user side, and through instruction expansion of each preset execution unit, the situation that the specificity of the instruction field is insufficient is avoided, and the operation efficiency of the database is improved.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and in particular, to a database acceleration system and a database acceleration method. Background Art

[0002] Database query is a query that retrieves data from a database through a user's specific query statement. In the process of database query, structured query language is mainly used to set query conditions and filter target data, and the corresponding query results are returned to the user in the form of a table, etc. With the surge in the demand for database query, it is particularly important to improve the database response speed.

[0003] In the related art, current database queries mainly process the corresponding data in the database through structured query language with fixed data processing instructions to obtain processing results. However, in the related art, the method of processing database data through fixed data processing instructions is prone to the situation of insufficient domain specificity of instructions, resulting in low operation efficiency of the database. Summary of the Invention

[0004] This application provides a database acceleration system and a database acceleration method to at least solve the problem that in the related art, the method of processing database data through fixed data processing instructions is prone to the situation of insufficient domain specificity of instructions, resulting in low operation efficiency of the database.

[0005] This application provides a database acceleration system, including: a central processing unit (10) and a coprocessor (20), and the coprocessor (20) at least includes an internal bus (201) and a vector processor (202); the central processing unit (10) is communicatively connected to the internal bus (201); the internal bus (201) is communicatively connected to the vector processor (202); the vector processor (202) at least includes a plurality of preset execution units (2021), and each preset execution unit (2021) includes one or more instructions;

[0006] The central processing unit (10) receives an operation request sent by a user terminal (30); parses the operation request into an operation plan, where the operation plan is the operation steps corresponding to the operation request; retrieves corresponding target data from the database according to the operation plan; and sends the operation plan and the target data to the internal bus (201);

[0007] The internal bus (201) sends the operation plan and the target data to the vector processor (202);

[0008] The vector processor (202) controls one or more preset execution units (2021) to process target data according to an operation plan, so as to obtain a processing result corresponding to the operation plan; and returns the processing result to the central processing unit (10).

[0009] The central processing unit (10) outputs the processing result to the client (30).

[0010] This application also provides a database acceleration method, including:

[0011] The central processing unit receives an operation request sent by the client; parses the operation request into an operation plan; loads corresponding operation microcodes from the host memory according to the operation plan; and sends the operation microcodes to the internal bus.

[0012] The internal bus sends the operation microcodes to the vector processor.

[0013] The vector processor prefetches corresponding target data from the database data of the memory controller through the operation microcodes; controls one or more preset execution units to process the target data through the operation microcodes, so as to obtain a processing result corresponding to the operation plan; and returns the processing result to the central processing unit.

[0014] The central processing unit outputs the processing result to the client.

[0015] The database acceleration system and the database acceleration method provided by the embodiments of this application constitute a database acceleration system through a central processing unit, an internal bus, a vector processor, and multiple preset execution units; the central processing unit receives an operation request sent by the client; parses the operation request into an operation plan; retrieves corresponding target data from the database according to the operation plan; sends the operation plan and the database data to the internal bus; the internal bus sends the operation plan and the target data to the vector processor; the vector processor controls one or more preset execution units to process the target data according to the operation plan, so as to obtain a processing result corresponding to the operation plan; returns the processing result to the central processing unit; the central processing unit outputs the processing result to the client, and by expanding the instructions of each preset execution unit, the situation of insufficient domain specificity of instructions is avoided, and the operation efficiency of the database is improved. Description of the Drawings

[0016] In order to more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1Structural schematic of the database acceleration system provided by the embodiment of the present application Figure 1 ;

[0018] Figure 2 Structural schematic of the database acceleration system provided by the embodiment of the present application Figure 2 ;

[0019] Figure 3 Flow schematic of the database acceleration method provided by the embodiment of the present application. Detailed implementation manners

[0020] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0021] It should be noted that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. The terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two elements. The terms "parallel", "perpendicular", and "equal" include the described situations and situations similar to the described situations, and the range of the similar situations is within the acceptable deviation range, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurement being discussed and the error related to the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and approximate parallel, where the acceptable deviation range of approximate parallel can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicular and approximate perpendicular, where the acceptable deviation range of approximate perpendicular can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range of approximate equality can be, for example, that the difference between the two equal ones is less than or equal to 5% of any one of them. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood in specific situations.

[0022] It should be noted that in the description of this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0023] Database query is to retrieve data from a database through a user's specific query statement. In the process of database query, structured query language is mainly used to set query conditions and filter target data, and the corresponding query results are returned to the user in the form of a table, etc., which is often used in scenarios such as data analysis and system development. With the surge in the demand for database query, it is particularly important to improve the database response speed. In the related art, the current database query mainly processes the corresponding data in the database through structured query language with fixed data processing instructions to obtain the processing result. However, in the related art, the method of processing database data through fixed data processing instructions is prone to the situation of insufficient domain specificity of instructions, resulting in low operation efficiency of the database.

[0024] To solve the above technical problems, the embodiments of this application propose the following technical concept: The inventor considers the operation request sent by the user terminal, constructs a database acceleration system based on the central processing unit and the coprocessor, uses the central processing unit to parse the operation request into an operation plan, and retrieves the target data from the database according to the operation plan. Using the internal bus, the operation plan and the target data are sent to the vector processor, and one or more preset execution units in the vector processor are used to process the target data according to the operation plan to obtain the processing result, and the processing result is output by the central processing unit to the user terminal. By expanding the instructions of each preset execution unit, the situation of insufficient domain specificity of instructions is avoided, and the operation efficiency of the database is improved.

[0025] To enable those skilled in the art of this technology to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific embodiments.

[0026] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the database acceleration system depends, the specific application environment architecture or specific hardware architecture is described herein. Refer to Figure 1 , Figure 1 is the structural schematic diagram of the database acceleration system provided by the embodiments of this application Figure 1 .

[0027] As Figure 1, A database acceleration system, comprising: a central processing unit 10 and a coprocessor 20, the coprocessor 20 at least includes an internal bus 201 and a vector processor 202; the central processing unit 10 is communicatively connected to the internal bus 201; the internal bus 201 is communicatively connected to the vector processor 202; the vector processor 202 at least includes a plurality of preset execution units 2021, and each preset execution unit 2021 includes one or more instructions.

[0028] Among them, the coprocessor can be a coprocessor based on an open source instruction set or other processors.

[0029] Among them, the open source instruction set can be RISC-V or other instruction sets.

[0030] Among them, the RISC-V coprocessor is a coprocessor with an open standard instruction set architecture designed based on the principle of reduced instruction set computing.

[0031] In this embodiment, the structure data of the preset execution unit includes one or more of the following: opcode, function code, sub-function code, target register, first source register, second source register, and mask mode.

[0032] In this embodiment, the field of the opcode is opcode, which is used to customize instructions; the field of the function code is funct7, which is used to distinguish different instructions; the field of the sub-function code is funct3, which is used to further subdivide instructions; the field of the target register is rd; the field of the first source register is rs1; the field of the second source register is rs2; the field of the mask mode is vm, where the number 0 represents no mask and the number 1 represents mask control.

[0033] Among them, the structure data of the opcode includes one or more of the following: arithmetic operation code, load code, store code, branch code, system instruction, and custom instruction.

[0034] Among them, the arithmetic operation code is 0110011, and the example instructions are add, sub, and xor; the load code is 0000011, and the example instructions are lw, lb, and lh; the store code is 0100011, and the example instructions are sw, sb, and sh; the branch code is 1100011, and the example instructions are beq, bne, and blt; the system instruction is 1110011, and the example instructions are ecall and csrrw; the custom instruction is 1101011, and the example instructions are vfilter and vhash.

[0035] Exemplarily, 1101011 is an opcode reserved by the open-source instruction set for non-standard extensions to implement custom instructions. After the CPU recognizes opcode = 1101011, it routes the instruction to the vector processor and selects the corresponding hardware circuit according to funct7 / funct3.

[0036] Exemplarily, when vm = 1, mask control is enabled, and operations are only performed on vector elements where the corresponding bit of vm is 1; when vm = 0, the mask is disabled, and all elements participate in the calculation.

[0037] Among them, vm is a 1-bit mask register or consists of specific bits of the vector mask register v0. Each mask bit corresponds to a vector element. For example, the i-th bit of vm controls the comparison of v2[i] and v3[i].

[0038] In this embodiment, the multiple preset execution units 2021 include one or more of the following: data filtering execution unit, hash join execution unit, aggregation calculation execution unit, regular expression matching execution unit, sorting execution unit, full table scan execution unit, and index tree operation execution unit.

[0039] Among them, the data filtering execution unit contains comparison operation instructions; the hash join execution unit contains hash table construction instructions, hash probing instructions, and nested loop join instructions; the aggregation calculation execution unit contains sum calculation instructions, count calculation instructions, maximum and minimum value extraction instructions, and average value instructions; the regular expression matching execution unit contains pattern compilation instructions, vector matching instructions, and result extraction instructions; the sorting execution unit contains radix sorting instructions and merge sorting instructions; the full table scan execution unit contains initialization scan instructions, batch data acquisition instructions, and column projection instructions; the index tree operation execution unit contains initialization index instructions, exact operation instructions, and range operation instructions.

[0040] Among them, the index tree operation execution unit is an index B+ tree operation execution unit.

[0041] Among them, the instruction format of the data filtering execution unit is:

[0042]

[0043] Among them, the last three bits of the function code funct7 represent the data type, and 001 represents fixed-point (default).

[0044] In addition, 010 of the last three bits of the function code funct7 represents floating-point (single precision); 011 represents floating-point (double precision); 100 represents 16-bit fixed-point; 101 represents character type; 110 represents boolean type; 111 represents special mode (such as NULL value processing).

[0045] The last five bits of function code funct7 represent the instruction type, and 00001 represents the data filtering instruction vfilter.

[0046] The sub - function code funct3 = 000 is the equal mode; funct3 = 001 is the greater than mode; funct3 = 010 is the less than mode; funct3 = 011 is the greater than or equal to mode; funct3 = 100 is the less than or equal to mode.

[0047] Among them, the equal mode, greater than mode, less than mode, greater than or equal to mode, and less than or equal to mode are collectively called comparison operation instructions.

[0048] The operation is vd[i]=(vs1[i] op vs2[i])?1:0. Exemplarily, vfilter v1, v2, v3, vm, funct3 = 101, funct7 = 1100001#v1=(v2>v3)?1:0; if v2 = [10, 20, 30], v3 = [5, 25, 30], then v1 = [1, 0, 0].

[0049] Among them, the instruction format of the hash join execution unit is:

[0050]

[0051] Among them, the last five bits of function code funct7 represent the instruction type, and 00010 represents the hash join instruction vhash.

[0052] The sub - function code funct3 = 010 is the hash table construction instruction.

[0053] In addition, funct3 = 011 is the hash probing instruction; funct3 = 100 is the nested loop join instruction.

[0054] Exemplarily, vhash.build v1, v2, funct7 = 0000001#Construct a hash table with the keys of v2 and store it in v1; vhash.probe v3, v1, v4, funct7 = 0000001#Search for the keys of v4 in the hash table of v1.

[0055] Among them, the instruction format of the aggregation calculation execution unit is:

[0056]

[0057] Among them, the last five bits of function code funct7 represent the instruction type, and 00011 represents the aggregation calculation instruction vagg.

[0058] The sub - function code funct3 = 010 is the summation calculation instruction.

[0059] In addition, funct3 = 011 is the maximum value instruction; funct3 = 100 is the minimum value instruction; funct3 = 101 is the average value instruction; funct3 = 110 is the counting calculation instruction.

[0060] Example: vagg.SUM v1, v2, v3 # v1 = SUM(v2 + v3).

[0061] In addition, the aggregation function accelerator supports the sum calculation instruction, the counting calculation instruction, the maximum and minimum value instructions, and the average value instruction, a multi-level accumulator array vectorized grouping key matching engine, and a distributed result cache.

[0062] Among them, the instruction format of the regular matching execution unit is:

[0063]

[0064] Among them, the last five bits of the function code funct7 represent the instruction type, and 00100 represents the regular matching instruction vregex.

[0065] The sub-function code funct3 = 001 is the pattern compilation instruction.

[0066] In addition, funct3 = 010 is the vector matching instruction; funct3 = 011 is the result extraction instruction.

[0067] Exemplarily: vregex.match v1, v2, v3 # v1 = (whether v3 matches the regular expression of v2).

[0068] Among them, the instruction format of the sorting execution unit is:

[0069]

[0070] Among them, the last five bits of the function code funct7 represent the instruction type, and 00101 represents the sorting instruction vsort.

[0071] The sub-function code funct3 = 000 is the radix sorting instruction. In addition, funct3 = 001 is the merge sorting instruction.

[0072] Example 1, vsort.radix v1, v2 # Sort the data in v2 by radix, and store the result in v1.

[0073] Input: v2 = [3, 1, 4, 2]

[0074] Output: v1 = [1, 2, 3, 4]

[0075] Example 2, vsort.merge v1, v2, v3 # Merge the sorted v2 and v3, and store the result in v1.

[0076] Input: v2 = [1, 3], v3 = [2, 4]

[0077] Output: v1 = [1, 2, 3, 4]

[0078] Among them, the instruction format of the full table scan execution unit is:

[0079]

[0080] Among them, the last five bits of the function code funct7 represent the instruction type, and 00110 represents the full table scan instruction vscan.

[0081] The sub-function code funct3 = 000 is the initialization scan instruction. In addition, funct3 = 001 is the batch data acquisition instruction; funct3 = 010 is the column projection instruction.

[0082] Among them, the initialization scan instruction is: vscan.init v1, 0x8000 # Load the table descriptor from the memory address 0x8000 into v1.

[0083] The table description is: the starting address of the table data in memory, the number of bytes occupied by each row of data in the table, and the offsets of each column in the table relative to the row starting position (supporting up to 8 columns at most).

[0084] Among them, the batch data acquisition instruction is: vscan.next v2 # Load the next batch of data into v2.

[0085] The data layout is: columnar storage, v2 is organized by column. For example: v2[0:63] = column 1, v2[64:127] = column 2; row storage: v2 is organized by row.

[0086] The column-row adaptive processing is: Column storage processing optimization mode: Dynamically identify the hot columns within a row and process them preferentially; Use the vscan.next instruction to batch acquire column data; Prefetch column data and align it with the vector register

[0087] Hybrid processing mode: Use columnar processing for frequently accessed columns; Use row-based processing for operations that require full-row access; Select the optimal access mode.

[0088] Among them, the column projection instruction is: vscan.project v3, v2, 0x0F # Select columns 1-4 from v2 (mask 0x0F = 00001111).

[0089] Input: v2 = [A1, B1, C1, D1, A2, B2, C2, D2,...]

[0090] Output: v3 = [A1, A2,..., B1, B2,..., C1, C2,...]

[0091] Among them, the instruction format of the index tree operation execution unit is as follows:

[0092]

[0093] Among them, the last five bits of the function code funct7 represent the instruction type, and 00111 represents the index query instruction vindex.

[0094] The sub-function code funct3 = 000 is the initialization index instruction.

[0095] In addition, funct3 = 001 is the exact operation instruction; funct3 = 010 is the range operation instruction.

[0096] Exemplarily, the initialization index instruction is: vindex.init v1, 0x9000 # Load the B+ tree index descriptor (address 0x9000) into v1.

[0097] The index descriptor is: the root node address, the key type, and the key byte count.

[0098] Exemplarily, the exact query instruction is: vindex.search v2, v1, v3 # Search for the key v3 in the index v1, and store the result in v2.

[0099] Input: v3 =

[42] (query key value)

[0100] Output: v2 = [0x1234] (matched row address)

[0101] Exemplarily, the range operation instruction: vindex.range v2, v1, v3 # Query the entries in v1 that satisfy v3[0] ≤ key ≤ v3[1].

[0102] Input: v3 = [10, 20] (range boundary)

[0103] Output: v2 = [0x1234, 0x5678,...] (list of matched row addresses)

[0104] The central processing unit 10 receives the operation request sent by the user terminal 30; parses the operation request into an operation plan, where the operation plan is the operation steps corresponding to the operation request; retrieves the corresponding target data from the database according to the operation plan; and sends the operation plan and the target data to the internal bus 201.

[0105] In this embodiment, the original data source in the database is the hard disk. Specifically, the central processing unit retrieves the original data in the hard disk into the database and runs the database.

[0106] Specifically, the central processing unit 10 receives the operation request sent by the user terminal 30; parses the syntax and checks the semantics of the operation request to obtain a preliminary operation plan; intervenes in the initial operation plan according to the preset plug-in, and rewrites the operation plan based on the rule and cost model to identify the operation fragments that can be accelerated (such as large-scale data filtering, complex joins, and aggregation calculations, etc.) to obtain an operation plan containing acceleration instructions; retrieves the corresponding target data from the database according to the operation plan; and sends the operation plan and the target data to the internal bus 201.

[0107] Among them, the operation request can be an SQL operation request or other operation requests.

[0108] Among them, the preset plug-in can be a Hook plug-in or other plug-ins.

[0109] In addition, it is also necessary to judge the feasibility of the operation plan containing acceleration instructions and check whether the operation plan can trigger the preset execution unit.

[0110] In addition, for the operations that can be accelerated, an optimized vector instruction sequence is generated to insert necessary control instructions and data transfer instructions.

[0111] Exemplarily: the vfilter.cond instruction corresponding to the traditional WHERE condition; the instruction sequence of vhash.build + vhash.probe corresponding to the JOIN operation; the instruction sequence of vagg.group + vagg.reduce corresponding to the GROUP BY aggregation.

[0112] The internal bus 201 sends the operation plan and the target data to the vector processor 202.

[0113] The vector processor 202 controls one or more preset execution units 2021 to process the target data according to the operation plan to obtain the processing result corresponding to the operation plan; and returns the processing result to the central processing unit 10;

[0114] Exemplarily, one or more preset execution units are a data filtering execution unit, a hash join execution unit, and an aggregation calculation execution unit.

[0115] Exemplarily, the vector processor executes database-specific instructions in parallel: the vector filtering execution unit, and the parallel comparator array processes the predicate judgment of the target data; the hash join execution unit, and the dedicated hash calculation unit accelerates the probing stage; the aggregation calculation execution unit, and the multi-stage accumulator array realizes parallel aggregation.

[0116] In addition, if only some segments in the operation plan need to be processed with acceleration, the data corresponding to these segments needs to be processed with acceleration, and the data corresponding to the remaining part of the operation plan needs to be processed normally, so as to obtain the processing result integrated with accelerated processing and normal processing.

[0117] In addition, memory consistency management also needs to be performed: maintaining cache consistency through an extended protocol; using atomic operations for critical data structures, such as: indexing B+ tree operations.

[0118] In addition, if a data processing exception occurs, when abnormal data is detected during vectorized execution, save the exception context and trigger an interrupt, and the central processing unit takes over the exception handling.

[0119] In addition, when each preset execution unit competes for accelerator resources, it is retrieved based on priority and time slice rotation.

[0120] The central processing unit 10 outputs the processing result to the client 30.

[0121] In this embodiment, the client can be a display terminal, a mobile device terminal, and other terminals.

[0122] The database acceleration system provided in this embodiment is composed of a central processing unit, an internal bus, a vector processor, and multiple preset execution units; the central processing unit receives an operation request sent by the client; parses the operation request into an operation plan; retrieves corresponding target data from the database according to the operation plan; sends the operation plan and the database data to the internal bus; the internal bus sends the operation plan and the target data to the vector processor; the vector processor controls one or more preset execution units to process the target data according to the operation plan to obtain the processing result corresponding to the operation plan; returns the processing result to the central processing unit; the central processing unit outputs the processing result to the client. By extending the instructions of each preset execution unit, the situation of insufficient domain specificity of the instructions is avoided, and the operation efficiency of the database is improved.

[0123] Figure 2 The structural schematic of the database acceleration system provided in the embodiment of the present application Figure 2 .

[0124] Such as Figure 2 , on the basis of the embodiment of Figure 1 , the coprocessor 20 further includes: a memory controller 203; the memory controller 203 is communicatively connected to the internal bus 201; wherein, the central processing unit 10 has previously retrieved the database data in the database to the memory controller 203, and the memory controller 203 includes multiple storage channels.

[0125] Among them, the memory controller can be an HBM memory controller or other controllers.

[0126] Among them, the HBM memory controller is a high-bandwidth memory controller.

[0127] Among them, the number of multiple memory channels can be any one of 4, 6, or 8, or other numbers.

[0128] The central processing unit 10 receives the operation request sent by the user end 30; parses the operation request into an operation plan; loads the corresponding operation microcode from the host memory according to the operation plan; and sends the operation microcode to the internal bus 201.

[0129] In this embodiment, the operation microcode is an abstraction layer of the computer or processor for the hardware structure, or a data structure for implementing complex machine instructions.

[0130] Among them, the format of the microcode includes: operation code, address attribute, format string of the output address, batch size, and binary mask.

[0131] Among them, the operation code, type: uint8_t, description: operation code field, following the open-source instruction set standard, used to identify the specific micro-operation type (such as load, store, or data movement).

[0132] The address attribute, type: uint64_t, description: the address pointing to the predicate condition, used to implement conditional execution. Through this address, the conditional judgment result can be read to determine whether to execute the current micro-instruction.

[0133] The format string of the output address, type: uint64_t, description: the target address of the result buffer. After the operation is completed, the data will be written to this location, which may be used in memory-mapped I / O or direct memory access scenarios.

[0134] The batch size, type: uint32_t, description: specifies the batch size for single processing, supporting batch operation optimization. For example, multiple data units can be processed at one time to reduce overhead.

[0135] The binary mask, type: uint8_t, description: column selection mask, used to select specific columns during multi-column data operations. Each bit may correspond to a column, and a mask value of 1 indicates that the column is selected.

[0136] In addition, if the microcode is in a missing state, it will fallback to the central processing unit for execution and record the characteristics of the missing microcode, triggering the dynamic microcode generation process.

[0137] The internal bus 201 sends the operation microcode to the vector processor 202.

[0138] The vector processor 202 prefetches corresponding target data from the database data of the memory controller 203 through operation microcode; controls one or more preset execution units 2021 to process the target data through operation microcode to obtain a processing result corresponding to the operation plan; and returns the processing result to the central processing unit 10.

[0139] In this embodiment, the discussion about the preset execution unit has been elaborated in Figure 1 the corresponding embodiment and will not be repeated here.

[0140] The central processing unit 10 outputs the processing result to the client 30.

[0141] In this embodiment, the discussion about the client has been elaborated in Figure 1 the corresponding embodiment and will not be repeated here.

[0142] Continue to refer to Figure 2 , the vector processor 202 further includes: a vector register 2022.

[0143] The vector processor 202 prefetches corresponding target data from the database data of the memory controller 203 through operation microcode.

[0144] In this embodiment, the database data is a set of original records or information stored in a structured manner.

[0145] One or more preset execution units 2021 process the target data according to the operation microcode to obtain a processing result corresponding to the operation plan; and output the processing result to the vector register 2022.

[0146] The vector register 2022 returns the processing result to the central processing unit 10.

[0147] Continue to refer to Figure 2 , the coprocessor 20 further includes: a scalar processor 204.

[0148] The coprocessor 20 verifies the operation microcode to obtain a verification result.

[0149] The scalar processor 204, after determining that the verification result is passed, initializes the operation microcode to complete the initialization of the operation microcode.

[0150] Continue to refer to Figure 2 , the scalar processor 204 further includes: a control register 2041.

[0151] The control register 2041 activates the operation microcode and establishes a mapping relationship from the instruction operation code to the operation microcode to complete the initialization of the operation microcode.

[0152] In addition, when adding new processing microcode, there is no need to restart the system. The new microcode can be directly loaded to overwrite the old microcode.

[0153] The database acceleration system provided in this embodiment further includes a memory controller. The central processing unit has previously fetched database data in the database to the memory controller; through the central processing unit, an operation request sent by the client is received; the operation request is parsed into an operation plan; the corresponding operation microcode is loaded from the host memory according to the operation plan; the operation microcode is sent to the internal bus; the internal bus sends the operation microcode to the vector processor; the vector processor prefetches the corresponding target data from the database data of the memory controller through the operation microcode; one or more preset execution units are controlled by the operation microcode to process the target data to obtain the processing result corresponding to the operation plan; the processing result is returned to the central processing unit; the central processing unit outputs the processing result to the client. By fetching the database data in the database to the memory controller through the central processing unit and prefetching the corresponding target data from the database data of the memory controller by the operation microcode, near storage of the database acceleration system is achieved, breaking through the storage wall bottleneck to accelerate the database and further improving the operation efficiency of the database.

[0154] In addition, the database acceleration system provided in this embodiment integrates a multi-channel memory controller, supports concurrent access, and thus improves the bandwidth utilization rate.

[0155] Figure 3 It is a schematic flow chart of the database acceleration method provided in an embodiment of the present application. The execution subject of this embodiment may be Figure 2 the database acceleration system in the embodiment shown, and there is no special limitation here in this embodiment. As Figure 3 shown, the method includes:

[0156] S301: The central processing unit receives an operation request sent by the client; parses the operation request into an operation plan; loads the corresponding operation microcode from the host memory according to the operation plan; and sends the operation microcode to the internal bus.

[0157] Specifically, through the microcode loading instruction, the corresponding operation microcode is loaded from the host memory according to the operation plan.

[0158] Among them, the microcode loading instruction is xLOAD_MICROCODE.

[0159] Among them, the format of the microcode loading instruction: microcode address, source register, sub-function code, target register, and operation code. Function: Load the microcode from the host memory to the coprocessor cache.

[0160] Exemplarily, LOAD_MICROCODE 0x8000 # Load the microcode from 0x8000.

[0161] In addition, it is also necessary to identify the special microcode corresponding to the operation plan and check whether the corresponding version already exists in the coprocessor microcode cache.

[0162] S302: The internal bus sends the operation microcode to the vector processor.

[0163] S303: The vector processor prefetches the corresponding target data from the database data of the memory controller through the operation microcode; controls one or more preset execution units to process the target data through the operation microcode to obtain the processing result corresponding to the operation plan; and returns the processing result to the central processor.

[0164] In this embodiment, the microcode is decomposed into storage microcode and computing microcode. Correspondingly, prefetching the corresponding target data from the database data of the memory controller through the operation microcode in step S303 specifically means: prefetching the corresponding target data from the database data of the memory controller through the storage microcode.

[0165] In this embodiment, the storage microcode is responsible for data transfer, storage format conversion (row-column conversion), and prefetch strategy control.

[0166] Exemplarily, store_microcode_trans defines the data transfer path from the memory controller to the vector processor, supports dynamic adjustment of the prefetch size, prefetching 64KB for sequential access, and 8KB for random access.

[0167] In this embodiment, the computing microcode is used to implement the hardware acceleration logic for specific complex database operations.

[0168] Exemplarily, compute_microcode_regex contains the logic for regular expression matching operations.

[0169] Among them, the prefetch process is as follows: Query start: The access mode analysis unit is initialized, and the memory controller loads data in the default row format; Pattern recognition: When the access mode analysis unit detects a sequential scan of columns, it is marked as hot data and triggers column conversion; Prefetch trigger: The intelligent prefetch engine prefetches 256KB of data for the subsequent columns; Instruction execution: vscan.project directly operates on the columnar data to avoid row parsing overhead, for example: vscan.project v3, v2, 0x03# Select columns 1-2; Dynamic adjustment: If the subsequent query changes to random access of columns, switch the prefetch strategy to 8KB and may convert the column to hot data.

[0170] In this embodiment, the target data includes hot data and cold data, and the database data includes multiple column data; correspondingly, the above steps specifically include:

[0171] S3031: Obtain the access times of each column of data according to a predetermined dominant access pattern by storing microcode in a pre-designed counter array.

[0172] Specifically, the determination process of the dominant access pattern in step S3031 specifically includes:

[0173] S30311: Obtain the access times of multiple access patterns to the memory controller within a preset time.

[0174] In this embodiment, the structure of the access pattern includes one or more of the following types: prefetch data size, prefetch trigger condition, and prefetch address cache.

[0175] In this embodiment, the multiple access patterns at least include: sequential access pattern and random access pattern.

[0176] Among them, the sequential access pattern is: prefetch data size: prefetch data from the memory controller, using high-bandwidth concurrency; prefetch trigger condition: trigger prefetch after detecting 3 consecutive sequential accesses; prefetch address calculation: predict the next batch of data addresses based on the current address step.

[0177] Among them, the random access pattern is: prefetch data size: conservatively prefetch 8KB to reduce invalid data transfer; prefetch trigger condition: trigger based on access locality (such as cache line alignment); prefetch address cache: record the address range of recent random accesses and preferentially prefetch high-frequency regions.

[0178] Among them, the relevant bandwidth allocation is: in the sequential mode, the memory controller channel bandwidth is allocated 70% for prefetch and 30% for real-time requests; in the random mode, it is adjusted to 50% for prefetch and 50% for real-time requests.

[0179] S30312: Determine the dominant access pattern from multiple access patterns according to each access time.

[0180] Specifically, determine the dominant access pattern from multiple access patterns according to each access time and a preset threshold.

[0181] Among them, the preset threshold can be any one of 100 times, 200 times, or 300 times, or other times.

[0182] S3032: Sort each access time to obtain an access sequence.

[0183] S3033: Determine the high-frequency access column data in each column of data according to the access sequence.

[0184] In this embodiment, determine the high-frequency access column data from the columns of data with a preset Top number in the access sequence.

[0185] Among them, the preset Top quantity can be Top10%, Top20% or other quantities.

[0186] S3034: Determine the frequently accessed column data as hot data, and determine the remaining column data in each column of data as cold data.

[0187] In addition, after step S3034, it further includes: steps a - b:

[0188] Step a: Store the hot data in columnar form into the memory controller, and record the starting address, length, and data type of each corresponding column of data.

[0189] Specifically, store continuously in columnar form in the memory controller, align each column of data to a 512 - bit vector register, and record the starting address, length, and data type of each column of data for the vscan.project instruction to parse.

[0190] Step b: Store the cold data in row - form into the memory controller.

[0191] Specifically, store the cold data in row - form into the memory controller to reduce the conversion overhead.

[0192] In addition, for lazy conversion, the row - column conversion is triggered only when a column is promoted to hot data.

[0193] Specifically, in step S303, controlling one or more preset execution units to process the target data through operation microcode to obtain the processing result corresponding to the operation plan is specifically: controlling one or more preset execution units to process the target data through calculation microcode to obtain the processing result corresponding to the operation plan.

[0194] In this embodiment, where the processing result includes one or more sub - processing results; correspondingly, the above steps specifically include:

[0195] S3035: Through calculation microcode, operate the corresponding one or more preset execution units to process the target data to obtain one or more sub - processing results.

[0196] S3036: Sort each sub - processing result to obtain a processing result sequence.

[0197] S3037: Aggregate the processing result sequence to obtain the aggregated processing result.

[0198] S3038: Merge the processing result sequence to obtain the merged processing result.

[0199] S3039: Convert the merged processing result to obtain the processing result.

[0200] Specifically, the processed result after merging is converted into a row storage format to obtain the processed result.

[0201] S304: The central processing unit outputs the processed result to the client.

[0202] The database acceleration method provided in this embodiment receives an operation request sent by the client through the central processing unit; parses the operation request into an operation plan; loads the corresponding operation microcode from the host memory according to the operation plan; sends the operation microcode to the internal bus; the internal bus sends the operation microcode to the vector processor; the vector processor prefetches the corresponding target data from the database data of the memory controller through the operation microcode; controls one or more preset execution units to process the target data through the operation microcode to obtain the processed result corresponding to the operation plan; returns the processed result to the central processing unit; the central processing unit outputs the processed result to the client, and retrieves the database data in the database to the memory controller through the central processing unit, and the operation microcode prefetches the corresponding target data from the database data of the memory controller, realizing near storage of the database acceleration system and improving the operation efficiency of the database.

[0203] In addition, the database acceleration method provided in this embodiment processes the database data by decomposing the microcode into a storage microcode and a calculation microcode to enhance the hardware dynamic adaptability.

[0204] It should be noted that the database acceleration method provided in this embodiment further includes a dynamic conversion mechanism, specifically:

[0205] Mask control: An 8-bit mask selects the target column. For example, 0x0F selects the first 4 columns.

[0206] Column offset configuration: Specify the offset of the corresponding column in the row through the control register.

[0207] Row-column conversion unit: A dedicated circuit realizes real-time conversion from row to column or from column to row, and supports parallel processing of multiple rows.

[0208] Cache optimization: The conversion result is cached in the vector register to avoid repeated conversion.

[0209] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0210] The above has introduced in detail a database acceleration system and a database acceleration method provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A database acceleration system, characterized in that, Comprising: A central processing unit (10) and a coprocessor (20), the coprocessor (20) at least includes an internal bus (201) and a vector processor (202); the central processing unit (10) is communicatively connected to the internal bus (201); the internal bus (201) is communicatively connected to the vector processor (202); the vector processor (202) at least includes a plurality of preset execution units (2021), and each preset execution unit (2021) includes one or more instructions; The central processing unit (10) receives an operation request sent by a user terminal (30); parses the operation request into an operation plan, where the operation plan is the operation steps corresponding to the operation request; Retrieves corresponding target data from a database according to the operation plan; Sends the operation plan and the target data to the internal bus (201); The internal bus (201) sends the operation plan and the target data to the vector processor (202); The vector processor (202) controls one or more preset execution units (2021) to process the target data according to the operation plan to obtain a processing result corresponding to the operation plan; returns the processing result to the central processing unit (10); The central processing unit (10) outputs the processing result to the user terminal (30).

2. The database acceleration system according to claim 1, wherein The plurality of preset execution units (2021) include one or more of the following: A data filtering execution unit, a hash join execution unit, an aggregation calculation execution unit, a regular expression matching execution unit, a sorting execution unit, a full table scan execution unit, and an index tree operation execution unit; Among them, the data filtering execution unit includes comparison operation instructions; the hash join execution unit includes hash table construction instructions, hash probing instructions, and nested loop join instructions; the aggregation calculation execution unit includes sum calculation instructions, count calculation instructions, maximum and minimum value fetching instructions, and average value instructions; the regular expression matching execution unit includes pattern compilation instructions, vector matching instructions, and result extraction instructions; the sorting execution unit includes radix sorting instructions and merge sorting instructions; the full table scan execution unit includes initialization scan instructions, batch data acquisition instructions, and column projection instructions; the index tree operation execution unit includes initialization index instructions, exact operation instructions, and range operation instructions.

3. The database acceleration system according to claim 1, wherein The coprocessor (20) further includes: a memory controller (203); the memory controller (203) is communicatively connected to the internal bus (201); Among them, the central processing unit (10) has previously retrieved database data in the database to the memory controller (203), and the memory controller (203) includes multiple storage channels; The central processing unit (10) receives an operation request sent by a user terminal (30); parses the operation request into an operation plan; loads corresponding operation microcode from the host memory according to the operation plan; sends the operation microcode to the internal bus (201); The internal bus (201) sends the operation microcode to the vector processor (202); The vector processor (202) prefetches corresponding target data from the database data of the memory controller (203) through the operation microcode; controls one or more preset execution units (2021) to process the target data through the operation microcode to obtain a processing result corresponding to the operation plan; and returns the processing result to the central processing unit (10); The central processing unit (10) outputs the processing result to the client (30).

4. The database acceleration system according to claim 3, wherein The vector processor (202) further includes: a vector register (2022); The vector processor (202) prefetches corresponding target data from the database data of the memory controller (203) through the operation microcode; The one or more preset execution units (2021) process the target data according to the operation microcode to obtain a processing result corresponding to the operation plan; and output the processing result to the vector register (2022); The vector register (2022) returns the processing result to the central processing unit (10).

5. The database acceleration system according to claim 3, wherein The coprocessor (20) further includes: a scalar processor (204); The coprocessor (20) verifies the operation microcode to obtain a verification result; After determining that the verification result is a pass, the scalar processor (204) initializes the operation microcode to complete the initialization of the operation microcode.

6. The database acceleration system according to claim 5, wherein The scalar processor (204) further includes: a control register (2041); The control register (2041) activates the operation microcode and establishes a mapping relationship from the instruction operation code to the operation microcode to complete the initialization of the operation microcode.

7. The database acceleration system according to claim 1, wherein The structural data of the preset execution unit (2021) includes one or more of the following: An operation code, a function code, a sub-function code, a target register, a first source register, a second source register, and a mask mode.

8. The database acceleration system according to claim 7, wherein The structural data of the operation code includes one or more of the following: An arithmetic operation code, a load code, a store code, a branch code, a system instruction, and a custom instruction.

9. A database acceleration method, characterized in that, Applied to the database acceleration system as described in claim 3, including: The central processing unit receives an operation request sent by the client; parses the operation request into an operation plan; loads a corresponding operation microcode from the host memory according to the operation plan; and sends the operation microcode to the internal bus; The internal bus sends the operation microcode to the vector processor; The vector processor prefetches corresponding target data from the database data of the memory controller through the operation microcode; controls one or more preset execution units to process the target data through the operation microcode to obtain a processing result corresponding to the operation plan; and returns the processing result to the central processing unit; The central processing unit outputs the processing result to the client.

10. The database acceleration method according to claim 9, wherein, Wherein the microcode is decomposed into a storage microcode and a calculation microcode; Accordingly, the prefetching of corresponding target data from the database data of the memory controller through the operation microcode includes: Prefetching corresponding target data from the database data of the memory controller through the storage microcode; Accordingly, the controlling of one or more preset execution units to process the target data through the operation microcode to obtain the processing result corresponding to the operation plan includes: Controlling the one or more preset execution units to process the target data through the calculation microcode to obtain the processing result corresponding to the operation plan.

11. The database acceleration method according to claim 10, wherein Wherein the target data includes hot data and cold data, and the database data includes multiple column data; Accordingly, the prefetching of corresponding target data from the database data of the memory controller through the operation microcode includes: Through the storage microcode, obtaining the access times of each column data according to a preset counter array in a pre-determined dominant access mode; Performing a sorting process on each access time to obtain an access sequence; Determining the frequently accessed column data among the column data according to the access sequence; Determining the frequently accessed column data as the hot data, and determining the remaining column data among the column data as the cold data.

12. The database acceleration method according to claim 11, wherein The determination process of the dominant access mode includes: Obtaining the access times of multiple access modes to the memory controller within a preset time; Determining the dominant access mode from the multiple access modes according to each access time.

13. The database acceleration method according to claim 12, wherein The structure of the access mode includes one or more of the following types: prefetch data size, prefetch trigger condition, and prefetch address cache.

14. The database acceleration method according to claim 11, wherein After determining the frequently accessed column data as the hot data and the remaining column data among the column data as the cold data, it further includes: Storing the hot data in columnar form in the memory controller, and recording the starting address, length, and data type of the corresponding column data; Storing the cold data in row form in the memory controller.

15. The database acceleration method according to claim 10, wherein Wherein the processing result includes one or more sub-processing results; Accordingly, the controlling of one or more preset execution units to process the target data through the calculation microcode to obtain the processing result corresponding to the operation plan includes: Operating the corresponding one or more preset execution units through the calculation microcode to process the target data to obtain one or more sub-processing results; Sorting each sub-processing result to obtain a processing result sequence; Aggregating the processing result sequence to obtain an aggregated processing result; Merging the processing result sequence to obtain a merged processing result; Converting the merged processing result to obtain the processing result.

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