Modeling and optimizing method for thermal resistance network of high-power semiconductor module

Abstract

The invention discloses a modeling and optimizing method for a thermal resistance network of a high-power semiconductor module. The method is based on an electricity-heat-fluid field dynamic coupling simulation technology, the turbulence state is judged through Reynolds numbers, and the enhancement effect of fluid flow on heat transfer is quantified in combination with a standard k-epsilon model and a Navier-Stokes equation; a module thermal resistance curve is extracted through transient simulation, thermal resistance parameters are fitted through a high-order Foster model, a thermal resistance network model containing self-heating impedance and coupling thermal impedance is constructed, and matrix representation of temperature distribution in a multi-chip heat source coupling scene is achieved. Loss parameters are further corrected through iteration in combination with experimental data. Experimental results show that the model has high precision in the aspect of junction temperature prediction, and the calculation efficiency is remarkably improved compared with a traditional finite element method. The invention provides a high-precision and low-complexity solution for the thermal management design of the high-power semiconductor module, and can be widely applied to the fields of new energy automobile electric control systems and high-density power electronic equipment.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology and relates to a method for modeling and optimizing a thermal resistance network for high-power semiconductor modules. Background Art

[0002] As a core component of an electric control system, a high-power semiconductor module undertakes important responsibilities of energy conversion, thermal management, and steady-state operation of the system, and its temperature is closely related to the system reliability. At present, the commonly used junction temperature monitoring methods can be divided into five categories: temperature sensor contact measurement method, optical measurement method, thermosensitive parameter method, finite element simulation method, and thermal resistance network method. The thermal resistance network model of high-power semiconductor devices has been widely used in temperature monitoring of power semiconductor modules due to advantages such as low usage cost and short simulation time. The accuracy of temperature monitoring is related to the transient thermal resistance value, device loss, and thermal resistance network structure.

[0003] For obtaining the transient thermal resistance value, the step response test method based on the JESD51 series standard is widely used. By measuring the change curve of the device junction temperature over time and combining the structure function analysis method (Structure Function) to extract the thermal impedance parameters. This method needs to rely on high-precision thermosensitive parameters (such as saturation voltage drop V_CE(sat)) to calibrate the junction temperature, but it is easily affected by electrical noise. In terms of numerical simulation, finite element analysis (FEA) constructs a three-dimensional thermal model including multiple layers such as chips, solder layers, and substrates, and combines transient boundary conditions to solve the heat conduction equation, which can intuitively characterize the non-linear distribution characteristics of the heat flow path. In the junction temperature analysis of multi-chip high-power modules based on the thermal resistance network (H. Wang, Z. Zhou, Z. Xu, X. Ge, Y. Yang, Y. Zhang et al., A Thermal Network Model for Multichip Power Modules Enabling to Characterize the Thermal Coupling Effects, IEEE Transactions on Power Electronics, vol. 39, no. 5, pp. 6225-6245, May 2024.), the thermal resistance value is obtained through the transient thermal resistance curve, only considering the solid heat conduction process, without considering the influence of heat-fluid coupling in the heat sink on the results.

[0004] Regarding the optimization of the thermal resistance network structure, related research focuses on high-precision dynamic thermal modeling and real-time temperature prediction technologies. The current breakthrough directions include: parametric modeling of multi-layer packages based on different structural Cauer / Foster networks, integrating frequency-domain thermal impedance analysis and three-dimensional finite element simulation to establish the mapping relationship between transient thermal response and structural defects; a new online identification method driven by data-physics fusion, using deep Kalman filtering and transfer learning technologies to achieve dynamic correction of thermal resistance parameters under aging conditions; a multi-physical field coupling monitoring system, combining electro-thermal-mechanical joint feature extraction to develop an intelligent diagnostic algorithm with extremely small junction temperature inversion error. The junction temperature monitoring method based on the three-dimensional thermal resistance network ( . Zhang, Y., Zhang, M., Luo, L., Li, W., Ma, and B. Zhang, "Fast and Accurate Three-Dimensional Thermal Model Based on Discrete Green's Function for Power Electronics," IEEE Transactions on Power Electronics, vol. 40, no. 6, pp. 8036-8048, June 2025.) studied a three-dimensional thermal resistance network modeling method for high-power modules based on the discrete Green's function (DGF). This method uses a matrix algorithm instead of an integral algorithm to solve the junction temperature results monitored by the thermal resistance network, but does not consider the thermal coupling effect of multiple lateral chips and the coupling influence of fluid heat dissipation on the results.

[0005] For device loss calculation, multi-physics field coupling analysis is required, covering static conduction loss (generated by the interaction between the device conduction resistance or forward voltage drop and the effective current value), dynamic switching loss (resulting from the transient overlap of voltage and current and high-frequency switching characteristics during the switching process), and additional losses (such as energy dissipation caused by the reverse recovery charge of the diode and the charging and discharging losses of the gate drive charge). The influence of the total loss on the junction temperature is quantified through the thermal resistance network model, and then it guides the collaborative design of the low-loss characteristics selection of wide-bandgap semiconductor materials (such as silicon carbide, gallium nitride), soft-switching control strategies (such as zero-voltage / zero-current switching technology), and efficient thermal management solutions (such as heat pipes, phase change materials, and liquid cooling systems). Finally, the accuracy of the loss model needs to be verified by combining experimental calibration and numerical simulation to achieve multi-objective optimization of the power electronic system in terms of efficiency, thermal stability, and long-term reliability. Device loss calculation based on a specific modulation method (P. Zhang, S. Wang and H. Li, Full-Si-Based Two-Stage VSI and Its Specialized Modulation Strategy to ReduceSwitching Power Loss and Increase PWM Harmonic Frequency, IEEE Transactions onPower Electronics, vol. 40, no. 5, pp. 7110-7124, May 2025 . ) only considers the losses of a single device chip under a specific PWM modulation method, without considering the different losses of different chips due to the influence of packaging and fluid heat dissipation, etc. Summary of the Invention

[0006] Aiming at the defects in the prior art, the purpose of the present invention is to provide a modeling and optimization method for the thermal resistance network of high-power semiconductor modules.

[0007] The technical solution adopted by the present invention is as follows:

[0008] A modeling and optimization method for the thermal resistance network of high-power semiconductor modules is based on the dynamic coupling simulation technology of electro-thermal-fluid fields. The turbulent state is determined by the Reynolds number, and the standard k-ε model and Navier-Stokes equation are combined to quantify the enhancement effect of fluid flow on heat transfer. The thermal resistance curve of the module is extracted by transient simulation, and the thermal resistance parameters are fitted by the high-order Foster model. A thermal resistance network model including self-thermal impedance and coupled thermal impedance is constructed to realize the matrix representation of the temperature distribution in the multi-chip heat source coupling scenario. Further, the loss parameters are iteratively corrected. The prediction results show that the model has high accuracy in junction temperature prediction, and the calculation efficiency is significantly improved compared with the traditional finite element method. The present invention provides a high-precision and low-complexity solution for the thermal management design of high-power semiconductor modules, which can be widely applied to the fields of new energy vehicle electronic control systems and high-density power electronic devices.

[0009] The method specifically may include the following steps:

[0010] Step 1: Construct a three-dimensional model in the simulation software according to the three-dimensional data of the actual model, and set the material parameters and cooling medium parameters of the module according to the actual model;

[0011] Step 2: Establish a multi-physics field coupling simulation model including a three-dimensional flow field domain and a solid heat transfer domain. First, the Reynolds number needs to be calculated and estimated through the fluid inlet flow rate and the radiator inlet size to determine the flow state, and then an appropriate fluid dynamics model is selected; based on the target operating condition parameters and the voltage-current characteristic curve provided by the device manual, the loss of the power device in the high-power semiconductor module at the rated operating point is calculated.

[0012] Step 3: Apply different loss power loads to the chip heat source, and use the finite volume method to perform unsteady fluid-thermal coupling solution, and synchronously extract transient impedance parameters such as chip junction-case thermal resistance and case-radiator thermal resistance;

[0013] Step 4: Import the transient impedance data into the Foster thermal network modeling system, establish a multi-node thermal circuit model through impedance parameter matrix decomposition, realize the matrix representation of the temperature distribution in the multi-chip heat source coupling scenario, quantitatively represent the internal self-thermal impedance, inter-chip coupling impedance and packaging-level heat transfer path of the module, and form an equivalent network topology structure;

[0014] Step 5: Conduct a reactive power test experiment, obtain the junction temperature data by using an infrared tester, compare the predicted values of the thermal network model with the measured temperature field distribution data, dynamically correct the loss value, and finally achieve the convergence of the prediction error of the module thermal distribution;

[0015] In the above technical solution, further, in Steps 1 and 2, according to the target operating condition requirements and combining the characteristic parameters in the device data sheet, the loss of the device under the corresponding operating conditions is initially calculated. The device loss is mainly determined by the conduction loss and the switching loss. The calculation method of the conduction loss within one cycle is as follows:

[0016]

[0017] In the formula, M is the modulation ratio, is the current-voltage phase difference, V CE0 is the threshold voltage, I CP is the peak current, r CE is the on-state equivalent resistance, which can be obtained by fitting the current-voltage curve from the manufacturer's manual.

[0018] The calculation method of the switching loss is as follows:

[0019]

[0020] Among them, E SW(on) is the energy lost during one turn-on at the rated current I CN and the rated voltage V CEN , E SW(off ) is the energy lost during one turn-off at the rated current I CN and the rated voltage V CEN , which can be obtained from the corresponding device manual. V dc is the DC bus voltage.

[0021] Based on the above key parameters, a multi-physics field simulation framework integrating the fluid-thermal coupling mechanism needs to be established: During the modeling process, first, the flow state needs to be determined by estimating the Reynolds number, and then an appropriate fluid dynamics model is selected. Specifically, by calculating the numerical range of the Reynolds number Re of the fluid domain, the demarcation threshold between the laminar flow and turbulent flow states can be accurately determined, providing a theoretical criterion for subsequent selection of the standard k-ε model or the laminar flow model. The flow state discrimination mechanism is directly related to the coupling calculation accuracy of the fluid velocity field and the temperature field, and the calculation method is as follows:

[0022] R e =ρνD h / μ

[0023] In the formula, ρ is the fluid density (kg / m 3 ), v is the flow velocity of the coolant (m / s), D h is the characteristic length (m), and μ is the dynamic viscosity (Pa·s). When the Reynolds number Re = ρνD hWhen Re>4000, the flow is in a turbulent state. Therefore, the standard k-ε model (refer to the ANSYS Fluent Turbulence Model Guide) is used to describe the flow characteristics of the fluid in the liquid-cooled radiator. Thus, the losses caused by the electric field and the heat generated by the rated power consumption in the thermal field settings will conduct from the chip, diffuse upward through the convective heat transfer coefficient, and downward along the heat transfer path through the chip, chip solder layer, Direct Bonding Copper (DBC) structure, DBC solder layer, and substrate in sequence, and finally complete the heat transfer process through the heat exchange between the radiator and the coolant.

[0024] Furthermore, in the established multi-physics field coupling simulation framework, it is necessary to configure the heat-fluid coupling boundary conditions matching the target working conditions, including parameters such as the fluid inlet velocity, turbulence intensity, and the time-varying curve of the chip power load. Through transient fluid-thermal coupled simulation and solution, the dynamic temperature response data of key monitoring points inside the module (such as the junction temperature T j , the case temperature T c ) can be extracted synchronously. According to the physical definition of the transient thermal impedance, its mathematical representation is:

[0025]

[0026] In the formula, P is the applied steady-state thermal power load. This transient thermal impedance curve essentially constitutes the step response function of the heat conduction system, completely containing the dynamic heat transfer characteristic parameters such as the medium heat capacity, contact thermal resistance, and convective heat transfer. Based on this thermodynamic system identification theory, the Z jc (t) curve obtained by simulation is parameterized by the Prony series expansion method, and its expression can be decomposed as:

[0027]

[0028] In the formula, R i is the thermal resistance value of the i-th order, C i is the heat capacity value of the i-th order, and n is the maximum cascade layer number of the thermal resistance and heat capacity. The parameters can be obtained through the fitting process of the thermal impedance curve. The higher the order of the thermal resistance network modeling, the relatively more accurate the fitting result, but the greater the computational complexity and the amount of calculation.

[0029] Furthermore, based on the extracted transient thermal resistance values, a thermal resistance network model of the module is constructed. The complex thermal resistance distribution inside the module is transformed into a network form to clarify the thermal resistance relationship between each node. The thermal resistance network model includes the self-thermal impedance and the coupled thermal impedance. When multiple chip heat sources are coupled, the temperature distribution of the entire module can be expressed in matrix form as follows:

[0030]

[0031] Where Denote the junction temperature of chip n at the j-th layer, is the self-heat impedance of chip n from the j-th layer to the substrate, Denote the coupled thermal impedance of chip n to chip m from the j-th layer to the substrate, T refn represents the substrate temperature directly below the center position of the n-th chip. Convert the simulation results into a network model that is easier to analyze and optimize. Compare and verify the constructed thermal resistance network model with the simulation results to ensure the accuracy and reliability of the model.

[0032] According to the actual temperature measured in the reactive power test experiment, compare it with the output characteristic results of the IGBT device at different temperatures in the manual, and recalculate the device loss formula for the total power loss. Correct the loss parameter values, and substitute them into Step 4 to further iteratively correct the loss values and optimize and verify the thermal impedance model, ultimately achieving accurate prediction and optimized design of the module temperature distribution.

[0033] The beneficial effects of the present invention are:

[0034] The present invention extracts the module thermal resistance curve by using transient simulation, fits the thermal resistance parameters with a high-order Foster model, constructs a thermal resistance network model including self-heat impedance and coupled thermal impedance, and realizes the matrix representation of the temperature distribution in the multi-chip heat source coupling scenario. And iteratively correct the loss parameters by combining experimental data. Experimental results show that the model has high accuracy in junction temperature prediction, and the calculation efficiency is significantly improved compared with the traditional finite element method. The present invention provides a high-precision and low-complexity solution for the thermal management design of high-power semiconductor modules, and can be widely applied to the fields of new energy vehicle electronic control systems and high-density power electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is the flow chart of the thermal resistance network method for high-power semiconductor modules according to the present invention.

[0036] Figure 2 is the temperature field distribution diagram of the IGBT module obtained by simulation.

[0037] Figure 3 is the internal package structure diagram of the high-power IGBT module.

[0038] Figure 4 is the vertical temperature distribution diagram of the IGBT module.

[0039] Figure 5 is the waveform diagram of the excitation source when testing the transient thermal impedance.

[0040] Figure 6 is the schematic diagram of the thermal resistance network model proposed by the present invention.

[0041] Figure 7It is a schematic diagram of the chip numbers inside the IGBT module.

[0042] Figure 8 It is the IGBT junction temperature test bench.

[0043] Figure 9 It is a comparison graph of the junction temperature obtained from the thermal resistance network (TRN) and the junction temperature obtained from the finite element simulation (FEM) for different chips: (a) Chip numbered A; (b) Chip numbered B; (c) Chip numbered C; (d) Chip numbered D; (e) Chip numbered E; (f) Chip numbered F. Specific implementation manners

[0044] The technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and specific examples.

[0045] The core link of the thermal management problem lies in accurately evaluating the power loss of semiconductor devices. The present invention constructs a quantitative analysis method for power loss under specific working conditions by analyzing the electrical characteristic parameters provided in the device specification sheet. Research shows that the total device loss is mainly composed of two parts: steady-state conduction loss and dynamic switching loss: the calculation of conduction loss needs to comprehensively consider the relationship between the conduction resistance characteristics and the effective value of the current, while the evaluation of switching loss needs to combine the voltage and current change trajectories and working frequency parameters during the switching transient process. The following empirical formula gives the calculation method:

[0046]

[0047] In the formula, M is the modulation ratio, is the current-voltage phase difference, V CE0 is the threshold voltage, I CP is the peak current, r CE is the on-state equivalent resistance, which can be obtained by fitting the current-voltage curve from the manufacturer's manual.

[0048] The calculation method of switching loss is:

[0049]

[0050] where E SW(on) is the energy loss for one turn-on at the rated current I CN and the rated voltage V CEN , E SW(off ()) is the energy loss for one turn-off at the rated current I CN and the rated voltage V CEN , which can be obtained from the corresponding device manual, V dc is the DC bus voltage.

[0051] Considering the thermal-fluid coupling problem, based on the non-isothermal fluid dynamics (NSTF) theory, the Navier-Stokes equations are used to describe the coolant flow, combined with the heat conduction equation and the Joule heat equation, to establish a coupled partial differential equation system of multiple physical fields:

[0052]

[0053] where v is the fluid velocity vector (m / s), ρ is the fluid density (kg / m 3 ³), p is the pressure on the infinitesimal element (Pa / m), μ is the dynamic viscosity coefficient (Pa·s), F body is the body force (N / m 3 ³), c p is the specific heat capacity at constant pressure (J / (kg·K)), T is the temperature (°C), Q loss is the loss generated by chip loss (W / m 3 ³), and k is the thermal conductivity. By discretely solving using the finite volume method (FVM), the enhanced effect of fluid flow on heat transfer (such as turbulent mixing and reduction of boundary layer thermal resistance) can be accurately characterized. According to the Reynolds number Re = ρνD h / μ to judge the flow state. When Re > 4000, the standard k-ε turbulence model is used to capture the turbulent characteristics at high flow velocities, and its transport equations are:

[0054]

[0055] where G k is the turbulent kinetic energy generation term (kg / (m·s 3 ³)), μ t is the turbulent viscosity (Pa·s), σ k is the Prandtl constant of turbulent kinetic energy, and ∈ is the turbulent kinetic energy dissipation rate (m 2 ² / s 3 ³). This model can effectively predict the flow separation and local heat transfer coefficient distribution of the coolant in the radiator. Therefore, the losses caused by the electric field and the heat generated by the rated power consumption in the thermal field setting will conduct from the chip, diffuse upward through the convective heat transfer coefficient, and downward along the heat transfer path through the chip, chip solder layer, DBC structure, DBC solder layer, and substrate in sequence, and finally complete the heat transfer process through the heat exchange between the radiator and the coolant. Considering the steady-state finite element simulation results of thermal-fluid coupling as Figure 2 shown. After completing the coupled modeling of multiple physical fields, it is necessary to further convert the simulation results into heat resistance network parameters that can be quantitatively analyzed. This process depends on the accurate extraction and network construction of transient thermal impedance, so as to lay a foundation for temperature prediction and optimization.

[0056] Based on the basic process of steady-state solution, on the basis of the steady-state setting, a time step function is multiplied by the excitation source to convert it into a transient step excitation source, so as to simulate the dynamic response of the system under time variation. Through transient simulation and further extraction of the transient simulation results at different positions in the vertical direction of the IGBT module. In the established multi-physics coupling simulation framework, it is necessary to configure the heat-fluid coupling boundary conditions matching the target working conditions, including parameters such as the fluid inlet velocity, turbulence intensity, and the time-varying curve of the chip power load. Through the transient fluid-thermal coupled simulation solution, the dynamic temperature response data of the key monitoring points inside the module (such as the junction temperature T j , the case temperature T c ) can be extracted synchronously. According to the physical definition of the transient thermal impedance, its mathematical representation is:

[0057]

[0058] where P is the steady-state thermal power load applied. This transient thermal impedance curve essentially constitutes the step response function of the heat conduction system, and completely includes the dynamic heat transfer characteristic parameters such as the medium heat capacity, contact thermal resistance, and convective heat transfer. Based on this thermodynamic system identification theory, the Z jc (t) curve obtained by simulation is parametrically modeled by the Prony series expansion method, and its expression can be decomposed as:

[0059]

[0060] where R i is the thermal resistance value of the i-th order, C i is the heat capacity value of the i-th order, and n is the maximum cascading layer number of the thermal resistance and heat capacity. The parameters can be obtained through the fitting process of the thermal impedance curve. The higher the order of the thermal resistance network modeling, the relatively more accurate the fitting result, but the greater the computational complexity and the amount of calculation.

[0061] Based on the extracted transient thermal resistance values, a thermal resistance network model of the module is constructed. The complex thermal resistance distribution inside the module is transformed into a network form, and the thermal resistance relationship between each node is clarified. The thermal resistance network model includes the self-thermal impedance and the coupled thermal impedance. When multiple chip heat sources are coupled, the temperature distribution of the entire module can be expressed in matrix form as follows:

[0062]

[0063] where represents the junction temperature of chip n at the j-th layer, is the self-thermal impedance of chip n from the j-th layer to the substrate, represents the coupled thermal impedance of chip n to chip m from the j-th layer to the substrate, T refnRepresents the substrate temperature corresponding to directly below the center position of the nth chip. The constructed fourth-order Foster model is as Figure 6 shown. Substitute the loss value into the model for calculation. Finally, compare and verify the constructed thermal resistance network model with the simulation results to ensure the accuracy and reliability of the model. Specifically, collect the measured data through a reactive power test bench, as Figure 8 shown. According to the simulation output results and experimental results, iteratively adjust the loss parameter values to further optimize the model, and finally achieve the accurate prediction and optimal design of the module temperature distribution.

[0064] Select the chips named as Figure 7 shown as the objects for comparative analysis. The simulation results are as Figure 9 shown, where (a) represents chip No. A; (b) represents chip No. B; (c) represents chip No. C; (d) represents chip No. D; (e) represents chip No. E; (f) represents chip No. F. As Figure 9 shown, the deviations between the junction temperature curves predicted by the thermal resistance network model and the finite element simulation results under steady state are 0.11 °C (chip No. A), 0.29 °C (chip No. B), 0.10 °C (chip No. C), 0.09 °C (chip No. D), 0.31 °C (chip No. E), 0.18 °C (chip No. F) respectively, and the maximum deviation of the transient response is 0.5 °C (chip No. A), 0.63 °C (chip No. B), 0.68 °C (chip No. C), 0.49 °C (chip No. D), 0.57 °C (chip No. E), 0.61 °C (chip No. F). The error analysis shows that the model has a high characterization accuracy for the multi-source coupling effect.

Claims

1. A modeling and optimization method for the thermal resistance network of high-power semiconductor modules, characterized in that It includes the following steps: The first step: construct a three-dimensional model in the simulation software according to the three-dimensional data of the actual model, and set the material parameters and cooling medium parameters of the module according to the actual model at the same time; The second step: establish a multi-physics field coupling simulation model including a three-dimensional flow field domain and a solid heat transfer domain. First, it is necessary to calculate the Reynolds number through the fluid inlet flow velocity and the radiator inlet size to estimate and determine the flow state, and then select an appropriate fluid dynamics model; based on the target working condition parameters and the voltage-current characteristic curve provided by the device manual, calculate the losses of the power devices in the high-power semiconductor module at the rated operating point; The third step: apply different loss power loads to the chip heat source, and use the finite volume method to solve the unsteady flow-thermal coupling, and synchronously extract transient impedance parameters such as the chip junction-case thermal resistance and the case-radiator thermal resistance; The fourth step: import the transient impedance data into the Foster thermal network modeling system, establish a multi-node thermal circuit model through impedance parameter matrix decomposition, realize the matrix representation of the temperature distribution in the multi-chip heat source coupling scenario, quantitatively characterize the internal self-heat impedance, the coupling impedance between chips and the heat transfer path at the package level, and form an equivalent network topology; The fifth step: conduct a reactive power test experiment, obtain the junction temperature data using an infrared tester, compare the predicted values of the thermal network model with the measured temperature field distribution data, dynamically correct the loss value, and finally achieve the convergence of the module thermal distribution prediction error.

2. The modeling and optimization method for the thermal resistance network of high-power semiconductor modules according to claim 1, characterized in that: The device losses described in the first step include conduction losses and switching losses; the conduction loss P within one period is ss calculated as follows: where M is the modulation ratio, is the current-voltage phase difference, V CE0 is the threshold voltage, I CP is the peak current, r CE is the on-state equivalent resistance, obtained by fitting the current-voltage curve from the manufacturer's manual; Switching loss P sw The calculation method is as follows: Among them, f SW is the IGBT switching frequency, E SW(on) is the energy lost during one turn-on at the rated current I CN and the rated voltage V CEN E SW(off) is the energy lost during one turn-off at the rated current I CN and the rated voltage V CEN E SW(on) and E SW(off) are both obtained from the corresponding device manuals, and V dc is the DC bus voltage.

3. The modeling and optimization method for the thermal resistance network of high-power semiconductor modules according to claim 1, characterized in that: In the second step, when establishing a multi-physics field coupling simulation architecture including a three-dimensional flow field domain and a solid heat transfer domain, that is, it is necessary to establish a multi-physics field simulation framework integrating the flow-thermal coupling mechanism. In the modeling process, first, it is necessary to calculate the Reynolds number to estimate and determine the flow state, and then select an appropriate fluid dynamics model. By calculating the numerical range of the Reynolds number Re in the fluid domain, determine the boundary threshold between the laminar flow and turbulent flow states. When the Reynolds number Re > 4000, the flow is in the turbulent state, and the standard k-ε model is used to describe the flow characteristics of the fluid in the liquid-cooled radiator.

4. The modeling and optimization method for the thermal resistance network of high-power semiconductor modules according to claim 1, wherein: The losses caused by the electric field and the heat generated by the rated power consumption in the thermal field setting are conducted from the chip, and its heat transfer path is: diffused upward through the convective heat transfer coefficient, and downward through the chip, the chip solder layer, the direct copper clad ceramic board DBC structure, the DBC solder layer and the substrate in turn, and finally complete the heat transfer process through the heat exchange between the radiator and the coolant.

5. The modeling and optimization method for the thermal resistance network of high-power semiconductor modules according to claim 1, characterized in that: In the established multi-physics field coupling simulation architecture, it is necessary to configure the heat-flow coupling boundary conditions matching the target working conditions, including the fluid inlet flow velocity, the turbulence intensity and the time-varying curve of the chip power load; for a single chip, through the transient flow-thermal joint simulation solution, synchronously extract the dynamic temperature response data of the key monitoring points inside the module to obtain the transient impedance parameters.

6. The modeling and optimization method for the thermal resistance network of a high-power semiconductor module according to claim 5, characterized in that: The transient impedance parameters are: where, T j (t), T c (t) are the temperatures at different key monitoring points at time t, respectively, and P is the steady-state thermal power load applied; the thermal impedance Z jc (t) curve obtained by simulation is parametrically modeled by the Prony series expansion method, and its expression can be decomposed into: R in the formula i is the thermal resistance value of the i-th order, C i is the heat capacity value of the i-th order, n is the maximum number of cascaded layers of thermal resistance and heat capacity, and the parameters are obtained through the fitting process of the thermal impedance curve.

7. The modeling and optimization method for the thermal resistance network of a high-power semiconductor module according to claim 6, wherein: In the fourth step, based on the extracted transient thermal resistance values, construct a thermal resistance network model of the module, transform the complex thermal resistance distribution inside the module into a network form, clarify the thermal resistance relationship between each node. The thermal resistance network model includes self-heat impedance and coupling thermal impedance. When multiple chip heat sources are coupled, the temperature distribution of the entire module is expressed in matrix form as follows: Among them represents the junction temperature of chip n at the j-th layer is the self-heating impedance of chip n from the j-th layer to the substrate represents the coupled thermal impedance of chip n to chip m from the j-th layer to the substrate, T refn represents the substrate temperature corresponding to directly below the center position of the n-th chip, P n is the total loss value calculated for different chips; The constructed thermal resistance network model is compared and verified with the simulation results, and the loss parameter values are corrected according to the reactive test junction temperature data results, further optimizing the thermal resistance network model, and finally achieving accurate prediction and optimal design of the module temperature distribution.

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