A post-simulation verification method and device for integrated circuits

Abstract

The present invention relates to the technical field of circuit post-simulation verification, and includes a method and apparatus for integrated circuit post-simulation verification, comprising: determining whether a simulation object is a preset functional iteration object; if not, utilizing a post-simulation verification environment to obtain delay data and netlist data corresponding to the simulation object, and back-labeling the delay data into the netlist data to obtain a timing-annotated netlist; performing a post-simulation verification operation on the timing-annotated netlist to obtain a first verification result; storing a first SDF precompiled file in the first verification result in the SDF precompilation device; and when the simulation object is the functional iteration object, utilizing the top-level simulation environment to obtain a historical SDF precompiled file corresponding to the simulation object from the SDF precompilation device, and performing a post-simulation verification operation on the simulation object based on the historical SDF precompiled file to obtain a second verification result. The present invention can improve the efficiency of post-simulation verification.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit post-simulation verification, and in particular to a post-simulation verification method and device for an integrated circuit. Background Art

[0002] Post-simulation can also be called timing simulation or post-placement and routing simulation. It mainly targets the netlist after layout and routing, adds timing analysis, and mainly verifies the timing correctness.

[0003] Currently, the main method for post-simulation is to annotate the various delay parameters on the physical lines onto the netlist file through back-annotation. This then simulates the actual device delay behavior during simulation to check for constraint errors during synthesis. However, this method consumes excessive resources, requires frequent RTL modifications during debugging, and rerunning the simulation after modifications is a significant amount of repetitive work, resulting in low post-simulation efficiency. Summary of the Invention

[0004] The present invention provides a post-simulation verification method for an integrated circuit, the main purpose of which is to improve the efficiency of post-simulation verification.

[0005] To achieve the above-mentioned object, the present invention provides a post-simulation verification method for an integrated circuit, comprising:

[0006] Obtain the top-level verification environment, top-level simulation environment and SDF pre-compiler, and obtain the simulation object;

[0007] Using the top-level verification environment and the SDF pre-compiler, determining whether the simulation object is a preset function iteration object;

[0008] When the simulation object is not the function iteration object, using the pre-built post-simulation macro definition in the top-level simulation environment to call the pre-built post-simulation verification environment;

[0009] Using the post-simulation verification environment, obtaining delay data and netlist data corresponding to the simulation object, back-annotating the delay data to the netlist data to obtain a timing-annotated netlist, and sending the timing-annotated netlist to the top-level simulation environment;

[0010] Performing a post-simulation verification operation on the timing-annotated netlist using the top-level simulation environment to obtain a first verification result, wherein the first verification result includes a first SDF precompiled file, a first FSDB waveform file, and a first simulation result;

[0011] Storing the first SDF precompiled file in the first verification result in the SDF precompilation device;

[0012] When the simulation object is the function iteration object, the top-level simulation environment is used to obtain the historical SDF precompilation file corresponding to the simulation object from the SDF precompilation device, and a post-simulation verification operation is performed on the simulation object based on the historical SDF precompilation file to obtain a second verification result.

[0013] Optionally, the using the top-level verification environment and the SDF pre-compiler to determine whether the simulation object is a preset function iteration object includes:

[0014] Obtaining each verified simulation object in the SDF pre-compilation device;

[0015] Utilizing a top-level verification environment to parse the simulation object and obtain SDF data and RTL data;

[0016] Using the top-level verification environment, and according to the SDF data and the RTL data, performing a repeated judgment operation based on the SDF and the RTL on the simulation object and each of the verified simulation objects;

[0017] When there exists a verified simulation object in the SDF pre-compiler that has the same SDF data as the simulation object but different RTL data, the simulation object is determined to be a preset function iteration object.

[0018] Optionally, the using the post-simulation verification environment to obtain delay data and netlist data corresponding to the simulation object, and back-labeling the delay data to the netlist data to obtain a timing-annotated netlist includes:

[0019] Using the post-simulation verification environment to call a pre-built UTL device, using the UTL device to call a pre-built DEF device, and using the DEF device to call a pre-built SDF device;

[0020] Using the UTL device to call the pre-built NETLIST device;

[0021] Using the NETLIST device, according to the simulation object, a NETLIST file is obtained, and netlist data is obtained from the NETLIST file;

[0022] Obtaining an SDF file according to the simulation object using the SDF device, and obtaining delay data from the SDF file;

[0023] The UTL device is used to aggregate the netlist data and delay data, and a post-simulation verification environment is used to back-label the delay data into the netlist data to obtain a timing-annotated netlist.

[0024] Optionally, the obtaining of the SDF file according to the simulation object by using the SDF device includes:

[0025] Get component timing library;

[0026] Using a pre-built timing filtering device, marking the timings belonging to a preset low-attention timing type in the component timing library to obtain a marked timing set;

[0027] When the SDF device obtains a timing set from the component timing library according to the simulation object to construct an SDF file, the marked timing set in the timing set is deleted to obtain an SDF file.

[0028] Optionally, performing a post-simulation verification operation on the timing-annotated netlist using the top-level simulation environment to obtain a first verification result includes:

[0029] Using pre-built simulation instructions in the top-level simulation environment, calling a pre-built EDA tool;

[0030] Performing a post-simulation verification operation on the timing-annotated netlist using the EDA tool to obtain a first SDF precompiled file, a first FSDB waveform file, and a first simulation result;

[0031] The first SDF precompiled file, the first FSDB waveform file, and the first simulation result are summarized to obtain a first verification result.

[0032] Optionally, the second verification result includes a second FSDB waveform file and a second simulation result.

[0033] Optionally, storing the first SDF precompiled file in the first verification result in the SDF precompilation device includes:

[0034] Extracting a first SDF precompiled file from the first verification result;

[0035] According to the pre-constructed path storage in the top-level simulation environment, the first SDF pre-compiled file is stored in the SDF pre-compilation device.

[0036] To achieve the above-mentioned object, the present invention further provides an integrated circuit post-simulation verification device, comprising:

[0037] An object verification module, configured to obtain a top-level verification environment, a top-level simulation environment, and an SDF precompiler, obtain a simulation object, and use the top-level verification environment and the SDF precompiler to determine whether the simulation object is a preset function iteration object;

[0038] a post-simulation verification module, configured to, when the simulation object is not the functional iteration object, utilize a pre-built post-simulation macro definition in the top-level simulation environment to call the pre-built post-simulation verification environment, and utilize the post-simulation verification environment to obtain delay data and netlist data corresponding to the simulation object, and back-annotate the delay data into the netlist data to obtain a timing-annotated netlist, and send the timing-annotated netlist to the top-level simulation environment;

[0039] A top-level simulation module is used to use the top-level simulation environment to perform a post-simulation verification operation on the timing-annotated netlist to obtain a first verification result, wherein the first verification result includes a first SDF precompiled file, a first FSDB waveform file and a first simulation result, and the first SDF precompiled file in the first verification result is stored in the SDF precompilation device, and when the simulation object is the functional iteration object, the top-level simulation environment is used to obtain the historical SDF precompiled file corresponding to the simulation object from the SDF precompilation device, and a post-simulation verification operation is performed on the simulation object according to the historical SDF precompiled file to obtain a second verification result.

[0040] Optionally, the using the top-level verification environment and the SDF pre-compiler to determine whether the simulation object is a preset function iteration object includes:

[0041] Obtaining each verified simulation object in the SDF pre-compilation device;

[0042] Utilizing a top-level verification environment to parse the simulation object and obtain SDF data and RTL data;

[0043] Using the top-level verification environment, and according to the SDF data and the RTL data, performing a repeated judgment operation based on the SDF and the RTL on the simulation object and each of the verified simulation objects;

[0044] When there exists a verified simulation object in the SDF pre-compiler that has the same SDF data as the simulation object but different RTL data, the simulation object is determined to be a preset function iteration object.

[0045] Optionally, the using the post-simulation verification environment to obtain delay data and netlist data corresponding to the simulation object, and back-labeling the delay data to the netlist data to obtain a timing-annotated netlist includes:

[0046] Using the post-simulation verification environment to call a pre-built UTL device, using the UTL device to call a pre-built DEF device, and using the DEF device to call a pre-built SDF device;

[0047] Using the UTL device to call the pre-built NETLIST device;

[0048] Using the NETLIST device, according to the simulation object, a NETLIST file is obtained, and netlist data is obtained from the NETLIST file;

[0049] Obtaining an SDF file according to the simulation object using the SDF device, and obtaining delay data from the SDF file;

[0050] The UTL device is used to aggregate the netlist data and delay data, and a post-simulation verification environment is used to back-label the delay data into the netlist data to obtain a timing-annotated netlist.

[0051] In order to solve the above problem, the present invention further provides an electronic device, comprising:

[0052] a memory storing at least one instruction;

[0053] The processor executes the instructions stored in the memory to implement the above-mentioned integrated circuit post-simulation verification method.

[0054] In order to solve the above problems, the present invention also provides a computer-readable storage medium, in which at least one instruction is stored. The at least one instruction is executed by a processor in an electronic device to implement the above-mentioned integrated circuit post-simulation verification method.

[0055] The present invention solves the problem described in the background technology. The present invention verifies the SDF information of each simulation object in advance. When the simulation object is not a functional iteration object, it indicates that the simulation object is relatively new and has not undergone a post-simulation verification process. A timing-annotated netlist can be constructed as in the traditional post-verification method to perform post-verification simulation. However, when constructing the timing-annotated netlist, the present invention separately manages the netlist data and delay data required in the timing-annotated netlist, and records and monitors the delay data. When the simulation object is a functional iteration object, it indicates that the simulation device has simulated a similar simulation object before. In this way, past data can be directly called from the recorded and monitored delay data without having to reconstruct the delay data, thereby improving the efficiency of post-simulation verification. Therefore, the present invention can improve the efficiency of post-simulation verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A schematic flow chart of a post-simulation verification method for an integrated circuit provided by one embodiment of the present invention;

[0057] Figure 2 A schematic diagram of the structure of an apparatus for a post-simulation verification method for an integrated circuit provided by an embodiment of the present invention;

[0058] Figure 3 A functional module diagram of a post-simulation verification device for an integrated circuit provided by one embodiment of the present invention;

[0059] Figure 4 A schematic structural diagram of an electronic device for implementing the integrated circuit post-simulation verification method provided by an embodiment of the present invention.

[0060] Description of reference numerals:

[0061] 1. Electronic device; 10. Processor; 11. Memory; 12. Bus.

[0062] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0063] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0064] The present embodiment provides a post-simulation verification method for an integrated circuit. The execution entity of the post-simulation verification method includes, but is not limited to, at least one of electronic devices such as a server and a terminal that can be configured to execute the method provided by the embodiment of the present application. In other words, the post-simulation verification method can be executed by software or hardware installed on a terminal device or a server device, where the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0065] Reference Figure 1 FIG. 1 is a flow chart of a post-simulation verification method for an integrated circuit according to an embodiment of the present invention. In this embodiment, the post-simulation verification method for an integrated circuit includes:

[0066] S1. Obtain the top-level verification environment, top-level simulation environment and SDF pre-compiler, and obtain the simulation object.

[0067] The top-level verification environment refers to a computing environment used to support the function of determining the function iteration object.

[0068] The top-level simulation environment refers to the working environment used to support EDA tools in retrieving data and executing simulation processes. The EDA (Electronic Design Automation) tool refers to electronic design automation, a type of industrial software used to assist in the design of very large-scale integrated circuits.

[0069] The SDF pre-compilation device is a device for managing SDF pre-compiled files.

[0070] The simulation object refers to an object that requires post-simulation verification, including component distribution and connection information of an integrated circuit, as well as scenarios and functional areas that require post-simulation verification.

[0071] Specifically, in the embodiment of the present invention, Figure 2 As shown, a post-simulation verification environment, a top-level simulation environment and an SDF pre-compilation device are constructed, wherein the post-simulation verification environment includes an SDF device, a DEF device, a NETLIST device and a UTL device, wherein the Figure 2 The FSDB file and simulation results in are the output results of this solution.

[0072] Specifically, in the embodiment of the present invention, the post-simulation verification environment is enabled by defining a post-simulation macro (macro definition POSTGSIM) in the top-level simulation verification environment (TB_TOP). The process is as follows:

[0073] First, TB_TOP calls the UTL device through POSTGSIM. The UTL device is the master dispatcher for the post-simulation verification environment. It divides the SDF back-annotation work for post-simulation verification into different verification cases. By setting macro definitions for the corresponding cases in the top-level simulation environment, the SDF device for the corresponding case is subsequently called and integrated into the top-level simulation environment.

[0074] In this embodiment of the present invention, the UTL device can simultaneously call the NETLIST device to obtain a netlist and the DEF device to obtain an SDF file. Finally, the UTL device's upper-level environment (the top layer of the overall post-simulation verification environment) is used to back-annotate the timing information in the SDF file into the netlist, generating a netlist verification file with timing information.

[0075] Specifically, in an embodiment of the present invention, the NETLIST device is a netlist management device. During the EDA tool compilation and verification environment, by calling the NETLIST device, the local storage path of the NETLIST file can be obtained, and the netlist of the integrated circuit can be further integrated into the post-top-level verification environment. To achieve multi-person collaboration, the storage path of the NETLIST file in the NETLIST device is a relative path. By defining user address variables, post-simulation verification is performed in the user's local workspace. The NETLIST (netlist) is a file that converts the logic / circuit design RTL into a physical implementation, and is composed of cells, pins, ports, and networks.

[0076] Specifically, the DEF (Define) device is a CORNER management device. It can invoke different CORNER scenarios through simulation instructions, such as the maximum process corner for high temperature and high pressure, with three or more process corners configurable. The CORNER further invokes its corresponding SDF device. The CORNER refers to process deviations during chip production, and scenarios are divided into multiple corners based on temperature, process, and voltage. Corner conditions are added to post-simulation to ensure the chip can function properly in extreme scenarios, such as high temperature, high voltage, fast transistors, and minimum capacitance x resistance.

[0077] Specifically, in an embodiment of the present invention, the SDF device is an SDF file management device. To enable multi-person collaboration, the storage path of the SDF file is also a relative path. By defining user address variables, post-simulation verification is performed in the user's local workspace. The SDF file is configured and generated by the EDA tool based on the component timing library and process requirements. The SDF (standard delay format) describes the delay data of cells and interconnects after circuit layout and routing. Its main function is to back-annotate delay information into the functional model to simulate the chip's actual operating state.

[0078] S2. Using the top-level verification environment and the SDF pre-compiler, determine whether the simulation object is a preset function iteration object.

[0079] In detail, in an embodiment of the present invention, the use of the top-level verification environment and the SDF pre-compiler to determine whether the simulation object is a preset function iteration object includes:

[0080] Obtaining each verified simulation object in the SDF pre-compilation device;

[0081] Utilizing a top-level verification environment to parse the simulation object and obtain SDF data and RTL data;

[0082] Using the top-level verification environment, and according to the SDF data and the RTL data, performing a repeated judgment operation based on the SDF and the RTL on the simulation object and each of the verified simulation objects;

[0083] When there exists a verified simulation object in the SDF pre-compiler that has the same SDF data as the simulation object but different RTL data, the simulation object is determined to be a preset function iteration object.

[0084] The verified simulation objects refer to a set of simulation objects that have undergone a post-verification process.

[0085] Parsing refers to the process of extracting key information from the simulation object, including at least SDF data and RTL data. RTL (Register Transfer Level) is a type of hardware description language (HDL) used to describe the register transfer-level behavior of a circuit. RTL code specifically describes the register transfer-level behavior of a circuit, specifically how data is transferred between registers and when these transfers are triggered. It describes the relationships between registers within a circuit, such as data transfer and control logic between registers.

[0086] The repeated determination operation refers to a process of determining whether the SDF data has equivalent data in the SDF pre-compiler by methods such as file structure check and syntax check.

[0087] Specifically, in an embodiment of the present invention, each verified simulation object is first obtained from the SDF pre-compilation device, and then the key information of the simulation object is parsed to obtain SDF data and RTL data. By repeating the judgment operation, it is determined whether the SDF data and RTL data already exist in the SDF pre-compilation device. If there is neither SDF data nor RTL data, it indicates that the simulation object is relatively novel and is a completely new type of simulation object. If there is both SDF data and RTL data, it indicates that the simulation object may be repeatedly post-simulated. If there is SDF data but no RTL data, it indicates that the component distribution circuit of the simulation object has been recorded, but a new verification area or function needs to be post-simulated.

[0088] Specifically, in an embodiment of the present invention, when there exists a verified simulation object in the SDF pre-compiler that has the same SDF data as the simulation object but different RTL data, the simulation object is determined to be a preset function iteration object.

[0089] When the simulation object is not the function iteration object, S3, using the pre-built post-simulation macro definition in the top-level simulation environment to call the pre-built post-simulation verification environment.

[0090] Among them, the macro definition is an important mechanism in the C language, which allows programmers to define an identifier in the source code so that the identifier can be used to replace a specific value or code block in subsequent codes.

[0091] Specifically, in the embodiment of the present invention, Figure 2 The process in the post-simulation verification environment is coded and replaced by the post-simulation macro definition (macro definition POSTGSIM).

[0092] Therefore, in the embodiment of the present invention, as long as the macro definition POSTGSIM is called in the top-level verification environment, the actions in the simulation verification environment part will be automatically executed.

[0093] S4. Utilize the post-simulation verification environment to obtain the delay data and netlist data corresponding to the simulation object, and back-label the delay data to the netlist data to obtain a timing-annotated netlist, and send the timing-annotated netlist to the top-level simulation environment.

[0094] In the embodiment of the present invention, the delay data refers to the data content in the SDF file. The netlist data refers to the data content in the NETLIST file.

[0095] Among them, the back-annotation refers to the process of dynamically injecting (annotating) the actual delay information extracted in the physical design stage into the gate-level netlist file to replace the original ideal delay value.

[0096] The timing-annotated netlist refers to the result of converting the timing marks in the delay data into the netlist data.

[0097] In detail, in an embodiment of the present invention, the post-simulation verification environment is used to obtain delay data and netlist data corresponding to the simulation object, and the delay data is back-annotated into the netlist data to obtain a timing-annotated netlist, including:

[0098] Using the post-simulation verification environment to call a pre-built UTL device, using the UTL device to call a pre-built DEF device, and using the DEF device to call a pre-built SDF device;

[0099] Using the UTL device to call the pre-built NETLIST device;

[0100] Using the NETLIST device, according to the simulation object, a NETLIST file is obtained, and netlist data is obtained from the NETLIST file;

[0101] Obtaining an SDF file according to the simulation object using the SDF device, and obtaining delay data from the SDF file;

[0102] The UTL device is used to aggregate the netlist data and delay data, and a post-simulation verification environment is used to back-label the delay data into the netlist data to obtain a timing-annotated netlist.

[0103] Specifically, in the embodiment of the present invention, reference Figure 2As can be seen, the post-simulation verification environment calls the UTL device. One route is: the UTL device calls the DEF device, which in turn calls the SDF device. Another route is for the UTL device to call the NETLIST device. The SDF device is responsible for managing SDF files, and the NETLIST device is responsible for managing NETLIST files. Therefore, when the SDF and NETLIST devices are activated, they can directly access the SDF and NETLIST files, and then obtain key information from them, resulting in netlist data and delay data.

[0104] Then, the UTL device is used to aggregate the netlist data and delay data and send them to the top-level environment of the post-simulation verification environment, and the delay data is back-annotated into the netlist data to obtain a timing-annotated netlist.

[0105] In detail, in an embodiment of the present invention, the step of obtaining an SDF file according to the simulation object by using the SDF device includes:

[0106] Get component timing library;

[0107] Using a pre-built timing filtering device, marking the timings belonging to a preset low-attention timing type in the component timing library to obtain a marked timing set;

[0108] When the SDF device obtains a timing set from the component timing library according to the simulation object to construct an SDF file, the marked timing set in the timing set is deleted to obtain an SDF file.

[0109] The component timing library stores the timing of all electronic components in all integrated circuits in the enterprise. Timing refers to the length of time it takes for a signal to pass through a component.

[0110] The timing filter device is a device for deleting the timing of some components in the SDF file, so as to disable the timing check of a certain component during the post-simulation process.

[0111] The low-attention timing type refers to timings that are not of concern to post-simulation technicians, such as the first level of synchronization, etc. The marked timing set refers to a set of timings marked with the low-attention timing type.

[0112] Specifically, in an embodiment of the present invention, the post-simulation verification environment may further include a timing filter device to uniformly manage timing that is not of concern to relevant technical personnel, such as the first level of synchronization, and define instructions that can be recognized by EDA tools. In an embodiment of the present invention, during the compilation process of the top-level verification environment, instructions are used to call the timing filter device, further obtain the component path in the timing preprocessing device, and disable the timing check of the component during the post-simulation verification process. The filtering device includes but is not limited to methods such as set_false_path and no_timing_check.

[0113] S5. Perform a post-simulation verification operation on the timing-annotated netlist using the top-level simulation environment to obtain a first verification result, wherein the first verification result includes a first SDF precompiled file, a first FSDB waveform file, and a first simulation result.

[0114] The post-simulation verification operation refers to the specific simulation work process of the EDA tool.

[0115] The first verification result refers to the post-simulation result of a simulation object that is not a functional iteration object. The first verification result includes the first SDF precompiled file, the first FSDB waveform file, and the first simulation result. The "first" is used to distinguish the "second" represented by the post-simulation result of a simulation object of the subsequent functional iteration object type.

[0116] The SDF pre-compiled file includes the first compilation result, that is, the header file that passes the compilation check. The header file is used to call each SDF file.

[0117] The simulation results are simulation process records, including but not limited to compilation process logs, simulation process logs, and timing violation logs. The FSDB waveform file is a high-performance waveform file format specifically designed for digital circuit simulation and verification.

[0118] In detail, in an embodiment of the present invention, the post-simulation verification operation is performed on the timing-annotated netlist using the top-level simulation environment to obtain a first verification result, including:

[0119] Using pre-built simulation instructions in the top-level simulation environment, calling a pre-built EDA tool;

[0120] Performing a post-simulation verification operation on the timing-annotated netlist using the EDA tool to obtain a first SDF precompiled file, a first FSDB waveform file, and a first simulation result;

[0121] The first SDF precompiled file, the first FSDB waveform file, and the first simulation result are summarized to obtain a first verification result.

[0122] The simulation instructions are instructions for controlling the working state of the EDA tool.

[0123] Specifically, in an embodiment of the present invention, an EDA tool is first invoked according to the simulation instruction. The timing-annotated netlist is then executed using the EDA tool to obtain a first SDF precompiled file, a first FSDB waveform file, and a first simulation result. Finally, these three types of results are aggregated to obtain a first verification result.

[0124] S6. Store the first SDF precompiled file in the first verification result into the SDF precompilation device.

[0125] In detail, in an embodiment of the present invention, storing the first SDF precompiled file in the first verification result in the SDF precompilation device includes:

[0126] Extracting a first SDF precompiled file from the first verification result;

[0127] According to the pre-constructed path storage in the top-level simulation environment, the first SDF pre-compiled file is stored in the SDF pre-compilation device.

[0128] The path storage refers to the storage address of the SDF precompiled file in the SDF precompiled device, which is used to quickly find the file.

[0129] Specifically, in the embodiment of the present invention, the SDF pre-compiled file is stored in the pre-compiled device according to the path specified in the post-simulation verification environment, and can be used for subsequent simulation after the RTL is modified.

[0130] When the simulation object is the function iteration object, S7, using the top-level simulation environment, obtain the historical SDF precompilation file corresponding to the simulation object from the SDF precompilation device, and perform a post-simulation verification operation on the simulation object according to the historical SDF precompilation file to obtain a second verification result.

[0131] When the simulation object is the functional iteration object, it indicates that the circuit structure of the current simulation object already exists and may be a device modified after product iteration. Therefore, it is possible to directly obtain the historical SDF pre-compiled file corresponding to the simulation object without executing the post-simulation verification environment.

[0132] Specifically, in an embodiment of the present invention, the second verification result includes a second FSDB waveform file and a second simulation result. Since the SDF precompiled file uses a historical SDF precompiled file, the second verification result may or may not include the SDF precompiled file.

[0133] Specifically, in an embodiment of the present invention, post-simulation verification, in which the RTL file is modified but the SDF file is not, directly calls the SDF precompiler via simulation instructions, further calls the SDF precompiled file, and integrates the SDF precompiled file into the top-level simulation verification environment. Because the SDF file is not modified, the SDF compilation results in the SDF precompiled file can be directly called, eliminating the need to recompile the SDF file. This reduces the number of SDF file compilations and improves post-simulation verification efficiency.

[0134] The present invention solves the problem described in the background technology. The present invention verifies the SDF information of each simulation object in advance. When the simulation object is not a functional iteration object, it indicates that the simulation object is relatively new and has not undergone a post-simulation verification process. A timing-annotated netlist can be constructed as in the traditional post-verification method to perform post-verification simulation. However, when constructing the timing-annotated netlist, the present invention separately manages the netlist data and delay data required in the timing-annotated netlist, and records and monitors the delay data. When the simulation object is a functional iteration object, it indicates that the simulation device has simulated a similar simulation object before. In this way, past data can be directly called from the recorded and monitored delay data without having to reconstruct the delay data, thereby improving the efficiency of post-simulation verification. Therefore, the present invention can improve the efficiency of post-simulation verification.

[0135] like Figure 2 , which is a functional module diagram of an integrated circuit post-simulation verification device provided by an embodiment of the present invention.

[0136] The integrated circuit post-simulation verification apparatus 100 of the present invention can be installed in an electronic device. Depending on the functionality implemented, the integrated circuit post-simulation verification apparatus 100 may include an object verification module 101, a post-simulation verification module 102, and a top-level simulation module 103. A module, also referred to as a unit, is a series of computer program segments that can be executed by an electronic device processor and perform a fixed function, and is stored in the electronic device's memory.

[0137] The object verification module 101 is used to obtain a top-level verification environment, a top-level simulation environment, and an SDF precompiler, obtain a simulation object, and use the top-level verification environment and the SDF precompiler to determine whether the simulation object is a preset function iteration object;

[0138] The post-simulation verification module 102 is configured to, when the simulation object is not the functional iteration object, use the pre-built post-simulation macro definition in the top-level simulation environment to call the pre-built post-simulation verification environment, and use the post-simulation verification environment to obtain delay data and netlist data corresponding to the simulation object, and back-annotate the delay data into the netlist data to obtain a timing-annotated netlist, and send the timing-annotated netlist to the top-level simulation environment;

[0139] The top-level simulation module 103 is used to use the top-level simulation environment to perform a post-simulation verification operation on the timing-annotated netlist to obtain a first verification result, wherein the first verification result includes a first SDF precompiled file, a first FSDB waveform file and a first simulation result, and the first SDF precompiled file in the first verification result is stored in the SDF precompilation device, and when the simulation object is the functional iteration object, the top-level simulation environment is used to obtain the historical SDF precompiled file corresponding to the simulation object from the SDF precompilation device, and the simulation object is post-simulation verification based on the historical SDF precompiled file to obtain a second verification result.

[0140] In detail, each module in the integrated circuit post-simulation verification device 100 according to the embodiment of the present invention adopts the same method as above when in use. Figure 1 The technical means are the same as the integrated circuit post-simulation verification method described in and can produce the same technical effects, so they will not be repeated here.

[0141] like Figure 4 FIG. 1 is a schematic structural diagram of an electronic device for implementing a post-simulation verification method for an integrated circuit provided by an embodiment of the present invention.

[0142] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may further include a computer program stored in the memory 11 and executable on the processor 10, such as an integrated circuit post-simulation verification method program.

[0143] The memory 11 includes at least one type of readable storage medium, including flash memory, a mobile hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory 11 may be an internal storage unit of the electronic device 1, such as a mobile hard disk of the electronic device 1. In other embodiments, the memory 11 may also be an external storage device of the electronic device 1, such as a plug-in mobile hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. equipped on the electronic device 1. Furthermore, the memory 11 includes both the internal storage unit of the electronic device 1 and an external storage device. The memory 11 can be used not only to store application software installed in the electronic device 1 and various types of data, such as the code of the integrated circuit post-simulation verification method program, but also to temporarily store data that has been output or is about to be output.

[0144] In some embodiments, the processor 10 may be comprised of an integrated circuit, such as a single packaged integrated circuit or a combination of multiple packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control core (control unit) of the electronic device, connecting the various components of the electronic device using various interfaces and circuits. It executes programs or modules stored in the memory 11 (e.g., integrated circuit post-simulation verification method programs) and accesses data stored in the memory 11 to perform various functions and process data.

[0145] The bus 12 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus 12 may be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to enable communication between the memory 11 and at least one processor 10, etc.

[0146] Figure 4 Only the electronic device with components is shown, and it can be understood by those skilled in the art that Figure 4 The structure shown does not constitute a limitation on the electronic device 1 , and may include fewer or more components than shown in the figure, or combine certain components, or arrange the components differently.

[0147] For example, although not shown, the electronic device 1 may further include a power supply (e.g., a battery) to power various components. Preferably, the power supply may be logically connected to the at least one processor 10 via a power management device, thereby enabling functions such as charge management, discharge management, and power consumption management via the power management device. The power supply may further include any components such as one or more DC or AC power supplies, a recharging device, a power failure detection circuit, a power converter or inverter, and a power status indicator. The electronic device 1 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which are not further described here.

[0148] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0149] Optionally, the electronic device 1 may further include a user interface, which may be a display or an input unit (such as a keyboard). Optionally, the user interface may also be a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen. The display may also be appropriately referred to as a display screen or a display unit, and is used to display information processed by the electronic device 1 and to display a visual user interface.

[0150] The integrated circuit post-simulation verification method program stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When executed in the processor 10, it can achieve the following:

[0151] Obtain the top-level verification environment, top-level simulation environment and SDF pre-compiler, and obtain the simulation object;

[0152] Using the top-level verification environment and the SDF pre-compiler, determining whether the simulation object is a preset function iteration object;

[0153] When the simulation object is not the function iteration object, using the pre-built post-simulation macro definition in the top-level simulation environment to call the pre-built post-simulation verification environment;

[0154] Using the post-simulation verification environment, obtaining delay data and netlist data corresponding to the simulation object, back-annotating the delay data to the netlist data to obtain a timing-annotated netlist, and sending the timing-annotated netlist to the top-level simulation environment;

[0155] Performing a post-simulation verification operation on the timing-annotated netlist using the top-level simulation environment to obtain a first verification result, wherein the first verification result includes a first SDF precompiled file, a first FSDB waveform file, and a first simulation result;

[0156] Storing the first SDF precompiled file in the first verification result in the SDF precompilation device;

[0157] When the simulation object is the function iteration object, the top-level simulation environment is used to obtain the historical SDF precompilation file corresponding to the simulation object from the SDF precompilation device, and a post-simulation verification operation is performed on the simulation object based on the historical SDF precompilation file to obtain a second verification result.

[0158] Specifically, the specific implementation method of the processor 10 for the above instructions can refer to Figures 1 to 4The description of the relevant steps in the corresponding embodiments will not be repeated here.

[0159] Furthermore, if the modules / units integrated into the electronic device 1 are implemented as software functional units and sold or used as independent products, they may be stored in a computer-readable storage medium. The computer-readable storage medium may be volatile or non-volatile. For example, the computer-readable medium may include any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0160] The present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program. When the computer program is executed by a processor of an electronic device, the computer program can implement:

[0161] Obtain the top-level verification environment, top-level simulation environment and SDF pre-compiler, and obtain the simulation object;

[0162] Using the top-level verification environment and the SDF pre-compiler, determining whether the simulation object is a preset function iteration object;

[0163] When the simulation object is not the function iteration object, using the pre-built post-simulation macro definition in the top-level simulation environment to call the pre-built post-simulation verification environment;

[0164] Using the post-simulation verification environment, obtaining delay data and netlist data corresponding to the simulation object, back-annotating the delay data to the netlist data to obtain a timing-annotated netlist, and sending the timing-annotated netlist to the top-level simulation environment;

[0165] Performing a post-simulation verification operation on the timing-annotated netlist using the top-level simulation environment to obtain a first verification result, wherein the first verification result includes a first SDF precompiled file, a first FSDB waveform file, and a first simulation result;

[0166] Storing the first SDF precompiled file in the first verification result in the SDF precompilation device;

[0167] When the simulation object is the function iteration object, the top-level simulation environment is used to obtain the historical SDF precompilation file corresponding to the simulation object from the SDF precompilation device, and a post-simulation verification operation is performed on the simulation object based on the historical SDF precompilation file to obtain a second verification result.

[0168] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, and actual implementation may have other division methods.

[0169] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network elements. Some or all of the modules may be selected to achieve the purpose of the solution of this embodiment according to actual needs.

[0170] In addition, the functional modules in various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or hardware plus software functional modules.

[0171] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0172] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A post-simulation verification method for an integrated circuit, characterized in that: The method comprises: Obtain the top-level verification environment, top-level simulation environment and SDF pre-compiler, and obtain the simulation object; Obtaining each verified simulation object in the SDF pre-compilation device; Utilizing a top-level verification environment to parse the simulation object and obtain SDF data and RTL data; Using the top-level verification environment, and according to the SDF data and the RTL data, performing a repeated judgment operation based on the SDF and the RTL on the simulation object and each of the verified simulation objects; When there is a verified simulation object in the SDF pre-compiler that has the same SDF data as the simulation object but different RTL data, determining that the simulation object is a preset function iteration object; When the simulation object is not the function iteration object, using the pre-built post-simulation macro definition in the top-level simulation environment to call the pre-built post-simulation verification environment; Using the post-simulation verification environment, obtaining delay data and netlist data corresponding to the simulation object, back-annotating the delay data to the netlist data to obtain a timing-annotated netlist, and sending the timing-annotated netlist to the top-level simulation environment; Performing a post-simulation verification operation on the timing-annotated netlist using the top-level simulation environment to obtain a first verification result, wherein the first verification result includes a first SDF precompiled file, a first FSDB waveform file, and a first simulation result; Storing the first SDF precompiled file in the first verification result in the SDF precompilation device; When the simulation object is the function iteration object, the top-level simulation environment is used to obtain the historical SDF precompilation file corresponding to the simulation object from the SDF precompilation device, and a post-simulation verification operation is performed on the simulation object based on the historical SDF precompilation file to obtain a second verification result.

2. The integrated circuit post-simulation verification method according to claim 1, wherein: The method of using the post-simulation verification environment to obtain delay data and netlist data corresponding to the simulation object, and back-labeling the delay data to the netlist data to obtain a timing-annotated netlist includes: Using the post-simulation verification environment to call a pre-built UTL device, using the UTL device to call a pre-built DEF device, and using the DEF device to call a pre-built SDF device; Using the UTL device to call the pre-built NETLIST device; Using the NETLIST device, according to the simulation object, a NETLIST file is obtained, and netlist data is obtained from the NETLIST file; Obtaining an SDF file according to the simulation object using the SDF device, and obtaining delay data from the SDF file; The UTL device is used to aggregate the netlist data and delay data, and a post-simulation verification environment is used to back-label the delay data into the netlist data to obtain a timing-annotated netlist.

3. The integrated circuit post-simulation verification method according to claim 2, wherein: The method of obtaining an SDF file according to the simulation object by using the SDF device includes: Get component timing library; Using a pre-built timing filtering device, marking the timings belonging to a preset low-attention timing type in the component timing library to obtain a marked timing set; When the SDF device obtains a timing set from the component timing library according to the simulation object to construct an SDF file, the marked timing set in the timing set is deleted to obtain an SDF file.

4. The integrated circuit post-simulation verification method according to claim 3, wherein: The post-simulation verification operation is performed on the timing-annotated netlist using the top-level simulation environment to obtain a first verification result, including: Using pre-built simulation instructions in the top-level simulation environment, calling a pre-built EDA tool; Performing a post-simulation verification operation on the timing-annotated netlist using the EDA tool to obtain a first SDF precompiled file, a first FSDB waveform file, and a first simulation result; The first SDF precompiled file, the first FSDB waveform file, and the first simulation result are summarized to obtain a first verification result.

5. The integrated circuit post-simulation verification method according to claim 4, wherein: The second verification result includes a second FSDB waveform file and a second simulation result.

6. The integrated circuit post-simulation verification method according to claim 5, wherein: The storing the first SDF precompiled file in the first verification result into the SDF precompilation device includes: Extracting a first SDF precompiled file from the first verification result; According to the pre-constructed path storage in the top-level simulation environment, the first SDF pre-compiled file is stored in the SDF pre-compilation device.

7. An integrated circuit post-simulation verification device, used to execute the integrated circuit post-simulation verification method according to claim 1, characterized in that: The device comprises: An object verification module, configured to obtain a top-level verification environment, a top-level simulation environment, and an SDF precompiler, obtain a simulation object, and use the top-level verification environment and the SDF precompiler to determine whether the simulation object is a preset function iteration object; a post-simulation verification module, configured to, when the simulation object is not the functional iteration object, utilize a pre-built post-simulation macro definition in the top-level simulation environment to call the pre-built post-simulation verification environment, and utilize the post-simulation verification environment to obtain delay data and netlist data corresponding to the simulation object, and back-annotate the delay data into the netlist data to obtain a timing-annotated netlist, and send the timing-annotated netlist to the top-level simulation environment; A top-level simulation module is used to use the top-level simulation environment to perform a post-simulation verification operation on the timing-annotated netlist to obtain a first verification result, wherein the first verification result includes a first SDF precompiled file, a first FSDB waveform file and a first simulation result, and the first SDF precompiled file in the first verification result is stored in the SDF precompilation device, and when the simulation object is the functional iteration object, the top-level simulation environment is used to obtain the historical SDF precompiled file corresponding to the simulation object from the SDF precompilation device, and a post-simulation verification operation is performed on the simulation object according to the historical SDF precompiled file to obtain a second verification result.

8. The integrated circuit post-simulation verification device according to claim 7, wherein: The using the top-level verification environment and the SDF pre-compiler to determine whether the simulation object is a preset function iteration object includes: Obtaining each verified simulation object in the SDF pre-compilation device; Utilizing a top-level verification environment to parse the simulation object and obtain SDF data and RTL data; Using the top-level verification environment, and according to the SDF data and the RTL data, performing a repeated judgment operation based on the SDF and the RTL on the simulation object and each of the verified simulation objects; When there exists a verified simulation object in the SDF pre-compiler that has the same SDF data as the simulation object but different RTL data, the simulation object is determined to be a preset function iteration object.

9. The integrated circuit post-simulation verification device according to claim 8, wherein: The method of using the post-simulation verification environment to obtain delay data and netlist data corresponding to the simulation object, and back-labeling the delay data to the netlist data to obtain a timing-annotated netlist includes: Using the post-simulation verification environment to call a pre-built UTL device, using the UTL device to call a pre-built DEF device, and using the DEF device to call a pre-built SDF device; Using the UTL device to call the pre-built NETLIST device; Using the NETLIST device, according to the simulation object, a NETLIST file is obtained, and netlist data is obtained from the NETLIST file; Obtaining an SDF file according to the simulation object using the SDF device, and obtaining delay data from the SDF file; The UTL device is used to aggregate the netlist data and delay data, and a post-simulation verification environment is used to back-label the delay data into the netlist data to obtain a timing-annotated netlist.

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